]> git.proxmox.com Git - mirror_ubuntu-bionic-kernel.git/blame - drivers/gpu/drm/i915/intel_drv.h
projects / mirror_ubuntu-bionic-kernel.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
drm/i915: ensure the force pipe A quirk is actually followed
[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / i915 / intel_drv.h
CommitLineData
79e53945
JB		 1/*
2 * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
3 * Copyright (c) 2007-2008 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
23 * IN THE SOFTWARE.
24 */
25#ifndef __INTEL_DRV_H__
26#define __INTEL_DRV_H__
27
28#include <linux/i2c.h>
8ea30864 29#include "i915_drm.h"
80824003 30#include "i915_drv.h"
79e53945 31#include "drm_crtc.h"
79e53945 32#include "drm_crtc_helper.h"
37811fcc 33#include "drm_fb_helper.h"
54d63ca6 34#include "drm_dp_helper.h"
913d8d11 35
481b6af3 36#define _wait_for(COND, MS, W) ({ \
913d8d11
CW		 37 unsigned long timeout__ = jiffies + msecs_to_jiffies(MS); \
38 int ret__ = 0; \
0206e353 39 while (!(COND)) { \
913d8d11
CW		 40 if (time_after(jiffies, timeout__)) { \
41 ret__ = -ETIMEDOUT; \
42 break; \
43 } \
cc1f7194 44 if (W && drm_can_sleep()) msleep(W); \
913d8d11
CW		 45 } \
46 ret__; \
47})
48
57f350b6 49#define wait_for_atomic_us(COND, US) ({ \
bcf9dcc1
CW		 50 unsigned long timeout__ = jiffies + usecs_to_jiffies(US); \
51 int ret__ = 0; \
52 while (!(COND)) { \
53 if (time_after(jiffies, timeout__)) { \
54 ret__ = -ETIMEDOUT; \
55 break; \
56 } \
57 cpu_relax(); \
58 } \
59 ret__; \
57f350b6
JB		 60})
61
481b6af3
CW		 62#define wait_for(COND, MS) _wait_for(COND, MS, 1)
63#define wait_for_atomic(COND, MS) _wait_for(COND, MS, 0)
64
021357ac
CW		 65#define KHz(x) (1000*x)
66#define MHz(x) KHz(1000*x)
67
79e53945
JB		 68/*
69 * Display related stuff
70 */
71
72/* store information about an Ixxx DVO */
73/* The i830->i865 use multiple DVOs with multiple i2cs */
74/* the i915, i945 have a single sDVO i2c bus - which is different */
75#define MAX_OUTPUTS 6
76/* maximum connectors per crtcs in the mode set */
77#define INTELFB_CONN_LIMIT 4
78
79#define INTEL_I2C_BUS_DVO 1
80#define INTEL_I2C_BUS_SDVO 2
81
82/* these are outputs from the chip - integrated only
83 external chips are via DVO or SDVO output */
84#define INTEL_OUTPUT_UNUSED 0
85#define INTEL_OUTPUT_ANALOG 1
86#define INTEL_OUTPUT_DVO 2
87#define INTEL_OUTPUT_SDVO 3
88#define INTEL_OUTPUT_LVDS 4
89#define INTEL_OUTPUT_TVOUT 5
7d57382e 90#define INTEL_OUTPUT_HDMI 6
a4fc5ed6 91#define INTEL_OUTPUT_DISPLAYPORT 7
32f9d658 92#define INTEL_OUTPUT_EDP 8
79e53945
JB		 93
94#define INTEL_DVO_CHIP_NONE 0
95#define INTEL_DVO_CHIP_LVDS 1
96#define INTEL_DVO_CHIP_TMDS 2
97#define INTEL_DVO_CHIP_TVOUT 4
98
6c9547ff
CW		 99/* drm_display_mode->private_flags */
100#define INTEL_MODE_PIXEL_MULTIPLIER_SHIFT (0x0)
101#define INTEL_MODE_PIXEL_MULTIPLIER_MASK (0xf << INTEL_MODE_PIXEL_MULTIPLIER_SHIFT)
3b5c78a3 102#define INTEL_MODE_DP_FORCE_6BPC (0x10)
f9bef081
DV		 103/* This flag must be set by the encoder's mode_fixup if it changes the crtc
104 * timings in the mode to prevent the crtc fixup from overwriting them.
105 * Currently only lvds needs that. */
106#define INTEL_MODE_CRTC_TIMINGS_SET (0x20)
6c9547ff
CW		 107
108static inline void
109intel_mode_set_pixel_multiplier(struct drm_display_mode *mode,
110 int multiplier)
111{
112 mode->clock *= multiplier;
113 mode->private_flags |= multiplier;
114}
115
116static inline int
117intel_mode_get_pixel_multiplier(const struct drm_display_mode *mode)
118{
119 return (mode->private_flags & INTEL_MODE_PIXEL_MULTIPLIER_MASK) >> INTEL_MODE_PIXEL_MULTIPLIER_SHIFT;
120}
121
79e53945
JB		 122struct intel_framebuffer {
123 struct drm_framebuffer base;
05394f39 124 struct drm_i915_gem_object *obj;
79e53945
JB		 125};
126
37811fcc
CW		 127struct intel_fbdev {
128 struct drm_fb_helper helper;
129 struct intel_framebuffer ifb;
130 struct list_head fbdev_list;
131 struct drm_display_mode *our_mode;
132};
79e53945 133
21d40d37 134struct intel_encoder {
4ef69c7a 135 struct drm_encoder base;
79e53945 136 int type;
e2f0ba97 137 bool needs_tv_clock;
66a9278e
DV		 138 /*
139 * Intel hw has only one MUX where encoders could be clone, hence a
140 * simple flag is enough to compute the possible_clones mask.
141 */
142 bool cloneable;
5ab432ef 143 bool connectors_active;
21d40d37 144 void (*hot_plug)(struct intel_encoder *);
ef9c3aee
DV		 145 void (*enable)(struct intel_encoder *);
146 void (*disable)(struct intel_encoder *);
f0947c37
DV		 147 /* Read out the current hw state of this connector, returning true if
148 * the encoder is active. If the encoder is enabled it also set the pipe
149 * it is connected to in the pipe parameter. */
150 bool (*get_hw_state)(struct intel_encoder *, enum pipe *pipe);
f8aed700 151 int crtc_mask;
79e53945
JB		 152};
153
5daa55eb
ZW		 154struct intel_connector {
155 struct drm_connector base;
df0e9248 156 struct intel_encoder *encoder;
f0947c37
DV		 157 /* Reads out the current hw, returning true if the connector is enabled
158 * and active (i.e. dpms ON state). */
159 bool (*get_hw_state)(struct intel_connector *);
5daa55eb
ZW		 160};
161
79e53945
JB		 162struct intel_crtc {
163 struct drm_crtc base;
80824003
JB		 164 enum pipe pipe;
165 enum plane plane;
79e53945 166 u8 lut_r[256], lut_g[256], lut_b[256];
08a48469
DV		 167 /*
168 * Whether the crtc and the connected output pipeline is active. Implies
169 * that crtc->enabled is set, i.e. the current mode configuration has
170 * some outputs connected to this crtc.
171 *
172 * Atm crtc->enabled is unconditionally updated _before_ the hw state is
173 * changed, hence we can only check this when enabling the crtc.
174 */
175 bool active;
93314b5b 176 bool primary_disabled; /* is the crtc obscured by a plane? */
652c393a 177 bool lowfreq_avail;
02e792fb 178 struct intel_overlay *overlay;
6b95a207 179 struct intel_unpin_work *unpin_work;
77ffb597 180 int fdi_lanes;
cda4b7d3 181
e506a0c6
DV		 182 /* Display surface base address adjustement for pageflips. Note that on
183 * gen4+ this only adjusts up to a tile, offsets within a tile are
184 * handled in the hw itself (with the TILEOFF register). */
185 unsigned long dspaddr_offset;
186
05394f39 187 struct drm_i915_gem_object *cursor_bo;
cda4b7d3
CW		 188 uint32_t cursor_addr;
189 int16_t cursor_x, cursor_y;
190 int16_t cursor_width, cursor_height;
6b383a7f 191 bool cursor_visible;
5a354204 192 unsigned int bpp;
4b645f14 193
ee7b9f93
JB		 194 /* We can share PLLs across outputs if the timings match */
195 struct intel_pch_pll *pch_pll;
79e53945
JB		 196};
197
b840d907
JB		 198struct intel_plane {
199 struct drm_plane base;
200 enum pipe pipe;
201 struct drm_i915_gem_object *obj;
202 int max_downscale;
203 u32 lut_r[1024], lut_g[1024], lut_b[1024];
204 void (*update_plane)(struct drm_plane *plane,
205 struct drm_framebuffer *fb,
206 struct drm_i915_gem_object *obj,
207 int crtc_x, int crtc_y,
208 unsigned int crtc_w, unsigned int crtc_h,
209 uint32_t x, uint32_t y,
210 uint32_t src_w, uint32_t src_h);
211 void (*disable_plane)(struct drm_plane *plane);
8ea30864
JB		 212 int (*update_colorkey)(struct drm_plane *plane,
213 struct drm_intel_sprite_colorkey *key);
214 void (*get_colorkey)(struct drm_plane *plane,
215 struct drm_intel_sprite_colorkey *key);
b840d907
JB		 216};
217
b445e3b0
ED		 218struct intel_watermark_params {
219 unsigned long fifo_size;
220 unsigned long max_wm;
221 unsigned long default_wm;
222 unsigned long guard_size;
223 unsigned long cacheline_size;
224};
225
226struct cxsr_latency {
227 int is_desktop;
228 int is_ddr3;
229 unsigned long fsb_freq;
230 unsigned long mem_freq;
231 unsigned long display_sr;
232 unsigned long display_hpll_disable;
233 unsigned long cursor_sr;
234 unsigned long cursor_hpll_disable;
235};
236
79e53945 237#define to_intel_crtc(x) container_of(x, struct intel_crtc, base)
5daa55eb 238#define to_intel_connector(x) container_of(x, struct intel_connector, base)
4ef69c7a 239#define to_intel_encoder(x) container_of(x, struct intel_encoder, base)
79e53945 240#define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base)
b840d907 241#define to_intel_plane(x) container_of(x, struct intel_plane, base)
79e53945 242
45187ace
JB		 243#define DIP_HEADER_SIZE 5
244
3c17fe4b
DH		 245#define DIP_TYPE_AVI 0x82
246#define DIP_VERSION_AVI 0x2
247#define DIP_LEN_AVI 13
c846b619
PZ		 248#define DIP_AVI_PR_1 0
249#define DIP_AVI_PR_2 1
3c17fe4b 250
26005210 251#define DIP_TYPE_SPD 0x83
c0864cb3
JB		 252#define DIP_VERSION_SPD 0x1
253#define DIP_LEN_SPD 25
254#define DIP_SPD_UNKNOWN 0
255#define DIP_SPD_DSTB 0x1
256#define DIP_SPD_DVDP 0x2
257#define DIP_SPD_DVHS 0x3
258#define DIP_SPD_HDDVR 0x4
259#define DIP_SPD_DVC 0x5
260#define DIP_SPD_DSC 0x6
261#define DIP_SPD_VCD 0x7
262#define DIP_SPD_GAME 0x8
263#define DIP_SPD_PC 0x9
264#define DIP_SPD_BD 0xa
265#define DIP_SPD_SCD 0xb
266
3c17fe4b
DH		 267struct dip_infoframe {
268 uint8_t type; /* HB0 */
269 uint8_t ver; /* HB1 */
270 uint8_t len; /* HB2 - body len, not including checksum */
271 uint8_t ecc; /* Header ECC */
272 uint8_t checksum; /* PB0 */
273 union {
274 struct {
275 /* PB1 - Y 6:5, A 4:4, B 3:2, S 1:0 */
276 uint8_t Y_A_B_S;
277 /* PB2 - C 7:6, M 5:4, R 3:0 */
278 uint8_t C_M_R;
279 /* PB3 - ITC 7:7, EC 6:4, Q 3:2, SC 1:0 */
280 uint8_t ITC_EC_Q_SC;
281 /* PB4 - VIC 6:0 */
282 uint8_t VIC;
0aa534df
PZ		 283 /* PB5 - YQ 7:6, CN 5:4, PR 3:0 */
284 uint8_t YQ_CN_PR;
3c17fe4b
DH		 285 /* PB6 to PB13 */
286 uint16_t top_bar_end;
287 uint16_t bottom_bar_start;
288 uint16_t left_bar_end;
289 uint16_t right_bar_start;
81014b9d 290 } __attribute__ ((packed)) avi;
c0864cb3
JB		 291 struct {
292 uint8_t vn[8];
293 uint8_t pd[16];
294 uint8_t sdi;
81014b9d 295 } __attribute__ ((packed)) spd;
3c17fe4b
DH		 296 uint8_t payload[27];
297 } __attribute__ ((packed)) body;
298} __attribute__((packed));
299
f5bbfca3
ED		 300struct intel_hdmi {
301 struct intel_encoder base;
302 u32 sdvox_reg;
303 int ddc_bus;
304 int ddi_port;
305 uint32_t color_range;
306 bool has_hdmi_sink;
307 bool has_audio;
308 enum hdmi_force_audio force_audio;
309 void (*write_infoframe)(struct drm_encoder *encoder,
310 struct dip_infoframe *frame);
687f4d06
PZ		 311 void (*set_infoframes)(struct drm_encoder *encoder,
312 struct drm_display_mode *adjusted_mode);
f5bbfca3
ED		 313};
314
54d63ca6
SK		 315#define DP_RECEIVER_CAP_SIZE 0xf
316#define DP_LINK_CONFIGURATION_SIZE 9
317
318struct intel_dp {
319 struct intel_encoder base;
320 uint32_t output_reg;
321 uint32_t DP;
322 uint8_t link_configuration[DP_LINK_CONFIGURATION_SIZE];
323 bool has_audio;
324 enum hdmi_force_audio force_audio;
ab9d7c30 325 enum port port;
54d63ca6 326 uint32_t color_range;
54d63ca6
SK		 327 uint8_t link_bw;
328 uint8_t lane_count;
329 uint8_t dpcd[DP_RECEIVER_CAP_SIZE];
330 struct i2c_adapter adapter;
331 struct i2c_algo_dp_aux_data algo;
332 bool is_pch_edp;
333 uint8_t train_set[4];
334 int panel_power_up_delay;
335 int panel_power_down_delay;
336 int panel_power_cycle_delay;
337 int backlight_on_delay;
338 int backlight_off_delay;
339 struct drm_display_mode *panel_fixed_mode; /* for eDP */
340 struct delayed_work panel_vdd_work;
341 bool want_panel_vdd;
342 struct edid *edid; /* cached EDID for eDP */
343 int edid_mode_count;
344};
345
f875c15a
CW		 346static inline struct drm_crtc *
347intel_get_crtc_for_pipe(struct drm_device *dev, int pipe)
348{
349 struct drm_i915_private *dev_priv = dev->dev_private;
350 return dev_priv->pipe_to_crtc_mapping[pipe];
351}
352
417ae147
CW		 353static inline struct drm_crtc *
354intel_get_crtc_for_plane(struct drm_device *dev, int plane)
355{
356 struct drm_i915_private *dev_priv = dev->dev_private;
357 return dev_priv->plane_to_crtc_mapping[plane];
358}
359
4e5359cd
SF		 360struct intel_unpin_work {
361 struct work_struct work;
362 struct drm_device *dev;
05394f39
CW		 363 struct drm_i915_gem_object *old_fb_obj;
364 struct drm_i915_gem_object *pending_flip_obj;
4e5359cd
SF		 365 struct drm_pending_vblank_event *event;
366 int pending;
367 bool enable_stall_check;
368};
369
1630fe75
CW		 370struct intel_fbc_work {
371 struct delayed_work work;
372 struct drm_crtc *crtc;
373 struct drm_framebuffer *fb;
374 int interval;
375};
376
335af9a2 377int intel_ddc_get_modes(struct drm_connector *c, struct i2c_adapter *adapter);
f0217c42 378
3f43c48d 379extern void intel_attach_force_audio_property(struct drm_connector *connector);
e953fd7b
CW		 380extern void intel_attach_broadcast_rgb_property(struct drm_connector *connector);
381
79e53945 382extern void intel_crt_init(struct drm_device *dev);
08d644ad
DV		 383extern void intel_hdmi_init(struct drm_device *dev,
384 int sdvox_reg, enum port port);
f5bbfca3 385extern struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder);
f5bbfca3 386extern void intel_dip_infoframe_csum(struct dip_infoframe *avi_if);
eef4eacb
DV		 387extern bool intel_sdvo_init(struct drm_device *dev, uint32_t sdvo_reg,
388 bool is_sdvob);
79e53945
JB		 389extern void intel_dvo_init(struct drm_device *dev);
390extern void intel_tv_init(struct drm_device *dev);
f047e395
CW		 391extern void intel_mark_busy(struct drm_device *dev);
392extern void intel_mark_idle(struct drm_device *dev);
393extern void intel_mark_fb_busy(struct drm_i915_gem_object *obj);
394extern void intel_mark_fb_idle(struct drm_i915_gem_object *obj);
c5d1b51d 395extern bool intel_lvds_init(struct drm_device *dev);
ab9d7c30
PZ		 396extern void intel_dp_init(struct drm_device *dev, int output_reg,
397 enum port port);
a4fc5ed6
KP		 398void
399intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode,
400 struct drm_display_mode *adjusted_mode);
cb0953d7 401extern bool intel_dpd_is_edp(struct drm_device *dev);
0206e353 402extern void intel_edp_link_config(struct intel_encoder *, int *, int *);
94bf2ced
DV		 403extern int intel_edp_target_clock(struct intel_encoder *,
404 struct drm_display_mode *mode);
814948ad 405extern bool intel_encoder_is_pch_edp(struct drm_encoder *encoder);
b840d907 406extern int intel_plane_init(struct drm_device *dev, enum pipe pipe);
6f1d69b0
ED		 407extern void intel_flush_display_plane(struct drm_i915_private *dev_priv,
408 enum plane plane);
32f9d658 409
a9573556 410/* intel_panel.c */
1d8e1c75
CW		 411extern void intel_fixed_panel_mode(struct drm_display_mode *fixed_mode,
412 struct drm_display_mode *adjusted_mode);
413extern void intel_pch_panel_fitting(struct drm_device *dev,
414 int fitting_mode,
cb1793ce 415 const struct drm_display_mode *mode,
1d8e1c75 416 struct drm_display_mode *adjusted_mode);
a9573556 417extern u32 intel_panel_get_max_backlight(struct drm_device *dev);
a9573556 418extern void intel_panel_set_backlight(struct drm_device *dev, u32 level);
aaa6fd2a 419extern int intel_panel_setup_backlight(struct drm_device *dev);
24ded204
DV		 420extern void intel_panel_enable_backlight(struct drm_device *dev,
421 enum pipe pipe);
47356eb6 422extern void intel_panel_disable_backlight(struct drm_device *dev);
aaa6fd2a 423extern void intel_panel_destroy_backlight(struct drm_device *dev);
fe16d949 424extern enum drm_connector_status intel_panel_detect(struct drm_device *dev);
1d8e1c75 425
a6778b3c
DV		 426extern bool intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode,
427 int x, int y, struct drm_framebuffer *old_fb);
79e53945 428extern void intel_crtc_load_lut(struct drm_crtc *crtc);
b2cabb0e 429extern void intel_crtc_update_dpms(struct drm_crtc *crtc);
5ab432ef 430extern void intel_encoder_disable(struct drm_encoder *encoder);
ea5b213a 431extern void intel_encoder_destroy(struct drm_encoder *encoder);
5ab432ef
DV		 432extern void intel_encoder_dpms(struct intel_encoder *encoder, int mode);
433extern void intel_connector_dpms(struct drm_connector *, int mode);
f0947c37 434extern bool intel_connector_get_hw_state(struct intel_connector *connector);
0a91ca29 435extern void intel_connector_check_state(struct intel_connector *);
79e53945 436
df0e9248
CW		 437static inline struct intel_encoder *intel_attached_encoder(struct drm_connector *connector)
438{
439 return to_intel_connector(connector)->encoder;
440}
441
442extern void intel_connector_attach_encoder(struct intel_connector *connector,
443 struct intel_encoder *encoder);
444extern struct drm_encoder *intel_best_encoder(struct drm_connector *connector);
79e53945
JB		 445
446extern struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
447 struct drm_crtc *crtc);
08d7b3d1
CW		 448int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
449 struct drm_file *file_priv);
9d0498a2 450extern void intel_wait_for_vblank(struct drm_device *dev, int pipe);
58e10eb9 451extern void intel_wait_for_pipe_off(struct drm_device *dev, int pipe);
8261b191
CW		 452
453struct intel_load_detect_pipe {
d2dff872 454 struct drm_framebuffer *release_fb;
8261b191
CW		 455 bool load_detect_temp;
456 int dpms_mode;
457};
d2434ab7 458extern bool intel_get_load_detect_pipe(struct drm_connector *connector,
7173188d 459 struct drm_display_mode *mode,
8261b191 460 struct intel_load_detect_pipe *old);
d2434ab7 461extern void intel_release_load_detect_pipe(struct drm_connector *connector,
8261b191 462 struct intel_load_detect_pipe *old);
79e53945 463
79e53945
JB		 464extern void intelfb_restore(void);
465extern void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
466 u16 blue, int regno);
b8c00ac5
DA		 467extern void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
468 u16 *blue, int regno);
0cdab21f 469extern void intel_enable_clock_gating(struct drm_device *dev);
79e53945 470
127bd2ac 471extern int intel_pin_and_fence_fb_obj(struct drm_device *dev,
05394f39 472 struct drm_i915_gem_object *obj,
919926ae 473 struct intel_ring_buffer *pipelined);
1690e1eb 474extern void intel_unpin_fb_obj(struct drm_i915_gem_object *obj);
127bd2ac 475
38651674
DA		 476extern int intel_framebuffer_init(struct drm_device *dev,
477 struct intel_framebuffer *ifb,
308e5bcb 478 struct drm_mode_fb_cmd2 *mode_cmd,
05394f39 479 struct drm_i915_gem_object *obj);
38651674
DA		 480extern int intel_fbdev_init(struct drm_device *dev);
481extern void intel_fbdev_fini(struct drm_device *dev);
3fa016a0 482extern void intel_fbdev_set_suspend(struct drm_device *dev, int state);
6b95a207
KH		 483extern void intel_prepare_page_flip(struct drm_device *dev, int plane);
484extern void intel_finish_page_flip(struct drm_device *dev, int pipe);
1afe3e9d 485extern void intel_finish_page_flip_plane(struct drm_device *dev, int plane);
6b95a207 486
02e792fb
DV		 487extern void intel_setup_overlay(struct drm_device *dev);
488extern void intel_cleanup_overlay(struct drm_device *dev);
ce453d81 489extern int intel_overlay_switch_off(struct intel_overlay *overlay);
02e792fb
DV		 490extern int intel_overlay_put_image(struct drm_device *dev, void *data,
491 struct drm_file *file_priv);
492extern int intel_overlay_attrs(struct drm_device *dev, void *data,
493 struct drm_file *file_priv);
4abe3520 494
eb1f8e4f 495extern void intel_fb_output_poll_changed(struct drm_device *dev);
e8e7a2b8 496extern void intel_fb_restore_mode(struct drm_device *dev);
645c62a5 497
b840d907
JB		 498extern void assert_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
499 bool state);
500#define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
501#define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
502
645c62a5 503extern void intel_init_clock_gating(struct drm_device *dev);
e0dac65e
WF		 504extern void intel_write_eld(struct drm_encoder *encoder,
505 struct drm_display_mode *mode);
d4270e57 506extern void intel_cpt_verify_modeset(struct drm_device *dev, int pipe);
45244b87 507extern void intel_prepare_ddi(struct drm_device *dev);
c82e4d26 508extern void hsw_fdi_link_train(struct drm_crtc *crtc);
0e72a5b5 509extern void intel_ddi_init(struct drm_device *dev, enum port port);
d4270e57 510
b840d907 511/* For use by IVB LP watermark workaround in intel_sprite.c */
f681fa23 512extern void intel_update_watermarks(struct drm_device *dev);
b840d907
JB		 513extern void intel_update_sprite_watermarks(struct drm_device *dev, int pipe,
514 uint32_t sprite_width,
515 int pixel_size);
1f8eeabf
ED		 516extern void intel_update_linetime_watermarks(struct drm_device *dev, int pipe,
517 struct drm_display_mode *mode);
8ea30864
JB		 518
519extern int intel_sprite_set_colorkey(struct drm_device *dev, void *data,
520 struct drm_file *file_priv);
521extern int intel_sprite_get_colorkey(struct drm_device *dev, void *data,
522 struct drm_file *file_priv);
523
57f350b6
JB		 524extern u32 intel_dpio_read(struct drm_i915_private *dev_priv, int reg);
525
85208be0 526/* Power-related functions, located in intel_pm.c */
1fa61106 527extern void intel_init_pm(struct drm_device *dev);
85208be0 528/* FBC */
85208be0
ED		 529extern bool intel_fbc_enabled(struct drm_device *dev);
530extern void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval);
531extern void intel_update_fbc(struct drm_device *dev);
eb48eb00
DV		 532/* IPS */
533extern void intel_gpu_ips_init(struct drm_i915_private *dev_priv);
534extern void intel_gpu_ips_teardown(void);
85208be0 535
0232e927 536extern void intel_init_power_wells(struct drm_device *dev);
8090c6b9
DV		 537extern void intel_enable_gt_powersave(struct drm_device *dev);
538extern void intel_disable_gt_powersave(struct drm_device *dev);
6590190d 539extern void gen6_gt_check_fifodbg(struct drm_i915_private *dev_priv);
930ebb46 540extern void ironlake_teardown_rc6(struct drm_device *dev);
b3daeaef 541
5ab432ef
DV		 542extern void intel_enable_ddi(struct intel_encoder *encoder);
543extern void intel_disable_ddi(struct intel_encoder *encoder);
85234cdc
DV		 544extern bool intel_ddi_get_hw_state(struct intel_encoder *encoder,
545 enum pipe *pipe);
72662e10
ED		 546extern void intel_ddi_mode_set(struct drm_encoder *encoder,
547 struct drm_display_mode *mode,
548 struct drm_display_mode *adjusted_mode);
549
79e53945 550#endif /* __INTEL_DRV_H__ */
ubuntu-bionic-kernel mirror