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79e53945 JB |
1 | /* |
2 | * Copyright (c) 2006 Dave Airlie <airlied@linux.ie> | |
3 | * Copyright (c) 2007-2008 Intel Corporation | |
4 | * Jesse Barnes <jesse.barnes@intel.com> | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | |
7 | * copy of this software and associated documentation files (the "Software"), | |
8 | * to deal in the Software without restriction, including without limitation | |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
10 | * and/or sell copies of the Software, and to permit persons to whom the | |
11 | * Software is furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice (including the next | |
14 | * paragraph) shall be included in all copies or substantial portions of the | |
15 | * Software. | |
16 | * | |
17 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
18 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
19 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
20 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
21 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
22 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
23 | * IN THE SOFTWARE. | |
24 | */ | |
25 | #ifndef __INTEL_DRV_H__ | |
26 | #define __INTEL_DRV_H__ | |
27 | ||
28 | #include <linux/i2c.h> | |
178f736a | 29 | #include <linux/hdmi.h> |
760285e7 | 30 | #include <drm/i915_drm.h> |
80824003 | 31 | #include "i915_drv.h" |
760285e7 DH |
32 | #include <drm/drm_crtc.h> |
33 | #include <drm/drm_crtc_helper.h> | |
34 | #include <drm/drm_fb_helper.h> | |
612a9aab | 35 | #include <drm/drm_dp_helper.h> |
913d8d11 | 36 | |
1d5bfac9 DV |
37 | /** |
38 | * _wait_for - magic (register) wait macro | |
39 | * | |
40 | * Does the right thing for modeset paths when run under kdgb or similar atomic | |
41 | * contexts. Note that it's important that we check the condition again after | |
42 | * having timed out, since the timeout could be due to preemption or similar and | |
43 | * we've never had a chance to check the condition before the timeout. | |
44 | */ | |
481b6af3 | 45 | #define _wait_for(COND, MS, W) ({ \ |
1d5bfac9 | 46 | unsigned long timeout__ = jiffies + msecs_to_jiffies(MS) + 1; \ |
913d8d11 | 47 | int ret__ = 0; \ |
0206e353 | 48 | while (!(COND)) { \ |
913d8d11 | 49 | if (time_after(jiffies, timeout__)) { \ |
1d5bfac9 DV |
50 | if (!(COND)) \ |
51 | ret__ = -ETIMEDOUT; \ | |
913d8d11 CW |
52 | break; \ |
53 | } \ | |
0cc2764c BW |
54 | if (W && drm_can_sleep()) { \ |
55 | msleep(W); \ | |
56 | } else { \ | |
57 | cpu_relax(); \ | |
58 | } \ | |
913d8d11 CW |
59 | } \ |
60 | ret__; \ | |
61 | }) | |
62 | ||
481b6af3 CW |
63 | #define wait_for(COND, MS) _wait_for(COND, MS, 1) |
64 | #define wait_for_atomic(COND, MS) _wait_for(COND, MS, 0) | |
6effa33b DV |
65 | #define wait_for_atomic_us(COND, US) _wait_for((COND), \ |
66 | DIV_ROUND_UP((US), 1000), 0) | |
481b6af3 | 67 | |
021357ac CW |
68 | #define KHz(x) (1000*x) |
69 | #define MHz(x) KHz(1000*x) | |
70 | ||
79e53945 JB |
71 | /* |
72 | * Display related stuff | |
73 | */ | |
74 | ||
75 | /* store information about an Ixxx DVO */ | |
76 | /* The i830->i865 use multiple DVOs with multiple i2cs */ | |
77 | /* the i915, i945 have a single sDVO i2c bus - which is different */ | |
78 | #define MAX_OUTPUTS 6 | |
79 | /* maximum connectors per crtcs in the mode set */ | |
79e53945 JB |
80 | |
81 | #define INTEL_I2C_BUS_DVO 1 | |
82 | #define INTEL_I2C_BUS_SDVO 2 | |
83 | ||
84 | /* these are outputs from the chip - integrated only | |
85 | external chips are via DVO or SDVO output */ | |
86 | #define INTEL_OUTPUT_UNUSED 0 | |
87 | #define INTEL_OUTPUT_ANALOG 1 | |
88 | #define INTEL_OUTPUT_DVO 2 | |
89 | #define INTEL_OUTPUT_SDVO 3 | |
90 | #define INTEL_OUTPUT_LVDS 4 | |
91 | #define INTEL_OUTPUT_TVOUT 5 | |
7d57382e | 92 | #define INTEL_OUTPUT_HDMI 6 |
a4fc5ed6 | 93 | #define INTEL_OUTPUT_DISPLAYPORT 7 |
32f9d658 | 94 | #define INTEL_OUTPUT_EDP 8 |
72ffa333 JN |
95 | #define INTEL_OUTPUT_DSI 9 |
96 | #define INTEL_OUTPUT_UNKNOWN 10 | |
79e53945 JB |
97 | |
98 | #define INTEL_DVO_CHIP_NONE 0 | |
99 | #define INTEL_DVO_CHIP_LVDS 1 | |
100 | #define INTEL_DVO_CHIP_TMDS 2 | |
101 | #define INTEL_DVO_CHIP_TVOUT 4 | |
102 | ||
72ffa333 JN |
103 | #define INTEL_DSI_COMMAND_MODE 0 |
104 | #define INTEL_DSI_VIDEO_MODE 1 | |
105 | ||
79e53945 JB |
106 | struct intel_framebuffer { |
107 | struct drm_framebuffer base; | |
05394f39 | 108 | struct drm_i915_gem_object *obj; |
79e53945 JB |
109 | }; |
110 | ||
37811fcc CW |
111 | struct intel_fbdev { |
112 | struct drm_fb_helper helper; | |
113 | struct intel_framebuffer ifb; | |
114 | struct list_head fbdev_list; | |
115 | struct drm_display_mode *our_mode; | |
116 | }; | |
79e53945 | 117 | |
21d40d37 | 118 | struct intel_encoder { |
4ef69c7a | 119 | struct drm_encoder base; |
9a935856 DV |
120 | /* |
121 | * The new crtc this encoder will be driven from. Only differs from | |
122 | * base->crtc while a modeset is in progress. | |
123 | */ | |
124 | struct intel_crtc *new_crtc; | |
125 | ||
79e53945 | 126 | int type; |
66a9278e DV |
127 | /* |
128 | * Intel hw has only one MUX where encoders could be clone, hence a | |
129 | * simple flag is enough to compute the possible_clones mask. | |
130 | */ | |
131 | bool cloneable; | |
5ab432ef | 132 | bool connectors_active; |
21d40d37 | 133 | void (*hot_plug)(struct intel_encoder *); |
7ae89233 DV |
134 | bool (*compute_config)(struct intel_encoder *, |
135 | struct intel_crtc_config *); | |
dafd226c | 136 | void (*pre_pll_enable)(struct intel_encoder *); |
bf49ec8c | 137 | void (*pre_enable)(struct intel_encoder *); |
ef9c3aee | 138 | void (*enable)(struct intel_encoder *); |
6cc5f341 | 139 | void (*mode_set)(struct intel_encoder *intel_encoder); |
ef9c3aee | 140 | void (*disable)(struct intel_encoder *); |
bf49ec8c | 141 | void (*post_disable)(struct intel_encoder *); |
f0947c37 DV |
142 | /* Read out the current hw state of this connector, returning true if |
143 | * the encoder is active. If the encoder is enabled it also set the pipe | |
144 | * it is connected to in the pipe parameter. */ | |
145 | bool (*get_hw_state)(struct intel_encoder *, enum pipe *pipe); | |
045ac3b5 | 146 | /* Reconstructs the equivalent mode flags for the current hardware |
fdafa9e2 | 147 | * state. This must be called _after_ display->get_pipe_config has |
63000ef6 XZ |
148 | * pre-filled the pipe config. Note that intel_encoder->base.crtc must |
149 | * be set correctly before calling this function. */ | |
045ac3b5 JB |
150 | void (*get_config)(struct intel_encoder *, |
151 | struct intel_crtc_config *pipe_config); | |
f8aed700 | 152 | int crtc_mask; |
1d843f9d | 153 | enum hpd_pin hpd_pin; |
79e53945 JB |
154 | }; |
155 | ||
1d508706 | 156 | struct intel_panel { |
dd06f90e | 157 | struct drm_display_mode *fixed_mode; |
4d891523 | 158 | int fitting_mode; |
58c68779 JN |
159 | |
160 | /* backlight */ | |
161 | struct { | |
c91c9f32 | 162 | bool present; |
58c68779 | 163 | u32 level; |
7bd688cd | 164 | u32 max; |
58c68779 JN |
165 | bool enabled; |
166 | struct backlight_device *device; | |
167 | } backlight; | |
1d508706 JN |
168 | }; |
169 | ||
5daa55eb ZW |
170 | struct intel_connector { |
171 | struct drm_connector base; | |
9a935856 DV |
172 | /* |
173 | * The fixed encoder this connector is connected to. | |
174 | */ | |
df0e9248 | 175 | struct intel_encoder *encoder; |
9a935856 DV |
176 | |
177 | /* | |
178 | * The new encoder this connector will be driven. Only differs from | |
179 | * encoder while a modeset is in progress. | |
180 | */ | |
181 | struct intel_encoder *new_encoder; | |
182 | ||
f0947c37 DV |
183 | /* Reads out the current hw, returning true if the connector is enabled |
184 | * and active (i.e. dpms ON state). */ | |
185 | bool (*get_hw_state)(struct intel_connector *); | |
1d508706 JN |
186 | |
187 | /* Panel info for eDP and LVDS */ | |
188 | struct intel_panel panel; | |
9cd300e0 JN |
189 | |
190 | /* Cached EDID for eDP and LVDS. May hold ERR_PTR for invalid EDID. */ | |
191 | struct edid *edid; | |
821450c6 EE |
192 | |
193 | /* since POLL and HPD connectors may use the same HPD line keep the native | |
194 | state of connector->polled in case hotplug storm detection changes it */ | |
195 | u8 polled; | |
5daa55eb ZW |
196 | }; |
197 | ||
80ad9206 VS |
198 | typedef struct dpll { |
199 | /* given values */ | |
200 | int n; | |
201 | int m1, m2; | |
202 | int p1, p2; | |
203 | /* derived values */ | |
204 | int dot; | |
205 | int vco; | |
206 | int m; | |
207 | int p; | |
208 | } intel_clock_t; | |
209 | ||
b8cecdf5 | 210 | struct intel_crtc_config { |
bb760063 DV |
211 | /** |
212 | * quirks - bitfield with hw state readout quirks | |
213 | * | |
214 | * For various reasons the hw state readout code might not be able to | |
215 | * completely faithfully read out the current state. These cases are | |
216 | * tracked with quirk flags so that fastboot and state checker can act | |
217 | * accordingly. | |
218 | */ | |
219 | #define PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS (1<<0) /* unreliable sync mode.flags */ | |
220 | unsigned long quirks; | |
221 | ||
5113bc9b VS |
222 | /* User requested mode, only valid as a starting point to |
223 | * compute adjusted_mode, except in the case of (S)DVO where | |
224 | * it's also for the output timings of the (S)DVO chip. | |
225 | * adjusted_mode will then correspond to the S(DVO) chip's | |
226 | * preferred input timings. */ | |
b8cecdf5 | 227 | struct drm_display_mode requested_mode; |
3c52f4eb | 228 | /* Actual pipe timings ie. what we program into the pipe timing |
241bfc38 | 229 | * registers. adjusted_mode.crtc_clock is the pipe pixel clock. */ |
b8cecdf5 | 230 | struct drm_display_mode adjusted_mode; |
37327abd VS |
231 | |
232 | /* Pipe source size (ie. panel fitter input size) | |
233 | * All planes will be positioned inside this space, | |
234 | * and get clipped at the edges. */ | |
235 | int pipe_src_w, pipe_src_h; | |
236 | ||
5bfe2ac0 DV |
237 | /* Whether to set up the PCH/FDI. Note that we never allow sharing |
238 | * between pch encoders and cpu encoders. */ | |
239 | bool has_pch_encoder; | |
50f3b016 | 240 | |
3b117c8f DV |
241 | /* CPU Transcoder for the pipe. Currently this can only differ from the |
242 | * pipe on Haswell (where we have a special eDP transcoder). */ | |
243 | enum transcoder cpu_transcoder; | |
244 | ||
50f3b016 DV |
245 | /* |
246 | * Use reduced/limited/broadcast rbg range, compressing from the full | |
247 | * range fed into the crtcs. | |
248 | */ | |
249 | bool limited_color_range; | |
250 | ||
03afc4a2 DV |
251 | /* DP has a bunch of special case unfortunately, so mark the pipe |
252 | * accordingly. */ | |
253 | bool has_dp_encoder; | |
d8b32247 DV |
254 | |
255 | /* | |
256 | * Enable dithering, used when the selected pipe bpp doesn't match the | |
257 | * plane bpp. | |
258 | */ | |
965e0c48 | 259 | bool dither; |
f47709a9 DV |
260 | |
261 | /* Controls for the clock computation, to override various stages. */ | |
262 | bool clock_set; | |
263 | ||
09ede541 DV |
264 | /* SDVO TV has a bunch of special case. To make multifunction encoders |
265 | * work correctly, we need to track this at runtime.*/ | |
266 | bool sdvo_tv_clock; | |
267 | ||
e29c22c0 DV |
268 | /* |
269 | * crtc bandwidth limit, don't increase pipe bpp or clock if not really | |
270 | * required. This is set in the 2nd loop of calling encoder's | |
271 | * ->compute_config if the first pick doesn't work out. | |
272 | */ | |
273 | bool bw_constrained; | |
274 | ||
f47709a9 DV |
275 | /* Settings for the intel dpll used on pretty much everything but |
276 | * haswell. */ | |
80ad9206 | 277 | struct dpll dpll; |
f47709a9 | 278 | |
a43f6e0f DV |
279 | /* Selected dpll when shared or DPLL_ID_PRIVATE. */ |
280 | enum intel_dpll_id shared_dpll; | |
281 | ||
66e985c0 DV |
282 | /* Actual register state of the dpll, for shared dpll cross-checking. */ |
283 | struct intel_dpll_hw_state dpll_hw_state; | |
284 | ||
965e0c48 | 285 | int pipe_bpp; |
6cf86a5e | 286 | struct intel_link_m_n dp_m_n; |
ff9a6750 DV |
287 | |
288 | /* | |
289 | * Frequence the dpll for the port should run at. Differs from the | |
3c52f4eb VS |
290 | * adjusted dotclock e.g. for DP or 12bpc hdmi mode. This is also |
291 | * already multiplied by pixel_multiplier. | |
df92b1e6 | 292 | */ |
ff9a6750 DV |
293 | int port_clock; |
294 | ||
6cc5f341 DV |
295 | /* Used by SDVO (and if we ever fix it, HDMI). */ |
296 | unsigned pixel_multiplier; | |
2dd24552 JB |
297 | |
298 | /* Panel fitter controls for gen2-gen4 + VLV */ | |
b074cec8 JB |
299 | struct { |
300 | u32 control; | |
301 | u32 pgm_ratios; | |
68fc8742 | 302 | u32 lvds_border_bits; |
b074cec8 JB |
303 | } gmch_pfit; |
304 | ||
305 | /* Panel fitter placement and size for Ironlake+ */ | |
306 | struct { | |
307 | u32 pos; | |
308 | u32 size; | |
fd4daa9c | 309 | bool enabled; |
b074cec8 | 310 | } pch_pfit; |
33d29b14 | 311 | |
ca3a0ff8 | 312 | /* FDI configuration, only valid if has_pch_encoder is set. */ |
33d29b14 | 313 | int fdi_lanes; |
ca3a0ff8 | 314 | struct intel_link_m_n fdi_m_n; |
42db64ef PZ |
315 | |
316 | bool ips_enabled; | |
cf532bb2 VS |
317 | |
318 | bool double_wide; | |
b8cecdf5 DV |
319 | }; |
320 | ||
0b2ae6d7 VS |
321 | struct intel_pipe_wm { |
322 | struct intel_wm_level wm[5]; | |
323 | uint32_t linetime; | |
324 | bool fbc_wm_enabled; | |
325 | }; | |
326 | ||
79e53945 JB |
327 | struct intel_crtc { |
328 | struct drm_crtc base; | |
80824003 JB |
329 | enum pipe pipe; |
330 | enum plane plane; | |
79e53945 | 331 | u8 lut_r[256], lut_g[256], lut_b[256]; |
08a48469 DV |
332 | /* |
333 | * Whether the crtc and the connected output pipeline is active. Implies | |
334 | * that crtc->enabled is set, i.e. the current mode configuration has | |
335 | * some outputs connected to this crtc. | |
08a48469 DV |
336 | */ |
337 | bool active; | |
6efdf354 | 338 | unsigned long enabled_power_domains; |
7b9f35a6 | 339 | bool eld_vld; |
4c445e0e | 340 | bool primary_enabled; /* is the primary plane (partially) visible? */ |
652c393a | 341 | bool lowfreq_avail; |
02e792fb | 342 | struct intel_overlay *overlay; |
6b95a207 | 343 | struct intel_unpin_work *unpin_work; |
cda4b7d3 | 344 | |
b4a98e57 CW |
345 | atomic_t unpin_work_count; |
346 | ||
e506a0c6 DV |
347 | /* Display surface base address adjustement for pageflips. Note that on |
348 | * gen4+ this only adjusts up to a tile, offsets within a tile are | |
349 | * handled in the hw itself (with the TILEOFF register). */ | |
350 | unsigned long dspaddr_offset; | |
351 | ||
05394f39 | 352 | struct drm_i915_gem_object *cursor_bo; |
cda4b7d3 CW |
353 | uint32_t cursor_addr; |
354 | int16_t cursor_x, cursor_y; | |
355 | int16_t cursor_width, cursor_height; | |
6b383a7f | 356 | bool cursor_visible; |
4b645f14 | 357 | |
b8cecdf5 DV |
358 | struct intel_crtc_config config; |
359 | ||
6441ab5f | 360 | uint32_t ddi_pll_sel; |
10d83730 VS |
361 | |
362 | /* reset counter value when the last flip was submitted */ | |
363 | unsigned int reset_counter; | |
8664281b PZ |
364 | |
365 | /* Access to these should be protected by dev_priv->irq_lock. */ | |
366 | bool cpu_fifo_underrun_disabled; | |
367 | bool pch_fifo_underrun_disabled; | |
0b2ae6d7 VS |
368 | |
369 | /* per-pipe watermark state */ | |
370 | struct { | |
371 | /* watermarks currently being used */ | |
372 | struct intel_pipe_wm active; | |
373 | } wm; | |
79e53945 JB |
374 | }; |
375 | ||
c35426d2 VS |
376 | struct intel_plane_wm_parameters { |
377 | uint32_t horiz_pixels; | |
378 | uint8_t bytes_per_pixel; | |
379 | bool enabled; | |
380 | bool scaled; | |
381 | }; | |
382 | ||
b840d907 JB |
383 | struct intel_plane { |
384 | struct drm_plane base; | |
7f1f3851 | 385 | int plane; |
b840d907 JB |
386 | enum pipe pipe; |
387 | struct drm_i915_gem_object *obj; | |
2d354c34 | 388 | bool can_scale; |
b840d907 JB |
389 | int max_downscale; |
390 | u32 lut_r[1024], lut_g[1024], lut_b[1024]; | |
5e1bac2f JB |
391 | int crtc_x, crtc_y; |
392 | unsigned int crtc_w, crtc_h; | |
393 | uint32_t src_x, src_y; | |
394 | uint32_t src_w, src_h; | |
526682e9 PZ |
395 | |
396 | /* Since we need to change the watermarks before/after | |
397 | * enabling/disabling the planes, we need to store the parameters here | |
398 | * as the other pieces of the struct may not reflect the values we want | |
399 | * for the watermark calculations. Currently only Haswell uses this. | |
400 | */ | |
c35426d2 | 401 | struct intel_plane_wm_parameters wm; |
526682e9 | 402 | |
b840d907 | 403 | void (*update_plane)(struct drm_plane *plane, |
b39d53f6 | 404 | struct drm_crtc *crtc, |
b840d907 JB |
405 | struct drm_framebuffer *fb, |
406 | struct drm_i915_gem_object *obj, | |
407 | int crtc_x, int crtc_y, | |
408 | unsigned int crtc_w, unsigned int crtc_h, | |
409 | uint32_t x, uint32_t y, | |
410 | uint32_t src_w, uint32_t src_h); | |
b39d53f6 VS |
411 | void (*disable_plane)(struct drm_plane *plane, |
412 | struct drm_crtc *crtc); | |
8ea30864 JB |
413 | int (*update_colorkey)(struct drm_plane *plane, |
414 | struct drm_intel_sprite_colorkey *key); | |
415 | void (*get_colorkey)(struct drm_plane *plane, | |
416 | struct drm_intel_sprite_colorkey *key); | |
b840d907 JB |
417 | }; |
418 | ||
b445e3b0 ED |
419 | struct intel_watermark_params { |
420 | unsigned long fifo_size; | |
421 | unsigned long max_wm; | |
422 | unsigned long default_wm; | |
423 | unsigned long guard_size; | |
424 | unsigned long cacheline_size; | |
425 | }; | |
426 | ||
427 | struct cxsr_latency { | |
428 | int is_desktop; | |
429 | int is_ddr3; | |
430 | unsigned long fsb_freq; | |
431 | unsigned long mem_freq; | |
432 | unsigned long display_sr; | |
433 | unsigned long display_hpll_disable; | |
434 | unsigned long cursor_sr; | |
435 | unsigned long cursor_hpll_disable; | |
436 | }; | |
437 | ||
79e53945 | 438 | #define to_intel_crtc(x) container_of(x, struct intel_crtc, base) |
5daa55eb | 439 | #define to_intel_connector(x) container_of(x, struct intel_connector, base) |
4ef69c7a | 440 | #define to_intel_encoder(x) container_of(x, struct intel_encoder, base) |
79e53945 | 441 | #define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base) |
b840d907 | 442 | #define to_intel_plane(x) container_of(x, struct intel_plane, base) |
79e53945 | 443 | |
f5bbfca3 | 444 | struct intel_hdmi { |
b242b7f7 | 445 | u32 hdmi_reg; |
f5bbfca3 | 446 | int ddc_bus; |
f5bbfca3 | 447 | uint32_t color_range; |
55bc60db | 448 | bool color_range_auto; |
f5bbfca3 ED |
449 | bool has_hdmi_sink; |
450 | bool has_audio; | |
451 | enum hdmi_force_audio force_audio; | |
abedc077 | 452 | bool rgb_quant_range_selectable; |
f5bbfca3 | 453 | void (*write_infoframe)(struct drm_encoder *encoder, |
178f736a DL |
454 | enum hdmi_infoframe_type type, |
455 | const uint8_t *frame, ssize_t len); | |
687f4d06 PZ |
456 | void (*set_infoframes)(struct drm_encoder *encoder, |
457 | struct drm_display_mode *adjusted_mode); | |
f5bbfca3 ED |
458 | }; |
459 | ||
b091cd92 | 460 | #define DP_MAX_DOWNSTREAM_PORTS 0x10 |
54d63ca6 SK |
461 | |
462 | struct intel_dp { | |
54d63ca6 | 463 | uint32_t output_reg; |
9ed35ab1 | 464 | uint32_t aux_ch_ctl_reg; |
54d63ca6 | 465 | uint32_t DP; |
54d63ca6 SK |
466 | bool has_audio; |
467 | enum hdmi_force_audio force_audio; | |
468 | uint32_t color_range; | |
55bc60db | 469 | bool color_range_auto; |
54d63ca6 SK |
470 | uint8_t link_bw; |
471 | uint8_t lane_count; | |
472 | uint8_t dpcd[DP_RECEIVER_CAP_SIZE]; | |
2293bb5c | 473 | uint8_t psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE]; |
b091cd92 | 474 | uint8_t downstream_ports[DP_MAX_DOWNSTREAM_PORTS]; |
54d63ca6 SK |
475 | struct i2c_adapter adapter; |
476 | struct i2c_algo_dp_aux_data algo; | |
54d63ca6 SK |
477 | uint8_t train_set[4]; |
478 | int panel_power_up_delay; | |
479 | int panel_power_down_delay; | |
480 | int panel_power_cycle_delay; | |
481 | int backlight_on_delay; | |
482 | int backlight_off_delay; | |
54d63ca6 SK |
483 | struct delayed_work panel_vdd_work; |
484 | bool want_panel_vdd; | |
2b28bb1b | 485 | bool psr_setup_done; |
dd06f90e | 486 | struct intel_connector *attached_connector; |
54d63ca6 SK |
487 | }; |
488 | ||
da63a9f2 PZ |
489 | struct intel_digital_port { |
490 | struct intel_encoder base; | |
174edf1f | 491 | enum port port; |
bcf53de4 | 492 | u32 saved_port_bits; |
da63a9f2 PZ |
493 | struct intel_dp dp; |
494 | struct intel_hdmi hdmi; | |
495 | }; | |
496 | ||
89b667f8 JB |
497 | static inline int |
498 | vlv_dport_to_channel(struct intel_digital_port *dport) | |
499 | { | |
500 | switch (dport->port) { | |
501 | case PORT_B: | |
502 | return 0; | |
503 | case PORT_C: | |
504 | return 1; | |
505 | default: | |
506 | BUG(); | |
507 | } | |
508 | } | |
509 | ||
f875c15a CW |
510 | static inline struct drm_crtc * |
511 | intel_get_crtc_for_pipe(struct drm_device *dev, int pipe) | |
512 | { | |
513 | struct drm_i915_private *dev_priv = dev->dev_private; | |
514 | return dev_priv->pipe_to_crtc_mapping[pipe]; | |
515 | } | |
516 | ||
417ae147 CW |
517 | static inline struct drm_crtc * |
518 | intel_get_crtc_for_plane(struct drm_device *dev, int plane) | |
519 | { | |
520 | struct drm_i915_private *dev_priv = dev->dev_private; | |
521 | return dev_priv->plane_to_crtc_mapping[plane]; | |
522 | } | |
523 | ||
4e5359cd SF |
524 | struct intel_unpin_work { |
525 | struct work_struct work; | |
b4a98e57 | 526 | struct drm_crtc *crtc; |
05394f39 CW |
527 | struct drm_i915_gem_object *old_fb_obj; |
528 | struct drm_i915_gem_object *pending_flip_obj; | |
4e5359cd | 529 | struct drm_pending_vblank_event *event; |
e7d841ca CW |
530 | atomic_t pending; |
531 | #define INTEL_FLIP_INACTIVE 0 | |
532 | #define INTEL_FLIP_PENDING 1 | |
533 | #define INTEL_FLIP_COMPLETE 2 | |
4e5359cd SF |
534 | bool enable_stall_check; |
535 | }; | |
536 | ||
d9e55608 | 537 | struct intel_set_config { |
1aa4b628 DV |
538 | struct drm_encoder **save_connector_encoders; |
539 | struct drm_crtc **save_encoder_crtcs; | |
5e2b584e DV |
540 | |
541 | bool fb_changed; | |
542 | bool mode_changed; | |
d9e55608 DV |
543 | }; |
544 | ||
5f1aae65 PZ |
545 | struct intel_load_detect_pipe { |
546 | struct drm_framebuffer *release_fb; | |
547 | bool load_detect_temp; | |
548 | int dpms_mode; | |
549 | }; | |
79e53945 | 550 | |
5f1aae65 PZ |
551 | static inline struct intel_encoder * |
552 | intel_attached_encoder(struct drm_connector *connector) | |
df0e9248 CW |
553 | { |
554 | return to_intel_connector(connector)->encoder; | |
555 | } | |
556 | ||
da63a9f2 PZ |
557 | static inline struct intel_digital_port * |
558 | enc_to_dig_port(struct drm_encoder *encoder) | |
559 | { | |
560 | return container_of(encoder, struct intel_digital_port, base.base); | |
9ff8c9ba ID |
561 | } |
562 | ||
563 | static inline struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder) | |
564 | { | |
565 | return &enc_to_dig_port(encoder)->dp; | |
da63a9f2 PZ |
566 | } |
567 | ||
568 | static inline struct intel_digital_port * | |
569 | dp_to_dig_port(struct intel_dp *intel_dp) | |
570 | { | |
571 | return container_of(intel_dp, struct intel_digital_port, dp); | |
572 | } | |
573 | ||
574 | static inline struct intel_digital_port * | |
575 | hdmi_to_dig_port(struct intel_hdmi *intel_hdmi) | |
576 | { | |
577 | return container_of(intel_hdmi, struct intel_digital_port, hdmi); | |
7739c33b PZ |
578 | } |
579 | ||
5f1aae65 PZ |
580 | |
581 | /* i915_irq.c */ | |
87440425 PZ |
582 | bool intel_set_cpu_fifo_underrun_reporting(struct drm_device *dev, |
583 | enum pipe pipe, bool enable); | |
584 | bool intel_set_pch_fifo_underrun_reporting(struct drm_device *dev, | |
585 | enum transcoder pch_transcoder, | |
586 | bool enable); | |
587 | void ilk_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask); | |
588 | void ilk_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask); | |
589 | void snb_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask); | |
590 | void snb_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask); | |
591 | void hsw_pc8_disable_interrupts(struct drm_device *dev); | |
592 | void hsw_pc8_restore_interrupts(struct drm_device *dev); | |
5f1aae65 PZ |
593 | |
594 | ||
595 | /* intel_crt.c */ | |
87440425 | 596 | void intel_crt_init(struct drm_device *dev); |
5f1aae65 PZ |
597 | |
598 | ||
599 | /* intel_ddi.c */ | |
87440425 PZ |
600 | void intel_prepare_ddi(struct drm_device *dev); |
601 | void hsw_fdi_link_train(struct drm_crtc *crtc); | |
602 | void intel_ddi_init(struct drm_device *dev, enum port port); | |
603 | enum port intel_ddi_get_encoder_port(struct intel_encoder *intel_encoder); | |
604 | bool intel_ddi_get_hw_state(struct intel_encoder *encoder, enum pipe *pipe); | |
605 | int intel_ddi_get_cdclk_freq(struct drm_i915_private *dev_priv); | |
606 | void intel_ddi_pll_init(struct drm_device *dev); | |
607 | void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc); | |
608 | void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv, | |
609 | enum transcoder cpu_transcoder); | |
610 | void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc); | |
611 | void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc); | |
612 | void intel_ddi_setup_hw_pll_state(struct drm_device *dev); | |
613 | bool intel_ddi_pll_mode_set(struct drm_crtc *crtc); | |
614 | void intel_ddi_put_crtc_pll(struct drm_crtc *crtc); | |
615 | void intel_ddi_set_pipe_settings(struct drm_crtc *crtc); | |
616 | void intel_ddi_prepare_link_retrain(struct drm_encoder *encoder); | |
617 | bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector); | |
618 | void intel_ddi_fdi_disable(struct drm_crtc *crtc); | |
619 | void intel_ddi_get_config(struct intel_encoder *encoder, | |
620 | struct intel_crtc_config *pipe_config); | |
5f1aae65 PZ |
621 | |
622 | ||
623 | /* intel_display.c */ | |
624 | int intel_pch_rawclk(struct drm_device *dev); | |
87440425 PZ |
625 | void intel_mark_busy(struct drm_device *dev); |
626 | void intel_mark_fb_busy(struct drm_i915_gem_object *obj, | |
627 | struct intel_ring_buffer *ring); | |
628 | void intel_mark_idle(struct drm_device *dev); | |
629 | void intel_crtc_restore_mode(struct drm_crtc *crtc); | |
630 | void intel_crtc_update_dpms(struct drm_crtc *crtc); | |
631 | void intel_encoder_destroy(struct drm_encoder *encoder); | |
632 | void intel_connector_dpms(struct drm_connector *, int mode); | |
633 | bool intel_connector_get_hw_state(struct intel_connector *connector); | |
634 | void intel_modeset_check_state(struct drm_device *dev); | |
b0ea7d37 DL |
635 | bool ibx_digital_port_connected(struct drm_i915_private *dev_priv, |
636 | struct intel_digital_port *port); | |
87440425 PZ |
637 | void intel_connector_attach_encoder(struct intel_connector *connector, |
638 | struct intel_encoder *encoder); | |
639 | struct drm_encoder *intel_best_encoder(struct drm_connector *connector); | |
640 | struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev, | |
641 | struct drm_crtc *crtc); | |
752aa88a | 642 | enum pipe intel_get_pipe_from_connector(struct intel_connector *connector); |
08d7b3d1 CW |
643 | int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data, |
644 | struct drm_file *file_priv); | |
87440425 PZ |
645 | enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv, |
646 | enum pipe pipe); | |
647 | void intel_wait_for_vblank(struct drm_device *dev, int pipe); | |
648 | void intel_wait_for_pipe_off(struct drm_device *dev, int pipe); | |
649 | int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp); | |
650 | void vlv_wait_port_ready(struct drm_i915_private *dev_priv, int port); | |
651 | bool intel_get_load_detect_pipe(struct drm_connector *connector, | |
652 | struct drm_display_mode *mode, | |
653 | struct intel_load_detect_pipe *old); | |
654 | void intel_release_load_detect_pipe(struct drm_connector *connector, | |
655 | struct intel_load_detect_pipe *old); | |
656 | int intel_pin_and_fence_fb_obj(struct drm_device *dev, | |
657 | struct drm_i915_gem_object *obj, | |
658 | struct intel_ring_buffer *pipelined); | |
659 | void intel_unpin_fb_obj(struct drm_i915_gem_object *obj); | |
660 | int intel_framebuffer_init(struct drm_device *dev, | |
661 | struct intel_framebuffer *ifb, | |
662 | struct drm_mode_fb_cmd2 *mode_cmd, | |
663 | struct drm_i915_gem_object *obj); | |
664 | void intel_framebuffer_fini(struct intel_framebuffer *fb); | |
665 | void intel_prepare_page_flip(struct drm_device *dev, int plane); | |
666 | void intel_finish_page_flip(struct drm_device *dev, int pipe); | |
667 | void intel_finish_page_flip_plane(struct drm_device *dev, int plane); | |
5f1aae65 | 668 | struct intel_shared_dpll *intel_crtc_to_shared_dpll(struct intel_crtc *crtc); |
55607e8a DV |
669 | void assert_shared_dpll(struct drm_i915_private *dev_priv, |
670 | struct intel_shared_dpll *pll, | |
671 | bool state); | |
672 | #define assert_shared_dpll_enabled(d, p) assert_shared_dpll(d, p, true) | |
673 | #define assert_shared_dpll_disabled(d, p) assert_shared_dpll(d, p, false) | |
674 | void assert_pll(struct drm_i915_private *dev_priv, | |
675 | enum pipe pipe, bool state); | |
676 | #define assert_pll_enabled(d, p) assert_pll(d, p, true) | |
677 | #define assert_pll_disabled(d, p) assert_pll(d, p, false) | |
678 | void assert_fdi_rx_pll(struct drm_i915_private *dev_priv, | |
679 | enum pipe pipe, bool state); | |
680 | #define assert_fdi_rx_pll_enabled(d, p) assert_fdi_rx_pll(d, p, true) | |
681 | #define assert_fdi_rx_pll_disabled(d, p) assert_fdi_rx_pll(d, p, false) | |
87440425 | 682 | void assert_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, bool state); |
b840d907 JB |
683 | #define assert_pipe_enabled(d, p) assert_pipe(d, p, true) |
684 | #define assert_pipe_disabled(d, p) assert_pipe(d, p, false) | |
87440425 PZ |
685 | void intel_write_eld(struct drm_encoder *encoder, |
686 | struct drm_display_mode *mode); | |
687 | unsigned long intel_gen4_compute_page_offset(int *x, int *y, | |
688 | unsigned int tiling_mode, | |
689 | unsigned int bpp, | |
690 | unsigned int pitch); | |
691 | void intel_display_handle_reset(struct drm_device *dev); | |
692 | void hsw_enable_pc8_work(struct work_struct *__work); | |
693 | void hsw_enable_package_c8(struct drm_i915_private *dev_priv); | |
694 | void hsw_disable_package_c8(struct drm_i915_private *dev_priv); | |
695 | void intel_dp_get_m_n(struct intel_crtc *crtc, | |
696 | struct intel_crtc_config *pipe_config); | |
697 | int intel_dotclock_calculate(int link_freq, const struct intel_link_m_n *m_n); | |
698 | void | |
5f1aae65 PZ |
699 | ironlake_check_encoder_dotclock(const struct intel_crtc_config *pipe_config, |
700 | int dotclock); | |
87440425 PZ |
701 | bool intel_crtc_active(struct drm_crtc *crtc); |
702 | void i915_disable_vga_mem(struct drm_device *dev); | |
20bc8673 VS |
703 | void hsw_enable_ips(struct intel_crtc *crtc); |
704 | void hsw_disable_ips(struct intel_crtc *crtc); | |
baa70707 | 705 | void intel_display_set_init_power(struct drm_device *dev, bool enable); |
5a35e99e | 706 | |
8ea30864 | 707 | |
5f1aae65 | 708 | /* intel_dp.c */ |
87440425 PZ |
709 | void intel_dp_init(struct drm_device *dev, int output_reg, enum port port); |
710 | bool intel_dp_init_connector(struct intel_digital_port *intel_dig_port, | |
711 | struct intel_connector *intel_connector); | |
87440425 PZ |
712 | void intel_dp_start_link_train(struct intel_dp *intel_dp); |
713 | void intel_dp_complete_link_train(struct intel_dp *intel_dp); | |
714 | void intel_dp_stop_link_train(struct intel_dp *intel_dp); | |
715 | void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode); | |
716 | void intel_dp_encoder_destroy(struct drm_encoder *encoder); | |
717 | void intel_dp_check_link_status(struct intel_dp *intel_dp); | |
718 | bool intel_dp_compute_config(struct intel_encoder *encoder, | |
719 | struct intel_crtc_config *pipe_config); | |
720 | bool intel_dpd_is_edp(struct drm_device *dev); | |
721 | void ironlake_edp_backlight_on(struct intel_dp *intel_dp); | |
722 | void ironlake_edp_backlight_off(struct intel_dp *intel_dp); | |
723 | void ironlake_edp_panel_on(struct intel_dp *intel_dp); | |
724 | void ironlake_edp_panel_off(struct intel_dp *intel_dp); | |
725 | void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp); | |
726 | void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync); | |
727 | void intel_edp_psr_enable(struct intel_dp *intel_dp); | |
728 | void intel_edp_psr_disable(struct intel_dp *intel_dp); | |
729 | void intel_edp_psr_update(struct drm_device *dev); | |
5f1aae65 PZ |
730 | |
731 | ||
732 | /* intel_dsi.c */ | |
87440425 | 733 | bool intel_dsi_init(struct drm_device *dev); |
5f1aae65 PZ |
734 | |
735 | ||
736 | /* intel_dvo.c */ | |
87440425 | 737 | void intel_dvo_init(struct drm_device *dev); |
5f1aae65 PZ |
738 | |
739 | ||
0632fef6 | 740 | /* legacy fbdev emulation in intel_fbdev.c */ |
4520f53a DV |
741 | #ifdef CONFIG_DRM_I915_FBDEV |
742 | extern int intel_fbdev_init(struct drm_device *dev); | |
743 | extern void intel_fbdev_initial_config(struct drm_device *dev); | |
744 | extern void intel_fbdev_fini(struct drm_device *dev); | |
745 | extern void intel_fbdev_set_suspend(struct drm_device *dev, int state); | |
0632fef6 DV |
746 | extern void intel_fbdev_output_poll_changed(struct drm_device *dev); |
747 | extern void intel_fbdev_restore_mode(struct drm_device *dev); | |
4520f53a DV |
748 | #else |
749 | static inline int intel_fbdev_init(struct drm_device *dev) | |
750 | { | |
751 | return 0; | |
752 | } | |
5f1aae65 | 753 | |
4520f53a DV |
754 | static inline void intel_fbdev_initial_config(struct drm_device *dev) |
755 | { | |
756 | } | |
757 | ||
758 | static inline void intel_fbdev_fini(struct drm_device *dev) | |
759 | { | |
760 | } | |
761 | ||
762 | static inline void intel_fbdev_set_suspend(struct drm_device *dev, int state) | |
763 | { | |
764 | } | |
765 | ||
0632fef6 | 766 | static inline void intel_fbdev_restore_mode(struct drm_device *dev) |
4520f53a DV |
767 | { |
768 | } | |
769 | #endif | |
5f1aae65 PZ |
770 | |
771 | /* intel_hdmi.c */ | |
87440425 PZ |
772 | void intel_hdmi_init(struct drm_device *dev, int hdmi_reg, enum port port); |
773 | void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port, | |
774 | struct intel_connector *intel_connector); | |
775 | struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder); | |
776 | bool intel_hdmi_compute_config(struct intel_encoder *encoder, | |
777 | struct intel_crtc_config *pipe_config); | |
5f1aae65 PZ |
778 | |
779 | ||
780 | /* intel_lvds.c */ | |
87440425 PZ |
781 | void intel_lvds_init(struct drm_device *dev); |
782 | bool intel_is_dual_link_lvds(struct drm_device *dev); | |
5f1aae65 PZ |
783 | |
784 | ||
785 | /* intel_modes.c */ | |
786 | int intel_connector_update_modes(struct drm_connector *connector, | |
87440425 | 787 | struct edid *edid); |
5f1aae65 | 788 | int intel_ddc_get_modes(struct drm_connector *c, struct i2c_adapter *adapter); |
87440425 PZ |
789 | void intel_attach_force_audio_property(struct drm_connector *connector); |
790 | void intel_attach_broadcast_rgb_property(struct drm_connector *connector); | |
5f1aae65 PZ |
791 | |
792 | ||
793 | /* intel_overlay.c */ | |
87440425 PZ |
794 | void intel_setup_overlay(struct drm_device *dev); |
795 | void intel_cleanup_overlay(struct drm_device *dev); | |
796 | int intel_overlay_switch_off(struct intel_overlay *overlay); | |
797 | int intel_overlay_put_image(struct drm_device *dev, void *data, | |
798 | struct drm_file *file_priv); | |
799 | int intel_overlay_attrs(struct drm_device *dev, void *data, | |
800 | struct drm_file *file_priv); | |
5f1aae65 PZ |
801 | |
802 | ||
803 | /* intel_panel.c */ | |
87440425 PZ |
804 | int intel_panel_init(struct intel_panel *panel, |
805 | struct drm_display_mode *fixed_mode); | |
806 | void intel_panel_fini(struct intel_panel *panel); | |
807 | void intel_fixed_panel_mode(const struct drm_display_mode *fixed_mode, | |
808 | struct drm_display_mode *adjusted_mode); | |
809 | void intel_pch_panel_fitting(struct intel_crtc *crtc, | |
810 | struct intel_crtc_config *pipe_config, | |
811 | int fitting_mode); | |
812 | void intel_gmch_panel_fitting(struct intel_crtc *crtc, | |
813 | struct intel_crtc_config *pipe_config, | |
814 | int fitting_mode); | |
752aa88a JB |
815 | void intel_panel_set_backlight(struct intel_connector *connector, u32 level, |
816 | u32 max); | |
87440425 | 817 | int intel_panel_setup_backlight(struct drm_connector *connector); |
752aa88a JB |
818 | void intel_panel_enable_backlight(struct intel_connector *connector); |
819 | void intel_panel_disable_backlight(struct intel_connector *connector); | |
db31af1d | 820 | void intel_panel_destroy_backlight(struct drm_connector *connector); |
7bd688cd | 821 | void intel_panel_init_backlight_funcs(struct drm_device *dev); |
87440425 | 822 | enum drm_connector_status intel_panel_detect(struct drm_device *dev); |
5f1aae65 PZ |
823 | |
824 | ||
825 | /* intel_pm.c */ | |
87440425 PZ |
826 | void intel_init_clock_gating(struct drm_device *dev); |
827 | void intel_suspend_hw(struct drm_device *dev); | |
828 | void intel_update_watermarks(struct drm_crtc *crtc); | |
829 | void intel_update_sprite_watermarks(struct drm_plane *plane, | |
830 | struct drm_crtc *crtc, | |
831 | uint32_t sprite_width, int pixel_size, | |
832 | bool enabled, bool scaled); | |
833 | void intel_init_pm(struct drm_device *dev); | |
834 | bool intel_fbc_enabled(struct drm_device *dev); | |
835 | void intel_update_fbc(struct drm_device *dev); | |
836 | void intel_gpu_ips_init(struct drm_i915_private *dev_priv); | |
837 | void intel_gpu_ips_teardown(void); | |
ddb642fb ID |
838 | int intel_power_domains_init(struct drm_device *dev); |
839 | void intel_power_domains_remove(struct drm_device *dev); | |
87440425 PZ |
840 | bool intel_display_power_enabled(struct drm_device *dev, |
841 | enum intel_display_power_domain domain); | |
842 | void intel_display_power_get(struct drm_device *dev, | |
843 | enum intel_display_power_domain domain); | |
844 | void intel_display_power_put(struct drm_device *dev, | |
845 | enum intel_display_power_domain domain); | |
ddb642fb | 846 | void intel_power_domains_init_hw(struct drm_device *dev); |
87440425 | 847 | void intel_set_power_well(struct drm_device *dev, bool enable); |
87440425 PZ |
848 | void intel_enable_gt_powersave(struct drm_device *dev); |
849 | void intel_disable_gt_powersave(struct drm_device *dev); | |
850 | void ironlake_teardown_rc6(struct drm_device *dev); | |
c67a470b | 851 | void gen6_update_ring_freq(struct drm_device *dev); |
076e29f2 DV |
852 | void gen6_rps_idle(struct drm_i915_private *dev_priv); |
853 | void gen6_rps_boost(struct drm_i915_private *dev_priv); | |
87440425 PZ |
854 | void intel_aux_display_runtime_get(struct drm_i915_private *dev_priv); |
855 | void intel_aux_display_runtime_put(struct drm_i915_private *dev_priv); | |
243e6a44 | 856 | void ilk_wm_get_hw_state(struct drm_device *dev); |
b3daeaef | 857 | |
72662e10 | 858 | |
5f1aae65 | 859 | /* intel_sdvo.c */ |
87440425 | 860 | bool intel_sdvo_init(struct drm_device *dev, uint32_t sdvo_reg, bool is_sdvob); |
96a02917 | 861 | |
2b28bb1b | 862 | |
5f1aae65 | 863 | /* intel_sprite.c */ |
87440425 | 864 | int intel_plane_init(struct drm_device *dev, enum pipe pipe, int plane); |
1dba99f4 | 865 | void intel_flush_primary_plane(struct drm_i915_private *dev_priv, |
87440425 PZ |
866 | enum plane plane); |
867 | void intel_plane_restore(struct drm_plane *plane); | |
868 | void intel_plane_disable(struct drm_plane *plane); | |
869 | int intel_sprite_set_colorkey(struct drm_device *dev, void *data, | |
870 | struct drm_file *file_priv); | |
871 | int intel_sprite_get_colorkey(struct drm_device *dev, void *data, | |
872 | struct drm_file *file_priv); | |
5f1aae65 PZ |
873 | |
874 | ||
875 | /* intel_tv.c */ | |
87440425 | 876 | void intel_tv_init(struct drm_device *dev); |
20ddf665 | 877 | |
79e53945 | 878 | #endif /* __INTEL_DRV_H__ */ |