]>
Commit | Line | Data |
---|---|---|
79e53945 JB |
1 | /* |
2 | * Copyright (c) 2006 Dave Airlie <airlied@linux.ie> | |
3 | * Copyright (c) 2007-2008 Intel Corporation | |
4 | * Jesse Barnes <jesse.barnes@intel.com> | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | |
7 | * copy of this software and associated documentation files (the "Software"), | |
8 | * to deal in the Software without restriction, including without limitation | |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
10 | * and/or sell copies of the Software, and to permit persons to whom the | |
11 | * Software is furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice (including the next | |
14 | * paragraph) shall be included in all copies or substantial portions of the | |
15 | * Software. | |
16 | * | |
17 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
18 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
19 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
20 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
21 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
22 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
23 | * IN THE SOFTWARE. | |
24 | */ | |
25 | #ifndef __INTEL_DRV_H__ | |
26 | #define __INTEL_DRV_H__ | |
27 | ||
28 | #include <linux/i2c.h> | |
178f736a | 29 | #include <linux/hdmi.h> |
760285e7 | 30 | #include <drm/i915_drm.h> |
80824003 | 31 | #include "i915_drv.h" |
760285e7 DH |
32 | #include <drm/drm_crtc.h> |
33 | #include <drm/drm_crtc_helper.h> | |
34 | #include <drm/drm_fb_helper.h> | |
612a9aab | 35 | #include <drm/drm_dp_helper.h> |
913d8d11 | 36 | |
1d5bfac9 DV |
37 | /** |
38 | * _wait_for - magic (register) wait macro | |
39 | * | |
40 | * Does the right thing for modeset paths when run under kdgb or similar atomic | |
41 | * contexts. Note that it's important that we check the condition again after | |
42 | * having timed out, since the timeout could be due to preemption or similar and | |
43 | * we've never had a chance to check the condition before the timeout. | |
44 | */ | |
481b6af3 | 45 | #define _wait_for(COND, MS, W) ({ \ |
1d5bfac9 | 46 | unsigned long timeout__ = jiffies + msecs_to_jiffies(MS) + 1; \ |
913d8d11 | 47 | int ret__ = 0; \ |
0206e353 | 48 | while (!(COND)) { \ |
913d8d11 | 49 | if (time_after(jiffies, timeout__)) { \ |
1d5bfac9 DV |
50 | if (!(COND)) \ |
51 | ret__ = -ETIMEDOUT; \ | |
913d8d11 CW |
52 | break; \ |
53 | } \ | |
0cc2764c BW |
54 | if (W && drm_can_sleep()) { \ |
55 | msleep(W); \ | |
56 | } else { \ | |
57 | cpu_relax(); \ | |
58 | } \ | |
913d8d11 CW |
59 | } \ |
60 | ret__; \ | |
61 | }) | |
62 | ||
481b6af3 CW |
63 | #define wait_for(COND, MS) _wait_for(COND, MS, 1) |
64 | #define wait_for_atomic(COND, MS) _wait_for(COND, MS, 0) | |
6effa33b DV |
65 | #define wait_for_atomic_us(COND, US) _wait_for((COND), \ |
66 | DIV_ROUND_UP((US), 1000), 0) | |
481b6af3 | 67 | |
021357ac CW |
68 | #define KHz(x) (1000*x) |
69 | #define MHz(x) KHz(1000*x) | |
70 | ||
79e53945 JB |
71 | /* |
72 | * Display related stuff | |
73 | */ | |
74 | ||
75 | /* store information about an Ixxx DVO */ | |
76 | /* The i830->i865 use multiple DVOs with multiple i2cs */ | |
77 | /* the i915, i945 have a single sDVO i2c bus - which is different */ | |
78 | #define MAX_OUTPUTS 6 | |
79 | /* maximum connectors per crtcs in the mode set */ | |
79e53945 JB |
80 | |
81 | #define INTEL_I2C_BUS_DVO 1 | |
82 | #define INTEL_I2C_BUS_SDVO 2 | |
83 | ||
84 | /* these are outputs from the chip - integrated only | |
85 | external chips are via DVO or SDVO output */ | |
86 | #define INTEL_OUTPUT_UNUSED 0 | |
87 | #define INTEL_OUTPUT_ANALOG 1 | |
88 | #define INTEL_OUTPUT_DVO 2 | |
89 | #define INTEL_OUTPUT_SDVO 3 | |
90 | #define INTEL_OUTPUT_LVDS 4 | |
91 | #define INTEL_OUTPUT_TVOUT 5 | |
7d57382e | 92 | #define INTEL_OUTPUT_HDMI 6 |
a4fc5ed6 | 93 | #define INTEL_OUTPUT_DISPLAYPORT 7 |
32f9d658 | 94 | #define INTEL_OUTPUT_EDP 8 |
72ffa333 JN |
95 | #define INTEL_OUTPUT_DSI 9 |
96 | #define INTEL_OUTPUT_UNKNOWN 10 | |
79e53945 JB |
97 | |
98 | #define INTEL_DVO_CHIP_NONE 0 | |
99 | #define INTEL_DVO_CHIP_LVDS 1 | |
100 | #define INTEL_DVO_CHIP_TMDS 2 | |
101 | #define INTEL_DVO_CHIP_TVOUT 4 | |
102 | ||
72ffa333 JN |
103 | #define INTEL_DSI_COMMAND_MODE 0 |
104 | #define INTEL_DSI_VIDEO_MODE 1 | |
105 | ||
79e53945 JB |
106 | struct intel_framebuffer { |
107 | struct drm_framebuffer base; | |
05394f39 | 108 | struct drm_i915_gem_object *obj; |
79e53945 JB |
109 | }; |
110 | ||
37811fcc CW |
111 | struct intel_fbdev { |
112 | struct drm_fb_helper helper; | |
113 | struct intel_framebuffer ifb; | |
114 | struct list_head fbdev_list; | |
115 | struct drm_display_mode *our_mode; | |
116 | }; | |
79e53945 | 117 | |
21d40d37 | 118 | struct intel_encoder { |
4ef69c7a | 119 | struct drm_encoder base; |
9a935856 DV |
120 | /* |
121 | * The new crtc this encoder will be driven from. Only differs from | |
122 | * base->crtc while a modeset is in progress. | |
123 | */ | |
124 | struct intel_crtc *new_crtc; | |
125 | ||
79e53945 | 126 | int type; |
66a9278e DV |
127 | /* |
128 | * Intel hw has only one MUX where encoders could be clone, hence a | |
129 | * simple flag is enough to compute the possible_clones mask. | |
130 | */ | |
131 | bool cloneable; | |
5ab432ef | 132 | bool connectors_active; |
21d40d37 | 133 | void (*hot_plug)(struct intel_encoder *); |
7ae89233 DV |
134 | bool (*compute_config)(struct intel_encoder *, |
135 | struct intel_crtc_config *); | |
dafd226c | 136 | void (*pre_pll_enable)(struct intel_encoder *); |
bf49ec8c | 137 | void (*pre_enable)(struct intel_encoder *); |
ef9c3aee | 138 | void (*enable)(struct intel_encoder *); |
6cc5f341 | 139 | void (*mode_set)(struct intel_encoder *intel_encoder); |
ef9c3aee | 140 | void (*disable)(struct intel_encoder *); |
bf49ec8c | 141 | void (*post_disable)(struct intel_encoder *); |
f0947c37 DV |
142 | /* Read out the current hw state of this connector, returning true if |
143 | * the encoder is active. If the encoder is enabled it also set the pipe | |
144 | * it is connected to in the pipe parameter. */ | |
145 | bool (*get_hw_state)(struct intel_encoder *, enum pipe *pipe); | |
045ac3b5 | 146 | /* Reconstructs the equivalent mode flags for the current hardware |
fdafa9e2 | 147 | * state. This must be called _after_ display->get_pipe_config has |
63000ef6 XZ |
148 | * pre-filled the pipe config. Note that intel_encoder->base.crtc must |
149 | * be set correctly before calling this function. */ | |
045ac3b5 JB |
150 | void (*get_config)(struct intel_encoder *, |
151 | struct intel_crtc_config *pipe_config); | |
f8aed700 | 152 | int crtc_mask; |
1d843f9d | 153 | enum hpd_pin hpd_pin; |
79e53945 JB |
154 | }; |
155 | ||
1d508706 | 156 | struct intel_panel { |
dd06f90e | 157 | struct drm_display_mode *fixed_mode; |
4d891523 | 158 | int fitting_mode; |
1d508706 JN |
159 | }; |
160 | ||
5daa55eb ZW |
161 | struct intel_connector { |
162 | struct drm_connector base; | |
9a935856 DV |
163 | /* |
164 | * The fixed encoder this connector is connected to. | |
165 | */ | |
df0e9248 | 166 | struct intel_encoder *encoder; |
9a935856 DV |
167 | |
168 | /* | |
169 | * The new encoder this connector will be driven. Only differs from | |
170 | * encoder while a modeset is in progress. | |
171 | */ | |
172 | struct intel_encoder *new_encoder; | |
173 | ||
f0947c37 DV |
174 | /* Reads out the current hw, returning true if the connector is enabled |
175 | * and active (i.e. dpms ON state). */ | |
176 | bool (*get_hw_state)(struct intel_connector *); | |
1d508706 JN |
177 | |
178 | /* Panel info for eDP and LVDS */ | |
179 | struct intel_panel panel; | |
9cd300e0 JN |
180 | |
181 | /* Cached EDID for eDP and LVDS. May hold ERR_PTR for invalid EDID. */ | |
182 | struct edid *edid; | |
821450c6 EE |
183 | |
184 | /* since POLL and HPD connectors may use the same HPD line keep the native | |
185 | state of connector->polled in case hotplug storm detection changes it */ | |
186 | u8 polled; | |
5daa55eb ZW |
187 | }; |
188 | ||
80ad9206 VS |
189 | typedef struct dpll { |
190 | /* given values */ | |
191 | int n; | |
192 | int m1, m2; | |
193 | int p1, p2; | |
194 | /* derived values */ | |
195 | int dot; | |
196 | int vco; | |
197 | int m; | |
198 | int p; | |
199 | } intel_clock_t; | |
200 | ||
b8cecdf5 | 201 | struct intel_crtc_config { |
bb760063 DV |
202 | /** |
203 | * quirks - bitfield with hw state readout quirks | |
204 | * | |
205 | * For various reasons the hw state readout code might not be able to | |
206 | * completely faithfully read out the current state. These cases are | |
207 | * tracked with quirk flags so that fastboot and state checker can act | |
208 | * accordingly. | |
209 | */ | |
210 | #define PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS (1<<0) /* unreliable sync mode.flags */ | |
211 | unsigned long quirks; | |
212 | ||
5113bc9b VS |
213 | /* User requested mode, only valid as a starting point to |
214 | * compute adjusted_mode, except in the case of (S)DVO where | |
215 | * it's also for the output timings of the (S)DVO chip. | |
216 | * adjusted_mode will then correspond to the S(DVO) chip's | |
217 | * preferred input timings. */ | |
b8cecdf5 | 218 | struct drm_display_mode requested_mode; |
3c52f4eb VS |
219 | /* Actual pipe timings ie. what we program into the pipe timing |
220 | * registers. adjusted_mode.clock is the pipe pixel clock. */ | |
b8cecdf5 | 221 | struct drm_display_mode adjusted_mode; |
37327abd VS |
222 | |
223 | /* Pipe source size (ie. panel fitter input size) | |
224 | * All planes will be positioned inside this space, | |
225 | * and get clipped at the edges. */ | |
226 | int pipe_src_w, pipe_src_h; | |
227 | ||
5bfe2ac0 DV |
228 | /* Whether to set up the PCH/FDI. Note that we never allow sharing |
229 | * between pch encoders and cpu encoders. */ | |
230 | bool has_pch_encoder; | |
50f3b016 | 231 | |
3b117c8f DV |
232 | /* CPU Transcoder for the pipe. Currently this can only differ from the |
233 | * pipe on Haswell (where we have a special eDP transcoder). */ | |
234 | enum transcoder cpu_transcoder; | |
235 | ||
50f3b016 DV |
236 | /* |
237 | * Use reduced/limited/broadcast rbg range, compressing from the full | |
238 | * range fed into the crtcs. | |
239 | */ | |
240 | bool limited_color_range; | |
241 | ||
03afc4a2 DV |
242 | /* DP has a bunch of special case unfortunately, so mark the pipe |
243 | * accordingly. */ | |
244 | bool has_dp_encoder; | |
d8b32247 DV |
245 | |
246 | /* | |
247 | * Enable dithering, used when the selected pipe bpp doesn't match the | |
248 | * plane bpp. | |
249 | */ | |
965e0c48 | 250 | bool dither; |
f47709a9 DV |
251 | |
252 | /* Controls for the clock computation, to override various stages. */ | |
253 | bool clock_set; | |
254 | ||
09ede541 DV |
255 | /* SDVO TV has a bunch of special case. To make multifunction encoders |
256 | * work correctly, we need to track this at runtime.*/ | |
257 | bool sdvo_tv_clock; | |
258 | ||
e29c22c0 DV |
259 | /* |
260 | * crtc bandwidth limit, don't increase pipe bpp or clock if not really | |
261 | * required. This is set in the 2nd loop of calling encoder's | |
262 | * ->compute_config if the first pick doesn't work out. | |
263 | */ | |
264 | bool bw_constrained; | |
265 | ||
f47709a9 DV |
266 | /* Settings for the intel dpll used on pretty much everything but |
267 | * haswell. */ | |
80ad9206 | 268 | struct dpll dpll; |
f47709a9 | 269 | |
a43f6e0f DV |
270 | /* Selected dpll when shared or DPLL_ID_PRIVATE. */ |
271 | enum intel_dpll_id shared_dpll; | |
272 | ||
66e985c0 DV |
273 | /* Actual register state of the dpll, for shared dpll cross-checking. */ |
274 | struct intel_dpll_hw_state dpll_hw_state; | |
275 | ||
965e0c48 | 276 | int pipe_bpp; |
6cf86a5e | 277 | struct intel_link_m_n dp_m_n; |
ff9a6750 DV |
278 | |
279 | /* | |
280 | * Frequence the dpll for the port should run at. Differs from the | |
3c52f4eb VS |
281 | * adjusted dotclock e.g. for DP or 12bpc hdmi mode. This is also |
282 | * already multiplied by pixel_multiplier. | |
df92b1e6 | 283 | */ |
ff9a6750 DV |
284 | int port_clock; |
285 | ||
6cc5f341 DV |
286 | /* Used by SDVO (and if we ever fix it, HDMI). */ |
287 | unsigned pixel_multiplier; | |
2dd24552 JB |
288 | |
289 | /* Panel fitter controls for gen2-gen4 + VLV */ | |
b074cec8 JB |
290 | struct { |
291 | u32 control; | |
292 | u32 pgm_ratios; | |
68fc8742 | 293 | u32 lvds_border_bits; |
b074cec8 JB |
294 | } gmch_pfit; |
295 | ||
296 | /* Panel fitter placement and size for Ironlake+ */ | |
297 | struct { | |
298 | u32 pos; | |
299 | u32 size; | |
fd4daa9c | 300 | bool enabled; |
b074cec8 | 301 | } pch_pfit; |
33d29b14 | 302 | |
ca3a0ff8 | 303 | /* FDI configuration, only valid if has_pch_encoder is set. */ |
33d29b14 | 304 | int fdi_lanes; |
ca3a0ff8 | 305 | struct intel_link_m_n fdi_m_n; |
42db64ef PZ |
306 | |
307 | bool ips_enabled; | |
cf532bb2 VS |
308 | |
309 | bool double_wide; | |
b8cecdf5 DV |
310 | }; |
311 | ||
79e53945 JB |
312 | struct intel_crtc { |
313 | struct drm_crtc base; | |
80824003 JB |
314 | enum pipe pipe; |
315 | enum plane plane; | |
79e53945 | 316 | u8 lut_r[256], lut_g[256], lut_b[256]; |
08a48469 DV |
317 | /* |
318 | * Whether the crtc and the connected output pipeline is active. Implies | |
319 | * that crtc->enabled is set, i.e. the current mode configuration has | |
320 | * some outputs connected to this crtc. | |
08a48469 DV |
321 | */ |
322 | bool active; | |
7b9f35a6 | 323 | bool eld_vld; |
93314b5b | 324 | bool primary_disabled; /* is the crtc obscured by a plane? */ |
652c393a | 325 | bool lowfreq_avail; |
02e792fb | 326 | struct intel_overlay *overlay; |
6b95a207 | 327 | struct intel_unpin_work *unpin_work; |
cda4b7d3 | 328 | |
b4a98e57 CW |
329 | atomic_t unpin_work_count; |
330 | ||
e506a0c6 DV |
331 | /* Display surface base address adjustement for pageflips. Note that on |
332 | * gen4+ this only adjusts up to a tile, offsets within a tile are | |
333 | * handled in the hw itself (with the TILEOFF register). */ | |
334 | unsigned long dspaddr_offset; | |
335 | ||
05394f39 | 336 | struct drm_i915_gem_object *cursor_bo; |
cda4b7d3 CW |
337 | uint32_t cursor_addr; |
338 | int16_t cursor_x, cursor_y; | |
339 | int16_t cursor_width, cursor_height; | |
6b383a7f | 340 | bool cursor_visible; |
4b645f14 | 341 | |
b8cecdf5 DV |
342 | struct intel_crtc_config config; |
343 | ||
6441ab5f | 344 | uint32_t ddi_pll_sel; |
10d83730 VS |
345 | |
346 | /* reset counter value when the last flip was submitted */ | |
347 | unsigned int reset_counter; | |
8664281b PZ |
348 | |
349 | /* Access to these should be protected by dev_priv->irq_lock. */ | |
350 | bool cpu_fifo_underrun_disabled; | |
351 | bool pch_fifo_underrun_disabled; | |
79e53945 JB |
352 | }; |
353 | ||
c35426d2 VS |
354 | struct intel_plane_wm_parameters { |
355 | uint32_t horiz_pixels; | |
356 | uint8_t bytes_per_pixel; | |
357 | bool enabled; | |
358 | bool scaled; | |
359 | }; | |
360 | ||
b840d907 JB |
361 | struct intel_plane { |
362 | struct drm_plane base; | |
7f1f3851 | 363 | int plane; |
b840d907 JB |
364 | enum pipe pipe; |
365 | struct drm_i915_gem_object *obj; | |
2d354c34 | 366 | bool can_scale; |
b840d907 JB |
367 | int max_downscale; |
368 | u32 lut_r[1024], lut_g[1024], lut_b[1024]; | |
5e1bac2f JB |
369 | int crtc_x, crtc_y; |
370 | unsigned int crtc_w, crtc_h; | |
371 | uint32_t src_x, src_y; | |
372 | uint32_t src_w, src_h; | |
526682e9 PZ |
373 | |
374 | /* Since we need to change the watermarks before/after | |
375 | * enabling/disabling the planes, we need to store the parameters here | |
376 | * as the other pieces of the struct may not reflect the values we want | |
377 | * for the watermark calculations. Currently only Haswell uses this. | |
378 | */ | |
c35426d2 | 379 | struct intel_plane_wm_parameters wm; |
526682e9 | 380 | |
b840d907 | 381 | void (*update_plane)(struct drm_plane *plane, |
b39d53f6 | 382 | struct drm_crtc *crtc, |
b840d907 JB |
383 | struct drm_framebuffer *fb, |
384 | struct drm_i915_gem_object *obj, | |
385 | int crtc_x, int crtc_y, | |
386 | unsigned int crtc_w, unsigned int crtc_h, | |
387 | uint32_t x, uint32_t y, | |
388 | uint32_t src_w, uint32_t src_h); | |
b39d53f6 VS |
389 | void (*disable_plane)(struct drm_plane *plane, |
390 | struct drm_crtc *crtc); | |
8ea30864 JB |
391 | int (*update_colorkey)(struct drm_plane *plane, |
392 | struct drm_intel_sprite_colorkey *key); | |
393 | void (*get_colorkey)(struct drm_plane *plane, | |
394 | struct drm_intel_sprite_colorkey *key); | |
b840d907 JB |
395 | }; |
396 | ||
b445e3b0 ED |
397 | struct intel_watermark_params { |
398 | unsigned long fifo_size; | |
399 | unsigned long max_wm; | |
400 | unsigned long default_wm; | |
401 | unsigned long guard_size; | |
402 | unsigned long cacheline_size; | |
403 | }; | |
404 | ||
405 | struct cxsr_latency { | |
406 | int is_desktop; | |
407 | int is_ddr3; | |
408 | unsigned long fsb_freq; | |
409 | unsigned long mem_freq; | |
410 | unsigned long display_sr; | |
411 | unsigned long display_hpll_disable; | |
412 | unsigned long cursor_sr; | |
413 | unsigned long cursor_hpll_disable; | |
414 | }; | |
415 | ||
79e53945 | 416 | #define to_intel_crtc(x) container_of(x, struct intel_crtc, base) |
5daa55eb | 417 | #define to_intel_connector(x) container_of(x, struct intel_connector, base) |
4ef69c7a | 418 | #define to_intel_encoder(x) container_of(x, struct intel_encoder, base) |
79e53945 | 419 | #define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base) |
b840d907 | 420 | #define to_intel_plane(x) container_of(x, struct intel_plane, base) |
79e53945 | 421 | |
f5bbfca3 | 422 | struct intel_hdmi { |
b242b7f7 | 423 | u32 hdmi_reg; |
f5bbfca3 | 424 | int ddc_bus; |
f5bbfca3 | 425 | uint32_t color_range; |
55bc60db | 426 | bool color_range_auto; |
f5bbfca3 ED |
427 | bool has_hdmi_sink; |
428 | bool has_audio; | |
429 | enum hdmi_force_audio force_audio; | |
abedc077 | 430 | bool rgb_quant_range_selectable; |
f5bbfca3 | 431 | void (*write_infoframe)(struct drm_encoder *encoder, |
178f736a DL |
432 | enum hdmi_infoframe_type type, |
433 | const uint8_t *frame, ssize_t len); | |
687f4d06 PZ |
434 | void (*set_infoframes)(struct drm_encoder *encoder, |
435 | struct drm_display_mode *adjusted_mode); | |
f5bbfca3 ED |
436 | }; |
437 | ||
b091cd92 | 438 | #define DP_MAX_DOWNSTREAM_PORTS 0x10 |
54d63ca6 SK |
439 | #define DP_LINK_CONFIGURATION_SIZE 9 |
440 | ||
441 | struct intel_dp { | |
54d63ca6 | 442 | uint32_t output_reg; |
9ed35ab1 | 443 | uint32_t aux_ch_ctl_reg; |
54d63ca6 SK |
444 | uint32_t DP; |
445 | uint8_t link_configuration[DP_LINK_CONFIGURATION_SIZE]; | |
446 | bool has_audio; | |
447 | enum hdmi_force_audio force_audio; | |
448 | uint32_t color_range; | |
55bc60db | 449 | bool color_range_auto; |
54d63ca6 SK |
450 | uint8_t link_bw; |
451 | uint8_t lane_count; | |
452 | uint8_t dpcd[DP_RECEIVER_CAP_SIZE]; | |
2293bb5c | 453 | uint8_t psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE]; |
b091cd92 | 454 | uint8_t downstream_ports[DP_MAX_DOWNSTREAM_PORTS]; |
54d63ca6 SK |
455 | struct i2c_adapter adapter; |
456 | struct i2c_algo_dp_aux_data algo; | |
54d63ca6 SK |
457 | uint8_t train_set[4]; |
458 | int panel_power_up_delay; | |
459 | int panel_power_down_delay; | |
460 | int panel_power_cycle_delay; | |
461 | int backlight_on_delay; | |
462 | int backlight_off_delay; | |
54d63ca6 SK |
463 | struct delayed_work panel_vdd_work; |
464 | bool want_panel_vdd; | |
2b28bb1b | 465 | bool psr_setup_done; |
dd06f90e | 466 | struct intel_connector *attached_connector; |
54d63ca6 SK |
467 | }; |
468 | ||
da63a9f2 PZ |
469 | struct intel_digital_port { |
470 | struct intel_encoder base; | |
174edf1f | 471 | enum port port; |
bcf53de4 | 472 | u32 saved_port_bits; |
da63a9f2 PZ |
473 | struct intel_dp dp; |
474 | struct intel_hdmi hdmi; | |
475 | }; | |
476 | ||
89b667f8 JB |
477 | static inline int |
478 | vlv_dport_to_channel(struct intel_digital_port *dport) | |
479 | { | |
480 | switch (dport->port) { | |
481 | case PORT_B: | |
482 | return 0; | |
483 | case PORT_C: | |
484 | return 1; | |
485 | default: | |
486 | BUG(); | |
487 | } | |
488 | } | |
489 | ||
f875c15a CW |
490 | static inline struct drm_crtc * |
491 | intel_get_crtc_for_pipe(struct drm_device *dev, int pipe) | |
492 | { | |
493 | struct drm_i915_private *dev_priv = dev->dev_private; | |
494 | return dev_priv->pipe_to_crtc_mapping[pipe]; | |
495 | } | |
496 | ||
417ae147 CW |
497 | static inline struct drm_crtc * |
498 | intel_get_crtc_for_plane(struct drm_device *dev, int plane) | |
499 | { | |
500 | struct drm_i915_private *dev_priv = dev->dev_private; | |
501 | return dev_priv->plane_to_crtc_mapping[plane]; | |
502 | } | |
503 | ||
4e5359cd SF |
504 | struct intel_unpin_work { |
505 | struct work_struct work; | |
b4a98e57 | 506 | struct drm_crtc *crtc; |
05394f39 CW |
507 | struct drm_i915_gem_object *old_fb_obj; |
508 | struct drm_i915_gem_object *pending_flip_obj; | |
4e5359cd | 509 | struct drm_pending_vblank_event *event; |
e7d841ca CW |
510 | atomic_t pending; |
511 | #define INTEL_FLIP_INACTIVE 0 | |
512 | #define INTEL_FLIP_PENDING 1 | |
513 | #define INTEL_FLIP_COMPLETE 2 | |
4e5359cd SF |
514 | bool enable_stall_check; |
515 | }; | |
516 | ||
d2acd215 DV |
517 | int intel_pch_rawclk(struct drm_device *dev); |
518 | ||
4eab8136 JN |
519 | int intel_connector_update_modes(struct drm_connector *connector, |
520 | struct edid *edid); | |
335af9a2 | 521 | int intel_ddc_get_modes(struct drm_connector *c, struct i2c_adapter *adapter); |
f0217c42 | 522 | |
3f43c48d | 523 | extern void intel_attach_force_audio_property(struct drm_connector *connector); |
e953fd7b CW |
524 | extern void intel_attach_broadcast_rgb_property(struct drm_connector *connector); |
525 | ||
8664281b | 526 | extern bool intel_pipe_has_type(struct drm_crtc *crtc, int type); |
79e53945 | 527 | extern void intel_crt_init(struct drm_device *dev); |
08d644ad | 528 | extern void intel_hdmi_init(struct drm_device *dev, |
b242b7f7 | 529 | int hdmi_reg, enum port port); |
00c09d70 PZ |
530 | extern void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port, |
531 | struct intel_connector *intel_connector); | |
f5bbfca3 | 532 | extern struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder); |
5bfe2ac0 DV |
533 | extern bool intel_hdmi_compute_config(struct intel_encoder *encoder, |
534 | struct intel_crtc_config *pipe_config); | |
eef4eacb DV |
535 | extern bool intel_sdvo_init(struct drm_device *dev, uint32_t sdvo_reg, |
536 | bool is_sdvob); | |
79e53945 JB |
537 | extern void intel_dvo_init(struct drm_device *dev); |
538 | extern void intel_tv_init(struct drm_device *dev); | |
f047e395 | 539 | extern void intel_mark_busy(struct drm_device *dev); |
c65355bb CW |
540 | extern void intel_mark_fb_busy(struct drm_i915_gem_object *obj, |
541 | struct intel_ring_buffer *ring); | |
725a5b54 | 542 | extern void intel_mark_idle(struct drm_device *dev); |
c9093354 | 543 | extern void intel_lvds_init(struct drm_device *dev); |
4e646495 | 544 | extern bool intel_dsi_init(struct drm_device *dev); |
1974cad0 | 545 | extern bool intel_is_dual_link_lvds(struct drm_device *dev); |
ab9d7c30 PZ |
546 | extern void intel_dp_init(struct drm_device *dev, int output_reg, |
547 | enum port port); | |
16c25533 | 548 | extern bool intel_dp_init_connector(struct intel_digital_port *intel_dig_port, |
00c09d70 | 549 | struct intel_connector *intel_connector); |
247d89f6 | 550 | extern void intel_dp_init_link_config(struct intel_dp *intel_dp); |
c19b0669 PZ |
551 | extern void intel_dp_start_link_train(struct intel_dp *intel_dp); |
552 | extern void intel_dp_complete_link_train(struct intel_dp *intel_dp); | |
3ab9c637 | 553 | extern void intel_dp_stop_link_train(struct intel_dp *intel_dp); |
c19b0669 | 554 | extern void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode); |
00c09d70 PZ |
555 | extern void intel_dp_encoder_destroy(struct drm_encoder *encoder); |
556 | extern void intel_dp_check_link_status(struct intel_dp *intel_dp); | |
5bfe2ac0 DV |
557 | extern bool intel_dp_compute_config(struct intel_encoder *encoder, |
558 | struct intel_crtc_config *pipe_config); | |
cb0953d7 | 559 | extern bool intel_dpd_is_edp(struct drm_device *dev); |
d6c50ff8 PZ |
560 | extern void ironlake_edp_backlight_on(struct intel_dp *intel_dp); |
561 | extern void ironlake_edp_backlight_off(struct intel_dp *intel_dp); | |
82a4d9c0 PZ |
562 | extern void ironlake_edp_panel_on(struct intel_dp *intel_dp); |
563 | extern void ironlake_edp_panel_off(struct intel_dp *intel_dp); | |
564 | extern void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp); | |
565 | extern void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync); | |
7f1f3851 | 566 | extern int intel_plane_init(struct drm_device *dev, enum pipe pipe, int plane); |
6f1d69b0 ED |
567 | extern void intel_flush_display_plane(struct drm_i915_private *dev_priv, |
568 | enum plane plane); | |
32f9d658 | 569 | |
a9573556 | 570 | /* intel_panel.c */ |
dd06f90e JN |
571 | extern int intel_panel_init(struct intel_panel *panel, |
572 | struct drm_display_mode *fixed_mode); | |
1d508706 JN |
573 | extern void intel_panel_fini(struct intel_panel *panel); |
574 | ||
4c6df4b4 | 575 | extern void intel_fixed_panel_mode(const struct drm_display_mode *fixed_mode, |
1d8e1c75 | 576 | struct drm_display_mode *adjusted_mode); |
b074cec8 JB |
577 | extern void intel_pch_panel_fitting(struct intel_crtc *crtc, |
578 | struct intel_crtc_config *pipe_config, | |
579 | int fitting_mode); | |
2dd24552 JB |
580 | extern void intel_gmch_panel_fitting(struct intel_crtc *crtc, |
581 | struct intel_crtc_config *pipe_config, | |
582 | int fitting_mode); | |
d6540632 JN |
583 | extern void intel_panel_set_backlight(struct drm_device *dev, |
584 | u32 level, u32 max); | |
0657b6b1 | 585 | extern int intel_panel_setup_backlight(struct drm_connector *connector); |
24ded204 DV |
586 | extern void intel_panel_enable_backlight(struct drm_device *dev, |
587 | enum pipe pipe); | |
47356eb6 | 588 | extern void intel_panel_disable_backlight(struct drm_device *dev); |
aaa6fd2a | 589 | extern void intel_panel_destroy_backlight(struct drm_device *dev); |
fe16d949 | 590 | extern enum drm_connector_status intel_panel_detect(struct drm_device *dev); |
1d8e1c75 | 591 | |
d9e55608 | 592 | struct intel_set_config { |
1aa4b628 DV |
593 | struct drm_encoder **save_connector_encoders; |
594 | struct drm_crtc **save_encoder_crtcs; | |
5e2b584e DV |
595 | |
596 | bool fb_changed; | |
597 | bool mode_changed; | |
d9e55608 DV |
598 | }; |
599 | ||
c0c36b94 | 600 | extern void intel_crtc_restore_mode(struct drm_crtc *crtc); |
79e53945 | 601 | extern void intel_crtc_load_lut(struct drm_crtc *crtc); |
b2cabb0e | 602 | extern void intel_crtc_update_dpms(struct drm_crtc *crtc); |
ea5b213a | 603 | extern void intel_encoder_destroy(struct drm_encoder *encoder); |
5ab432ef | 604 | extern void intel_connector_dpms(struct drm_connector *, int mode); |
f0947c37 | 605 | extern bool intel_connector_get_hw_state(struct intel_connector *connector); |
b980514c | 606 | extern void intel_modeset_check_state(struct drm_device *dev); |
5e1bac2f | 607 | extern void intel_plane_restore(struct drm_plane *plane); |
bb53d4ae | 608 | extern void intel_plane_disable(struct drm_plane *plane); |
b980514c | 609 | |
79e53945 | 610 | |
df0e9248 CW |
611 | static inline struct intel_encoder *intel_attached_encoder(struct drm_connector *connector) |
612 | { | |
613 | return to_intel_connector(connector)->encoder; | |
614 | } | |
615 | ||
da63a9f2 PZ |
616 | static inline struct intel_digital_port * |
617 | enc_to_dig_port(struct drm_encoder *encoder) | |
618 | { | |
619 | return container_of(encoder, struct intel_digital_port, base.base); | |
9ff8c9ba ID |
620 | } |
621 | ||
622 | static inline struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder) | |
623 | { | |
624 | return &enc_to_dig_port(encoder)->dp; | |
da63a9f2 PZ |
625 | } |
626 | ||
627 | static inline struct intel_digital_port * | |
628 | dp_to_dig_port(struct intel_dp *intel_dp) | |
629 | { | |
630 | return container_of(intel_dp, struct intel_digital_port, dp); | |
631 | } | |
632 | ||
633 | static inline struct intel_digital_port * | |
634 | hdmi_to_dig_port(struct intel_hdmi *intel_hdmi) | |
635 | { | |
636 | return container_of(intel_hdmi, struct intel_digital_port, hdmi); | |
7739c33b PZ |
637 | } |
638 | ||
b0ea7d37 DL |
639 | bool ibx_digital_port_connected(struct drm_i915_private *dev_priv, |
640 | struct intel_digital_port *port); | |
641 | ||
df0e9248 CW |
642 | extern void intel_connector_attach_encoder(struct intel_connector *connector, |
643 | struct intel_encoder *encoder); | |
644 | extern struct drm_encoder *intel_best_encoder(struct drm_connector *connector); | |
79e53945 JB |
645 | |
646 | extern struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev, | |
647 | struct drm_crtc *crtc); | |
08d7b3d1 CW |
648 | int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data, |
649 | struct drm_file *file_priv); | |
a5c961d1 PZ |
650 | extern enum transcoder |
651 | intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv, | |
652 | enum pipe pipe); | |
9d0498a2 | 653 | extern void intel_wait_for_vblank(struct drm_device *dev, int pipe); |
58e10eb9 | 654 | extern void intel_wait_for_pipe_off(struct drm_device *dev, int pipe); |
d4b1931c | 655 | extern int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp); |
89b667f8 | 656 | extern void vlv_wait_port_ready(struct drm_i915_private *dev_priv, int port); |
8261b191 CW |
657 | |
658 | struct intel_load_detect_pipe { | |
d2dff872 | 659 | struct drm_framebuffer *release_fb; |
8261b191 CW |
660 | bool load_detect_temp; |
661 | int dpms_mode; | |
662 | }; | |
d2434ab7 | 663 | extern bool intel_get_load_detect_pipe(struct drm_connector *connector, |
7173188d | 664 | struct drm_display_mode *mode, |
8261b191 | 665 | struct intel_load_detect_pipe *old); |
d2434ab7 | 666 | extern void intel_release_load_detect_pipe(struct drm_connector *connector, |
8261b191 | 667 | struct intel_load_detect_pipe *old); |
79e53945 | 668 | |
79e53945 JB |
669 | extern void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green, |
670 | u16 blue, int regno); | |
b8c00ac5 DA |
671 | extern void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green, |
672 | u16 *blue, int regno); | |
79e53945 | 673 | |
127bd2ac | 674 | extern int intel_pin_and_fence_fb_obj(struct drm_device *dev, |
05394f39 | 675 | struct drm_i915_gem_object *obj, |
919926ae | 676 | struct intel_ring_buffer *pipelined); |
1690e1eb | 677 | extern void intel_unpin_fb_obj(struct drm_i915_gem_object *obj); |
127bd2ac | 678 | |
38651674 DA |
679 | extern int intel_framebuffer_init(struct drm_device *dev, |
680 | struct intel_framebuffer *ifb, | |
308e5bcb | 681 | struct drm_mode_fb_cmd2 *mode_cmd, |
05394f39 | 682 | struct drm_i915_gem_object *obj); |
ddfe1567 | 683 | extern void intel_framebuffer_fini(struct intel_framebuffer *fb); |
38651674 | 684 | extern int intel_fbdev_init(struct drm_device *dev); |
20afbda2 | 685 | extern void intel_fbdev_initial_config(struct drm_device *dev); |
38651674 | 686 | extern void intel_fbdev_fini(struct drm_device *dev); |
3fa016a0 | 687 | extern void intel_fbdev_set_suspend(struct drm_device *dev, int state); |
6b95a207 KH |
688 | extern void intel_prepare_page_flip(struct drm_device *dev, int plane); |
689 | extern void intel_finish_page_flip(struct drm_device *dev, int pipe); | |
1afe3e9d | 690 | extern void intel_finish_page_flip_plane(struct drm_device *dev, int plane); |
6b95a207 | 691 | |
02e792fb DV |
692 | extern void intel_setup_overlay(struct drm_device *dev); |
693 | extern void intel_cleanup_overlay(struct drm_device *dev); | |
ce453d81 | 694 | extern int intel_overlay_switch_off(struct intel_overlay *overlay); |
02e792fb DV |
695 | extern int intel_overlay_put_image(struct drm_device *dev, void *data, |
696 | struct drm_file *file_priv); | |
697 | extern int intel_overlay_attrs(struct drm_device *dev, void *data, | |
698 | struct drm_file *file_priv); | |
4abe3520 | 699 | |
eb1f8e4f | 700 | extern void intel_fb_output_poll_changed(struct drm_device *dev); |
e8e7a2b8 | 701 | extern void intel_fb_restore_mode(struct drm_device *dev); |
645c62a5 | 702 | |
55607e8a DV |
703 | struct intel_shared_dpll * |
704 | intel_crtc_to_shared_dpll(struct intel_crtc *crtc); | |
705 | ||
706 | void assert_shared_dpll(struct drm_i915_private *dev_priv, | |
707 | struct intel_shared_dpll *pll, | |
708 | bool state); | |
709 | #define assert_shared_dpll_enabled(d, p) assert_shared_dpll(d, p, true) | |
710 | #define assert_shared_dpll_disabled(d, p) assert_shared_dpll(d, p, false) | |
711 | void assert_pll(struct drm_i915_private *dev_priv, | |
712 | enum pipe pipe, bool state); | |
713 | #define assert_pll_enabled(d, p) assert_pll(d, p, true) | |
714 | #define assert_pll_disabled(d, p) assert_pll(d, p, false) | |
715 | void assert_fdi_rx_pll(struct drm_i915_private *dev_priv, | |
716 | enum pipe pipe, bool state); | |
717 | #define assert_fdi_rx_pll_enabled(d, p) assert_fdi_rx_pll(d, p, true) | |
718 | #define assert_fdi_rx_pll_disabled(d, p) assert_fdi_rx_pll(d, p, false) | |
b840d907 JB |
719 | extern void assert_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, |
720 | bool state); | |
721 | #define assert_pipe_enabled(d, p) assert_pipe(d, p, true) | |
722 | #define assert_pipe_disabled(d, p) assert_pipe(d, p, false) | |
723 | ||
645c62a5 | 724 | extern void intel_init_clock_gating(struct drm_device *dev); |
7d708ee4 | 725 | extern void intel_suspend_hw(struct drm_device *dev); |
e0dac65e WF |
726 | extern void intel_write_eld(struct drm_encoder *encoder, |
727 | struct drm_display_mode *mode); | |
45244b87 | 728 | extern void intel_prepare_ddi(struct drm_device *dev); |
c82e4d26 | 729 | extern void hsw_fdi_link_train(struct drm_crtc *crtc); |
0e72a5b5 | 730 | extern void intel_ddi_init(struct drm_device *dev, enum port port); |
20f4dbe4 | 731 | extern enum port intel_ddi_get_encoder_port(struct intel_encoder *intel_encoder); |
d4270e57 | 732 | |
b840d907 | 733 | /* For use by IVB LP watermark workaround in intel_sprite.c */ |
46ba614c | 734 | extern void intel_update_watermarks(struct drm_crtc *crtc); |
adf3d35e VS |
735 | extern void intel_update_sprite_watermarks(struct drm_plane *plane, |
736 | struct drm_crtc *crtc, | |
bdd57d03 VS |
737 | uint32_t sprite_width, int pixel_size, |
738 | bool enabled, bool scaled); | |
8ea30864 | 739 | |
bc752862 CW |
740 | extern unsigned long intel_gen4_compute_page_offset(int *x, int *y, |
741 | unsigned int tiling_mode, | |
742 | unsigned int bpp, | |
743 | unsigned int pitch); | |
5a35e99e | 744 | |
8ea30864 JB |
745 | extern int intel_sprite_set_colorkey(struct drm_device *dev, void *data, |
746 | struct drm_file *file_priv); | |
747 | extern int intel_sprite_get_colorkey(struct drm_device *dev, void *data, | |
748 | struct drm_file *file_priv); | |
749 | ||
85208be0 | 750 | /* Power-related functions, located in intel_pm.c */ |
1fa61106 | 751 | extern void intel_init_pm(struct drm_device *dev); |
85208be0 | 752 | /* FBC */ |
85208be0 | 753 | extern bool intel_fbc_enabled(struct drm_device *dev); |
85208be0 | 754 | extern void intel_update_fbc(struct drm_device *dev); |
eb48eb00 DV |
755 | /* IPS */ |
756 | extern void intel_gpu_ips_init(struct drm_i915_private *dev_priv); | |
757 | extern void intel_gpu_ips_teardown(void); | |
85208be0 | 758 | |
a38911a3 WX |
759 | /* Power well */ |
760 | extern int i915_init_power_well(struct drm_device *dev); | |
761 | extern void i915_remove_power_well(struct drm_device *dev); | |
762 | ||
b97186f0 PZ |
763 | extern bool intel_display_power_enabled(struct drm_device *dev, |
764 | enum intel_display_power_domain domain); | |
6765625e VS |
765 | extern void intel_display_power_get(struct drm_device *dev, |
766 | enum intel_display_power_domain domain); | |
767 | extern void intel_display_power_put(struct drm_device *dev, | |
768 | enum intel_display_power_domain domain); | |
fa42e23c | 769 | extern void intel_init_power_well(struct drm_device *dev); |
cb10799c | 770 | extern void intel_set_power_well(struct drm_device *dev, bool enable); |
9cdb826c | 771 | extern void intel_resume_power_well(struct drm_device *dev); |
8090c6b9 DV |
772 | extern void intel_enable_gt_powersave(struct drm_device *dev); |
773 | extern void intel_disable_gt_powersave(struct drm_device *dev); | |
930ebb46 | 774 | extern void ironlake_teardown_rc6(struct drm_device *dev); |
c67a470b | 775 | void gen6_update_ring_freq(struct drm_device *dev); |
b3daeaef | 776 | |
85234cdc DV |
777 | extern bool intel_ddi_get_hw_state(struct intel_encoder *encoder, |
778 | enum pipe *pipe); | |
b8fc2f6a | 779 | extern int intel_ddi_get_cdclk_freq(struct drm_i915_private *dev_priv); |
79f689aa | 780 | extern void intel_ddi_pll_init(struct drm_device *dev); |
8228c251 | 781 | extern void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc); |
ad80a810 PZ |
782 | extern void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv, |
783 | enum transcoder cpu_transcoder); | |
fc914639 PZ |
784 | extern void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc); |
785 | extern void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc); | |
6441ab5f | 786 | extern void intel_ddi_setup_hw_pll_state(struct drm_device *dev); |
ff9a6750 | 787 | extern bool intel_ddi_pll_mode_set(struct drm_crtc *crtc); |
6441ab5f | 788 | extern void intel_ddi_put_crtc_pll(struct drm_crtc *crtc); |
dae84799 | 789 | extern void intel_ddi_set_pipe_settings(struct drm_crtc *crtc); |
c19b0669 | 790 | extern void intel_ddi_prepare_link_retrain(struct drm_encoder *encoder); |
1ad960f2 PZ |
791 | extern bool |
792 | intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector); | |
793 | extern void intel_ddi_fdi_disable(struct drm_crtc *crtc); | |
72662e10 | 794 | |
96a02917 | 795 | extern void intel_display_handle_reset(struct drm_device *dev); |
8664281b PZ |
796 | extern bool intel_set_cpu_fifo_underrun_reporting(struct drm_device *dev, |
797 | enum pipe pipe, | |
798 | bool enable); | |
799 | extern bool intel_set_pch_fifo_underrun_reporting(struct drm_device *dev, | |
800 | enum transcoder pch_transcoder, | |
801 | bool enable); | |
96a02917 | 802 | |
2b28bb1b RV |
803 | extern void intel_edp_psr_enable(struct intel_dp *intel_dp); |
804 | extern void intel_edp_psr_disable(struct intel_dp *intel_dp); | |
3d739d92 | 805 | extern void intel_edp_psr_update(struct drm_device *dev); |
be256dc7 PZ |
806 | extern void hsw_disable_lcpll(struct drm_i915_private *dev_priv, |
807 | bool switch_to_fclk, bool allow_power_down); | |
808 | extern void hsw_restore_lcpll(struct drm_i915_private *dev_priv); | |
43eaea13 PZ |
809 | extern void ilk_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask); |
810 | extern void ilk_disable_gt_irq(struct drm_i915_private *dev_priv, | |
811 | uint32_t mask); | |
edbfdb45 PZ |
812 | extern void snb_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask); |
813 | extern void snb_disable_pm_irq(struct drm_i915_private *dev_priv, | |
814 | uint32_t mask); | |
c67a470b PZ |
815 | extern void hsw_enable_pc8_work(struct work_struct *__work); |
816 | extern void hsw_enable_package_c8(struct drm_i915_private *dev_priv); | |
817 | extern void hsw_disable_package_c8(struct drm_i915_private *dev_priv); | |
818 | extern void hsw_pc8_disable_interrupts(struct drm_device *dev); | |
819 | extern void hsw_pc8_restore_interrupts(struct drm_device *dev); | |
820 | extern void intel_aux_display_runtime_get(struct drm_i915_private *dev_priv); | |
821 | extern void intel_aux_display_runtime_put(struct drm_i915_private *dev_priv); | |
eb14cb74 VS |
822 | extern void intel_dp_get_m_n(struct intel_crtc *crtc, |
823 | struct intel_crtc_config *pipe_config); | |
6878da05 VS |
824 | extern int intel_dotclock_calculate(int link_freq, |
825 | const struct intel_link_m_n *m_n); | |
18442d08 VS |
826 | extern void ironlake_check_encoder_dotclock(const struct intel_crtc_config *pipe_config, |
827 | int dotclock); | |
2b28bb1b | 828 | |
20ddf665 | 829 | extern bool intel_crtc_active(struct drm_crtc *crtc); |
6e1b4fda | 830 | extern void i915_disable_vga_mem(struct drm_device *dev); |
6801c18c VS |
831 | extern void intel_ddi_get_config(struct intel_encoder *encoder, |
832 | struct intel_crtc_config *pipe_config); | |
20ddf665 | 833 | |
79e53945 | 834 | #endif /* __INTEL_DRV_H__ */ |