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79e53945 JB |
1 | /* |
2 | * Copyright (c) 2006 Dave Airlie <airlied@linux.ie> | |
3 | * Copyright (c) 2007-2008 Intel Corporation | |
4 | * Jesse Barnes <jesse.barnes@intel.com> | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | |
7 | * copy of this software and associated documentation files (the "Software"), | |
8 | * to deal in the Software without restriction, including without limitation | |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
10 | * and/or sell copies of the Software, and to permit persons to whom the | |
11 | * Software is furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice (including the next | |
14 | * paragraph) shall be included in all copies or substantial portions of the | |
15 | * Software. | |
16 | * | |
17 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
18 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
19 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
20 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
21 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
22 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
23 | * IN THE SOFTWARE. | |
24 | */ | |
25 | #ifndef __INTEL_DRV_H__ | |
26 | #define __INTEL_DRV_H__ | |
27 | ||
28 | #include <linux/i2c.h> | |
760285e7 | 29 | #include <drm/i915_drm.h> |
80824003 | 30 | #include "i915_drv.h" |
760285e7 DH |
31 | #include <drm/drm_crtc.h> |
32 | #include <drm/drm_crtc_helper.h> | |
33 | #include <drm/drm_fb_helper.h> | |
612a9aab | 34 | #include <drm/drm_dp_helper.h> |
913d8d11 | 35 | |
1d5bfac9 DV |
36 | /** |
37 | * _wait_for - magic (register) wait macro | |
38 | * | |
39 | * Does the right thing for modeset paths when run under kdgb or similar atomic | |
40 | * contexts. Note that it's important that we check the condition again after | |
41 | * having timed out, since the timeout could be due to preemption or similar and | |
42 | * we've never had a chance to check the condition before the timeout. | |
43 | */ | |
481b6af3 | 44 | #define _wait_for(COND, MS, W) ({ \ |
1d5bfac9 | 45 | unsigned long timeout__ = jiffies + msecs_to_jiffies(MS) + 1; \ |
913d8d11 | 46 | int ret__ = 0; \ |
0206e353 | 47 | while (!(COND)) { \ |
913d8d11 | 48 | if (time_after(jiffies, timeout__)) { \ |
1d5bfac9 DV |
49 | if (!(COND)) \ |
50 | ret__ = -ETIMEDOUT; \ | |
913d8d11 CW |
51 | break; \ |
52 | } \ | |
0cc2764c BW |
53 | if (W && drm_can_sleep()) { \ |
54 | msleep(W); \ | |
55 | } else { \ | |
56 | cpu_relax(); \ | |
57 | } \ | |
913d8d11 CW |
58 | } \ |
59 | ret__; \ | |
60 | }) | |
61 | ||
481b6af3 CW |
62 | #define wait_for(COND, MS) _wait_for(COND, MS, 1) |
63 | #define wait_for_atomic(COND, MS) _wait_for(COND, MS, 0) | |
6effa33b DV |
64 | #define wait_for_atomic_us(COND, US) _wait_for((COND), \ |
65 | DIV_ROUND_UP((US), 1000), 0) | |
481b6af3 | 66 | |
021357ac CW |
67 | #define KHz(x) (1000*x) |
68 | #define MHz(x) KHz(1000*x) | |
69 | ||
79e53945 JB |
70 | /* |
71 | * Display related stuff | |
72 | */ | |
73 | ||
74 | /* store information about an Ixxx DVO */ | |
75 | /* The i830->i865 use multiple DVOs with multiple i2cs */ | |
76 | /* the i915, i945 have a single sDVO i2c bus - which is different */ | |
77 | #define MAX_OUTPUTS 6 | |
78 | /* maximum connectors per crtcs in the mode set */ | |
79 | #define INTELFB_CONN_LIMIT 4 | |
80 | ||
81 | #define INTEL_I2C_BUS_DVO 1 | |
82 | #define INTEL_I2C_BUS_SDVO 2 | |
83 | ||
84 | /* these are outputs from the chip - integrated only | |
85 | external chips are via DVO or SDVO output */ | |
86 | #define INTEL_OUTPUT_UNUSED 0 | |
87 | #define INTEL_OUTPUT_ANALOG 1 | |
88 | #define INTEL_OUTPUT_DVO 2 | |
89 | #define INTEL_OUTPUT_SDVO 3 | |
90 | #define INTEL_OUTPUT_LVDS 4 | |
91 | #define INTEL_OUTPUT_TVOUT 5 | |
7d57382e | 92 | #define INTEL_OUTPUT_HDMI 6 |
a4fc5ed6 | 93 | #define INTEL_OUTPUT_DISPLAYPORT 7 |
32f9d658 | 94 | #define INTEL_OUTPUT_EDP 8 |
00c09d70 | 95 | #define INTEL_OUTPUT_UNKNOWN 9 |
79e53945 JB |
96 | |
97 | #define INTEL_DVO_CHIP_NONE 0 | |
98 | #define INTEL_DVO_CHIP_LVDS 1 | |
99 | #define INTEL_DVO_CHIP_TMDS 2 | |
100 | #define INTEL_DVO_CHIP_TVOUT 4 | |
101 | ||
79e53945 JB |
102 | struct intel_framebuffer { |
103 | struct drm_framebuffer base; | |
05394f39 | 104 | struct drm_i915_gem_object *obj; |
79e53945 JB |
105 | }; |
106 | ||
37811fcc CW |
107 | struct intel_fbdev { |
108 | struct drm_fb_helper helper; | |
109 | struct intel_framebuffer ifb; | |
110 | struct list_head fbdev_list; | |
111 | struct drm_display_mode *our_mode; | |
112 | }; | |
79e53945 | 113 | |
21d40d37 | 114 | struct intel_encoder { |
4ef69c7a | 115 | struct drm_encoder base; |
9a935856 DV |
116 | /* |
117 | * The new crtc this encoder will be driven from. Only differs from | |
118 | * base->crtc while a modeset is in progress. | |
119 | */ | |
120 | struct intel_crtc *new_crtc; | |
121 | ||
79e53945 | 122 | int type; |
66a9278e DV |
123 | /* |
124 | * Intel hw has only one MUX where encoders could be clone, hence a | |
125 | * simple flag is enough to compute the possible_clones mask. | |
126 | */ | |
127 | bool cloneable; | |
5ab432ef | 128 | bool connectors_active; |
21d40d37 | 129 | void (*hot_plug)(struct intel_encoder *); |
7ae89233 DV |
130 | bool (*compute_config)(struct intel_encoder *, |
131 | struct intel_crtc_config *); | |
dafd226c | 132 | void (*pre_pll_enable)(struct intel_encoder *); |
bf49ec8c | 133 | void (*pre_enable)(struct intel_encoder *); |
ef9c3aee | 134 | void (*enable)(struct intel_encoder *); |
6cc5f341 | 135 | void (*mode_set)(struct intel_encoder *intel_encoder); |
ef9c3aee | 136 | void (*disable)(struct intel_encoder *); |
bf49ec8c | 137 | void (*post_disable)(struct intel_encoder *); |
f0947c37 DV |
138 | /* Read out the current hw state of this connector, returning true if |
139 | * the encoder is active. If the encoder is enabled it also set the pipe | |
140 | * it is connected to in the pipe parameter. */ | |
141 | bool (*get_hw_state)(struct intel_encoder *, enum pipe *pipe); | |
045ac3b5 JB |
142 | /* Reconstructs the equivalent mode flags for the current hardware |
143 | * state. */ | |
144 | void (*get_config)(struct intel_encoder *, | |
145 | struct intel_crtc_config *pipe_config); | |
f8aed700 | 146 | int crtc_mask; |
1d843f9d | 147 | enum hpd_pin hpd_pin; |
79e53945 JB |
148 | }; |
149 | ||
1d508706 | 150 | struct intel_panel { |
dd06f90e | 151 | struct drm_display_mode *fixed_mode; |
4d891523 | 152 | int fitting_mode; |
1d508706 JN |
153 | }; |
154 | ||
5daa55eb ZW |
155 | struct intel_connector { |
156 | struct drm_connector base; | |
9a935856 DV |
157 | /* |
158 | * The fixed encoder this connector is connected to. | |
159 | */ | |
df0e9248 | 160 | struct intel_encoder *encoder; |
9a935856 DV |
161 | |
162 | /* | |
163 | * The new encoder this connector will be driven. Only differs from | |
164 | * encoder while a modeset is in progress. | |
165 | */ | |
166 | struct intel_encoder *new_encoder; | |
167 | ||
f0947c37 DV |
168 | /* Reads out the current hw, returning true if the connector is enabled |
169 | * and active (i.e. dpms ON state). */ | |
170 | bool (*get_hw_state)(struct intel_connector *); | |
1d508706 JN |
171 | |
172 | /* Panel info for eDP and LVDS */ | |
173 | struct intel_panel panel; | |
9cd300e0 JN |
174 | |
175 | /* Cached EDID for eDP and LVDS. May hold ERR_PTR for invalid EDID. */ | |
176 | struct edid *edid; | |
821450c6 EE |
177 | |
178 | /* since POLL and HPD connectors may use the same HPD line keep the native | |
179 | state of connector->polled in case hotplug storm detection changes it */ | |
180 | u8 polled; | |
5daa55eb ZW |
181 | }; |
182 | ||
80ad9206 VS |
183 | typedef struct dpll { |
184 | /* given values */ | |
185 | int n; | |
186 | int m1, m2; | |
187 | int p1, p2; | |
188 | /* derived values */ | |
189 | int dot; | |
190 | int vco; | |
191 | int m; | |
192 | int p; | |
193 | } intel_clock_t; | |
194 | ||
b8cecdf5 | 195 | struct intel_crtc_config { |
bb760063 DV |
196 | /** |
197 | * quirks - bitfield with hw state readout quirks | |
198 | * | |
199 | * For various reasons the hw state readout code might not be able to | |
200 | * completely faithfully read out the current state. These cases are | |
201 | * tracked with quirk flags so that fastboot and state checker can act | |
202 | * accordingly. | |
203 | */ | |
204 | #define PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS (1<<0) /* unreliable sync mode.flags */ | |
205 | unsigned long quirks; | |
206 | ||
b8cecdf5 DV |
207 | struct drm_display_mode requested_mode; |
208 | struct drm_display_mode adjusted_mode; | |
7ae89233 DV |
209 | /* This flag must be set by the encoder's compute_config callback if it |
210 | * changes the crtc timings in the mode to prevent the crtc fixup from | |
211 | * overwriting them. Currently only lvds needs that. */ | |
212 | bool timings_set; | |
5bfe2ac0 DV |
213 | /* Whether to set up the PCH/FDI. Note that we never allow sharing |
214 | * between pch encoders and cpu encoders. */ | |
215 | bool has_pch_encoder; | |
50f3b016 | 216 | |
3b117c8f DV |
217 | /* CPU Transcoder for the pipe. Currently this can only differ from the |
218 | * pipe on Haswell (where we have a special eDP transcoder). */ | |
219 | enum transcoder cpu_transcoder; | |
220 | ||
50f3b016 DV |
221 | /* |
222 | * Use reduced/limited/broadcast rbg range, compressing from the full | |
223 | * range fed into the crtcs. | |
224 | */ | |
225 | bool limited_color_range; | |
226 | ||
03afc4a2 DV |
227 | /* DP has a bunch of special case unfortunately, so mark the pipe |
228 | * accordingly. */ | |
229 | bool has_dp_encoder; | |
d8b32247 DV |
230 | |
231 | /* | |
232 | * Enable dithering, used when the selected pipe bpp doesn't match the | |
233 | * plane bpp. | |
234 | */ | |
965e0c48 | 235 | bool dither; |
f47709a9 DV |
236 | |
237 | /* Controls for the clock computation, to override various stages. */ | |
238 | bool clock_set; | |
239 | ||
09ede541 DV |
240 | /* SDVO TV has a bunch of special case. To make multifunction encoders |
241 | * work correctly, we need to track this at runtime.*/ | |
242 | bool sdvo_tv_clock; | |
243 | ||
e29c22c0 DV |
244 | /* |
245 | * crtc bandwidth limit, don't increase pipe bpp or clock if not really | |
246 | * required. This is set in the 2nd loop of calling encoder's | |
247 | * ->compute_config if the first pick doesn't work out. | |
248 | */ | |
249 | bool bw_constrained; | |
250 | ||
f47709a9 DV |
251 | /* Settings for the intel dpll used on pretty much everything but |
252 | * haswell. */ | |
80ad9206 | 253 | struct dpll dpll; |
f47709a9 | 254 | |
965e0c48 | 255 | int pipe_bpp; |
6cf86a5e | 256 | struct intel_link_m_n dp_m_n; |
ff9a6750 DV |
257 | |
258 | /* | |
259 | * Frequence the dpll for the port should run at. Differs from the | |
260 | * adjusted dotclock e.g. for DP or 12bpc hdmi mode. | |
df92b1e6 | 261 | */ |
ff9a6750 DV |
262 | int port_clock; |
263 | ||
6cc5f341 DV |
264 | /* Used by SDVO (and if we ever fix it, HDMI). */ |
265 | unsigned pixel_multiplier; | |
2dd24552 JB |
266 | |
267 | /* Panel fitter controls for gen2-gen4 + VLV */ | |
b074cec8 JB |
268 | struct { |
269 | u32 control; | |
270 | u32 pgm_ratios; | |
68fc8742 | 271 | u32 lvds_border_bits; |
b074cec8 JB |
272 | } gmch_pfit; |
273 | ||
274 | /* Panel fitter placement and size for Ironlake+ */ | |
275 | struct { | |
276 | u32 pos; | |
277 | u32 size; | |
278 | } pch_pfit; | |
33d29b14 | 279 | |
ca3a0ff8 | 280 | /* FDI configuration, only valid if has_pch_encoder is set. */ |
33d29b14 | 281 | int fdi_lanes; |
ca3a0ff8 | 282 | struct intel_link_m_n fdi_m_n; |
42db64ef PZ |
283 | |
284 | bool ips_enabled; | |
b8cecdf5 DV |
285 | }; |
286 | ||
79e53945 JB |
287 | struct intel_crtc { |
288 | struct drm_crtc base; | |
80824003 JB |
289 | enum pipe pipe; |
290 | enum plane plane; | |
79e53945 | 291 | u8 lut_r[256], lut_g[256], lut_b[256]; |
08a48469 DV |
292 | /* |
293 | * Whether the crtc and the connected output pipeline is active. Implies | |
294 | * that crtc->enabled is set, i.e. the current mode configuration has | |
295 | * some outputs connected to this crtc. | |
08a48469 DV |
296 | */ |
297 | bool active; | |
7b9f35a6 | 298 | bool eld_vld; |
93314b5b | 299 | bool primary_disabled; /* is the crtc obscured by a plane? */ |
652c393a | 300 | bool lowfreq_avail; |
02e792fb | 301 | struct intel_overlay *overlay; |
6b95a207 | 302 | struct intel_unpin_work *unpin_work; |
cda4b7d3 | 303 | |
b4a98e57 CW |
304 | atomic_t unpin_work_count; |
305 | ||
e506a0c6 DV |
306 | /* Display surface base address adjustement for pageflips. Note that on |
307 | * gen4+ this only adjusts up to a tile, offsets within a tile are | |
308 | * handled in the hw itself (with the TILEOFF register). */ | |
309 | unsigned long dspaddr_offset; | |
310 | ||
05394f39 | 311 | struct drm_i915_gem_object *cursor_bo; |
cda4b7d3 CW |
312 | uint32_t cursor_addr; |
313 | int16_t cursor_x, cursor_y; | |
314 | int16_t cursor_width, cursor_height; | |
6b383a7f | 315 | bool cursor_visible; |
4b645f14 | 316 | |
b8cecdf5 DV |
317 | struct intel_crtc_config config; |
318 | ||
ee7b9f93 | 319 | /* We can share PLLs across outputs if the timings match */ |
e2b78267 | 320 | enum intel_dpll_id shared_dpll; |
6441ab5f | 321 | uint32_t ddi_pll_sel; |
10d83730 VS |
322 | |
323 | /* reset counter value when the last flip was submitted */ | |
324 | unsigned int reset_counter; | |
8664281b PZ |
325 | |
326 | /* Access to these should be protected by dev_priv->irq_lock. */ | |
327 | bool cpu_fifo_underrun_disabled; | |
328 | bool pch_fifo_underrun_disabled; | |
79e53945 JB |
329 | }; |
330 | ||
b840d907 JB |
331 | struct intel_plane { |
332 | struct drm_plane base; | |
7f1f3851 | 333 | int plane; |
b840d907 JB |
334 | enum pipe pipe; |
335 | struct drm_i915_gem_object *obj; | |
2d354c34 | 336 | bool can_scale; |
b840d907 JB |
337 | int max_downscale; |
338 | u32 lut_r[1024], lut_g[1024], lut_b[1024]; | |
5e1bac2f JB |
339 | int crtc_x, crtc_y; |
340 | unsigned int crtc_w, crtc_h; | |
341 | uint32_t src_x, src_y; | |
342 | uint32_t src_w, src_h; | |
526682e9 PZ |
343 | |
344 | /* Since we need to change the watermarks before/after | |
345 | * enabling/disabling the planes, we need to store the parameters here | |
346 | * as the other pieces of the struct may not reflect the values we want | |
347 | * for the watermark calculations. Currently only Haswell uses this. | |
348 | */ | |
349 | struct { | |
350 | bool enable; | |
351 | uint8_t bytes_per_pixel; | |
352 | uint32_t horiz_pixels; | |
353 | } wm; | |
354 | ||
b840d907 JB |
355 | void (*update_plane)(struct drm_plane *plane, |
356 | struct drm_framebuffer *fb, | |
357 | struct drm_i915_gem_object *obj, | |
358 | int crtc_x, int crtc_y, | |
359 | unsigned int crtc_w, unsigned int crtc_h, | |
360 | uint32_t x, uint32_t y, | |
361 | uint32_t src_w, uint32_t src_h); | |
362 | void (*disable_plane)(struct drm_plane *plane); | |
8ea30864 JB |
363 | int (*update_colorkey)(struct drm_plane *plane, |
364 | struct drm_intel_sprite_colorkey *key); | |
365 | void (*get_colorkey)(struct drm_plane *plane, | |
366 | struct drm_intel_sprite_colorkey *key); | |
b840d907 JB |
367 | }; |
368 | ||
b445e3b0 ED |
369 | struct intel_watermark_params { |
370 | unsigned long fifo_size; | |
371 | unsigned long max_wm; | |
372 | unsigned long default_wm; | |
373 | unsigned long guard_size; | |
374 | unsigned long cacheline_size; | |
375 | }; | |
376 | ||
377 | struct cxsr_latency { | |
378 | int is_desktop; | |
379 | int is_ddr3; | |
380 | unsigned long fsb_freq; | |
381 | unsigned long mem_freq; | |
382 | unsigned long display_sr; | |
383 | unsigned long display_hpll_disable; | |
384 | unsigned long cursor_sr; | |
385 | unsigned long cursor_hpll_disable; | |
386 | }; | |
387 | ||
79e53945 | 388 | #define to_intel_crtc(x) container_of(x, struct intel_crtc, base) |
5daa55eb | 389 | #define to_intel_connector(x) container_of(x, struct intel_connector, base) |
4ef69c7a | 390 | #define to_intel_encoder(x) container_of(x, struct intel_encoder, base) |
79e53945 | 391 | #define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base) |
b840d907 | 392 | #define to_intel_plane(x) container_of(x, struct intel_plane, base) |
79e53945 | 393 | |
45187ace JB |
394 | #define DIP_HEADER_SIZE 5 |
395 | ||
3c17fe4b DH |
396 | #define DIP_TYPE_AVI 0x82 |
397 | #define DIP_VERSION_AVI 0x2 | |
398 | #define DIP_LEN_AVI 13 | |
c846b619 PZ |
399 | #define DIP_AVI_PR_1 0 |
400 | #define DIP_AVI_PR_2 1 | |
abedc077 VS |
401 | #define DIP_AVI_RGB_QUANT_RANGE_DEFAULT (0 << 2) |
402 | #define DIP_AVI_RGB_QUANT_RANGE_LIMITED (1 << 2) | |
403 | #define DIP_AVI_RGB_QUANT_RANGE_FULL (2 << 2) | |
3c17fe4b | 404 | |
26005210 | 405 | #define DIP_TYPE_SPD 0x83 |
c0864cb3 JB |
406 | #define DIP_VERSION_SPD 0x1 |
407 | #define DIP_LEN_SPD 25 | |
408 | #define DIP_SPD_UNKNOWN 0 | |
409 | #define DIP_SPD_DSTB 0x1 | |
410 | #define DIP_SPD_DVDP 0x2 | |
411 | #define DIP_SPD_DVHS 0x3 | |
412 | #define DIP_SPD_HDDVR 0x4 | |
413 | #define DIP_SPD_DVC 0x5 | |
414 | #define DIP_SPD_DSC 0x6 | |
415 | #define DIP_SPD_VCD 0x7 | |
416 | #define DIP_SPD_GAME 0x8 | |
417 | #define DIP_SPD_PC 0x9 | |
418 | #define DIP_SPD_BD 0xa | |
419 | #define DIP_SPD_SCD 0xb | |
420 | ||
3c17fe4b DH |
421 | struct dip_infoframe { |
422 | uint8_t type; /* HB0 */ | |
423 | uint8_t ver; /* HB1 */ | |
424 | uint8_t len; /* HB2 - body len, not including checksum */ | |
425 | uint8_t ecc; /* Header ECC */ | |
426 | uint8_t checksum; /* PB0 */ | |
427 | union { | |
428 | struct { | |
429 | /* PB1 - Y 6:5, A 4:4, B 3:2, S 1:0 */ | |
430 | uint8_t Y_A_B_S; | |
431 | /* PB2 - C 7:6, M 5:4, R 3:0 */ | |
432 | uint8_t C_M_R; | |
433 | /* PB3 - ITC 7:7, EC 6:4, Q 3:2, SC 1:0 */ | |
434 | uint8_t ITC_EC_Q_SC; | |
435 | /* PB4 - VIC 6:0 */ | |
436 | uint8_t VIC; | |
0aa534df PZ |
437 | /* PB5 - YQ 7:6, CN 5:4, PR 3:0 */ |
438 | uint8_t YQ_CN_PR; | |
3c17fe4b DH |
439 | /* PB6 to PB13 */ |
440 | uint16_t top_bar_end; | |
441 | uint16_t bottom_bar_start; | |
442 | uint16_t left_bar_end; | |
443 | uint16_t right_bar_start; | |
81014b9d | 444 | } __attribute__ ((packed)) avi; |
c0864cb3 JB |
445 | struct { |
446 | uint8_t vn[8]; | |
447 | uint8_t pd[16]; | |
448 | uint8_t sdi; | |
81014b9d | 449 | } __attribute__ ((packed)) spd; |
3c17fe4b DH |
450 | uint8_t payload[27]; |
451 | } __attribute__ ((packed)) body; | |
452 | } __attribute__((packed)); | |
453 | ||
f5bbfca3 | 454 | struct intel_hdmi { |
b242b7f7 | 455 | u32 hdmi_reg; |
f5bbfca3 | 456 | int ddc_bus; |
f5bbfca3 | 457 | uint32_t color_range; |
55bc60db | 458 | bool color_range_auto; |
f5bbfca3 ED |
459 | bool has_hdmi_sink; |
460 | bool has_audio; | |
461 | enum hdmi_force_audio force_audio; | |
abedc077 | 462 | bool rgb_quant_range_selectable; |
f5bbfca3 ED |
463 | void (*write_infoframe)(struct drm_encoder *encoder, |
464 | struct dip_infoframe *frame); | |
687f4d06 PZ |
465 | void (*set_infoframes)(struct drm_encoder *encoder, |
466 | struct drm_display_mode *adjusted_mode); | |
f5bbfca3 ED |
467 | }; |
468 | ||
b091cd92 | 469 | #define DP_MAX_DOWNSTREAM_PORTS 0x10 |
54d63ca6 SK |
470 | #define DP_LINK_CONFIGURATION_SIZE 9 |
471 | ||
472 | struct intel_dp { | |
54d63ca6 | 473 | uint32_t output_reg; |
9ed35ab1 | 474 | uint32_t aux_ch_ctl_reg; |
54d63ca6 SK |
475 | uint32_t DP; |
476 | uint8_t link_configuration[DP_LINK_CONFIGURATION_SIZE]; | |
477 | bool has_audio; | |
478 | enum hdmi_force_audio force_audio; | |
479 | uint32_t color_range; | |
55bc60db | 480 | bool color_range_auto; |
54d63ca6 SK |
481 | uint8_t link_bw; |
482 | uint8_t lane_count; | |
483 | uint8_t dpcd[DP_RECEIVER_CAP_SIZE]; | |
b091cd92 | 484 | uint8_t downstream_ports[DP_MAX_DOWNSTREAM_PORTS]; |
54d63ca6 SK |
485 | struct i2c_adapter adapter; |
486 | struct i2c_algo_dp_aux_data algo; | |
54d63ca6 SK |
487 | uint8_t train_set[4]; |
488 | int panel_power_up_delay; | |
489 | int panel_power_down_delay; | |
490 | int panel_power_cycle_delay; | |
491 | int backlight_on_delay; | |
492 | int backlight_off_delay; | |
54d63ca6 SK |
493 | struct delayed_work panel_vdd_work; |
494 | bool want_panel_vdd; | |
dd06f90e | 495 | struct intel_connector *attached_connector; |
54d63ca6 SK |
496 | }; |
497 | ||
da63a9f2 PZ |
498 | struct intel_digital_port { |
499 | struct intel_encoder base; | |
174edf1f | 500 | enum port port; |
876a8cdf | 501 | u32 port_reversal; |
da63a9f2 PZ |
502 | struct intel_dp dp; |
503 | struct intel_hdmi hdmi; | |
504 | }; | |
505 | ||
89b667f8 JB |
506 | static inline int |
507 | vlv_dport_to_channel(struct intel_digital_port *dport) | |
508 | { | |
509 | switch (dport->port) { | |
510 | case PORT_B: | |
511 | return 0; | |
512 | case PORT_C: | |
513 | return 1; | |
514 | default: | |
515 | BUG(); | |
516 | } | |
517 | } | |
518 | ||
f875c15a CW |
519 | static inline struct drm_crtc * |
520 | intel_get_crtc_for_pipe(struct drm_device *dev, int pipe) | |
521 | { | |
522 | struct drm_i915_private *dev_priv = dev->dev_private; | |
523 | return dev_priv->pipe_to_crtc_mapping[pipe]; | |
524 | } | |
525 | ||
417ae147 CW |
526 | static inline struct drm_crtc * |
527 | intel_get_crtc_for_plane(struct drm_device *dev, int plane) | |
528 | { | |
529 | struct drm_i915_private *dev_priv = dev->dev_private; | |
530 | return dev_priv->plane_to_crtc_mapping[plane]; | |
531 | } | |
532 | ||
4e5359cd SF |
533 | struct intel_unpin_work { |
534 | struct work_struct work; | |
b4a98e57 | 535 | struct drm_crtc *crtc; |
05394f39 CW |
536 | struct drm_i915_gem_object *old_fb_obj; |
537 | struct drm_i915_gem_object *pending_flip_obj; | |
4e5359cd | 538 | struct drm_pending_vblank_event *event; |
e7d841ca CW |
539 | atomic_t pending; |
540 | #define INTEL_FLIP_INACTIVE 0 | |
541 | #define INTEL_FLIP_PENDING 1 | |
542 | #define INTEL_FLIP_COMPLETE 2 | |
4e5359cd SF |
543 | bool enable_stall_check; |
544 | }; | |
545 | ||
1630fe75 CW |
546 | struct intel_fbc_work { |
547 | struct delayed_work work; | |
548 | struct drm_crtc *crtc; | |
549 | struct drm_framebuffer *fb; | |
550 | int interval; | |
551 | }; | |
552 | ||
d2acd215 DV |
553 | int intel_pch_rawclk(struct drm_device *dev); |
554 | ||
4eab8136 JN |
555 | int intel_connector_update_modes(struct drm_connector *connector, |
556 | struct edid *edid); | |
335af9a2 | 557 | int intel_ddc_get_modes(struct drm_connector *c, struct i2c_adapter *adapter); |
f0217c42 | 558 | |
3f43c48d | 559 | extern void intel_attach_force_audio_property(struct drm_connector *connector); |
e953fd7b CW |
560 | extern void intel_attach_broadcast_rgb_property(struct drm_connector *connector); |
561 | ||
8664281b | 562 | extern bool intel_pipe_has_type(struct drm_crtc *crtc, int type); |
79e53945 | 563 | extern void intel_crt_init(struct drm_device *dev); |
08d644ad | 564 | extern void intel_hdmi_init(struct drm_device *dev, |
b242b7f7 | 565 | int hdmi_reg, enum port port); |
00c09d70 PZ |
566 | extern void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port, |
567 | struct intel_connector *intel_connector); | |
f5bbfca3 | 568 | extern struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder); |
5bfe2ac0 DV |
569 | extern bool intel_hdmi_compute_config(struct intel_encoder *encoder, |
570 | struct intel_crtc_config *pipe_config); | |
f5bbfca3 | 571 | extern void intel_dip_infoframe_csum(struct dip_infoframe *avi_if); |
eef4eacb DV |
572 | extern bool intel_sdvo_init(struct drm_device *dev, uint32_t sdvo_reg, |
573 | bool is_sdvob); | |
79e53945 JB |
574 | extern void intel_dvo_init(struct drm_device *dev); |
575 | extern void intel_tv_init(struct drm_device *dev); | |
f047e395 | 576 | extern void intel_mark_busy(struct drm_device *dev); |
c65355bb CW |
577 | extern void intel_mark_fb_busy(struct drm_i915_gem_object *obj, |
578 | struct intel_ring_buffer *ring); | |
725a5b54 | 579 | extern void intel_mark_idle(struct drm_device *dev); |
c5d1b51d | 580 | extern bool intel_lvds_init(struct drm_device *dev); |
1974cad0 | 581 | extern bool intel_is_dual_link_lvds(struct drm_device *dev); |
ab9d7c30 PZ |
582 | extern void intel_dp_init(struct drm_device *dev, int output_reg, |
583 | enum port port); | |
00c09d70 PZ |
584 | extern void intel_dp_init_connector(struct intel_digital_port *intel_dig_port, |
585 | struct intel_connector *intel_connector); | |
247d89f6 | 586 | extern void intel_dp_init_link_config(struct intel_dp *intel_dp); |
c19b0669 PZ |
587 | extern void intel_dp_start_link_train(struct intel_dp *intel_dp); |
588 | extern void intel_dp_complete_link_train(struct intel_dp *intel_dp); | |
3ab9c637 | 589 | extern void intel_dp_stop_link_train(struct intel_dp *intel_dp); |
c19b0669 | 590 | extern void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode); |
00c09d70 PZ |
591 | extern void intel_dp_encoder_destroy(struct drm_encoder *encoder); |
592 | extern void intel_dp_check_link_status(struct intel_dp *intel_dp); | |
5bfe2ac0 DV |
593 | extern bool intel_dp_compute_config(struct intel_encoder *encoder, |
594 | struct intel_crtc_config *pipe_config); | |
cb0953d7 | 595 | extern bool intel_dpd_is_edp(struct drm_device *dev); |
d6c50ff8 PZ |
596 | extern void ironlake_edp_backlight_on(struct intel_dp *intel_dp); |
597 | extern void ironlake_edp_backlight_off(struct intel_dp *intel_dp); | |
82a4d9c0 PZ |
598 | extern void ironlake_edp_panel_on(struct intel_dp *intel_dp); |
599 | extern void ironlake_edp_panel_off(struct intel_dp *intel_dp); | |
600 | extern void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp); | |
601 | extern void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync); | |
7f1f3851 | 602 | extern int intel_plane_init(struct drm_device *dev, enum pipe pipe, int plane); |
6f1d69b0 ED |
603 | extern void intel_flush_display_plane(struct drm_i915_private *dev_priv, |
604 | enum plane plane); | |
32f9d658 | 605 | |
a9573556 | 606 | /* intel_panel.c */ |
dd06f90e JN |
607 | extern int intel_panel_init(struct intel_panel *panel, |
608 | struct drm_display_mode *fixed_mode); | |
1d508706 JN |
609 | extern void intel_panel_fini(struct intel_panel *panel); |
610 | ||
1d8e1c75 CW |
611 | extern void intel_fixed_panel_mode(struct drm_display_mode *fixed_mode, |
612 | struct drm_display_mode *adjusted_mode); | |
b074cec8 JB |
613 | extern void intel_pch_panel_fitting(struct intel_crtc *crtc, |
614 | struct intel_crtc_config *pipe_config, | |
615 | int fitting_mode); | |
2dd24552 JB |
616 | extern void intel_gmch_panel_fitting(struct intel_crtc *crtc, |
617 | struct intel_crtc_config *pipe_config, | |
618 | int fitting_mode); | |
d6540632 JN |
619 | extern void intel_panel_set_backlight(struct drm_device *dev, |
620 | u32 level, u32 max); | |
0657b6b1 | 621 | extern int intel_panel_setup_backlight(struct drm_connector *connector); |
24ded204 DV |
622 | extern void intel_panel_enable_backlight(struct drm_device *dev, |
623 | enum pipe pipe); | |
47356eb6 | 624 | extern void intel_panel_disable_backlight(struct drm_device *dev); |
aaa6fd2a | 625 | extern void intel_panel_destroy_backlight(struct drm_device *dev); |
fe16d949 | 626 | extern enum drm_connector_status intel_panel_detect(struct drm_device *dev); |
1d8e1c75 | 627 | |
d9e55608 | 628 | struct intel_set_config { |
1aa4b628 DV |
629 | struct drm_encoder **save_connector_encoders; |
630 | struct drm_crtc **save_encoder_crtcs; | |
5e2b584e DV |
631 | |
632 | bool fb_changed; | |
633 | bool mode_changed; | |
d9e55608 DV |
634 | }; |
635 | ||
c0c36b94 CW |
636 | extern int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode, |
637 | int x, int y, struct drm_framebuffer *old_fb); | |
a261b246 | 638 | extern void intel_modeset_disable(struct drm_device *dev); |
c0c36b94 | 639 | extern void intel_crtc_restore_mode(struct drm_crtc *crtc); |
79e53945 | 640 | extern void intel_crtc_load_lut(struct drm_crtc *crtc); |
b2cabb0e | 641 | extern void intel_crtc_update_dpms(struct drm_crtc *crtc); |
ea5b213a | 642 | extern void intel_encoder_destroy(struct drm_encoder *encoder); |
5ab432ef DV |
643 | extern void intel_encoder_dpms(struct intel_encoder *encoder, int mode); |
644 | extern void intel_connector_dpms(struct drm_connector *, int mode); | |
f0947c37 | 645 | extern bool intel_connector_get_hw_state(struct intel_connector *connector); |
b980514c | 646 | extern void intel_modeset_check_state(struct drm_device *dev); |
5e1bac2f | 647 | extern void intel_plane_restore(struct drm_plane *plane); |
bb53d4ae | 648 | extern void intel_plane_disable(struct drm_plane *plane); |
b980514c | 649 | |
79e53945 | 650 | |
df0e9248 CW |
651 | static inline struct intel_encoder *intel_attached_encoder(struct drm_connector *connector) |
652 | { | |
653 | return to_intel_connector(connector)->encoder; | |
654 | } | |
655 | ||
da63a9f2 PZ |
656 | static inline struct intel_digital_port * |
657 | enc_to_dig_port(struct drm_encoder *encoder) | |
658 | { | |
659 | return container_of(encoder, struct intel_digital_port, base.base); | |
9ff8c9ba ID |
660 | } |
661 | ||
662 | static inline struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder) | |
663 | { | |
664 | return &enc_to_dig_port(encoder)->dp; | |
da63a9f2 PZ |
665 | } |
666 | ||
667 | static inline struct intel_digital_port * | |
668 | dp_to_dig_port(struct intel_dp *intel_dp) | |
669 | { | |
670 | return container_of(intel_dp, struct intel_digital_port, dp); | |
671 | } | |
672 | ||
673 | static inline struct intel_digital_port * | |
674 | hdmi_to_dig_port(struct intel_hdmi *intel_hdmi) | |
675 | { | |
676 | return container_of(intel_hdmi, struct intel_digital_port, hdmi); | |
7739c33b PZ |
677 | } |
678 | ||
b0ea7d37 DL |
679 | bool ibx_digital_port_connected(struct drm_i915_private *dev_priv, |
680 | struct intel_digital_port *port); | |
681 | ||
df0e9248 CW |
682 | extern void intel_connector_attach_encoder(struct intel_connector *connector, |
683 | struct intel_encoder *encoder); | |
684 | extern struct drm_encoder *intel_best_encoder(struct drm_connector *connector); | |
79e53945 JB |
685 | |
686 | extern struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev, | |
687 | struct drm_crtc *crtc); | |
08d7b3d1 CW |
688 | int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data, |
689 | struct drm_file *file_priv); | |
a5c961d1 PZ |
690 | extern enum transcoder |
691 | intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv, | |
692 | enum pipe pipe); | |
9d0498a2 | 693 | extern void intel_wait_for_vblank(struct drm_device *dev, int pipe); |
58e10eb9 | 694 | extern void intel_wait_for_pipe_off(struct drm_device *dev, int pipe); |
d4b1931c | 695 | extern int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp); |
89b667f8 | 696 | extern void vlv_wait_port_ready(struct drm_i915_private *dev_priv, int port); |
8261b191 CW |
697 | |
698 | struct intel_load_detect_pipe { | |
d2dff872 | 699 | struct drm_framebuffer *release_fb; |
8261b191 CW |
700 | bool load_detect_temp; |
701 | int dpms_mode; | |
702 | }; | |
d2434ab7 | 703 | extern bool intel_get_load_detect_pipe(struct drm_connector *connector, |
7173188d | 704 | struct drm_display_mode *mode, |
8261b191 | 705 | struct intel_load_detect_pipe *old); |
d2434ab7 | 706 | extern void intel_release_load_detect_pipe(struct drm_connector *connector, |
8261b191 | 707 | struct intel_load_detect_pipe *old); |
79e53945 | 708 | |
79e53945 JB |
709 | extern void intelfb_restore(void); |
710 | extern void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green, | |
711 | u16 blue, int regno); | |
b8c00ac5 DA |
712 | extern void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green, |
713 | u16 *blue, int regno); | |
0cdab21f | 714 | extern void intel_enable_clock_gating(struct drm_device *dev); |
79e53945 | 715 | |
127bd2ac | 716 | extern int intel_pin_and_fence_fb_obj(struct drm_device *dev, |
05394f39 | 717 | struct drm_i915_gem_object *obj, |
919926ae | 718 | struct intel_ring_buffer *pipelined); |
1690e1eb | 719 | extern void intel_unpin_fb_obj(struct drm_i915_gem_object *obj); |
127bd2ac | 720 | |
38651674 DA |
721 | extern int intel_framebuffer_init(struct drm_device *dev, |
722 | struct intel_framebuffer *ifb, | |
308e5bcb | 723 | struct drm_mode_fb_cmd2 *mode_cmd, |
05394f39 | 724 | struct drm_i915_gem_object *obj); |
38651674 | 725 | extern int intel_fbdev_init(struct drm_device *dev); |
20afbda2 | 726 | extern void intel_fbdev_initial_config(struct drm_device *dev); |
38651674 | 727 | extern void intel_fbdev_fini(struct drm_device *dev); |
3fa016a0 | 728 | extern void intel_fbdev_set_suspend(struct drm_device *dev, int state); |
6b95a207 KH |
729 | extern void intel_prepare_page_flip(struct drm_device *dev, int plane); |
730 | extern void intel_finish_page_flip(struct drm_device *dev, int pipe); | |
1afe3e9d | 731 | extern void intel_finish_page_flip_plane(struct drm_device *dev, int plane); |
6b95a207 | 732 | |
02e792fb DV |
733 | extern void intel_setup_overlay(struct drm_device *dev); |
734 | extern void intel_cleanup_overlay(struct drm_device *dev); | |
ce453d81 | 735 | extern int intel_overlay_switch_off(struct intel_overlay *overlay); |
02e792fb DV |
736 | extern int intel_overlay_put_image(struct drm_device *dev, void *data, |
737 | struct drm_file *file_priv); | |
738 | extern int intel_overlay_attrs(struct drm_device *dev, void *data, | |
739 | struct drm_file *file_priv); | |
4abe3520 | 740 | |
eb1f8e4f | 741 | extern void intel_fb_output_poll_changed(struct drm_device *dev); |
e8e7a2b8 | 742 | extern void intel_fb_restore_mode(struct drm_device *dev); |
645c62a5 | 743 | |
b840d907 JB |
744 | extern void assert_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, |
745 | bool state); | |
746 | #define assert_pipe_enabled(d, p) assert_pipe(d, p, true) | |
747 | #define assert_pipe_disabled(d, p) assert_pipe(d, p, false) | |
748 | ||
645c62a5 | 749 | extern void intel_init_clock_gating(struct drm_device *dev); |
7d708ee4 | 750 | extern void intel_suspend_hw(struct drm_device *dev); |
e0dac65e WF |
751 | extern void intel_write_eld(struct drm_encoder *encoder, |
752 | struct drm_display_mode *mode); | |
45244b87 | 753 | extern void intel_prepare_ddi(struct drm_device *dev); |
c82e4d26 | 754 | extern void hsw_fdi_link_train(struct drm_crtc *crtc); |
0e72a5b5 | 755 | extern void intel_ddi_init(struct drm_device *dev, enum port port); |
d4270e57 | 756 | |
b840d907 | 757 | /* For use by IVB LP watermark workaround in intel_sprite.c */ |
f681fa23 | 758 | extern void intel_update_watermarks(struct drm_device *dev); |
b840d907 JB |
759 | extern void intel_update_sprite_watermarks(struct drm_device *dev, int pipe, |
760 | uint32_t sprite_width, | |
4c4ff43a | 761 | int pixel_size, bool enable); |
8ea30864 | 762 | |
bc752862 CW |
763 | extern unsigned long intel_gen4_compute_page_offset(int *x, int *y, |
764 | unsigned int tiling_mode, | |
765 | unsigned int bpp, | |
766 | unsigned int pitch); | |
5a35e99e | 767 | |
8ea30864 JB |
768 | extern int intel_sprite_set_colorkey(struct drm_device *dev, void *data, |
769 | struct drm_file *file_priv); | |
770 | extern int intel_sprite_get_colorkey(struct drm_device *dev, void *data, | |
771 | struct drm_file *file_priv); | |
772 | ||
85208be0 | 773 | /* Power-related functions, located in intel_pm.c */ |
1fa61106 | 774 | extern void intel_init_pm(struct drm_device *dev); |
85208be0 | 775 | /* FBC */ |
85208be0 ED |
776 | extern bool intel_fbc_enabled(struct drm_device *dev); |
777 | extern void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval); | |
778 | extern void intel_update_fbc(struct drm_device *dev); | |
eb48eb00 DV |
779 | /* IPS */ |
780 | extern void intel_gpu_ips_init(struct drm_i915_private *dev_priv); | |
781 | extern void intel_gpu_ips_teardown(void); | |
85208be0 | 782 | |
a38911a3 WX |
783 | /* Power well */ |
784 | extern int i915_init_power_well(struct drm_device *dev); | |
785 | extern void i915_remove_power_well(struct drm_device *dev); | |
786 | ||
b97186f0 PZ |
787 | extern bool intel_display_power_enabled(struct drm_device *dev, |
788 | enum intel_display_power_domain domain); | |
fa42e23c | 789 | extern void intel_init_power_well(struct drm_device *dev); |
cb10799c | 790 | extern void intel_set_power_well(struct drm_device *dev, bool enable); |
8090c6b9 DV |
791 | extern void intel_enable_gt_powersave(struct drm_device *dev); |
792 | extern void intel_disable_gt_powersave(struct drm_device *dev); | |
6590190d | 793 | extern void gen6_gt_check_fifodbg(struct drm_i915_private *dev_priv); |
930ebb46 | 794 | extern void ironlake_teardown_rc6(struct drm_device *dev); |
b3daeaef | 795 | |
85234cdc DV |
796 | extern bool intel_ddi_get_hw_state(struct intel_encoder *encoder, |
797 | enum pipe *pipe); | |
b8fc2f6a | 798 | extern int intel_ddi_get_cdclk_freq(struct drm_i915_private *dev_priv); |
79f689aa | 799 | extern void intel_ddi_pll_init(struct drm_device *dev); |
8228c251 | 800 | extern void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc); |
ad80a810 PZ |
801 | extern void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv, |
802 | enum transcoder cpu_transcoder); | |
fc914639 PZ |
803 | extern void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc); |
804 | extern void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc); | |
6441ab5f | 805 | extern void intel_ddi_setup_hw_pll_state(struct drm_device *dev); |
ff9a6750 | 806 | extern bool intel_ddi_pll_mode_set(struct drm_crtc *crtc); |
6441ab5f | 807 | extern void intel_ddi_put_crtc_pll(struct drm_crtc *crtc); |
dae84799 | 808 | extern void intel_ddi_set_pipe_settings(struct drm_crtc *crtc); |
c19b0669 | 809 | extern void intel_ddi_prepare_link_retrain(struct drm_encoder *encoder); |
1ad960f2 PZ |
810 | extern bool |
811 | intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector); | |
812 | extern void intel_ddi_fdi_disable(struct drm_crtc *crtc); | |
72662e10 | 813 | |
96a02917 | 814 | extern void intel_display_handle_reset(struct drm_device *dev); |
8664281b PZ |
815 | extern bool intel_set_cpu_fifo_underrun_reporting(struct drm_device *dev, |
816 | enum pipe pipe, | |
817 | bool enable); | |
818 | extern bool intel_set_pch_fifo_underrun_reporting(struct drm_device *dev, | |
819 | enum transcoder pch_transcoder, | |
820 | bool enable); | |
96a02917 | 821 | |
79e53945 | 822 | #endif /* __INTEL_DRV_H__ */ |