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79e53945 JB |
1 | /* |
2 | * Copyright (c) 2006 Dave Airlie <airlied@linux.ie> | |
3 | * Copyright (c) 2007-2008 Intel Corporation | |
4 | * Jesse Barnes <jesse.barnes@intel.com> | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | |
7 | * copy of this software and associated documentation files (the "Software"), | |
8 | * to deal in the Software without restriction, including without limitation | |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
10 | * and/or sell copies of the Software, and to permit persons to whom the | |
11 | * Software is furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice (including the next | |
14 | * paragraph) shall be included in all copies or substantial portions of the | |
15 | * Software. | |
16 | * | |
17 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
18 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
19 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
20 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
21 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
22 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
23 | * IN THE SOFTWARE. | |
24 | */ | |
25 | #ifndef __INTEL_DRV_H__ | |
26 | #define __INTEL_DRV_H__ | |
27 | ||
d1d70677 | 28 | #include <linux/async.h> |
79e53945 | 29 | #include <linux/i2c.h> |
178f736a | 30 | #include <linux/hdmi.h> |
760285e7 | 31 | #include <drm/i915_drm.h> |
80824003 | 32 | #include "i915_drv.h" |
760285e7 DH |
33 | #include <drm/drm_crtc.h> |
34 | #include <drm/drm_crtc_helper.h> | |
35 | #include <drm/drm_fb_helper.h> | |
0e32b39c | 36 | #include <drm/drm_dp_mst_helper.h> |
eeca778a | 37 | #include <drm/drm_rect.h> |
10f81c19 | 38 | #include <drm/drm_atomic.h> |
913d8d11 | 39 | |
1d5bfac9 DV |
40 | /** |
41 | * _wait_for - magic (register) wait macro | |
42 | * | |
43 | * Does the right thing for modeset paths when run under kdgb or similar atomic | |
44 | * contexts. Note that it's important that we check the condition again after | |
45 | * having timed out, since the timeout could be due to preemption or similar and | |
46 | * we've never had a chance to check the condition before the timeout. | |
47 | */ | |
481b6af3 | 48 | #define _wait_for(COND, MS, W) ({ \ |
1d5bfac9 | 49 | unsigned long timeout__ = jiffies + msecs_to_jiffies(MS) + 1; \ |
913d8d11 | 50 | int ret__ = 0; \ |
0206e353 | 51 | while (!(COND)) { \ |
913d8d11 | 52 | if (time_after(jiffies, timeout__)) { \ |
1d5bfac9 DV |
53 | if (!(COND)) \ |
54 | ret__ = -ETIMEDOUT; \ | |
913d8d11 CW |
55 | break; \ |
56 | } \ | |
9848de08 VS |
57 | if ((W) && drm_can_sleep()) { \ |
58 | usleep_range((W)*1000, (W)*2000); \ | |
0cc2764c BW |
59 | } else { \ |
60 | cpu_relax(); \ | |
61 | } \ | |
913d8d11 CW |
62 | } \ |
63 | ret__; \ | |
64 | }) | |
65 | ||
481b6af3 CW |
66 | #define wait_for(COND, MS) _wait_for(COND, MS, 1) |
67 | #define wait_for_atomic(COND, MS) _wait_for(COND, MS, 0) | |
6effa33b DV |
68 | #define wait_for_atomic_us(COND, US) _wait_for((COND), \ |
69 | DIV_ROUND_UP((US), 1000), 0) | |
481b6af3 | 70 | |
49938ac4 JN |
71 | #define KHz(x) (1000 * (x)) |
72 | #define MHz(x) KHz(1000 * (x)) | |
021357ac | 73 | |
79e53945 JB |
74 | /* |
75 | * Display related stuff | |
76 | */ | |
77 | ||
78 | /* store information about an Ixxx DVO */ | |
79 | /* The i830->i865 use multiple DVOs with multiple i2cs */ | |
80 | /* the i915, i945 have a single sDVO i2c bus - which is different */ | |
81 | #define MAX_OUTPUTS 6 | |
82 | /* maximum connectors per crtcs in the mode set */ | |
79e53945 | 83 | |
4726e0b0 SK |
84 | /* Maximum cursor sizes */ |
85 | #define GEN2_CURSOR_WIDTH 64 | |
86 | #define GEN2_CURSOR_HEIGHT 64 | |
068be561 DL |
87 | #define MAX_CURSOR_WIDTH 256 |
88 | #define MAX_CURSOR_HEIGHT 256 | |
4726e0b0 | 89 | |
79e53945 JB |
90 | #define INTEL_I2C_BUS_DVO 1 |
91 | #define INTEL_I2C_BUS_SDVO 2 | |
92 | ||
93 | /* these are outputs from the chip - integrated only | |
94 | external chips are via DVO or SDVO output */ | |
6847d71b PZ |
95 | enum intel_output_type { |
96 | INTEL_OUTPUT_UNUSED = 0, | |
97 | INTEL_OUTPUT_ANALOG = 1, | |
98 | INTEL_OUTPUT_DVO = 2, | |
99 | INTEL_OUTPUT_SDVO = 3, | |
100 | INTEL_OUTPUT_LVDS = 4, | |
101 | INTEL_OUTPUT_TVOUT = 5, | |
102 | INTEL_OUTPUT_HDMI = 6, | |
103 | INTEL_OUTPUT_DISPLAYPORT = 7, | |
104 | INTEL_OUTPUT_EDP = 8, | |
105 | INTEL_OUTPUT_DSI = 9, | |
106 | INTEL_OUTPUT_UNKNOWN = 10, | |
107 | INTEL_OUTPUT_DP_MST = 11, | |
108 | }; | |
79e53945 JB |
109 | |
110 | #define INTEL_DVO_CHIP_NONE 0 | |
111 | #define INTEL_DVO_CHIP_LVDS 1 | |
112 | #define INTEL_DVO_CHIP_TMDS 2 | |
113 | #define INTEL_DVO_CHIP_TVOUT 4 | |
114 | ||
dfba2e2d SK |
115 | #define INTEL_DSI_VIDEO_MODE 0 |
116 | #define INTEL_DSI_COMMAND_MODE 1 | |
72ffa333 | 117 | |
79e53945 JB |
118 | struct intel_framebuffer { |
119 | struct drm_framebuffer base; | |
05394f39 | 120 | struct drm_i915_gem_object *obj; |
79e53945 JB |
121 | }; |
122 | ||
37811fcc CW |
123 | struct intel_fbdev { |
124 | struct drm_fb_helper helper; | |
8bcd4553 | 125 | struct intel_framebuffer *fb; |
37811fcc CW |
126 | struct list_head fbdev_list; |
127 | struct drm_display_mode *our_mode; | |
d978ef14 | 128 | int preferred_bpp; |
37811fcc | 129 | }; |
79e53945 | 130 | |
21d40d37 | 131 | struct intel_encoder { |
4ef69c7a | 132 | struct drm_encoder base; |
9a935856 | 133 | |
6847d71b | 134 | enum intel_output_type type; |
bc079e8b | 135 | unsigned int cloneable; |
21d40d37 | 136 | void (*hot_plug)(struct intel_encoder *); |
7ae89233 | 137 | bool (*compute_config)(struct intel_encoder *, |
5cec258b | 138 | struct intel_crtc_state *); |
dafd226c | 139 | void (*pre_pll_enable)(struct intel_encoder *); |
bf49ec8c | 140 | void (*pre_enable)(struct intel_encoder *); |
ef9c3aee | 141 | void (*enable)(struct intel_encoder *); |
6cc5f341 | 142 | void (*mode_set)(struct intel_encoder *intel_encoder); |
ef9c3aee | 143 | void (*disable)(struct intel_encoder *); |
bf49ec8c | 144 | void (*post_disable)(struct intel_encoder *); |
f0947c37 DV |
145 | /* Read out the current hw state of this connector, returning true if |
146 | * the encoder is active. If the encoder is enabled it also set the pipe | |
147 | * it is connected to in the pipe parameter. */ | |
148 | bool (*get_hw_state)(struct intel_encoder *, enum pipe *pipe); | |
045ac3b5 | 149 | /* Reconstructs the equivalent mode flags for the current hardware |
fdafa9e2 | 150 | * state. This must be called _after_ display->get_pipe_config has |
63000ef6 XZ |
151 | * pre-filled the pipe config. Note that intel_encoder->base.crtc must |
152 | * be set correctly before calling this function. */ | |
045ac3b5 | 153 | void (*get_config)(struct intel_encoder *, |
5cec258b | 154 | struct intel_crtc_state *pipe_config); |
07f9cd0b ID |
155 | /* |
156 | * Called during system suspend after all pending requests for the | |
157 | * encoder are flushed (for example for DP AUX transactions) and | |
158 | * device interrupts are disabled. | |
159 | */ | |
160 | void (*suspend)(struct intel_encoder *); | |
f8aed700 | 161 | int crtc_mask; |
1d843f9d | 162 | enum hpd_pin hpd_pin; |
79e53945 JB |
163 | }; |
164 | ||
1d508706 | 165 | struct intel_panel { |
dd06f90e | 166 | struct drm_display_mode *fixed_mode; |
ec9ed197 | 167 | struct drm_display_mode *downclock_mode; |
4d891523 | 168 | int fitting_mode; |
58c68779 JN |
169 | |
170 | /* backlight */ | |
171 | struct { | |
c91c9f32 | 172 | bool present; |
58c68779 | 173 | u32 level; |
6dda730e | 174 | u32 min; |
7bd688cd | 175 | u32 max; |
58c68779 | 176 | bool enabled; |
636baebf JN |
177 | bool combination_mode; /* gen 2/4 only */ |
178 | bool active_low_pwm; | |
b029e66f SK |
179 | |
180 | /* PWM chip */ | |
181 | struct pwm_device *pwm; | |
182 | ||
58c68779 JN |
183 | struct backlight_device *device; |
184 | } backlight; | |
ab656bb9 JN |
185 | |
186 | void (*backlight_power)(struct intel_connector *, bool enable); | |
1d508706 JN |
187 | }; |
188 | ||
5daa55eb ZW |
189 | struct intel_connector { |
190 | struct drm_connector base; | |
9a935856 DV |
191 | /* |
192 | * The fixed encoder this connector is connected to. | |
193 | */ | |
df0e9248 | 194 | struct intel_encoder *encoder; |
9a935856 | 195 | |
f0947c37 DV |
196 | /* Reads out the current hw, returning true if the connector is enabled |
197 | * and active (i.e. dpms ON state). */ | |
198 | bool (*get_hw_state)(struct intel_connector *); | |
1d508706 | 199 | |
4932e2c3 ID |
200 | /* |
201 | * Removes all interfaces through which the connector is accessible | |
202 | * - like sysfs, debugfs entries -, so that no new operations can be | |
203 | * started on the connector. Also makes sure all currently pending | |
204 | * operations finish before returing. | |
205 | */ | |
206 | void (*unregister)(struct intel_connector *); | |
207 | ||
1d508706 JN |
208 | /* Panel info for eDP and LVDS */ |
209 | struct intel_panel panel; | |
9cd300e0 JN |
210 | |
211 | /* Cached EDID for eDP and LVDS. May hold ERR_PTR for invalid EDID. */ | |
212 | struct edid *edid; | |
beb60608 | 213 | struct edid *detect_edid; |
821450c6 EE |
214 | |
215 | /* since POLL and HPD connectors may use the same HPD line keep the native | |
216 | state of connector->polled in case hotplug storm detection changes it */ | |
217 | u8 polled; | |
0e32b39c DA |
218 | |
219 | void *port; /* store this opaque as its illegal to dereference it */ | |
220 | ||
221 | struct intel_dp *mst_port; | |
5daa55eb ZW |
222 | }; |
223 | ||
80ad9206 VS |
224 | typedef struct dpll { |
225 | /* given values */ | |
226 | int n; | |
227 | int m1, m2; | |
228 | int p1, p2; | |
229 | /* derived values */ | |
230 | int dot; | |
231 | int vco; | |
232 | int m; | |
233 | int p; | |
234 | } intel_clock_t; | |
235 | ||
de419ab6 ML |
236 | struct intel_atomic_state { |
237 | struct drm_atomic_state base; | |
238 | ||
27c329ed | 239 | unsigned int cdclk; |
de419ab6 ML |
240 | bool dpll_set; |
241 | struct intel_shared_dpll_config shared_dpll[I915_NUM_PLLS]; | |
242 | }; | |
243 | ||
eeca778a | 244 | struct intel_plane_state { |
2b875c22 | 245 | struct drm_plane_state base; |
eeca778a GP |
246 | struct drm_rect src; |
247 | struct drm_rect dst; | |
248 | struct drm_rect clip; | |
eeca778a | 249 | bool visible; |
32b7eeec | 250 | |
be41e336 CK |
251 | /* |
252 | * scaler_id | |
253 | * = -1 : not using a scaler | |
254 | * >= 0 : using a scalers | |
255 | * | |
256 | * plane requiring a scaler: | |
257 | * - During check_plane, its bit is set in | |
258 | * crtc_state->scaler_state.scaler_users by calling helper function | |
86adf9d7 | 259 | * update_scaler_plane. |
be41e336 CK |
260 | * - scaler_id indicates the scaler it got assigned. |
261 | * | |
262 | * plane doesn't require a scaler: | |
263 | * - this can happen when scaling is no more required or plane simply | |
264 | * got disabled. | |
265 | * - During check_plane, corresponding bit is reset in | |
266 | * crtc_state->scaler_state.scaler_users by calling helper function | |
86adf9d7 | 267 | * update_scaler_plane. |
be41e336 CK |
268 | */ |
269 | int scaler_id; | |
818ed961 ML |
270 | |
271 | struct drm_intel_sprite_colorkey ckey; | |
eeca778a GP |
272 | }; |
273 | ||
5724dbd1 | 274 | struct intel_initial_plane_config { |
2d14030b | 275 | struct intel_framebuffer *fb; |
49af449b | 276 | unsigned int tiling; |
46f297fb JB |
277 | int size; |
278 | u32 base; | |
279 | }; | |
280 | ||
be41e336 CK |
281 | #define SKL_MIN_SRC_W 8 |
282 | #define SKL_MAX_SRC_W 4096 | |
283 | #define SKL_MIN_SRC_H 8 | |
6156a456 | 284 | #define SKL_MAX_SRC_H 4096 |
be41e336 CK |
285 | #define SKL_MIN_DST_W 8 |
286 | #define SKL_MAX_DST_W 4096 | |
287 | #define SKL_MIN_DST_H 8 | |
6156a456 | 288 | #define SKL_MAX_DST_H 4096 |
be41e336 CK |
289 | |
290 | struct intel_scaler { | |
be41e336 CK |
291 | int in_use; |
292 | uint32_t mode; | |
293 | }; | |
294 | ||
295 | struct intel_crtc_scaler_state { | |
296 | #define SKL_NUM_SCALERS 2 | |
297 | struct intel_scaler scalers[SKL_NUM_SCALERS]; | |
298 | ||
299 | /* | |
300 | * scaler_users: keeps track of users requesting scalers on this crtc. | |
301 | * | |
302 | * If a bit is set, a user is using a scaler. | |
303 | * Here user can be a plane or crtc as defined below: | |
304 | * bits 0-30 - plane (bit position is index from drm_plane_index) | |
305 | * bit 31 - crtc | |
306 | * | |
307 | * Instead of creating a new index to cover planes and crtc, using | |
308 | * existing drm_plane_index for planes which is well less than 31 | |
309 | * planes and bit 31 for crtc. This should be fine to cover all | |
310 | * our platforms. | |
311 | * | |
312 | * intel_atomic_setup_scalers will setup available scalers to users | |
313 | * requesting scalers. It will gracefully fail if request exceeds | |
314 | * avilability. | |
315 | */ | |
316 | #define SKL_CRTC_INDEX 31 | |
317 | unsigned scaler_users; | |
318 | ||
319 | /* scaler used by crtc for panel fitting purpose */ | |
320 | int scaler_id; | |
321 | }; | |
322 | ||
1ed51de9 DV |
323 | /* drm_mode->private_flags */ |
324 | #define I915_MODE_FLAG_INHERITED 1 | |
325 | ||
5cec258b | 326 | struct intel_crtc_state { |
2d112de7 ACO |
327 | struct drm_crtc_state base; |
328 | ||
bb760063 DV |
329 | /** |
330 | * quirks - bitfield with hw state readout quirks | |
331 | * | |
332 | * For various reasons the hw state readout code might not be able to | |
333 | * completely faithfully read out the current state. These cases are | |
334 | * tracked with quirk flags so that fastboot and state checker can act | |
335 | * accordingly. | |
336 | */ | |
9953599b | 337 | #define PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS (1<<0) /* unreliable sync mode.flags */ |
bb760063 DV |
338 | unsigned long quirks; |
339 | ||
37327abd VS |
340 | /* Pipe source size (ie. panel fitter input size) |
341 | * All planes will be positioned inside this space, | |
342 | * and get clipped at the edges. */ | |
343 | int pipe_src_w, pipe_src_h; | |
344 | ||
5bfe2ac0 DV |
345 | /* Whether to set up the PCH/FDI. Note that we never allow sharing |
346 | * between pch encoders and cpu encoders. */ | |
347 | bool has_pch_encoder; | |
50f3b016 | 348 | |
e43823ec JB |
349 | /* Are we sending infoframes on the attached port */ |
350 | bool has_infoframe; | |
351 | ||
3b117c8f DV |
352 | /* CPU Transcoder for the pipe. Currently this can only differ from the |
353 | * pipe on Haswell (where we have a special eDP transcoder). */ | |
354 | enum transcoder cpu_transcoder; | |
355 | ||
50f3b016 DV |
356 | /* |
357 | * Use reduced/limited/broadcast rbg range, compressing from the full | |
358 | * range fed into the crtcs. | |
359 | */ | |
360 | bool limited_color_range; | |
361 | ||
03afc4a2 DV |
362 | /* DP has a bunch of special case unfortunately, so mark the pipe |
363 | * accordingly. */ | |
364 | bool has_dp_encoder; | |
d8b32247 | 365 | |
6897b4b5 DV |
366 | /* Whether we should send NULL infoframes. Required for audio. */ |
367 | bool has_hdmi_sink; | |
368 | ||
9ed109a7 DV |
369 | /* Audio enabled on this pipe. Only valid if either has_hdmi_sink or |
370 | * has_dp_encoder is set. */ | |
371 | bool has_audio; | |
372 | ||
d8b32247 DV |
373 | /* |
374 | * Enable dithering, used when the selected pipe bpp doesn't match the | |
375 | * plane bpp. | |
376 | */ | |
965e0c48 | 377 | bool dither; |
f47709a9 DV |
378 | |
379 | /* Controls for the clock computation, to override various stages. */ | |
380 | bool clock_set; | |
381 | ||
09ede541 DV |
382 | /* SDVO TV has a bunch of special case. To make multifunction encoders |
383 | * work correctly, we need to track this at runtime.*/ | |
384 | bool sdvo_tv_clock; | |
385 | ||
e29c22c0 DV |
386 | /* |
387 | * crtc bandwidth limit, don't increase pipe bpp or clock if not really | |
388 | * required. This is set in the 2nd loop of calling encoder's | |
389 | * ->compute_config if the first pick doesn't work out. | |
390 | */ | |
391 | bool bw_constrained; | |
392 | ||
f47709a9 DV |
393 | /* Settings for the intel dpll used on pretty much everything but |
394 | * haswell. */ | |
80ad9206 | 395 | struct dpll dpll; |
f47709a9 | 396 | |
a43f6e0f DV |
397 | /* Selected dpll when shared or DPLL_ID_PRIVATE. */ |
398 | enum intel_dpll_id shared_dpll; | |
399 | ||
96b7dfb7 S |
400 | /* |
401 | * - PORT_CLK_SEL for DDI ports on HSW/BDW. | |
402 | * - enum skl_dpll on SKL | |
403 | */ | |
de7cfc63 DV |
404 | uint32_t ddi_pll_sel; |
405 | ||
66e985c0 DV |
406 | /* Actual register state of the dpll, for shared dpll cross-checking. */ |
407 | struct intel_dpll_hw_state dpll_hw_state; | |
408 | ||
965e0c48 | 409 | int pipe_bpp; |
6cf86a5e | 410 | struct intel_link_m_n dp_m_n; |
ff9a6750 | 411 | |
439d7ac0 PB |
412 | /* m2_n2 for eDP downclock */ |
413 | struct intel_link_m_n dp_m2_n2; | |
f769cd24 | 414 | bool has_drrs; |
439d7ac0 | 415 | |
ff9a6750 DV |
416 | /* |
417 | * Frequence the dpll for the port should run at. Differs from the | |
3c52f4eb VS |
418 | * adjusted dotclock e.g. for DP or 12bpc hdmi mode. This is also |
419 | * already multiplied by pixel_multiplier. | |
df92b1e6 | 420 | */ |
ff9a6750 DV |
421 | int port_clock; |
422 | ||
6cc5f341 DV |
423 | /* Used by SDVO (and if we ever fix it, HDMI). */ |
424 | unsigned pixel_multiplier; | |
2dd24552 | 425 | |
90a6b7b0 VS |
426 | uint8_t lane_count; |
427 | ||
2dd24552 | 428 | /* Panel fitter controls for gen2-gen4 + VLV */ |
b074cec8 JB |
429 | struct { |
430 | u32 control; | |
431 | u32 pgm_ratios; | |
68fc8742 | 432 | u32 lvds_border_bits; |
b074cec8 JB |
433 | } gmch_pfit; |
434 | ||
435 | /* Panel fitter placement and size for Ironlake+ */ | |
436 | struct { | |
437 | u32 pos; | |
438 | u32 size; | |
fd4daa9c | 439 | bool enabled; |
fabf6e51 | 440 | bool force_thru; |
b074cec8 | 441 | } pch_pfit; |
33d29b14 | 442 | |
ca3a0ff8 | 443 | /* FDI configuration, only valid if has_pch_encoder is set. */ |
33d29b14 | 444 | int fdi_lanes; |
ca3a0ff8 | 445 | struct intel_link_m_n fdi_m_n; |
42db64ef PZ |
446 | |
447 | bool ips_enabled; | |
cf532bb2 VS |
448 | |
449 | bool double_wide; | |
0e32b39c DA |
450 | |
451 | bool dp_encoder_is_mst; | |
452 | int pbn; | |
be41e336 CK |
453 | |
454 | struct intel_crtc_scaler_state scaler_state; | |
99d736a2 ML |
455 | |
456 | /* w/a for waiting 2 vblanks during crtc enable */ | |
457 | enum pipe hsw_workaround_pipe; | |
b8cecdf5 DV |
458 | }; |
459 | ||
262cd2e1 VS |
460 | struct vlv_wm_state { |
461 | struct vlv_pipe_wm wm[3]; | |
462 | struct vlv_sr_wm sr[3]; | |
463 | uint8_t num_active_planes; | |
464 | uint8_t num_levels; | |
465 | uint8_t level; | |
466 | bool cxsr; | |
467 | }; | |
468 | ||
0b2ae6d7 VS |
469 | struct intel_pipe_wm { |
470 | struct intel_wm_level wm[5]; | |
471 | uint32_t linetime; | |
472 | bool fbc_wm_enabled; | |
2a44b76b VS |
473 | bool pipe_enabled; |
474 | bool sprites_enabled; | |
475 | bool sprites_scaled; | |
0b2ae6d7 VS |
476 | }; |
477 | ||
84c33a64 | 478 | struct intel_mmio_flip { |
9362c7c5 | 479 | struct work_struct work; |
bcafc4e3 | 480 | struct drm_i915_private *i915; |
eed29a5b | 481 | struct drm_i915_gem_request *req; |
b2cfe0ab | 482 | struct intel_crtc *crtc; |
84c33a64 SG |
483 | }; |
484 | ||
2ac96d2a PB |
485 | struct skl_pipe_wm { |
486 | struct skl_wm_level wm[8]; | |
487 | struct skl_wm_level trans_wm; | |
488 | uint32_t linetime; | |
489 | }; | |
490 | ||
32b7eeec MR |
491 | /* |
492 | * Tracking of operations that need to be performed at the beginning/end of an | |
493 | * atomic commit, outside the atomic section where interrupts are disabled. | |
494 | * These are generally operations that grab mutexes or might otherwise sleep | |
495 | * and thus can't be run with interrupts disabled. | |
496 | */ | |
497 | struct intel_crtc_atomic_commit { | |
498 | /* Sleepable operations to perform before commit */ | |
499 | bool wait_for_flips; | |
500 | bool disable_fbc; | |
066cf55b | 501 | bool disable_ips; |
852eb00d | 502 | bool disable_cxsr; |
32b7eeec | 503 | bool pre_disable_primary; |
f015c551 | 504 | bool update_wm_pre, update_wm_post; |
ea2c67bb | 505 | unsigned disabled_planes; |
32b7eeec MR |
506 | |
507 | /* Sleepable operations to perform after commit */ | |
508 | unsigned fb_bits; | |
509 | bool wait_vblank; | |
510 | bool update_fbc; | |
511 | bool post_enable_primary; | |
512 | unsigned update_sprite_watermarks; | |
513 | }; | |
514 | ||
79e53945 JB |
515 | struct intel_crtc { |
516 | struct drm_crtc base; | |
80824003 JB |
517 | enum pipe pipe; |
518 | enum plane plane; | |
79e53945 | 519 | u8 lut_r[256], lut_g[256], lut_b[256]; |
08a48469 DV |
520 | /* |
521 | * Whether the crtc and the connected output pipeline is active. Implies | |
522 | * that crtc->enabled is set, i.e. the current mode configuration has | |
523 | * some outputs connected to this crtc. | |
08a48469 DV |
524 | */ |
525 | bool active; | |
6efdf354 | 526 | unsigned long enabled_power_domains; |
652c393a | 527 | bool lowfreq_avail; |
02e792fb | 528 | struct intel_overlay *overlay; |
6b95a207 | 529 | struct intel_unpin_work *unpin_work; |
cda4b7d3 | 530 | |
b4a98e57 CW |
531 | atomic_t unpin_work_count; |
532 | ||
e506a0c6 DV |
533 | /* Display surface base address adjustement for pageflips. Note that on |
534 | * gen4+ this only adjusts up to a tile, offsets within a tile are | |
535 | * handled in the hw itself (with the TILEOFF register). */ | |
536 | unsigned long dspaddr_offset; | |
537 | ||
05394f39 | 538 | struct drm_i915_gem_object *cursor_bo; |
cda4b7d3 | 539 | uint32_t cursor_addr; |
4b0e333e | 540 | uint32_t cursor_cntl; |
dc41c154 | 541 | uint32_t cursor_size; |
4b0e333e | 542 | uint32_t cursor_base; |
4b645f14 | 543 | |
6e3c9717 | 544 | struct intel_crtc_state *config; |
b8cecdf5 | 545 | |
10d83730 VS |
546 | /* reset counter value when the last flip was submitted */ |
547 | unsigned int reset_counter; | |
8664281b PZ |
548 | |
549 | /* Access to these should be protected by dev_priv->irq_lock. */ | |
550 | bool cpu_fifo_underrun_disabled; | |
551 | bool pch_fifo_underrun_disabled; | |
0b2ae6d7 VS |
552 | |
553 | /* per-pipe watermark state */ | |
554 | struct { | |
555 | /* watermarks currently being used */ | |
556 | struct intel_pipe_wm active; | |
2ac96d2a PB |
557 | /* SKL wm values currently in use */ |
558 | struct skl_pipe_wm skl_active; | |
852eb00d VS |
559 | /* allow CxSR on this pipe */ |
560 | bool cxsr_allowed; | |
0b2ae6d7 | 561 | } wm; |
8d7849db | 562 | |
80715b2f | 563 | int scanline_offset; |
32b7eeec | 564 | |
8f539a83 | 565 | unsigned start_vbl_count; |
32b7eeec | 566 | struct intel_crtc_atomic_commit atomic; |
be41e336 CK |
567 | |
568 | /* scalers available on this crtc */ | |
569 | int num_scalers; | |
262cd2e1 VS |
570 | |
571 | struct vlv_wm_state wm_state; | |
79e53945 JB |
572 | }; |
573 | ||
c35426d2 VS |
574 | struct intel_plane_wm_parameters { |
575 | uint32_t horiz_pixels; | |
ed57cb8a | 576 | uint32_t vert_pixels; |
2cd601c6 CK |
577 | /* |
578 | * For packed pixel formats: | |
579 | * bytes_per_pixel - holds bytes per pixel | |
580 | * For planar pixel formats: | |
581 | * bytes_per_pixel - holds bytes per pixel for uv-plane | |
582 | * y_bytes_per_pixel - holds bytes per pixel for y-plane | |
583 | */ | |
c35426d2 | 584 | uint8_t bytes_per_pixel; |
2cd601c6 | 585 | uint8_t y_bytes_per_pixel; |
c35426d2 VS |
586 | bool enabled; |
587 | bool scaled; | |
0fda6568 | 588 | u64 tiling; |
1fc0a8f7 | 589 | unsigned int rotation; |
6eb1a681 | 590 | uint16_t fifo_size; |
c35426d2 VS |
591 | }; |
592 | ||
b840d907 JB |
593 | struct intel_plane { |
594 | struct drm_plane base; | |
7f1f3851 | 595 | int plane; |
b840d907 | 596 | enum pipe pipe; |
2d354c34 | 597 | bool can_scale; |
b840d907 | 598 | int max_downscale; |
a9ff8714 | 599 | uint32_t frontbuffer_bit; |
526682e9 PZ |
600 | |
601 | /* Since we need to change the watermarks before/after | |
602 | * enabling/disabling the planes, we need to store the parameters here | |
603 | * as the other pieces of the struct may not reflect the values we want | |
604 | * for the watermark calculations. Currently only Haswell uses this. | |
605 | */ | |
c35426d2 | 606 | struct intel_plane_wm_parameters wm; |
526682e9 | 607 | |
8e7d688b MR |
608 | /* |
609 | * NOTE: Do not place new plane state fields here (e.g., when adding | |
610 | * new plane properties). New runtime state should now be placed in | |
611 | * the intel_plane_state structure and accessed via drm_plane->state. | |
612 | */ | |
613 | ||
b840d907 | 614 | void (*update_plane)(struct drm_plane *plane, |
b39d53f6 | 615 | struct drm_crtc *crtc, |
b840d907 | 616 | struct drm_framebuffer *fb, |
b840d907 JB |
617 | int crtc_x, int crtc_y, |
618 | unsigned int crtc_w, unsigned int crtc_h, | |
619 | uint32_t x, uint32_t y, | |
620 | uint32_t src_w, uint32_t src_h); | |
b39d53f6 | 621 | void (*disable_plane)(struct drm_plane *plane, |
7fabf5ef | 622 | struct drm_crtc *crtc); |
c59cb179 | 623 | int (*check_plane)(struct drm_plane *plane, |
061e4b8d | 624 | struct intel_crtc_state *crtc_state, |
c59cb179 MR |
625 | struct intel_plane_state *state); |
626 | void (*commit_plane)(struct drm_plane *plane, | |
627 | struct intel_plane_state *state); | |
b840d907 JB |
628 | }; |
629 | ||
b445e3b0 ED |
630 | struct intel_watermark_params { |
631 | unsigned long fifo_size; | |
632 | unsigned long max_wm; | |
633 | unsigned long default_wm; | |
634 | unsigned long guard_size; | |
635 | unsigned long cacheline_size; | |
636 | }; | |
637 | ||
638 | struct cxsr_latency { | |
639 | int is_desktop; | |
640 | int is_ddr3; | |
641 | unsigned long fsb_freq; | |
642 | unsigned long mem_freq; | |
643 | unsigned long display_sr; | |
644 | unsigned long display_hpll_disable; | |
645 | unsigned long cursor_sr; | |
646 | unsigned long cursor_hpll_disable; | |
647 | }; | |
648 | ||
de419ab6 | 649 | #define to_intel_atomic_state(x) container_of(x, struct intel_atomic_state, base) |
79e53945 | 650 | #define to_intel_crtc(x) container_of(x, struct intel_crtc, base) |
10f81c19 | 651 | #define to_intel_crtc_state(x) container_of(x, struct intel_crtc_state, base) |
5daa55eb | 652 | #define to_intel_connector(x) container_of(x, struct intel_connector, base) |
4ef69c7a | 653 | #define to_intel_encoder(x) container_of(x, struct intel_encoder, base) |
79e53945 | 654 | #define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base) |
b840d907 | 655 | #define to_intel_plane(x) container_of(x, struct intel_plane, base) |
ea2c67bb | 656 | #define to_intel_plane_state(x) container_of(x, struct intel_plane_state, base) |
155e6369 | 657 | #define intel_fb_obj(x) (x ? to_intel_framebuffer(x)->obj : NULL) |
79e53945 | 658 | |
f5bbfca3 | 659 | struct intel_hdmi { |
b242b7f7 | 660 | u32 hdmi_reg; |
f5bbfca3 | 661 | int ddc_bus; |
0f2a2a75 | 662 | bool limited_color_range; |
55bc60db | 663 | bool color_range_auto; |
f5bbfca3 ED |
664 | bool has_hdmi_sink; |
665 | bool has_audio; | |
666 | enum hdmi_force_audio force_audio; | |
abedc077 | 667 | bool rgb_quant_range_selectable; |
94a11ddc | 668 | enum hdmi_picture_aspect aspect_ratio; |
f5bbfca3 | 669 | void (*write_infoframe)(struct drm_encoder *encoder, |
178f736a | 670 | enum hdmi_infoframe_type type, |
fff63867 | 671 | const void *frame, ssize_t len); |
687f4d06 | 672 | void (*set_infoframes)(struct drm_encoder *encoder, |
6897b4b5 | 673 | bool enable, |
687f4d06 | 674 | struct drm_display_mode *adjusted_mode); |
e43823ec | 675 | bool (*infoframe_enabled)(struct drm_encoder *encoder); |
f5bbfca3 ED |
676 | }; |
677 | ||
0e32b39c | 678 | struct intel_dp_mst_encoder; |
b091cd92 | 679 | #define DP_MAX_DOWNSTREAM_PORTS 0x10 |
54d63ca6 | 680 | |
fe3cd48d R |
681 | /* |
682 | * enum link_m_n_set: | |
683 | * When platform provides two set of M_N registers for dp, we can | |
684 | * program them and switch between them incase of DRRS. | |
685 | * But When only one such register is provided, we have to program the | |
686 | * required divider value on that registers itself based on the DRRS state. | |
687 | * | |
688 | * M1_N1 : Program dp_m_n on M1_N1 registers | |
689 | * dp_m2_n2 on M2_N2 registers (If supported) | |
690 | * | |
691 | * M2_N2 : Program dp_m2_n2 on M1_N1 registers | |
692 | * M2_N2 registers are not supported | |
693 | */ | |
694 | ||
695 | enum link_m_n_set { | |
696 | /* Sets the m1_n1 and m2_n2 */ | |
697 | M1_N1 = 0, | |
698 | M2_N2 | |
699 | }; | |
700 | ||
621d4c76 RV |
701 | struct sink_crc { |
702 | bool started; | |
703 | u8 last_crc[6]; | |
704 | int last_count; | |
705 | }; | |
706 | ||
54d63ca6 | 707 | struct intel_dp { |
54d63ca6 | 708 | uint32_t output_reg; |
9ed35ab1 | 709 | uint32_t aux_ch_ctl_reg; |
54d63ca6 | 710 | uint32_t DP; |
54d63ca6 SK |
711 | bool has_audio; |
712 | enum hdmi_force_audio force_audio; | |
0f2a2a75 | 713 | bool limited_color_range; |
55bc60db | 714 | bool color_range_auto; |
54d63ca6 | 715 | uint8_t dpcd[DP_RECEIVER_CAP_SIZE]; |
2293bb5c | 716 | uint8_t psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE]; |
b091cd92 | 717 | uint8_t downstream_ports[DP_MAX_DOWNSTREAM_PORTS]; |
94ca719e VS |
718 | /* sink rates as reported by DP_SUPPORTED_LINK_RATES */ |
719 | uint8_t num_sink_rates; | |
720 | int sink_rates[DP_MAX_SUPPORTED_RATES]; | |
621d4c76 | 721 | struct sink_crc sink_crc; |
9d1a1031 | 722 | struct drm_dp_aux aux; |
54d63ca6 SK |
723 | uint8_t train_set[4]; |
724 | int panel_power_up_delay; | |
725 | int panel_power_down_delay; | |
726 | int panel_power_cycle_delay; | |
727 | int backlight_on_delay; | |
728 | int backlight_off_delay; | |
54d63ca6 SK |
729 | struct delayed_work panel_vdd_work; |
730 | bool want_panel_vdd; | |
dce56b3c PZ |
731 | unsigned long last_power_cycle; |
732 | unsigned long last_power_on; | |
733 | unsigned long last_backlight_off; | |
5d42f82a | 734 | |
01527b31 CT |
735 | struct notifier_block edp_notifier; |
736 | ||
a4a5d2f8 VS |
737 | /* |
738 | * Pipe whose power sequencer is currently locked into | |
739 | * this port. Only relevant on VLV/CHV. | |
740 | */ | |
741 | enum pipe pps_pipe; | |
36b5f425 | 742 | struct edp_power_seq pps_delays; |
a4a5d2f8 | 743 | |
06ea66b6 | 744 | bool use_tps3; |
0e32b39c DA |
745 | bool can_mst; /* this port supports mst */ |
746 | bool is_mst; | |
747 | int active_mst_links; | |
748 | /* connector directly attached - won't be use for modeset in mst world */ | |
dd06f90e | 749 | struct intel_connector *attached_connector; |
ec5b01dd | 750 | |
0e32b39c DA |
751 | /* mst connector list */ |
752 | struct intel_dp_mst_encoder *mst_encoders[I915_MAX_PIPES]; | |
753 | struct drm_dp_mst_topology_mgr mst_mgr; | |
754 | ||
ec5b01dd | 755 | uint32_t (*get_aux_clock_divider)(struct intel_dp *dp, int index); |
153b1100 DL |
756 | /* |
757 | * This function returns the value we have to program the AUX_CTL | |
758 | * register with to kick off an AUX transaction. | |
759 | */ | |
760 | uint32_t (*get_aux_send_ctl)(struct intel_dp *dp, | |
761 | bool has_aux_irq, | |
762 | int send_bytes, | |
763 | uint32_t aux_clock_divider); | |
4e96c977 | 764 | bool train_set_valid; |
c5d5ab7a TP |
765 | |
766 | /* Displayport compliance testing */ | |
767 | unsigned long compliance_test_type; | |
559be30c TP |
768 | unsigned long compliance_test_data; |
769 | bool compliance_test_active; | |
54d63ca6 SK |
770 | }; |
771 | ||
da63a9f2 PZ |
772 | struct intel_digital_port { |
773 | struct intel_encoder base; | |
174edf1f | 774 | enum port port; |
bcf53de4 | 775 | u32 saved_port_bits; |
da63a9f2 PZ |
776 | struct intel_dp dp; |
777 | struct intel_hdmi hdmi; | |
b2c5c181 | 778 | enum irqreturn (*hpd_pulse)(struct intel_digital_port *, bool); |
da63a9f2 PZ |
779 | }; |
780 | ||
0e32b39c DA |
781 | struct intel_dp_mst_encoder { |
782 | struct intel_encoder base; | |
783 | enum pipe pipe; | |
784 | struct intel_digital_port *primary; | |
785 | void *port; /* store this opaque as its illegal to dereference it */ | |
786 | }; | |
787 | ||
89b667f8 JB |
788 | static inline int |
789 | vlv_dport_to_channel(struct intel_digital_port *dport) | |
790 | { | |
791 | switch (dport->port) { | |
792 | case PORT_B: | |
00fc31b7 | 793 | case PORT_D: |
e4607fcf | 794 | return DPIO_CH0; |
89b667f8 | 795 | case PORT_C: |
e4607fcf | 796 | return DPIO_CH1; |
89b667f8 JB |
797 | default: |
798 | BUG(); | |
799 | } | |
800 | } | |
801 | ||
eb69b0e5 CML |
802 | static inline int |
803 | vlv_pipe_to_channel(enum pipe pipe) | |
804 | { | |
805 | switch (pipe) { | |
806 | case PIPE_A: | |
807 | case PIPE_C: | |
808 | return DPIO_CH0; | |
809 | case PIPE_B: | |
810 | return DPIO_CH1; | |
811 | default: | |
812 | BUG(); | |
813 | } | |
814 | } | |
815 | ||
f875c15a CW |
816 | static inline struct drm_crtc * |
817 | intel_get_crtc_for_pipe(struct drm_device *dev, int pipe) | |
818 | { | |
819 | struct drm_i915_private *dev_priv = dev->dev_private; | |
820 | return dev_priv->pipe_to_crtc_mapping[pipe]; | |
821 | } | |
822 | ||
417ae147 CW |
823 | static inline struct drm_crtc * |
824 | intel_get_crtc_for_plane(struct drm_device *dev, int plane) | |
825 | { | |
826 | struct drm_i915_private *dev_priv = dev->dev_private; | |
827 | return dev_priv->plane_to_crtc_mapping[plane]; | |
828 | } | |
829 | ||
4e5359cd SF |
830 | struct intel_unpin_work { |
831 | struct work_struct work; | |
b4a98e57 | 832 | struct drm_crtc *crtc; |
ab8d6675 | 833 | struct drm_framebuffer *old_fb; |
05394f39 | 834 | struct drm_i915_gem_object *pending_flip_obj; |
4e5359cd | 835 | struct drm_pending_vblank_event *event; |
e7d841ca CW |
836 | atomic_t pending; |
837 | #define INTEL_FLIP_INACTIVE 0 | |
838 | #define INTEL_FLIP_PENDING 1 | |
839 | #define INTEL_FLIP_COMPLETE 2 | |
75f7f3ec VS |
840 | u32 flip_count; |
841 | u32 gtt_offset; | |
f06cc1b9 | 842 | struct drm_i915_gem_request *flip_queued_req; |
d6bbafa1 CW |
843 | int flip_queued_vblank; |
844 | int flip_ready_vblank; | |
4e5359cd SF |
845 | bool enable_stall_check; |
846 | }; | |
847 | ||
5f1aae65 PZ |
848 | struct intel_load_detect_pipe { |
849 | struct drm_framebuffer *release_fb; | |
850 | bool load_detect_temp; | |
851 | int dpms_mode; | |
852 | }; | |
79e53945 | 853 | |
5f1aae65 PZ |
854 | static inline struct intel_encoder * |
855 | intel_attached_encoder(struct drm_connector *connector) | |
df0e9248 CW |
856 | { |
857 | return to_intel_connector(connector)->encoder; | |
858 | } | |
859 | ||
da63a9f2 PZ |
860 | static inline struct intel_digital_port * |
861 | enc_to_dig_port(struct drm_encoder *encoder) | |
862 | { | |
863 | return container_of(encoder, struct intel_digital_port, base.base); | |
9ff8c9ba ID |
864 | } |
865 | ||
0e32b39c DA |
866 | static inline struct intel_dp_mst_encoder * |
867 | enc_to_mst(struct drm_encoder *encoder) | |
868 | { | |
869 | return container_of(encoder, struct intel_dp_mst_encoder, base.base); | |
870 | } | |
871 | ||
9ff8c9ba ID |
872 | static inline struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder) |
873 | { | |
874 | return &enc_to_dig_port(encoder)->dp; | |
da63a9f2 PZ |
875 | } |
876 | ||
877 | static inline struct intel_digital_port * | |
878 | dp_to_dig_port(struct intel_dp *intel_dp) | |
879 | { | |
880 | return container_of(intel_dp, struct intel_digital_port, dp); | |
881 | } | |
882 | ||
883 | static inline struct intel_digital_port * | |
884 | hdmi_to_dig_port(struct intel_hdmi *intel_hdmi) | |
885 | { | |
886 | return container_of(intel_hdmi, struct intel_digital_port, hdmi); | |
7739c33b PZ |
887 | } |
888 | ||
6af31a65 DL |
889 | /* |
890 | * Returns the number of planes for this pipe, ie the number of sprites + 1 | |
891 | * (primary plane). This doesn't count the cursor plane then. | |
892 | */ | |
893 | static inline unsigned int intel_num_planes(struct intel_crtc *crtc) | |
894 | { | |
895 | return INTEL_INFO(crtc->base.dev)->num_sprites[crtc->pipe] + 1; | |
896 | } | |
5f1aae65 | 897 | |
47339cd9 | 898 | /* intel_fifo_underrun.c */ |
a72e4c9f | 899 | bool intel_set_cpu_fifo_underrun_reporting(struct drm_i915_private *dev_priv, |
87440425 | 900 | enum pipe pipe, bool enable); |
a72e4c9f | 901 | bool intel_set_pch_fifo_underrun_reporting(struct drm_i915_private *dev_priv, |
87440425 PZ |
902 | enum transcoder pch_transcoder, |
903 | bool enable); | |
1f7247c0 DV |
904 | void intel_cpu_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv, |
905 | enum pipe pipe); | |
906 | void intel_pch_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv, | |
907 | enum transcoder pch_transcoder); | |
a72e4c9f | 908 | void i9xx_check_fifo_underruns(struct drm_i915_private *dev_priv); |
47339cd9 DV |
909 | |
910 | /* i915_irq.c */ | |
480c8033 DV |
911 | void gen5_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask); |
912 | void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask); | |
913 | void gen6_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask); | |
914 | void gen6_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask); | |
3cc134e3 | 915 | void gen6_reset_rps_interrupts(struct drm_device *dev); |
b900b949 ID |
916 | void gen6_enable_rps_interrupts(struct drm_device *dev); |
917 | void gen6_disable_rps_interrupts(struct drm_device *dev); | |
59d02a1f | 918 | u32 gen6_sanitize_rps_pm_mask(struct drm_i915_private *dev_priv, u32 mask); |
b963291c DV |
919 | void intel_runtime_pm_disable_interrupts(struct drm_i915_private *dev_priv); |
920 | void intel_runtime_pm_enable_interrupts(struct drm_i915_private *dev_priv); | |
9df7575f JB |
921 | static inline bool intel_irqs_enabled(struct drm_i915_private *dev_priv) |
922 | { | |
923 | /* | |
924 | * We only use drm_irq_uninstall() at unload and VT switch, so | |
925 | * this is the only thing we need to check. | |
926 | */ | |
2aeb7d3a | 927 | return dev_priv->pm.irqs_enabled; |
9df7575f JB |
928 | } |
929 | ||
a225f079 | 930 | int intel_get_crtc_scanline(struct intel_crtc *crtc); |
4c6c03be DL |
931 | void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv, |
932 | unsigned int pipe_mask); | |
5f1aae65 | 933 | |
5f1aae65 | 934 | /* intel_crt.c */ |
87440425 | 935 | void intel_crt_init(struct drm_device *dev); |
5f1aae65 PZ |
936 | |
937 | ||
938 | /* intel_ddi.c */ | |
87440425 PZ |
939 | void intel_prepare_ddi(struct drm_device *dev); |
940 | void hsw_fdi_link_train(struct drm_crtc *crtc); | |
941 | void intel_ddi_init(struct drm_device *dev, enum port port); | |
942 | enum port intel_ddi_get_encoder_port(struct intel_encoder *intel_encoder); | |
943 | bool intel_ddi_get_hw_state(struct intel_encoder *encoder, enum pipe *pipe); | |
87440425 PZ |
944 | void intel_ddi_pll_init(struct drm_device *dev); |
945 | void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc); | |
946 | void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv, | |
947 | enum transcoder cpu_transcoder); | |
948 | void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc); | |
949 | void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc); | |
190f68c5 ACO |
950 | bool intel_ddi_pll_select(struct intel_crtc *crtc, |
951 | struct intel_crtc_state *crtc_state); | |
87440425 PZ |
952 | void intel_ddi_set_pipe_settings(struct drm_crtc *crtc); |
953 | void intel_ddi_prepare_link_retrain(struct drm_encoder *encoder); | |
954 | bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector); | |
955 | void intel_ddi_fdi_disable(struct drm_crtc *crtc); | |
956 | void intel_ddi_get_config(struct intel_encoder *encoder, | |
5cec258b | 957 | struct intel_crtc_state *pipe_config); |
bcddf610 S |
958 | struct intel_encoder * |
959 | intel_ddi_get_crtc_new_encoder(struct intel_crtc_state *crtc_state); | |
5f1aae65 | 960 | |
44905a27 | 961 | void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder); |
0e32b39c | 962 | void intel_ddi_clock_get(struct intel_encoder *encoder, |
5cec258b | 963 | struct intel_crtc_state *pipe_config); |
0e32b39c | 964 | void intel_ddi_set_vc_payload_alloc(struct drm_crtc *crtc, bool state); |
f8896f5d | 965 | uint32_t ddi_signal_levels(struct intel_dp *intel_dp); |
5f1aae65 | 966 | |
b680c37a | 967 | /* intel_frontbuffer.c */ |
f99d7069 | 968 | void intel_fb_obj_invalidate(struct drm_i915_gem_object *obj, |
a4001f1b | 969 | enum fb_op_origin origin); |
f99d7069 DV |
970 | void intel_frontbuffer_flip_prepare(struct drm_device *dev, |
971 | unsigned frontbuffer_bits); | |
972 | void intel_frontbuffer_flip_complete(struct drm_device *dev, | |
973 | unsigned frontbuffer_bits); | |
f99d7069 | 974 | void intel_frontbuffer_flip(struct drm_device *dev, |
fdbff928 | 975 | unsigned frontbuffer_bits); |
6761dd31 TU |
976 | unsigned int intel_fb_align_height(struct drm_device *dev, |
977 | unsigned int height, | |
978 | uint32_t pixel_format, | |
979 | uint64_t fb_format_modifier); | |
de152b62 RV |
980 | void intel_fb_obj_flush(struct drm_i915_gem_object *obj, bool retire, |
981 | enum fb_op_origin origin); | |
b321803d DL |
982 | u32 intel_fb_stride_alignment(struct drm_device *dev, uint64_t fb_modifier, |
983 | uint32_t pixel_format); | |
b680c37a | 984 | |
7c10a2b5 JN |
985 | /* intel_audio.c */ |
986 | void intel_init_audio(struct drm_device *dev); | |
69bfe1a9 JN |
987 | void intel_audio_codec_enable(struct intel_encoder *encoder); |
988 | void intel_audio_codec_disable(struct intel_encoder *encoder); | |
58fddc28 ID |
989 | void i915_audio_component_init(struct drm_i915_private *dev_priv); |
990 | void i915_audio_component_cleanup(struct drm_i915_private *dev_priv); | |
7c10a2b5 | 991 | |
b680c37a | 992 | /* intel_display.c */ |
65a3fea0 | 993 | extern const struct drm_plane_funcs intel_plane_funcs; |
b680c37a DV |
994 | bool intel_has_pending_fb_unpin(struct drm_device *dev); |
995 | int intel_pch_rawclk(struct drm_device *dev); | |
996 | void intel_mark_busy(struct drm_device *dev); | |
87440425 PZ |
997 | void intel_mark_idle(struct drm_device *dev); |
998 | void intel_crtc_restore_mode(struct drm_crtc *crtc); | |
70e0bd74 | 999 | int intel_display_suspend(struct drm_device *dev); |
87440425 | 1000 | void intel_encoder_destroy(struct drm_encoder *encoder); |
08d9bc92 ACO |
1001 | int intel_connector_init(struct intel_connector *); |
1002 | struct intel_connector *intel_connector_alloc(void); | |
87440425 | 1003 | bool intel_connector_get_hw_state(struct intel_connector *connector); |
b0ea7d37 DL |
1004 | bool ibx_digital_port_connected(struct drm_i915_private *dev_priv, |
1005 | struct intel_digital_port *port); | |
87440425 PZ |
1006 | void intel_connector_attach_encoder(struct intel_connector *connector, |
1007 | struct intel_encoder *encoder); | |
1008 | struct drm_encoder *intel_best_encoder(struct drm_connector *connector); | |
1009 | struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev, | |
1010 | struct drm_crtc *crtc); | |
752aa88a | 1011 | enum pipe intel_get_pipe_from_connector(struct intel_connector *connector); |
08d7b3d1 CW |
1012 | int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data, |
1013 | struct drm_file *file_priv); | |
87440425 PZ |
1014 | enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv, |
1015 | enum pipe pipe); | |
4093561b | 1016 | bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type); |
4f905cf9 DV |
1017 | static inline void |
1018 | intel_wait_for_vblank(struct drm_device *dev, int pipe) | |
1019 | { | |
1020 | drm_wait_one_vblank(dev, pipe); | |
1021 | } | |
87440425 | 1022 | int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp); |
e4607fcf | 1023 | void vlv_wait_port_ready(struct drm_i915_private *dev_priv, |
9b6de0a1 VS |
1024 | struct intel_digital_port *dport, |
1025 | unsigned int expected_mask); | |
87440425 PZ |
1026 | bool intel_get_load_detect_pipe(struct drm_connector *connector, |
1027 | struct drm_display_mode *mode, | |
51fd371b RC |
1028 | struct intel_load_detect_pipe *old, |
1029 | struct drm_modeset_acquire_ctx *ctx); | |
87440425 | 1030 | void intel_release_load_detect_pipe(struct drm_connector *connector, |
49172fee ACO |
1031 | struct intel_load_detect_pipe *old, |
1032 | struct drm_modeset_acquire_ctx *ctx); | |
850c4cdc TU |
1033 | int intel_pin_and_fence_fb_obj(struct drm_plane *plane, |
1034 | struct drm_framebuffer *fb, | |
82bc3b2d | 1035 | const struct drm_plane_state *plane_state, |
91af127f JH |
1036 | struct intel_engine_cs *pipelined, |
1037 | struct drm_i915_gem_request **pipelined_request); | |
a8bb6818 DV |
1038 | struct drm_framebuffer * |
1039 | __intel_framebuffer_create(struct drm_device *dev, | |
87440425 PZ |
1040 | struct drm_mode_fb_cmd2 *mode_cmd, |
1041 | struct drm_i915_gem_object *obj); | |
87440425 PZ |
1042 | void intel_prepare_page_flip(struct drm_device *dev, int plane); |
1043 | void intel_finish_page_flip(struct drm_device *dev, int pipe); | |
1044 | void intel_finish_page_flip_plane(struct drm_device *dev, int plane); | |
d6bbafa1 | 1045 | void intel_check_page_flip(struct drm_device *dev, int pipe); |
6beb8c23 | 1046 | int intel_prepare_plane_fb(struct drm_plane *plane, |
d136dfee TU |
1047 | struct drm_framebuffer *fb, |
1048 | const struct drm_plane_state *new_state); | |
38f3ce3a | 1049 | void intel_cleanup_plane_fb(struct drm_plane *plane, |
d136dfee TU |
1050 | struct drm_framebuffer *fb, |
1051 | const struct drm_plane_state *old_state); | |
a98b3431 MR |
1052 | int intel_plane_atomic_get_property(struct drm_plane *plane, |
1053 | const struct drm_plane_state *state, | |
1054 | struct drm_property *property, | |
1055 | uint64_t *val); | |
1056 | int intel_plane_atomic_set_property(struct drm_plane *plane, | |
1057 | struct drm_plane_state *state, | |
1058 | struct drm_property *property, | |
1059 | uint64_t val); | |
da20eabd ML |
1060 | int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state, |
1061 | struct drm_plane_state *plane_state); | |
716c2e55 | 1062 | |
50470bb0 TU |
1063 | unsigned int |
1064 | intel_tile_height(struct drm_device *dev, uint32_t pixel_format, | |
1065 | uint64_t fb_format_modifier); | |
1066 | ||
121920fa TU |
1067 | static inline bool |
1068 | intel_rotation_90_or_270(unsigned int rotation) | |
1069 | { | |
1070 | return rotation & (BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270)); | |
1071 | } | |
1072 | ||
3b7a5119 SJ |
1073 | void intel_create_rotation_property(struct drm_device *dev, |
1074 | struct intel_plane *plane); | |
1075 | ||
716c2e55 | 1076 | /* shared dpll functions */ |
5f1aae65 | 1077 | struct intel_shared_dpll *intel_crtc_to_shared_dpll(struct intel_crtc *crtc); |
55607e8a DV |
1078 | void assert_shared_dpll(struct drm_i915_private *dev_priv, |
1079 | struct intel_shared_dpll *pll, | |
1080 | bool state); | |
1081 | #define assert_shared_dpll_enabled(d, p) assert_shared_dpll(d, p, true) | |
1082 | #define assert_shared_dpll_disabled(d, p) assert_shared_dpll(d, p, false) | |
190f68c5 ACO |
1083 | struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc, |
1084 | struct intel_crtc_state *state); | |
716c2e55 | 1085 | |
d288f65f VS |
1086 | void vlv_force_pll_on(struct drm_device *dev, enum pipe pipe, |
1087 | const struct dpll *dpll); | |
1088 | void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe); | |
1089 | ||
716c2e55 | 1090 | /* modesetting asserts */ |
b680c37a DV |
1091 | void assert_panel_unlocked(struct drm_i915_private *dev_priv, |
1092 | enum pipe pipe); | |
55607e8a DV |
1093 | void assert_pll(struct drm_i915_private *dev_priv, |
1094 | enum pipe pipe, bool state); | |
1095 | #define assert_pll_enabled(d, p) assert_pll(d, p, true) | |
1096 | #define assert_pll_disabled(d, p) assert_pll(d, p, false) | |
1097 | void assert_fdi_rx_pll(struct drm_i915_private *dev_priv, | |
1098 | enum pipe pipe, bool state); | |
1099 | #define assert_fdi_rx_pll_enabled(d, p) assert_fdi_rx_pll(d, p, true) | |
1100 | #define assert_fdi_rx_pll_disabled(d, p) assert_fdi_rx_pll(d, p, false) | |
87440425 | 1101 | void assert_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, bool state); |
b840d907 JB |
1102 | #define assert_pipe_enabled(d, p) assert_pipe(d, p, true) |
1103 | #define assert_pipe_disabled(d, p) assert_pipe(d, p, false) | |
4e9a86b6 VS |
1104 | unsigned long intel_gen4_compute_page_offset(struct drm_i915_private *dev_priv, |
1105 | int *x, int *y, | |
87440425 PZ |
1106 | unsigned int tiling_mode, |
1107 | unsigned int bpp, | |
1108 | unsigned int pitch); | |
7514747d VS |
1109 | void intel_prepare_reset(struct drm_device *dev); |
1110 | void intel_finish_reset(struct drm_device *dev); | |
a14cb6fc PZ |
1111 | void hsw_enable_pc8(struct drm_i915_private *dev_priv); |
1112 | void hsw_disable_pc8(struct drm_i915_private *dev_priv); | |
f8437dd1 VK |
1113 | void broxton_init_cdclk(struct drm_device *dev); |
1114 | void broxton_uninit_cdclk(struct drm_device *dev); | |
5c6706e5 VK |
1115 | void broxton_ddi_phy_init(struct drm_device *dev); |
1116 | void broxton_ddi_phy_uninit(struct drm_device *dev); | |
664326f8 SK |
1117 | void bxt_enable_dc9(struct drm_i915_private *dev_priv); |
1118 | void bxt_disable_dc9(struct drm_i915_private *dev_priv); | |
5d96d8af DL |
1119 | void skl_init_cdclk(struct drm_i915_private *dev_priv); |
1120 | void skl_uninit_cdclk(struct drm_i915_private *dev_priv); | |
87440425 | 1121 | void intel_dp_get_m_n(struct intel_crtc *crtc, |
5cec258b | 1122 | struct intel_crtc_state *pipe_config); |
fe3cd48d | 1123 | void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n); |
87440425 PZ |
1124 | int intel_dotclock_calculate(int link_freq, const struct intel_link_m_n *m_n); |
1125 | void | |
5cec258b | 1126 | ironlake_check_encoder_dotclock(const struct intel_crtc_state *pipe_config, |
5f1aae65 | 1127 | int dotclock); |
5ab7b0b7 ID |
1128 | bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock, |
1129 | intel_clock_t *best_clock); | |
dccbea3b ID |
1130 | int chv_calc_dpll_params(int refclk, intel_clock_t *pll_clock); |
1131 | ||
87440425 | 1132 | bool intel_crtc_active(struct drm_crtc *crtc); |
20bc8673 VS |
1133 | void hsw_enable_ips(struct intel_crtc *crtc); |
1134 | void hsw_disable_ips(struct intel_crtc *crtc); | |
319be8ae ID |
1135 | enum intel_display_power_domain |
1136 | intel_display_port_power_domain(struct intel_encoder *intel_encoder); | |
f6a83288 | 1137 | void intel_mode_from_pipe_config(struct drm_display_mode *mode, |
5cec258b | 1138 | struct intel_crtc_state *pipe_config); |
46a55d30 | 1139 | void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc); |
e2fcdaa9 | 1140 | void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file); |
86adf9d7 | 1141 | |
e435d6e5 | 1142 | int skl_update_scaler_crtc(struct intel_crtc_state *crtc_state); |
6156a456 | 1143 | int skl_max_scale(struct intel_crtc *crtc, struct intel_crtc_state *crtc_state); |
8ea30864 | 1144 | |
121920fa TU |
1145 | unsigned long intel_plane_obj_offset(struct intel_plane *intel_plane, |
1146 | struct drm_i915_gem_object *obj); | |
6156a456 CK |
1147 | u32 skl_plane_ctl_format(uint32_t pixel_format); |
1148 | u32 skl_plane_ctl_tiling(uint64_t fb_modifier); | |
1149 | u32 skl_plane_ctl_rotation(unsigned int rotation); | |
121920fa | 1150 | |
eb805623 DV |
1151 | /* intel_csr.c */ |
1152 | void intel_csr_ucode_init(struct drm_device *dev); | |
dc174300 SS |
1153 | enum csr_state intel_csr_load_status_get(struct drm_i915_private *dev_priv); |
1154 | void intel_csr_load_status_set(struct drm_i915_private *dev_priv, | |
1155 | enum csr_state state); | |
eb805623 DV |
1156 | void intel_csr_load_program(struct drm_device *dev); |
1157 | void intel_csr_ucode_fini(struct drm_device *dev); | |
5aefb239 | 1158 | void assert_csr_loaded(struct drm_i915_private *dev_priv); |
eb805623 | 1159 | |
5f1aae65 | 1160 | /* intel_dp.c */ |
87440425 PZ |
1161 | void intel_dp_init(struct drm_device *dev, int output_reg, enum port port); |
1162 | bool intel_dp_init_connector(struct intel_digital_port *intel_dig_port, | |
1163 | struct intel_connector *intel_connector); | |
87440425 PZ |
1164 | void intel_dp_start_link_train(struct intel_dp *intel_dp); |
1165 | void intel_dp_complete_link_train(struct intel_dp *intel_dp); | |
1166 | void intel_dp_stop_link_train(struct intel_dp *intel_dp); | |
1167 | void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode); | |
1168 | void intel_dp_encoder_destroy(struct drm_encoder *encoder); | |
d2e216d0 | 1169 | int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc); |
87440425 | 1170 | bool intel_dp_compute_config(struct intel_encoder *encoder, |
5cec258b | 1171 | struct intel_crtc_state *pipe_config); |
5d8a7752 | 1172 | bool intel_dp_is_edp(struct drm_device *dev, enum port port); |
b2c5c181 DV |
1173 | enum irqreturn intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, |
1174 | bool long_hpd); | |
4be73780 DV |
1175 | void intel_edp_backlight_on(struct intel_dp *intel_dp); |
1176 | void intel_edp_backlight_off(struct intel_dp *intel_dp); | |
24f3e092 | 1177 | void intel_edp_panel_vdd_on(struct intel_dp *intel_dp); |
4be73780 DV |
1178 | void intel_edp_panel_on(struct intel_dp *intel_dp); |
1179 | void intel_edp_panel_off(struct intel_dp *intel_dp); | |
0e32b39c DA |
1180 | void intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector); |
1181 | void intel_dp_mst_suspend(struct drm_device *dev); | |
1182 | void intel_dp_mst_resume(struct drm_device *dev); | |
50fec21a | 1183 | int intel_dp_max_link_rate(struct intel_dp *intel_dp); |
ed4e9c1d | 1184 | int intel_dp_rate_select(struct intel_dp *intel_dp, int rate); |
0e32b39c | 1185 | void intel_dp_hot_plug(struct intel_encoder *intel_encoder); |
773538e8 | 1186 | void vlv_power_sequencer_reset(struct drm_i915_private *dev_priv); |
0bc12bcb | 1187 | uint32_t intel_dp_pack_aux(const uint8_t *src, int src_bytes); |
4a3b8769 | 1188 | void intel_plane_destroy(struct drm_plane *plane); |
c395578e VK |
1189 | void intel_edp_drrs_enable(struct intel_dp *intel_dp); |
1190 | void intel_edp_drrs_disable(struct intel_dp *intel_dp); | |
a93fad0f VK |
1191 | void intel_edp_drrs_invalidate(struct drm_device *dev, |
1192 | unsigned frontbuffer_bits); | |
1193 | void intel_edp_drrs_flush(struct drm_device *dev, unsigned frontbuffer_bits); | |
0bc12bcb | 1194 | |
0e32b39c DA |
1195 | /* intel_dp_mst.c */ |
1196 | int intel_dp_mst_encoder_init(struct intel_digital_port *intel_dig_port, int conn_id); | |
1197 | void intel_dp_mst_encoder_cleanup(struct intel_digital_port *intel_dig_port); | |
5f1aae65 | 1198 | /* intel_dsi.c */ |
4328633d | 1199 | void intel_dsi_init(struct drm_device *dev); |
5f1aae65 PZ |
1200 | |
1201 | ||
1202 | /* intel_dvo.c */ | |
87440425 | 1203 | void intel_dvo_init(struct drm_device *dev); |
5f1aae65 PZ |
1204 | |
1205 | ||
0632fef6 | 1206 | /* legacy fbdev emulation in intel_fbdev.c */ |
4520f53a DV |
1207 | #ifdef CONFIG_DRM_I915_FBDEV |
1208 | extern int intel_fbdev_init(struct drm_device *dev); | |
d1d70677 | 1209 | extern void intel_fbdev_initial_config(void *data, async_cookie_t cookie); |
4520f53a | 1210 | extern void intel_fbdev_fini(struct drm_device *dev); |
82e3b8c1 | 1211 | extern void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous); |
0632fef6 DV |
1212 | extern void intel_fbdev_output_poll_changed(struct drm_device *dev); |
1213 | extern void intel_fbdev_restore_mode(struct drm_device *dev); | |
4520f53a DV |
1214 | #else |
1215 | static inline int intel_fbdev_init(struct drm_device *dev) | |
1216 | { | |
1217 | return 0; | |
1218 | } | |
5f1aae65 | 1219 | |
d1d70677 | 1220 | static inline void intel_fbdev_initial_config(void *data, async_cookie_t cookie) |
4520f53a DV |
1221 | { |
1222 | } | |
1223 | ||
1224 | static inline void intel_fbdev_fini(struct drm_device *dev) | |
1225 | { | |
1226 | } | |
1227 | ||
82e3b8c1 | 1228 | static inline void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous) |
4520f53a DV |
1229 | { |
1230 | } | |
1231 | ||
0632fef6 | 1232 | static inline void intel_fbdev_restore_mode(struct drm_device *dev) |
4520f53a DV |
1233 | { |
1234 | } | |
1235 | #endif | |
5f1aae65 | 1236 | |
7ff0ebcc | 1237 | /* intel_fbc.c */ |
7733b49b PZ |
1238 | bool intel_fbc_enabled(struct drm_i915_private *dev_priv); |
1239 | void intel_fbc_update(struct drm_i915_private *dev_priv); | |
7ff0ebcc | 1240 | void intel_fbc_init(struct drm_i915_private *dev_priv); |
7733b49b | 1241 | void intel_fbc_disable(struct drm_i915_private *dev_priv); |
25ad93fd | 1242 | void intel_fbc_disable_crtc(struct intel_crtc *crtc); |
dbef0f15 PZ |
1243 | void intel_fbc_invalidate(struct drm_i915_private *dev_priv, |
1244 | unsigned int frontbuffer_bits, | |
1245 | enum fb_op_origin origin); | |
1246 | void intel_fbc_flush(struct drm_i915_private *dev_priv, | |
6f4551fe | 1247 | unsigned int frontbuffer_bits, enum fb_op_origin origin); |
2e8144a5 | 1248 | const char *intel_no_fbc_reason_str(enum no_fbc_reason reason); |
7733b49b | 1249 | void intel_fbc_cleanup_cfb(struct drm_i915_private *dev_priv); |
7ff0ebcc | 1250 | |
5f1aae65 | 1251 | /* intel_hdmi.c */ |
87440425 PZ |
1252 | void intel_hdmi_init(struct drm_device *dev, int hdmi_reg, enum port port); |
1253 | void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port, | |
1254 | struct intel_connector *intel_connector); | |
1255 | struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder); | |
1256 | bool intel_hdmi_compute_config(struct intel_encoder *encoder, | |
5cec258b | 1257 | struct intel_crtc_state *pipe_config); |
5f1aae65 PZ |
1258 | |
1259 | ||
1260 | /* intel_lvds.c */ | |
87440425 PZ |
1261 | void intel_lvds_init(struct drm_device *dev); |
1262 | bool intel_is_dual_link_lvds(struct drm_device *dev); | |
5f1aae65 PZ |
1263 | |
1264 | ||
1265 | /* intel_modes.c */ | |
1266 | int intel_connector_update_modes(struct drm_connector *connector, | |
87440425 | 1267 | struct edid *edid); |
5f1aae65 | 1268 | int intel_ddc_get_modes(struct drm_connector *c, struct i2c_adapter *adapter); |
87440425 PZ |
1269 | void intel_attach_force_audio_property(struct drm_connector *connector); |
1270 | void intel_attach_broadcast_rgb_property(struct drm_connector *connector); | |
5f1aae65 PZ |
1271 | |
1272 | ||
1273 | /* intel_overlay.c */ | |
87440425 PZ |
1274 | void intel_setup_overlay(struct drm_device *dev); |
1275 | void intel_cleanup_overlay(struct drm_device *dev); | |
1276 | int intel_overlay_switch_off(struct intel_overlay *overlay); | |
1277 | int intel_overlay_put_image(struct drm_device *dev, void *data, | |
1278 | struct drm_file *file_priv); | |
1279 | int intel_overlay_attrs(struct drm_device *dev, void *data, | |
1280 | struct drm_file *file_priv); | |
1362b776 | 1281 | void intel_overlay_reset(struct drm_i915_private *dev_priv); |
5f1aae65 PZ |
1282 | |
1283 | ||
1284 | /* intel_panel.c */ | |
87440425 | 1285 | int intel_panel_init(struct intel_panel *panel, |
4b6ed685 VK |
1286 | struct drm_display_mode *fixed_mode, |
1287 | struct drm_display_mode *downclock_mode); | |
87440425 PZ |
1288 | void intel_panel_fini(struct intel_panel *panel); |
1289 | void intel_fixed_panel_mode(const struct drm_display_mode *fixed_mode, | |
1290 | struct drm_display_mode *adjusted_mode); | |
1291 | void intel_pch_panel_fitting(struct intel_crtc *crtc, | |
5cec258b | 1292 | struct intel_crtc_state *pipe_config, |
87440425 PZ |
1293 | int fitting_mode); |
1294 | void intel_gmch_panel_fitting(struct intel_crtc *crtc, | |
5cec258b | 1295 | struct intel_crtc_state *pipe_config, |
87440425 | 1296 | int fitting_mode); |
6dda730e JN |
1297 | void intel_panel_set_backlight_acpi(struct intel_connector *connector, |
1298 | u32 level, u32 max); | |
6517d273 | 1299 | int intel_panel_setup_backlight(struct drm_connector *connector, enum pipe pipe); |
752aa88a JB |
1300 | void intel_panel_enable_backlight(struct intel_connector *connector); |
1301 | void intel_panel_disable_backlight(struct intel_connector *connector); | |
db31af1d | 1302 | void intel_panel_destroy_backlight(struct drm_connector *connector); |
7bd688cd | 1303 | void intel_panel_init_backlight_funcs(struct drm_device *dev); |
87440425 | 1304 | enum drm_connector_status intel_panel_detect(struct drm_device *dev); |
ec9ed197 VK |
1305 | extern struct drm_display_mode *intel_find_panel_downclock( |
1306 | struct drm_device *dev, | |
1307 | struct drm_display_mode *fixed_mode, | |
1308 | struct drm_connector *connector); | |
0962c3c9 VS |
1309 | void intel_backlight_register(struct drm_device *dev); |
1310 | void intel_backlight_unregister(struct drm_device *dev); | |
1311 | ||
5f1aae65 | 1312 | |
0bc12bcb | 1313 | /* intel_psr.c */ |
0bc12bcb RV |
1314 | void intel_psr_enable(struct intel_dp *intel_dp); |
1315 | void intel_psr_disable(struct intel_dp *intel_dp); | |
1316 | void intel_psr_invalidate(struct drm_device *dev, | |
20c8838b | 1317 | unsigned frontbuffer_bits); |
0bc12bcb | 1318 | void intel_psr_flush(struct drm_device *dev, |
169de131 RV |
1319 | unsigned frontbuffer_bits, |
1320 | enum fb_op_origin origin); | |
0bc12bcb | 1321 | void intel_psr_init(struct drm_device *dev); |
20c8838b DV |
1322 | void intel_psr_single_frame_update(struct drm_device *dev, |
1323 | unsigned frontbuffer_bits); | |
0bc12bcb | 1324 | |
9c065a7d DV |
1325 | /* intel_runtime_pm.c */ |
1326 | int intel_power_domains_init(struct drm_i915_private *); | |
f458ebbc | 1327 | void intel_power_domains_fini(struct drm_i915_private *); |
9c065a7d | 1328 | void intel_power_domains_init_hw(struct drm_i915_private *dev_priv); |
f458ebbc | 1329 | void intel_runtime_pm_enable(struct drm_i915_private *dev_priv); |
9c065a7d | 1330 | |
f458ebbc DV |
1331 | bool intel_display_power_is_enabled(struct drm_i915_private *dev_priv, |
1332 | enum intel_display_power_domain domain); | |
1333 | bool __intel_display_power_is_enabled(struct drm_i915_private *dev_priv, | |
1334 | enum intel_display_power_domain domain); | |
9c065a7d DV |
1335 | void intel_display_power_get(struct drm_i915_private *dev_priv, |
1336 | enum intel_display_power_domain domain); | |
1337 | void intel_display_power_put(struct drm_i915_private *dev_priv, | |
1338 | enum intel_display_power_domain domain); | |
1339 | void intel_aux_display_runtime_get(struct drm_i915_private *dev_priv); | |
1340 | void intel_aux_display_runtime_put(struct drm_i915_private *dev_priv); | |
1341 | void intel_runtime_pm_get(struct drm_i915_private *dev_priv); | |
1342 | void intel_runtime_pm_get_noresume(struct drm_i915_private *dev_priv); | |
1343 | void intel_runtime_pm_put(struct drm_i915_private *dev_priv); | |
1344 | ||
d9bc89d9 DV |
1345 | void intel_display_set_init_power(struct drm_i915_private *dev, bool enable); |
1346 | ||
5f1aae65 | 1347 | /* intel_pm.c */ |
87440425 PZ |
1348 | void intel_init_clock_gating(struct drm_device *dev); |
1349 | void intel_suspend_hw(struct drm_device *dev); | |
546c81fd | 1350 | int ilk_wm_max_level(const struct drm_device *dev); |
87440425 PZ |
1351 | void intel_update_watermarks(struct drm_crtc *crtc); |
1352 | void intel_update_sprite_watermarks(struct drm_plane *plane, | |
1353 | struct drm_crtc *crtc, | |
ed57cb8a DL |
1354 | uint32_t sprite_width, |
1355 | uint32_t sprite_height, | |
1356 | int pixel_size, | |
87440425 PZ |
1357 | bool enabled, bool scaled); |
1358 | void intel_init_pm(struct drm_device *dev); | |
f742a552 | 1359 | void intel_pm_setup(struct drm_device *dev); |
87440425 PZ |
1360 | void intel_gpu_ips_init(struct drm_i915_private *dev_priv); |
1361 | void intel_gpu_ips_teardown(void); | |
ae48434c ID |
1362 | void intel_init_gt_powersave(struct drm_device *dev); |
1363 | void intel_cleanup_gt_powersave(struct drm_device *dev); | |
87440425 PZ |
1364 | void intel_enable_gt_powersave(struct drm_device *dev); |
1365 | void intel_disable_gt_powersave(struct drm_device *dev); | |
156c7ca0 | 1366 | void intel_suspend_gt_powersave(struct drm_device *dev); |
c6df39b5 | 1367 | void intel_reset_gt_powersave(struct drm_device *dev); |
c67a470b | 1368 | void gen6_update_ring_freq(struct drm_device *dev); |
43cf3bf0 CW |
1369 | void gen6_rps_busy(struct drm_i915_private *dev_priv); |
1370 | void gen6_rps_reset_ei(struct drm_i915_private *dev_priv); | |
076e29f2 | 1371 | void gen6_rps_idle(struct drm_i915_private *dev_priv); |
1854d5ca | 1372 | void gen6_rps_boost(struct drm_i915_private *dev_priv, |
e61b9958 CW |
1373 | struct intel_rps_client *rps, |
1374 | unsigned long submitted); | |
6ad790c0 | 1375 | void intel_queue_rps_boost_for_request(struct drm_device *dev, |
eed29a5b | 1376 | struct drm_i915_gem_request *req); |
6eb1a681 | 1377 | void vlv_wm_get_hw_state(struct drm_device *dev); |
243e6a44 | 1378 | void ilk_wm_get_hw_state(struct drm_device *dev); |
3078999f | 1379 | void skl_wm_get_hw_state(struct drm_device *dev); |
08db6652 DL |
1380 | void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv, |
1381 | struct skl_ddb_allocation *ddb /* out */); | |
8cfb3407 | 1382 | uint32_t ilk_pipe_pixel_rate(const struct intel_crtc_state *pipe_config); |
72662e10 | 1383 | |
5f1aae65 | 1384 | /* intel_sdvo.c */ |
87440425 | 1385 | bool intel_sdvo_init(struct drm_device *dev, uint32_t sdvo_reg, bool is_sdvob); |
96a02917 | 1386 | |
2b28bb1b | 1387 | |
5f1aae65 | 1388 | /* intel_sprite.c */ |
87440425 | 1389 | int intel_plane_init(struct drm_device *dev, enum pipe pipe, int plane); |
87440425 PZ |
1390 | int intel_sprite_set_colorkey(struct drm_device *dev, void *data, |
1391 | struct drm_file *file_priv); | |
8f539a83 | 1392 | void intel_pipe_update_start(struct intel_crtc *crtc, |
9362c7c5 ACO |
1393 | uint32_t *start_vbl_count); |
1394 | void intel_pipe_update_end(struct intel_crtc *crtc, u32 start_vbl_count); | |
5f1aae65 PZ |
1395 | |
1396 | /* intel_tv.c */ | |
87440425 | 1397 | void intel_tv_init(struct drm_device *dev); |
20ddf665 | 1398 | |
ea2c67bb | 1399 | /* intel_atomic.c */ |
2545e4a6 MR |
1400 | int intel_connector_atomic_get_property(struct drm_connector *connector, |
1401 | const struct drm_connector_state *state, | |
1402 | struct drm_property *property, | |
1403 | uint64_t *val); | |
1356837e MR |
1404 | struct drm_crtc_state *intel_crtc_duplicate_state(struct drm_crtc *crtc); |
1405 | void intel_crtc_destroy_state(struct drm_crtc *crtc, | |
1406 | struct drm_crtc_state *state); | |
de419ab6 ML |
1407 | struct drm_atomic_state *intel_atomic_state_alloc(struct drm_device *dev); |
1408 | void intel_atomic_state_clear(struct drm_atomic_state *); | |
1409 | struct intel_shared_dpll_config * | |
1410 | intel_atomic_get_shared_dpll_state(struct drm_atomic_state *s); | |
1411 | ||
10f81c19 ACO |
1412 | static inline struct intel_crtc_state * |
1413 | intel_atomic_get_crtc_state(struct drm_atomic_state *state, | |
1414 | struct intel_crtc *crtc) | |
1415 | { | |
1416 | struct drm_crtc_state *crtc_state; | |
1417 | crtc_state = drm_atomic_get_crtc_state(state, &crtc->base); | |
1418 | if (IS_ERR(crtc_state)) | |
0b6cc188 | 1419 | return ERR_CAST(crtc_state); |
10f81c19 ACO |
1420 | |
1421 | return to_intel_crtc_state(crtc_state); | |
1422 | } | |
d03c93d4 CK |
1423 | int intel_atomic_setup_scalers(struct drm_device *dev, |
1424 | struct intel_crtc *intel_crtc, | |
1425 | struct intel_crtc_state *crtc_state); | |
5ee67f1c MR |
1426 | |
1427 | /* intel_atomic_plane.c */ | |
8e7d688b | 1428 | struct intel_plane_state *intel_create_plane_state(struct drm_plane *plane); |
ea2c67bb MR |
1429 | struct drm_plane_state *intel_plane_duplicate_state(struct drm_plane *plane); |
1430 | void intel_plane_destroy_state(struct drm_plane *plane, | |
1431 | struct drm_plane_state *state); | |
1432 | extern const struct drm_plane_helper_funcs intel_plane_helper_funcs; | |
1433 | ||
79e53945 | 1434 | #endif /* __INTEL_DRV_H__ */ |