[mirror_ubuntu-artful-kernel.git] / drivers / gpu / drm / i915 / intel_drv.h

/*
 * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
 * Copyright (c) 2007-2008 Intel Corporation
 *   Jesse Barnes <jesse.barnes@intel.com>
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
 * IN THE SOFTWARE.
 */
#ifndef __INTEL_DRV_H__
#define __INTEL_DRV_H__

#include <linux/i2c.h>
#include "i915_drm.h"
#include "i915_drv.h"
#include "drm_crtc.h"
#include "drm_crtc_helper.h"
#include "drm_fb_helper.h"

#define _wait_for(COND, MS, W) ({ \
	unsigned long timeout__ = jiffies + msecs_to_jiffies(MS);	\
	int ret__ = 0;							\
	while (!(COND)) {						\
		if (time_after(jiffies, timeout__)) {			\
			ret__ = -ETIMEDOUT;				\
			break;						\
		}							\
		if (W && drm_can_sleep()) msleep(W);	\
	}								\
	ret__;								\
})

#define wait_for_atomic_us(COND, US) ({ \
	int i, ret__ = -ETIMEDOUT;	\
	for (i = 0; i < (US); i++) {	\
		if ((COND)) {		\
			ret__ = 0;	\
			break;		\
		}			\
		udelay(1);		\
	}				\
	ret__;				\
})

#define wait_for(COND, MS) _wait_for(COND, MS, 1)
#define wait_for_atomic(COND, MS) _wait_for(COND, MS, 0)

#define KHz(x) (1000*x)
#define MHz(x) KHz(1000*x)

/*
 * Display related stuff
 */

/* store information about an Ixxx DVO */
/* The i830->i865 use multiple DVOs with multiple i2cs */
/* the i915, i945 have a single sDVO i2c bus - which is different */
#define MAX_OUTPUTS 6
/* maximum connectors per crtcs in the mode set */
#define INTELFB_CONN_LIMIT 4

#define INTEL_I2C_BUS_DVO 1
#define INTEL_I2C_BUS_SDVO 2

/* these are outputs from the chip - integrated only
   external chips are via DVO or SDVO output */
#define INTEL_OUTPUT_UNUSED 0
#define INTEL_OUTPUT_ANALOG 1
#define INTEL_OUTPUT_DVO 2
#define INTEL_OUTPUT_SDVO 3
#define INTEL_OUTPUT_LVDS 4
#define INTEL_OUTPUT_TVOUT 5
#define INTEL_OUTPUT_HDMI 6
#define INTEL_OUTPUT_DISPLAYPORT 7
#define INTEL_OUTPUT_EDP 8

/* Intel Pipe Clone Bit */
#define INTEL_HDMIB_CLONE_BIT 1
#define INTEL_HDMIC_CLONE_BIT 2
#define INTEL_HDMID_CLONE_BIT 3
#define INTEL_HDMIE_CLONE_BIT 4
#define INTEL_HDMIF_CLONE_BIT 5
#define INTEL_SDVO_NON_TV_CLONE_BIT 6
#define INTEL_SDVO_TV_CLONE_BIT 7
#define INTEL_SDVO_LVDS_CLONE_BIT 8
#define INTEL_ANALOG_CLONE_BIT 9
#define INTEL_TV_CLONE_BIT 10
#define INTEL_DP_B_CLONE_BIT 11
#define INTEL_DP_C_CLONE_BIT 12
#define INTEL_DP_D_CLONE_BIT 13
#define INTEL_LVDS_CLONE_BIT 14
#define INTEL_DVO_TMDS_CLONE_BIT 15
#define INTEL_DVO_LVDS_CLONE_BIT 16
#define INTEL_EDP_CLONE_BIT 17

#define INTEL_DVO_CHIP_NONE 0
#define INTEL_DVO_CHIP_LVDS 1
#define INTEL_DVO_CHIP_TMDS 2
#define INTEL_DVO_CHIP_TVOUT 4

/* drm_display_mode->private_flags */
#define INTEL_MODE_PIXEL_MULTIPLIER_SHIFT (0x0)
#define INTEL_MODE_PIXEL_MULTIPLIER_MASK (0xf << INTEL_MODE_PIXEL_MULTIPLIER_SHIFT)
#define INTEL_MODE_DP_FORCE_6BPC (0x10)

static inline void
intel_mode_set_pixel_multiplier(struct drm_display_mode *mode,
				int multiplier)
{
	mode->clock *= multiplier;
	mode->private_flags |= multiplier;
}

static inline int
intel_mode_get_pixel_multiplier(const struct drm_display_mode *mode)
{
	return (mode->private_flags & INTEL_MODE_PIXEL_MULTIPLIER_MASK) >> INTEL_MODE_PIXEL_MULTIPLIER_SHIFT;
}

struct intel_framebuffer {
	struct drm_framebuffer base;
	struct drm_i915_gem_object *obj;
};

struct intel_fbdev {
	struct drm_fb_helper helper;
	struct intel_framebuffer ifb;
	struct list_head fbdev_list;
	struct drm_display_mode *our_mode;
};

struct intel_encoder {
	struct drm_encoder base;
	int type;
	bool needs_tv_clock;
	void (*hot_plug)(struct intel_encoder *);
	int crtc_mask;
	int clone_mask;
};

struct intel_connector {
	struct drm_connector base;
	struct intel_encoder *encoder;
};

struct intel_crtc {
	struct drm_crtc base;
	enum pipe pipe;
	enum plane plane;
	u8 lut_r[256], lut_g[256], lut_b[256];
	int dpms_mode;
	bool active; /* is the crtc on? independent of the dpms mode */
	bool busy; /* is scanout buffer being updated frequently? */
	struct timer_list idle_timer;
	bool lowfreq_avail;
	struct intel_overlay *overlay;
	struct intel_unpin_work *unpin_work;
	int fdi_lanes;

	struct drm_i915_gem_object *cursor_bo;
	uint32_t cursor_addr;
	int16_t cursor_x, cursor_y;
	int16_t cursor_width, cursor_height;
	bool cursor_visible;
	unsigned int bpp;

	/* We can share PLLs across outputs if the timings match */
	struct intel_pch_pll *pch_pll;
};

struct intel_plane {
	struct drm_plane base;
	enum pipe pipe;
	struct drm_i915_gem_object *obj;
	bool primary_disabled;
	int max_downscale;
	u32 lut_r[1024], lut_g[1024], lut_b[1024];
	void (*update_plane)(struct drm_plane *plane,
			     struct drm_framebuffer *fb,
			     struct drm_i915_gem_object *obj,
			     int crtc_x, int crtc_y,
			     unsigned int crtc_w, unsigned int crtc_h,
			     uint32_t x, uint32_t y,
			     uint32_t src_w, uint32_t src_h);
	void (*disable_plane)(struct drm_plane *plane);
	int (*update_colorkey)(struct drm_plane *plane,
			       struct drm_intel_sprite_colorkey *key);
	void (*get_colorkey)(struct drm_plane *plane,
			     struct drm_intel_sprite_colorkey *key);
};

struct intel_watermark_params {
	unsigned long fifo_size;
	unsigned long max_wm;
	unsigned long default_wm;
	unsigned long guard_size;
	unsigned long cacheline_size;
};

struct cxsr_latency {
	int is_desktop;
	int is_ddr3;
	unsigned long fsb_freq;
	unsigned long mem_freq;
	unsigned long display_sr;
	unsigned long display_hpll_disable;
	unsigned long cursor_sr;
	unsigned long cursor_hpll_disable;
};

#define to_intel_crtc(x) container_of(x, struct intel_crtc, base)
#define to_intel_connector(x) container_of(x, struct intel_connector, base)
#define to_intel_encoder(x) container_of(x, struct intel_encoder, base)
#define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base)
#define to_intel_plane(x) container_of(x, struct intel_plane, base)

#define DIP_HEADER_SIZE	5

#define DIP_TYPE_AVI    0x82
#define DIP_VERSION_AVI 0x2
#define DIP_LEN_AVI     13

#define DIP_TYPE_SPD	0x83
#define DIP_VERSION_SPD	0x1
#define DIP_LEN_SPD	25
#define DIP_SPD_UNKNOWN	0
#define DIP_SPD_DSTB	0x1
#define DIP_SPD_DVDP	0x2
#define DIP_SPD_DVHS	0x3
#define DIP_SPD_HDDVR	0x4
#define DIP_SPD_DVC	0x5
#define DIP_SPD_DSC	0x6
#define DIP_SPD_VCD	0x7
#define DIP_SPD_GAME	0x8
#define DIP_SPD_PC	0x9
#define DIP_SPD_BD	0xa
#define DIP_SPD_SCD	0xb

struct dip_infoframe {
	uint8_t type;		/* HB0 */
	uint8_t ver;		/* HB1 */
	uint8_t len;		/* HB2 - body len, not including checksum */
	uint8_t ecc;		/* Header ECC */
	uint8_t checksum;	/* PB0 */
	union {
		struct {
			/* PB1 - Y 6:5, A 4:4, B 3:2, S 1:0 */
			uint8_t Y_A_B_S;
			/* PB2 - C 7:6, M 5:4, R 3:0 */
			uint8_t C_M_R;
			/* PB3 - ITC 7:7, EC 6:4, Q 3:2, SC 1:0 */
			uint8_t ITC_EC_Q_SC;
			/* PB4 - VIC 6:0 */
			uint8_t VIC;
			/* PB5 - PR 3:0 */
			uint8_t PR;
			/* PB6 to PB13 */
			uint16_t top_bar_end;
			uint16_t bottom_bar_start;
			uint16_t left_bar_end;
			uint16_t right_bar_start;
		} avi;
		struct {
			uint8_t vn[8];
			uint8_t pd[16];
			uint8_t sdi;
		} spd;
		uint8_t payload[27];
	} __attribute__ ((packed)) body;
} __attribute__((packed));

static inline struct drm_crtc *
intel_get_crtc_for_pipe(struct drm_device *dev, int pipe)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	return dev_priv->pipe_to_crtc_mapping[pipe];
}

static inline struct drm_crtc *
intel_get_crtc_for_plane(struct drm_device *dev, int plane)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	return dev_priv->plane_to_crtc_mapping[plane];
}

struct intel_unpin_work {
	struct work_struct work;
	struct drm_device *dev;
	struct drm_i915_gem_object *old_fb_obj;
	struct drm_i915_gem_object *pending_flip_obj;
	struct drm_pending_vblank_event *event;
	int pending;
	bool enable_stall_check;
};

struct intel_fbc_work {
	struct delayed_work work;
	struct drm_crtc *crtc;
	struct drm_framebuffer *fb;
	int interval;
};

int intel_ddc_get_modes(struct drm_connector *c, struct i2c_adapter *adapter);
extern bool intel_ddc_probe(struct intel_encoder *intel_encoder, int ddc_bus);

extern void intel_attach_force_audio_property(struct drm_connector *connector);
extern void intel_attach_broadcast_rgb_property(struct drm_connector *connector);

extern void intel_crt_init(struct drm_device *dev);
extern void intel_hdmi_init(struct drm_device *dev, int sdvox_reg);
void intel_dip_infoframe_csum(struct dip_infoframe *avi_if);
extern bool intel_sdvo_init(struct drm_device *dev, uint32_t sdvo_reg,
			    bool is_sdvob);
extern void intel_dvo_init(struct drm_device *dev);
extern void intel_tv_init(struct drm_device *dev);
extern void intel_mark_busy(struct drm_device *dev,
			    struct drm_i915_gem_object *obj);
extern bool intel_lvds_init(struct drm_device *dev);
extern void intel_dp_init(struct drm_device *dev, int dp_reg);
void
intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode,
		 struct drm_display_mode *adjusted_mode);
extern bool intel_dpd_is_edp(struct drm_device *dev);
extern void intel_edp_link_config(struct intel_encoder *, int *, int *);
extern bool intel_encoder_is_pch_edp(struct drm_encoder *encoder);
extern int intel_plane_init(struct drm_device *dev, enum pipe pipe);
extern void intel_flush_display_plane(struct drm_i915_private *dev_priv,
				      enum plane plane);

/* intel_panel.c */
extern void intel_fixed_panel_mode(struct drm_display_mode *fixed_mode,
				   struct drm_display_mode *adjusted_mode);
extern void intel_pch_panel_fitting(struct drm_device *dev,
				    int fitting_mode,
				    struct drm_display_mode *mode,
				    struct drm_display_mode *adjusted_mode);
extern u32 intel_panel_get_max_backlight(struct drm_device *dev);
extern u32 intel_panel_get_backlight(struct drm_device *dev);
extern void intel_panel_set_backlight(struct drm_device *dev, u32 level);
extern int intel_panel_setup_backlight(struct drm_device *dev);
extern void intel_panel_enable_backlight(struct drm_device *dev);
extern void intel_panel_disable_backlight(struct drm_device *dev);
extern void intel_panel_destroy_backlight(struct drm_device *dev);
extern enum drm_connector_status intel_panel_detect(struct drm_device *dev);

extern void intel_crtc_load_lut(struct drm_crtc *crtc);
extern void intel_encoder_prepare(struct drm_encoder *encoder);
extern void intel_encoder_commit(struct drm_encoder *encoder);
extern void intel_encoder_destroy(struct drm_encoder *encoder);

static inline struct intel_encoder *intel_attached_encoder(struct drm_connector *connector)
{
	return to_intel_connector(connector)->encoder;
}

extern void intel_connector_attach_encoder(struct intel_connector *connector,
					   struct intel_encoder *encoder);
extern struct drm_encoder *intel_best_encoder(struct drm_connector *connector);

extern struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
						    struct drm_crtc *crtc);
int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
				struct drm_file *file_priv);
extern void intel_wait_for_vblank(struct drm_device *dev, int pipe);
extern void intel_wait_for_pipe_off(struct drm_device *dev, int pipe);

struct intel_load_detect_pipe {
	struct drm_framebuffer *release_fb;
	bool load_detect_temp;
	int dpms_mode;
};
extern bool intel_get_load_detect_pipe(struct intel_encoder *intel_encoder,
				       struct drm_connector *connector,
				       struct drm_display_mode *mode,
				       struct intel_load_detect_pipe *old);
extern void intel_release_load_detect_pipe(struct intel_encoder *intel_encoder,
					   struct drm_connector *connector,
					   struct intel_load_detect_pipe *old);

extern void intelfb_restore(void);
extern void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
				    u16 blue, int regno);
extern void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
				    u16 *blue, int regno);
extern void intel_enable_clock_gating(struct drm_device *dev);
extern void ironlake_disable_rc6(struct drm_device *dev);
extern void ironlake_enable_drps(struct drm_device *dev);
extern void ironlake_disable_drps(struct drm_device *dev);
extern void gen6_enable_rps(struct drm_i915_private *dev_priv);
extern void gen6_update_ring_freq(struct drm_i915_private *dev_priv);
extern void gen6_disable_rps(struct drm_device *dev);
extern void intel_init_emon(struct drm_device *dev);

extern int intel_pin_and_fence_fb_obj(struct drm_device *dev,
				      struct drm_i915_gem_object *obj,
				      struct intel_ring_buffer *pipelined);
extern void intel_unpin_fb_obj(struct drm_i915_gem_object *obj);

extern int intel_framebuffer_init(struct drm_device *dev,
				  struct intel_framebuffer *ifb,
				  struct drm_mode_fb_cmd2 *mode_cmd,
				  struct drm_i915_gem_object *obj);
extern int intel_fbdev_init(struct drm_device *dev);
extern void intel_fbdev_fini(struct drm_device *dev);
extern void intel_fbdev_set_suspend(struct drm_device *dev, int state);
extern void intel_prepare_page_flip(struct drm_device *dev, int plane);
extern void intel_finish_page_flip(struct drm_device *dev, int pipe);
extern void intel_finish_page_flip_plane(struct drm_device *dev, int plane);

extern void intel_setup_overlay(struct drm_device *dev);
extern void intel_cleanup_overlay(struct drm_device *dev);
extern int intel_overlay_switch_off(struct intel_overlay *overlay);
extern int intel_overlay_put_image(struct drm_device *dev, void *data,
				   struct drm_file *file_priv);
extern int intel_overlay_attrs(struct drm_device *dev, void *data,
			       struct drm_file *file_priv);

extern void intel_fb_output_poll_changed(struct drm_device *dev);
extern void intel_fb_restore_mode(struct drm_device *dev);

extern void assert_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
			bool state);
#define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
#define assert_pipe_disabled(d, p) assert_pipe(d, p, false)

extern void intel_init_clock_gating(struct drm_device *dev);
extern void intel_write_eld(struct drm_encoder *encoder,
			    struct drm_display_mode *mode);
extern void intel_cpt_verify_modeset(struct drm_device *dev, int pipe);

/* For use by IVB LP watermark workaround in intel_sprite.c */
extern void intel_update_watermarks(struct drm_device *dev);
extern void intel_update_sprite_watermarks(struct drm_device *dev, int pipe,
					   uint32_t sprite_width,
					   int pixel_size);

extern int intel_sprite_set_colorkey(struct drm_device *dev, void *data,
				     struct drm_file *file_priv);
extern int intel_sprite_get_colorkey(struct drm_device *dev, void *data,
				     struct drm_file *file_priv);

extern u32 intel_dpio_read(struct drm_i915_private *dev_priv, int reg);

/* Power-related functions, located in intel_pm.c */
extern void intel_init_pm(struct drm_device *dev);
/* FBC */
extern bool intel_fbc_enabled(struct drm_device *dev);
extern void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval);
extern void intel_update_fbc(struct drm_device *dev);
/* IPS */
extern void intel_gpu_ips_init(struct drm_i915_private *dev_priv);
extern void intel_gpu_ips_teardown(void);

#endif /* __INTEL_DRV_H__ */
Commit	Line	Data
79e53945 JB	1	/*
	2	* Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
	3	* Copyright (c) 2007-2008 Intel Corporation
	4	* Jesse Barnes <jesse.barnes@intel.com>
	5	*
	6	* Permission is hereby granted, free of charge, to any person obtaining a
	7	* copy of this software and associated documentation files (the "Software"),
	8	* to deal in the Software without restriction, including without limitation
	9	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	10	* and/or sell copies of the Software, and to permit persons to whom the
	11	* Software is furnished to do so, subject to the following conditions:
	12	*
	13	* The above copyright notice and this permission notice (including the next
	14	* paragraph) shall be included in all copies or substantial portions of the
	15	* Software.
	16	*
	17	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	18	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	19	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	20	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	21	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
	22	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
	23	* IN THE SOFTWARE.
	24	*/
	25	#ifndef __INTEL_DRV_H__
	26	#define __INTEL_DRV_H__
	27
	28	#include <linux/i2c.h>
8ea30864	29	#include "i915_drm.h"
80824003	30	#include "i915_drv.h"
79e53945	31	#include "drm_crtc.h"
79e53945	32	#include "drm_crtc_helper.h"
37811fcc	33	#include "drm_fb_helper.h"
913d8d11	34
481b6af3	35	#define _wait_for(COND, MS, W) ({ \
913d8d11 CW	36	unsigned long timeout__ = jiffies + msecs_to_jiffies(MS); \
913d8d11 CW	37	int ret__ = 0; \
0206e353	38	while (!(COND)) { \
913d8d11 CW	39	if (time_after(jiffies, timeout__)) { \
	40	ret__ = -ETIMEDOUT; \
	41	break; \
	42	} \
cc1f7194	43	if (W && drm_can_sleep()) msleep(W); \
913d8d11 CW	44	} \
	45	ret__; \
	46	})
	47
57f350b6 JB	48	#define wait_for_atomic_us(COND, US) ({ \
	49	int i, ret__ = -ETIMEDOUT; \
	50	for (i = 0; i < (US); i++) { \
	51	if ((COND)) { \
	52	ret__ = 0; \
	53	break; \
	54	} \
	55	udelay(1); \
	56	} \
	57	ret__; \
	58	})
	59
481b6af3 CW	60	#define wait_for(COND, MS) _wait_for(COND, MS, 1)
	61	#define wait_for_atomic(COND, MS) _wait_for(COND, MS, 0)
	62
021357ac CW	63	#define KHz(x) (1000*x)
	64	#define MHz(x) KHz(1000*x)
	65
79e53945 JB	66	/*
	67	* Display related stuff
	68	*/
	69
	70	/* store information about an Ixxx DVO */
	71	/* The i830->i865 use multiple DVOs with multiple i2cs */
	72	/* the i915, i945 have a single sDVO i2c bus - which is different */
	73	#define MAX_OUTPUTS 6
	74	/* maximum connectors per crtcs in the mode set */
	75	#define INTELFB_CONN_LIMIT 4
	76
	77	#define INTEL_I2C_BUS_DVO 1
	78	#define INTEL_I2C_BUS_SDVO 2
	79
	80	/* these are outputs from the chip - integrated only
	81	external chips are via DVO or SDVO output */
	82	#define INTEL_OUTPUT_UNUSED 0
	83	#define INTEL_OUTPUT_ANALOG 1
	84	#define INTEL_OUTPUT_DVO 2
	85	#define INTEL_OUTPUT_SDVO 3
	86	#define INTEL_OUTPUT_LVDS 4
	87	#define INTEL_OUTPUT_TVOUT 5
7d57382e	88	#define INTEL_OUTPUT_HDMI 6
a4fc5ed6	89	#define INTEL_OUTPUT_DISPLAYPORT 7
32f9d658	90	#define INTEL_OUTPUT_EDP 8
79e53945	91
f8aed700 ML	92	/* Intel Pipe Clone Bit */
	93	#define INTEL_HDMIB_CLONE_BIT 1
	94	#define INTEL_HDMIC_CLONE_BIT 2
	95	#define INTEL_HDMID_CLONE_BIT 3
	96	#define INTEL_HDMIE_CLONE_BIT 4
	97	#define INTEL_HDMIF_CLONE_BIT 5
	98	#define INTEL_SDVO_NON_TV_CLONE_BIT 6
	99	#define INTEL_SDVO_TV_CLONE_BIT 7
	100	#define INTEL_SDVO_LVDS_CLONE_BIT 8
	101	#define INTEL_ANALOG_CLONE_BIT 9
	102	#define INTEL_TV_CLONE_BIT 10
	103	#define INTEL_DP_B_CLONE_BIT 11
	104	#define INTEL_DP_C_CLONE_BIT 12
	105	#define INTEL_DP_D_CLONE_BIT 13
	106	#define INTEL_LVDS_CLONE_BIT 14
	107	#define INTEL_DVO_TMDS_CLONE_BIT 15
	108	#define INTEL_DVO_LVDS_CLONE_BIT 16
7c8460db	109	#define INTEL_EDP_CLONE_BIT 17
f8aed700	110
79e53945 JB	111	#define INTEL_DVO_CHIP_NONE 0
	112	#define INTEL_DVO_CHIP_LVDS 1
	113	#define INTEL_DVO_CHIP_TMDS 2
	114	#define INTEL_DVO_CHIP_TVOUT 4
	115
6c9547ff CW	116	/* drm_display_mode->private_flags */
	117	#define INTEL_MODE_PIXEL_MULTIPLIER_SHIFT (0x0)
	118	#define INTEL_MODE_PIXEL_MULTIPLIER_MASK (0xf << INTEL_MODE_PIXEL_MULTIPLIER_SHIFT)
3b5c78a3	119	#define INTEL_MODE_DP_FORCE_6BPC (0x10)
6c9547ff CW	120
	121	static inline void
	122	intel_mode_set_pixel_multiplier(struct drm_display_mode *mode,
	123	int multiplier)
	124	{
	125	mode->clock *= multiplier;
	126	mode->private_flags \|= multiplier;
	127	}
	128
	129	static inline int
	130	intel_mode_get_pixel_multiplier(const struct drm_display_mode *mode)
	131	{
	132	return (mode->private_flags & INTEL_MODE_PIXEL_MULTIPLIER_MASK) >> INTEL_MODE_PIXEL_MULTIPLIER_SHIFT;
	133	}
	134
79e53945 JB	135	struct intel_framebuffer {
79e53945 JB	136	struct drm_framebuffer base;
05394f39	137	struct drm_i915_gem_object *obj;
79e53945 JB	138	};
79e53945 JB	139
37811fcc CW	140	struct intel_fbdev {
	141	struct drm_fb_helper helper;
	142	struct intel_framebuffer ifb;
	143	struct list_head fbdev_list;
	144	struct drm_display_mode *our_mode;
	145	};
79e53945	146
21d40d37	147	struct intel_encoder {
4ef69c7a	148	struct drm_encoder base;
79e53945	149	int type;
e2f0ba97	150	bool needs_tv_clock;
21d40d37	151	void (hot_plug)(struct intel_encoder );
f8aed700 ML	152	int crtc_mask;
f8aed700 ML	153	int clone_mask;
79e53945 JB	154	};
79e53945 JB	155
5daa55eb ZW	156	struct intel_connector {
5daa55eb ZW	157	struct drm_connector base;
df0e9248	158	struct intel_encoder *encoder;
5daa55eb ZW	159	};
5daa55eb ZW	160
79e53945 JB	161	struct intel_crtc {
79e53945 JB	162	struct drm_crtc base;
80824003 JB	163	enum pipe pipe;
80824003 JB	164	enum plane plane;
79e53945 JB	165	u8 lut_r[256], lut_g[256], lut_b[256];
79e53945 JB	166	int dpms_mode;
f7abfe8b	167	bool active; /* is the crtc on? independent of the dpms mode */
652c393a JB	168	bool busy; /* is scanout buffer being updated frequently? */
	169	struct timer_list idle_timer;
	170	bool lowfreq_avail;
02e792fb	171	struct intel_overlay *overlay;
6b95a207	172	struct intel_unpin_work *unpin_work;
77ffb597	173	int fdi_lanes;
cda4b7d3	174
05394f39	175	struct drm_i915_gem_object *cursor_bo;
cda4b7d3 CW	176	uint32_t cursor_addr;
	177	int16_t cursor_x, cursor_y;
	178	int16_t cursor_width, cursor_height;
6b383a7f	179	bool cursor_visible;
5a354204	180	unsigned int bpp;
4b645f14	181
ee7b9f93 JB	182	/* We can share PLLs across outputs if the timings match */
ee7b9f93 JB	183	struct intel_pch_pll *pch_pll;
79e53945 JB	184	};
79e53945 JB	185
b840d907 JB	186	struct intel_plane {
	187	struct drm_plane base;
	188	enum pipe pipe;
	189	struct drm_i915_gem_object *obj;
175bd420	190	bool primary_disabled;
b840d907 JB	191	int max_downscale;
	192	u32 lut_r[1024], lut_g[1024], lut_b[1024];
	193	void (update_plane)(struct drm_plane plane,
	194	struct drm_framebuffer *fb,
	195	struct drm_i915_gem_object *obj,
	196	int crtc_x, int crtc_y,
	197	unsigned int crtc_w, unsigned int crtc_h,
	198	uint32_t x, uint32_t y,
	199	uint32_t src_w, uint32_t src_h);
	200	void (disable_plane)(struct drm_plane plane);
8ea30864 JB	201	int (update_colorkey)(struct drm_plane plane,
	202	struct drm_intel_sprite_colorkey *key);
	203	void (get_colorkey)(struct drm_plane plane,
	204	struct drm_intel_sprite_colorkey *key);
b840d907 JB	205	};
b840d907 JB	206
b445e3b0 ED	207	struct intel_watermark_params {
	208	unsigned long fifo_size;
	209	unsigned long max_wm;
	210	unsigned long default_wm;
	211	unsigned long guard_size;
	212	unsigned long cacheline_size;
	213	};
	214
	215	struct cxsr_latency {
	216	int is_desktop;
	217	int is_ddr3;
	218	unsigned long fsb_freq;
	219	unsigned long mem_freq;
	220	unsigned long display_sr;
	221	unsigned long display_hpll_disable;
	222	unsigned long cursor_sr;
	223	unsigned long cursor_hpll_disable;
	224	};
	225
79e53945	226	#define to_intel_crtc(x) container_of(x, struct intel_crtc, base)
5daa55eb	227	#define to_intel_connector(x) container_of(x, struct intel_connector, base)
4ef69c7a	228	#define to_intel_encoder(x) container_of(x, struct intel_encoder, base)
79e53945	229	#define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base)
b840d907	230	#define to_intel_plane(x) container_of(x, struct intel_plane, base)
79e53945	231
45187ace JB	232	#define DIP_HEADER_SIZE 5
45187ace JB	233
3c17fe4b DH	234	#define DIP_TYPE_AVI 0x82
	235	#define DIP_VERSION_AVI 0x2
	236	#define DIP_LEN_AVI 13
	237
26005210	238	#define DIP_TYPE_SPD 0x83
c0864cb3 JB	239	#define DIP_VERSION_SPD 0x1
	240	#define DIP_LEN_SPD 25
	241	#define DIP_SPD_UNKNOWN 0
	242	#define DIP_SPD_DSTB 0x1
	243	#define DIP_SPD_DVDP 0x2
	244	#define DIP_SPD_DVHS 0x3
	245	#define DIP_SPD_HDDVR 0x4
	246	#define DIP_SPD_DVC 0x5
	247	#define DIP_SPD_DSC 0x6
	248	#define DIP_SPD_VCD 0x7
	249	#define DIP_SPD_GAME 0x8
	250	#define DIP_SPD_PC 0x9
	251	#define DIP_SPD_BD 0xa
	252	#define DIP_SPD_SCD 0xb
	253
3c17fe4b DH	254	struct dip_infoframe {
	255	uint8_t type; /* HB0 */
	256	uint8_t ver; /* HB1 */
	257	uint8_t len; /* HB2 - body len, not including checksum */
	258	uint8_t ecc; /* Header ECC */
	259	uint8_t checksum; /* PB0 */
	260	union {
	261	struct {
	262	/* PB1 - Y 6:5, A 4:4, B 3:2, S 1:0 */
	263	uint8_t Y_A_B_S;
	264	/* PB2 - C 7:6, M 5:4, R 3:0 */
	265	uint8_t C_M_R;
	266	/* PB3 - ITC 7:7, EC 6:4, Q 3:2, SC 1:0 */
	267	uint8_t ITC_EC_Q_SC;
	268	/* PB4 - VIC 6:0 */
	269	uint8_t VIC;
	270	/* PB5 - PR 3:0 */
	271	uint8_t PR;
	272	/* PB6 to PB13 */
	273	uint16_t top_bar_end;
	274	uint16_t bottom_bar_start;
	275	uint16_t left_bar_end;
	276	uint16_t right_bar_start;
	277	} avi;
c0864cb3 JB	278	struct {
	279	uint8_t vn[8];
	280	uint8_t pd[16];
	281	uint8_t sdi;
	282	} spd;
3c17fe4b DH	283	uint8_t payload[27];
	284	} __attribute__ ((packed)) body;
	285	} __attribute__((packed));
	286
f875c15a CW	287	static inline struct drm_crtc *
	288	intel_get_crtc_for_pipe(struct drm_device *dev, int pipe)
	289	{
	290	struct drm_i915_private *dev_priv = dev->dev_private;
	291	return dev_priv->pipe_to_crtc_mapping[pipe];
	292	}
	293
417ae147 CW	294	static inline struct drm_crtc *
	295	intel_get_crtc_for_plane(struct drm_device *dev, int plane)
	296	{
	297	struct drm_i915_private *dev_priv = dev->dev_private;
	298	return dev_priv->plane_to_crtc_mapping[plane];
	299	}
	300
4e5359cd SF	301	struct intel_unpin_work {
	302	struct work_struct work;
	303	struct drm_device *dev;
05394f39 CW	304	struct drm_i915_gem_object *old_fb_obj;
05394f39 CW	305	struct drm_i915_gem_object *pending_flip_obj;
4e5359cd SF	306	struct drm_pending_vblank_event *event;
	307	int pending;
	308	bool enable_stall_check;
	309	};
	310
1630fe75 CW	311	struct intel_fbc_work {
	312	struct delayed_work work;
	313	struct drm_crtc *crtc;
	314	struct drm_framebuffer *fb;
	315	int interval;
	316	};
	317
335af9a2	318	int intel_ddc_get_modes(struct drm_connector c, struct i2c_adapter adapter);
f899fc64	319	extern bool intel_ddc_probe(struct intel_encoder *intel_encoder, int ddc_bus);
f0217c42	320
3f43c48d	321	extern void intel_attach_force_audio_property(struct drm_connector *connector);
e953fd7b CW	322	extern void intel_attach_broadcast_rgb_property(struct drm_connector *connector);
e953fd7b CW	323
79e53945	324	extern void intel_crt_init(struct drm_device *dev);
7d57382e	325	extern void intel_hdmi_init(struct drm_device *dev, int sdvox_reg);
3c17fe4b	326	void intel_dip_infoframe_csum(struct dip_infoframe *avi_if);
eef4eacb DV	327	extern bool intel_sdvo_init(struct drm_device *dev, uint32_t sdvo_reg,
eef4eacb DV	328	bool is_sdvob);
79e53945 JB	329	extern void intel_dvo_init(struct drm_device *dev);
79e53945 JB	330	extern void intel_tv_init(struct drm_device *dev);
05394f39 CW	331	extern void intel_mark_busy(struct drm_device *dev,
05394f39 CW	332	struct drm_i915_gem_object *obj);
c5d1b51d	333	extern bool intel_lvds_init(struct drm_device *dev);
a4fc5ed6 KP	334	extern void intel_dp_init(struct drm_device *dev, int dp_reg);
	335	void
	336	intel_dp_set_m_n(struct drm_crtc crtc, struct drm_display_mode mode,
	337	struct drm_display_mode *adjusted_mode);
cb0953d7	338	extern bool intel_dpd_is_edp(struct drm_device *dev);
0206e353	339	extern void intel_edp_link_config(struct intel_encoder , int , int *);
814948ad	340	extern bool intel_encoder_is_pch_edp(struct drm_encoder *encoder);
b840d907	341	extern int intel_plane_init(struct drm_device *dev, enum pipe pipe);
6f1d69b0 ED	342	extern void intel_flush_display_plane(struct drm_i915_private *dev_priv,
6f1d69b0 ED	343	enum plane plane);
32f9d658	344
a9573556	345	/* intel_panel.c */
1d8e1c75 CW	346	extern void intel_fixed_panel_mode(struct drm_display_mode *fixed_mode,
	347	struct drm_display_mode *adjusted_mode);
	348	extern void intel_pch_panel_fitting(struct drm_device *dev,
	349	int fitting_mode,
	350	struct drm_display_mode *mode,
	351	struct drm_display_mode *adjusted_mode);
a9573556 CW	352	extern u32 intel_panel_get_max_backlight(struct drm_device *dev);
	353	extern u32 intel_panel_get_backlight(struct drm_device *dev);
	354	extern void intel_panel_set_backlight(struct drm_device *dev, u32 level);
aaa6fd2a	355	extern int intel_panel_setup_backlight(struct drm_device *dev);
47356eb6 CW	356	extern void intel_panel_enable_backlight(struct drm_device *dev);
47356eb6 CW	357	extern void intel_panel_disable_backlight(struct drm_device *dev);
aaa6fd2a	358	extern void intel_panel_destroy_backlight(struct drm_device *dev);
fe16d949	359	extern enum drm_connector_status intel_panel_detect(struct drm_device *dev);
1d8e1c75	360
79e53945	361	extern void intel_crtc_load_lut(struct drm_crtc *crtc);
0206e353 AJ	362	extern void intel_encoder_prepare(struct drm_encoder *encoder);
0206e353 AJ	363	extern void intel_encoder_commit(struct drm_encoder *encoder);
ea5b213a	364	extern void intel_encoder_destroy(struct drm_encoder *encoder);
79e53945	365
df0e9248 CW	366	static inline struct intel_encoder intel_attached_encoder(struct drm_connector connector)
	367	{
	368	return to_intel_connector(connector)->encoder;
	369	}
	370
	371	extern void intel_connector_attach_encoder(struct intel_connector *connector,
	372	struct intel_encoder *encoder);
	373	extern struct drm_encoder intel_best_encoder(struct drm_connector connector);
79e53945 JB	374
	375	extern struct drm_display_mode intel_crtc_mode_get(struct drm_device dev,
	376	struct drm_crtc *crtc);
08d7b3d1 CW	377	int intel_get_pipe_from_crtc_id(struct drm_device dev, void data,
08d7b3d1 CW	378	struct drm_file *file_priv);
9d0498a2	379	extern void intel_wait_for_vblank(struct drm_device *dev, int pipe);
58e10eb9	380	extern void intel_wait_for_pipe_off(struct drm_device *dev, int pipe);
8261b191 CW	381
8261b191 CW	382	struct intel_load_detect_pipe {
d2dff872	383	struct drm_framebuffer *release_fb;
8261b191 CW	384	bool load_detect_temp;
	385	int dpms_mode;
	386	};
7173188d CW	387	extern bool intel_get_load_detect_pipe(struct intel_encoder *intel_encoder,
	388	struct drm_connector *connector,
	389	struct drm_display_mode *mode,
8261b191	390	struct intel_load_detect_pipe *old);
21d40d37	391	extern void intel_release_load_detect_pipe(struct intel_encoder *intel_encoder,
c1c43977	392	struct drm_connector *connector,
8261b191	393	struct intel_load_detect_pipe *old);
79e53945	394
79e53945 JB	395	extern void intelfb_restore(void);
	396	extern void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
	397	u16 blue, int regno);
b8c00ac5 DA	398	extern void intel_crtc_fb_gamma_get(struct drm_crtc crtc, u16 red, u16 *green,
b8c00ac5 DA	399	u16 *blue, int regno);
0cdab21f	400	extern void intel_enable_clock_gating(struct drm_device *dev);
2b4e57bd	401	extern void ironlake_disable_rc6(struct drm_device *dev);
f97108d1 JB	402	extern void ironlake_enable_drps(struct drm_device *dev);
f97108d1 JB	403	extern void ironlake_disable_drps(struct drm_device *dev);
3b8d8d91	404	extern void gen6_enable_rps(struct drm_i915_private *dev_priv);
23b2f8bb	405	extern void gen6_update_ring_freq(struct drm_i915_private *dev_priv);
3b8d8d91	406	extern void gen6_disable_rps(struct drm_device *dev);
48fcfc88	407	extern void intel_init_emon(struct drm_device *dev);
79e53945	408
127bd2ac	409	extern int intel_pin_and_fence_fb_obj(struct drm_device *dev,
05394f39	410	struct drm_i915_gem_object *obj,
919926ae	411	struct intel_ring_buffer *pipelined);
1690e1eb	412	extern void intel_unpin_fb_obj(struct drm_i915_gem_object *obj);
127bd2ac	413
38651674 DA	414	extern int intel_framebuffer_init(struct drm_device *dev,
38651674 DA	415	struct intel_framebuffer *ifb,
308e5bcb	416	struct drm_mode_fb_cmd2 *mode_cmd,
05394f39	417	struct drm_i915_gem_object *obj);
38651674 DA	418	extern int intel_fbdev_init(struct drm_device *dev);
38651674 DA	419	extern void intel_fbdev_fini(struct drm_device *dev);
3fa016a0	420	extern void intel_fbdev_set_suspend(struct drm_device *dev, int state);
6b95a207 KH	421	extern void intel_prepare_page_flip(struct drm_device *dev, int plane);
6b95a207 KH	422	extern void intel_finish_page_flip(struct drm_device *dev, int pipe);
1afe3e9d	423	extern void intel_finish_page_flip_plane(struct drm_device *dev, int plane);
6b95a207	424
02e792fb DV	425	extern void intel_setup_overlay(struct drm_device *dev);
02e792fb DV	426	extern void intel_cleanup_overlay(struct drm_device *dev);
ce453d81	427	extern int intel_overlay_switch_off(struct intel_overlay *overlay);
02e792fb DV	428	extern int intel_overlay_put_image(struct drm_device dev, void data,
	429	struct drm_file *file_priv);
	430	extern int intel_overlay_attrs(struct drm_device dev, void data,
	431	struct drm_file *file_priv);
4abe3520	432
eb1f8e4f	433	extern void intel_fb_output_poll_changed(struct drm_device *dev);
e8e7a2b8	434	extern void intel_fb_restore_mode(struct drm_device *dev);
645c62a5	435
b840d907 JB	436	extern void assert_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
	437	bool state);
	438	#define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
	439	#define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
	440
645c62a5	441	extern void intel_init_clock_gating(struct drm_device *dev);
e0dac65e WF	442	extern void intel_write_eld(struct drm_encoder *encoder,
e0dac65e WF	443	struct drm_display_mode *mode);
d4270e57 JB	444	extern void intel_cpt_verify_modeset(struct drm_device *dev, int pipe);
d4270e57 JB	445
b840d907	446	/* For use by IVB LP watermark workaround in intel_sprite.c */
f681fa23	447	extern void intel_update_watermarks(struct drm_device *dev);
b840d907 JB	448	extern void intel_update_sprite_watermarks(struct drm_device *dev, int pipe,
	449	uint32_t sprite_width,
	450	int pixel_size);
8ea30864 JB	451
	452	extern int intel_sprite_set_colorkey(struct drm_device dev, void data,
	453	struct drm_file *file_priv);
	454	extern int intel_sprite_get_colorkey(struct drm_device dev, void data,
	455	struct drm_file *file_priv);
	456
57f350b6 JB	457	extern u32 intel_dpio_read(struct drm_i915_private *dev_priv, int reg);
57f350b6 JB	458
85208be0	459	/* Power-related functions, located in intel_pm.c */
1fa61106	460	extern void intel_init_pm(struct drm_device *dev);
85208be0	461	/* FBC */
85208be0 ED	462	extern bool intel_fbc_enabled(struct drm_device *dev);
	463	extern void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval);
	464	extern void intel_update_fbc(struct drm_device *dev);
eb48eb00 DV	465	/* IPS */
	466	extern void intel_gpu_ips_init(struct drm_i915_private *dev_priv);
	467	extern void intel_gpu_ips_teardown(void);
85208be0	468
79e53945	469	#endif /* __INTEL_DRV_H__ */