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4e646495 JN |
1 | /* |
2 | * Copyright © 2013 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
21 | * DEALINGS IN THE SOFTWARE. | |
22 | * | |
23 | * Author: Jani Nikula <jani.nikula@intel.com> | |
24 | */ | |
25 | ||
26 | #include <drm/drmP.h> | |
27 | #include <drm/drm_crtc.h> | |
28 | #include <drm/drm_edid.h> | |
29 | #include <drm/i915_drm.h> | |
30 | #include <linux/slab.h> | |
31 | #include "i915_drv.h" | |
32 | #include "intel_drv.h" | |
33 | #include "intel_dsi.h" | |
34 | #include "intel_dsi_cmd.h" | |
35 | ||
36 | /* the sub-encoders aka panel drivers */ | |
37 | static const struct intel_dsi_device intel_dsi_devices[] = { | |
2ab8b458 SK |
38 | { |
39 | .panel_id = MIPI_DSI_GENERIC_PANEL_ID, | |
40 | .name = "vbt-generic-dsi-vid-mode-display", | |
41 | .dev_ops = &vbt_generic_dsi_display_ops, | |
42 | }, | |
4e646495 JN |
43 | }; |
44 | ||
e9fe51c6 | 45 | static void band_gap_reset(struct drm_i915_private *dev_priv) |
4ce8c9a7 SK |
46 | { |
47 | mutex_lock(&dev_priv->dpio_lock); | |
48 | ||
e9fe51c6 SK |
49 | vlv_flisdsi_write(dev_priv, 0x08, 0x0001); |
50 | vlv_flisdsi_write(dev_priv, 0x0F, 0x0005); | |
51 | vlv_flisdsi_write(dev_priv, 0x0F, 0x0025); | |
52 | udelay(150); | |
53 | vlv_flisdsi_write(dev_priv, 0x0F, 0x0000); | |
54 | vlv_flisdsi_write(dev_priv, 0x08, 0x0000); | |
4ce8c9a7 SK |
55 | |
56 | mutex_unlock(&dev_priv->dpio_lock); | |
4ce8c9a7 SK |
57 | } |
58 | ||
4e646495 JN |
59 | static struct intel_dsi *intel_attached_dsi(struct drm_connector *connector) |
60 | { | |
61 | return container_of(intel_attached_encoder(connector), | |
62 | struct intel_dsi, base); | |
63 | } | |
64 | ||
65 | static inline bool is_vid_mode(struct intel_dsi *intel_dsi) | |
66 | { | |
dfba2e2d | 67 | return intel_dsi->operation_mode == INTEL_DSI_VIDEO_MODE; |
4e646495 JN |
68 | } |
69 | ||
70 | static inline bool is_cmd_mode(struct intel_dsi *intel_dsi) | |
71 | { | |
dfba2e2d | 72 | return intel_dsi->operation_mode == INTEL_DSI_COMMAND_MODE; |
4e646495 JN |
73 | } |
74 | ||
75 | static void intel_dsi_hot_plug(struct intel_encoder *encoder) | |
76 | { | |
77 | DRM_DEBUG_KMS("\n"); | |
78 | } | |
79 | ||
80 | static bool intel_dsi_compute_config(struct intel_encoder *encoder, | |
81 | struct intel_crtc_config *config) | |
82 | { | |
83 | struct intel_dsi *intel_dsi = container_of(encoder, struct intel_dsi, | |
84 | base); | |
85 | struct intel_connector *intel_connector = intel_dsi->attached_connector; | |
86 | struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode; | |
87 | struct drm_display_mode *adjusted_mode = &config->adjusted_mode; | |
88 | struct drm_display_mode *mode = &config->requested_mode; | |
89 | ||
90 | DRM_DEBUG_KMS("\n"); | |
91 | ||
92 | if (fixed_mode) | |
93 | intel_fixed_panel_mode(fixed_mode, adjusted_mode); | |
94 | ||
f573de5a SK |
95 | /* DSI uses short packets for sync events, so clear mode flags for DSI */ |
96 | adjusted_mode->flags = 0; | |
97 | ||
4e646495 JN |
98 | if (intel_dsi->dev.dev_ops->mode_fixup) |
99 | return intel_dsi->dev.dev_ops->mode_fixup(&intel_dsi->dev, | |
100 | mode, adjusted_mode); | |
101 | ||
102 | return true; | |
103 | } | |
104 | ||
5505a244 GS |
105 | static void intel_dsi_port_enable(struct intel_encoder *encoder) |
106 | { | |
107 | struct drm_device *dev = encoder->base.dev; | |
108 | struct drm_i915_private *dev_priv = dev->dev_private; | |
109 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); | |
110 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); | |
369602d3 | 111 | enum port port; |
5505a244 GS |
112 | u32 temp; |
113 | ||
a9da9bce GS |
114 | if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) { |
115 | temp = I915_READ(VLV_CHICKEN_3); | |
116 | temp &= ~PIXEL_OVERLAP_CNT_MASK | | |
117 | intel_dsi->pixel_overlap << | |
118 | PIXEL_OVERLAP_CNT_SHIFT; | |
119 | I915_WRITE(VLV_CHICKEN_3, temp); | |
120 | } | |
121 | ||
369602d3 GS |
122 | for_each_dsi_port(port, intel_dsi->ports) { |
123 | temp = I915_READ(MIPI_PORT_CTRL(port)); | |
124 | temp &= ~LANE_CONFIGURATION_MASK; | |
125 | temp &= ~DUAL_LINK_MODE_MASK; | |
126 | ||
127 | if (intel_dsi->ports == ((1 << PORT_A) | (1 << PORT_C))) { | |
128 | temp |= (intel_dsi->dual_link - 1) | |
129 | << DUAL_LINK_MODE_SHIFT; | |
130 | temp |= intel_crtc->pipe ? | |
131 | LANE_CONFIGURATION_DUAL_LINK_B : | |
132 | LANE_CONFIGURATION_DUAL_LINK_A; | |
133 | } | |
134 | /* assert ip_tg_enable signal */ | |
135 | I915_WRITE(MIPI_PORT_CTRL(port), temp | DPI_ENABLE); | |
136 | POSTING_READ(MIPI_PORT_CTRL(port)); | |
137 | } | |
5505a244 GS |
138 | } |
139 | ||
140 | static void intel_dsi_port_disable(struct intel_encoder *encoder) | |
141 | { | |
142 | struct drm_device *dev = encoder->base.dev; | |
143 | struct drm_i915_private *dev_priv = dev->dev_private; | |
369602d3 GS |
144 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); |
145 | enum port port; | |
5505a244 GS |
146 | u32 temp; |
147 | ||
369602d3 GS |
148 | for_each_dsi_port(port, intel_dsi->ports) { |
149 | /* de-assert ip_tg_enable signal */ | |
150 | temp = I915_READ(MIPI_PORT_CTRL(port)); | |
151 | I915_WRITE(MIPI_PORT_CTRL(port), temp & ~DPI_ENABLE); | |
152 | POSTING_READ(MIPI_PORT_CTRL(port)); | |
153 | } | |
5505a244 GS |
154 | } |
155 | ||
1dbd7cb2 | 156 | static void intel_dsi_device_ready(struct intel_encoder *encoder) |
4e646495 | 157 | { |
1dbd7cb2 SK |
158 | struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; |
159 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); | |
e7d7cad0 | 160 | enum port port = intel_dsi_pipe_to_port(intel_crtc->pipe); |
1dbd7cb2 SK |
161 | u32 val; |
162 | ||
4e646495 | 163 | DRM_DEBUG_KMS("\n"); |
4e646495 | 164 | |
2095f9fc SK |
165 | mutex_lock(&dev_priv->dpio_lock); |
166 | /* program rcomp for compliance, reduce from 50 ohms to 45 ohms | |
167 | * needed everytime after power gate */ | |
168 | vlv_flisdsi_write(dev_priv, 0x04, 0x0004); | |
169 | mutex_unlock(&dev_priv->dpio_lock); | |
170 | ||
171 | /* bandgap reset is needed after everytime we do power gate */ | |
172 | band_gap_reset(dev_priv); | |
173 | ||
e7d7cad0 | 174 | I915_WRITE(MIPI_DEVICE_READY(port), ULPS_STATE_ENTER); |
aceb365c SK |
175 | usleep_range(2500, 3000); |
176 | ||
e7d7cad0 JN |
177 | val = I915_READ(MIPI_PORT_CTRL(port)); |
178 | I915_WRITE(MIPI_PORT_CTRL(port), val | LP_OUTPUT_HOLD); | |
1dbd7cb2 | 179 | usleep_range(1000, 1500); |
aceb365c | 180 | |
e7d7cad0 | 181 | I915_WRITE(MIPI_DEVICE_READY(port), ULPS_STATE_EXIT); |
aceb365c SK |
182 | usleep_range(2500, 3000); |
183 | ||
e7d7cad0 | 184 | I915_WRITE(MIPI_DEVICE_READY(port), DEVICE_READY); |
aceb365c | 185 | usleep_range(2500, 3000); |
1dbd7cb2 | 186 | } |
1dbd7cb2 SK |
187 | |
188 | static void intel_dsi_enable(struct intel_encoder *encoder) | |
189 | { | |
190 | struct drm_device *dev = encoder->base.dev; | |
191 | struct drm_i915_private *dev_priv = dev->dev_private; | |
192 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); | |
193 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); | |
e7d7cad0 | 194 | enum port port = intel_dsi_pipe_to_port(intel_crtc->pipe); |
1dbd7cb2 SK |
195 | |
196 | DRM_DEBUG_KMS("\n"); | |
b9f5e07d | 197 | |
4e646495 | 198 | if (is_cmd_mode(intel_dsi)) |
e7d7cad0 | 199 | I915_WRITE(MIPI_MAX_RETURN_PKT_SIZE(port), 8 * 4); |
1dbd7cb2 | 200 | else { |
4e646495 | 201 | msleep(20); /* XXX */ |
e1047028 | 202 | dpi_send_cmd(intel_dsi, TURN_ON, DPI_LP_MODE_EN); |
4e646495 JN |
203 | msleep(100); |
204 | ||
2634fd7f SK |
205 | if (intel_dsi->dev.dev_ops->enable) |
206 | intel_dsi->dev.dev_ops->enable(&intel_dsi->dev); | |
207 | ||
1381308b SK |
208 | wait_for_dsi_fifo_empty(intel_dsi); |
209 | ||
5505a244 | 210 | intel_dsi_port_enable(encoder); |
4e646495 | 211 | } |
2634fd7f SK |
212 | } |
213 | ||
214 | static void intel_dsi_pre_enable(struct intel_encoder *encoder) | |
215 | { | |
20e5bf66 SK |
216 | struct drm_device *dev = encoder->base.dev; |
217 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2634fd7f | 218 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); |
20e5bf66 SK |
219 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); |
220 | enum pipe pipe = intel_crtc->pipe; | |
221 | u32 tmp; | |
2634fd7f SK |
222 | |
223 | DRM_DEBUG_KMS("\n"); | |
224 | ||
20e5bf66 SK |
225 | /* Disable DPOunit clock gating, can stall pipe |
226 | * and we need DPLL REFA always enabled */ | |
227 | tmp = I915_READ(DPLL(pipe)); | |
228 | tmp |= DPLL_REFA_CLK_ENABLE_VLV; | |
229 | I915_WRITE(DPLL(pipe), tmp); | |
230 | ||
f573de5a SK |
231 | /* update the hw state for DPLL */ |
232 | intel_crtc->config.dpll_hw_state.dpll = DPLL_INTEGRATED_CLOCK_VLV | | |
7f3de833 | 233 | DPLL_REFA_CLK_ENABLE_VLV; |
f573de5a | 234 | |
20e5bf66 SK |
235 | tmp = I915_READ(DSPCLK_GATE_D); |
236 | tmp |= DPOUNIT_CLOCK_GATE_DISABLE; | |
237 | I915_WRITE(DSPCLK_GATE_D, tmp); | |
2634fd7f SK |
238 | |
239 | /* put device in ready state */ | |
240 | intel_dsi_device_ready(encoder); | |
4e646495 | 241 | |
df38e655 SK |
242 | msleep(intel_dsi->panel_on_delay); |
243 | ||
20e5bf66 SK |
244 | if (intel_dsi->dev.dev_ops->panel_reset) |
245 | intel_dsi->dev.dev_ops->panel_reset(&intel_dsi->dev); | |
246 | ||
2634fd7f SK |
247 | if (intel_dsi->dev.dev_ops->send_otp_cmds) |
248 | intel_dsi->dev.dev_ops->send_otp_cmds(&intel_dsi->dev); | |
249 | ||
1381308b SK |
250 | wait_for_dsi_fifo_empty(intel_dsi); |
251 | ||
2634fd7f SK |
252 | /* Enable port in pre-enable phase itself because as per hw team |
253 | * recommendation, port should be enabled befor plane & pipe */ | |
254 | intel_dsi_enable(encoder); | |
255 | } | |
256 | ||
257 | static void intel_dsi_enable_nop(struct intel_encoder *encoder) | |
258 | { | |
259 | DRM_DEBUG_KMS("\n"); | |
260 | ||
261 | /* for DSI port enable has to be done before pipe | |
262 | * and plane enable, so port enable is done in | |
263 | * pre_enable phase itself unlike other encoders | |
264 | */ | |
4e646495 JN |
265 | } |
266 | ||
c315faf8 ID |
267 | static void intel_dsi_pre_disable(struct intel_encoder *encoder) |
268 | { | |
269 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); | |
270 | ||
271 | DRM_DEBUG_KMS("\n"); | |
272 | ||
273 | if (is_vid_mode(intel_dsi)) { | |
274 | /* Send Shutdown command to the panel in LP mode */ | |
275 | dpi_send_cmd(intel_dsi, SHUTDOWN, DPI_LP_MODE_EN); | |
276 | msleep(10); | |
277 | } | |
278 | } | |
279 | ||
4e646495 JN |
280 | static void intel_dsi_disable(struct intel_encoder *encoder) |
281 | { | |
1dbd7cb2 SK |
282 | struct drm_device *dev = encoder->base.dev; |
283 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4e646495 JN |
284 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); |
285 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); | |
e7d7cad0 | 286 | enum port port = intel_dsi_pipe_to_port(intel_crtc->pipe); |
4e646495 JN |
287 | u32 temp; |
288 | ||
289 | DRM_DEBUG_KMS("\n"); | |
290 | ||
4e646495 | 291 | if (is_vid_mode(intel_dsi)) { |
1381308b SK |
292 | wait_for_dsi_fifo_empty(intel_dsi); |
293 | ||
5505a244 | 294 | intel_dsi_port_disable(encoder); |
4e646495 JN |
295 | msleep(2); |
296 | } | |
297 | ||
339023ec | 298 | /* Panel commands can be sent when clock is in LP11 */ |
e7d7cad0 | 299 | I915_WRITE(MIPI_DEVICE_READY(port), 0x0); |
339023ec | 300 | |
e7d7cad0 | 301 | temp = I915_READ(MIPI_CTRL(port)); |
339023ec | 302 | temp &= ~ESCAPE_CLOCK_DIVIDER_MASK; |
e7d7cad0 | 303 | I915_WRITE(MIPI_CTRL(port), temp | |
7f3de833 DV |
304 | intel_dsi->escape_clk_div << |
305 | ESCAPE_CLOCK_DIVIDER_SHIFT); | |
339023ec | 306 | |
e7d7cad0 | 307 | I915_WRITE(MIPI_EOT_DISABLE(port), CLOCKSTOP); |
339023ec | 308 | |
e7d7cad0 | 309 | temp = I915_READ(MIPI_DSI_FUNC_PRG(port)); |
339023ec | 310 | temp &= ~VID_MODE_FORMAT_MASK; |
e7d7cad0 | 311 | I915_WRITE(MIPI_DSI_FUNC_PRG(port), temp); |
339023ec | 312 | |
e7d7cad0 | 313 | I915_WRITE(MIPI_DEVICE_READY(port), 0x1); |
339023ec | 314 | |
1dbd7cb2 SK |
315 | /* if disable packets are sent before sending shutdown packet then in |
316 | * some next enable sequence send turn on packet error is observed */ | |
317 | if (intel_dsi->dev.dev_ops->disable) | |
318 | intel_dsi->dev.dev_ops->disable(&intel_dsi->dev); | |
1381308b SK |
319 | |
320 | wait_for_dsi_fifo_empty(intel_dsi); | |
4e646495 JN |
321 | } |
322 | ||
1dbd7cb2 | 323 | static void intel_dsi_clear_device_ready(struct intel_encoder *encoder) |
4e646495 | 324 | { |
1dbd7cb2 SK |
325 | struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; |
326 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); | |
e7d7cad0 | 327 | enum port port = intel_dsi_pipe_to_port(intel_crtc->pipe); |
1dbd7cb2 SK |
328 | u32 val; |
329 | ||
4e646495 | 330 | DRM_DEBUG_KMS("\n"); |
be4fc046 | 331 | |
e7d7cad0 | 332 | I915_WRITE(MIPI_DEVICE_READY(port), DEVICE_READY | ULPS_STATE_ENTER); |
1dbd7cb2 SK |
333 | usleep_range(2000, 2500); |
334 | ||
e7d7cad0 | 335 | I915_WRITE(MIPI_DEVICE_READY(port), DEVICE_READY | ULPS_STATE_EXIT); |
1dbd7cb2 SK |
336 | usleep_range(2000, 2500); |
337 | ||
e7d7cad0 | 338 | I915_WRITE(MIPI_DEVICE_READY(port), DEVICE_READY | ULPS_STATE_ENTER); |
1dbd7cb2 SK |
339 | usleep_range(2000, 2500); |
340 | ||
e7d7cad0 | 341 | if (wait_for(((I915_READ(MIPI_PORT_CTRL(port)) & AFE_LATCHOUT) |
7f3de833 | 342 | == 0x00000), 30)) |
1dbd7cb2 SK |
343 | DRM_ERROR("DSI LP not going Low\n"); |
344 | ||
e7d7cad0 JN |
345 | val = I915_READ(MIPI_PORT_CTRL(port)); |
346 | I915_WRITE(MIPI_PORT_CTRL(port), val & ~LP_OUTPUT_HOLD); | |
aceb365c SK |
347 | usleep_range(1000, 1500); |
348 | ||
e7d7cad0 | 349 | I915_WRITE(MIPI_DEVICE_READY(port), 0x00); |
1dbd7cb2 SK |
350 | usleep_range(2000, 2500); |
351 | ||
be4fc046 | 352 | vlv_disable_dsi_pll(encoder); |
4e646495 | 353 | } |
20e5bf66 | 354 | |
1dbd7cb2 SK |
355 | static void intel_dsi_post_disable(struct intel_encoder *encoder) |
356 | { | |
20e5bf66 | 357 | struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; |
1dbd7cb2 | 358 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); |
20e5bf66 | 359 | u32 val; |
1dbd7cb2 SK |
360 | |
361 | DRM_DEBUG_KMS("\n"); | |
362 | ||
c315faf8 ID |
363 | intel_dsi_disable(encoder); |
364 | ||
1dbd7cb2 SK |
365 | intel_dsi_clear_device_ready(encoder); |
366 | ||
20e5bf66 SK |
367 | val = I915_READ(DSPCLK_GATE_D); |
368 | val &= ~DPOUNIT_CLOCK_GATE_DISABLE; | |
369 | I915_WRITE(DSPCLK_GATE_D, val); | |
370 | ||
1dbd7cb2 SK |
371 | if (intel_dsi->dev.dev_ops->disable_panel_power) |
372 | intel_dsi->dev.dev_ops->disable_panel_power(&intel_dsi->dev); | |
df38e655 SK |
373 | |
374 | msleep(intel_dsi->panel_off_delay); | |
375 | msleep(intel_dsi->panel_pwr_cycle_delay); | |
1dbd7cb2 | 376 | } |
4e646495 JN |
377 | |
378 | static bool intel_dsi_get_hw_state(struct intel_encoder *encoder, | |
379 | enum pipe *pipe) | |
380 | { | |
381 | struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; | |
6d129bea | 382 | enum intel_display_power_domain power_domain; |
e7d7cad0 JN |
383 | u32 port_ctl, func; |
384 | enum port port; | |
4e646495 JN |
385 | |
386 | DRM_DEBUG_KMS("\n"); | |
387 | ||
6d129bea | 388 | power_domain = intel_display_port_power_domain(encoder); |
f458ebbc | 389 | if (!intel_display_power_is_enabled(dev_priv, power_domain)) |
6d129bea ID |
390 | return false; |
391 | ||
4e646495 | 392 | /* XXX: this only works for one DSI output */ |
e7d7cad0 JN |
393 | for_each_dsi_port(port, (1 << PORT_A) | (1 << PORT_C)) { |
394 | port_ctl = I915_READ(MIPI_PORT_CTRL(port)); | |
395 | func = I915_READ(MIPI_DSI_FUNC_PRG(port)); | |
4e646495 | 396 | |
e7d7cad0 JN |
397 | if ((port_ctl & DPI_ENABLE) || (func & CMD_MODE_DATA_WIDTH_MASK)) { |
398 | if (I915_READ(MIPI_DEVICE_READY(port)) & DEVICE_READY) { | |
399 | *pipe = port == PORT_A ? PIPE_A : PIPE_C; | |
4e646495 JN |
400 | return true; |
401 | } | |
402 | } | |
403 | } | |
404 | ||
405 | return false; | |
406 | } | |
407 | ||
408 | static void intel_dsi_get_config(struct intel_encoder *encoder, | |
409 | struct intel_crtc_config *pipe_config) | |
410 | { | |
f573de5a | 411 | u32 pclk; |
4e646495 JN |
412 | DRM_DEBUG_KMS("\n"); |
413 | ||
f573de5a SK |
414 | /* |
415 | * DPLL_MD is not used in case of DSI, reading will get some default value | |
416 | * set dpll_md = 0 | |
417 | */ | |
418 | pipe_config->dpll_hw_state.dpll_md = 0; | |
419 | ||
420 | pclk = vlv_get_dsi_pclk(encoder, pipe_config->pipe_bpp); | |
421 | if (!pclk) | |
422 | return; | |
423 | ||
424 | pipe_config->adjusted_mode.crtc_clock = pclk; | |
425 | pipe_config->port_clock = pclk; | |
4e646495 JN |
426 | } |
427 | ||
c19de8eb DL |
428 | static enum drm_mode_status |
429 | intel_dsi_mode_valid(struct drm_connector *connector, | |
430 | struct drm_display_mode *mode) | |
4e646495 JN |
431 | { |
432 | struct intel_connector *intel_connector = to_intel_connector(connector); | |
433 | struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode; | |
434 | struct intel_dsi *intel_dsi = intel_attached_dsi(connector); | |
435 | ||
436 | DRM_DEBUG_KMS("\n"); | |
437 | ||
438 | if (mode->flags & DRM_MODE_FLAG_DBLSCAN) { | |
439 | DRM_DEBUG_KMS("MODE_NO_DBLESCAN\n"); | |
440 | return MODE_NO_DBLESCAN; | |
441 | } | |
442 | ||
443 | if (fixed_mode) { | |
444 | if (mode->hdisplay > fixed_mode->hdisplay) | |
445 | return MODE_PANEL; | |
446 | if (mode->vdisplay > fixed_mode->vdisplay) | |
447 | return MODE_PANEL; | |
448 | } | |
449 | ||
450 | return intel_dsi->dev.dev_ops->mode_valid(&intel_dsi->dev, mode); | |
451 | } | |
452 | ||
453 | /* return txclkesc cycles in terms of divider and duration in us */ | |
454 | static u16 txclkesc(u32 divider, unsigned int us) | |
455 | { | |
456 | switch (divider) { | |
457 | case ESCAPE_CLOCK_DIVIDER_1: | |
458 | default: | |
459 | return 20 * us; | |
460 | case ESCAPE_CLOCK_DIVIDER_2: | |
461 | return 10 * us; | |
462 | case ESCAPE_CLOCK_DIVIDER_4: | |
463 | return 5 * us; | |
464 | } | |
465 | } | |
466 | ||
467 | /* return pixels in terms of txbyteclkhs */ | |
7f0c8605 SK |
468 | static u16 txbyteclkhs(u16 pixels, int bpp, int lane_count, |
469 | u16 burst_mode_ratio) | |
4e646495 | 470 | { |
7f0c8605 | 471 | return DIV_ROUND_UP(DIV_ROUND_UP(pixels * bpp * burst_mode_ratio, |
7f3de833 | 472 | 8 * 100), lane_count); |
4e646495 JN |
473 | } |
474 | ||
475 | static void set_dsi_timings(struct drm_encoder *encoder, | |
476 | const struct drm_display_mode *mode) | |
477 | { | |
478 | struct drm_device *dev = encoder->dev; | |
479 | struct drm_i915_private *dev_priv = dev->dev_private; | |
480 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); | |
481 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); | |
e7d7cad0 | 482 | enum port port = intel_dsi_pipe_to_port(intel_crtc->pipe); |
4e646495 JN |
483 | unsigned int bpp = intel_crtc->config.pipe_bpp; |
484 | unsigned int lane_count = intel_dsi->lane_count; | |
485 | ||
486 | u16 hactive, hfp, hsync, hbp, vfp, vsync, vbp; | |
487 | ||
488 | hactive = mode->hdisplay; | |
489 | hfp = mode->hsync_start - mode->hdisplay; | |
490 | hsync = mode->hsync_end - mode->hsync_start; | |
491 | hbp = mode->htotal - mode->hsync_end; | |
492 | ||
493 | vfp = mode->vsync_start - mode->vdisplay; | |
494 | vsync = mode->vsync_end - mode->vsync_start; | |
495 | vbp = mode->vtotal - mode->vsync_end; | |
496 | ||
497 | /* horizontal values are in terms of high speed byte clock */ | |
7f0c8605 | 498 | hactive = txbyteclkhs(hactive, bpp, lane_count, |
7f3de833 | 499 | intel_dsi->burst_mode_ratio); |
7f0c8605 SK |
500 | hfp = txbyteclkhs(hfp, bpp, lane_count, intel_dsi->burst_mode_ratio); |
501 | hsync = txbyteclkhs(hsync, bpp, lane_count, | |
7f3de833 | 502 | intel_dsi->burst_mode_ratio); |
7f0c8605 | 503 | hbp = txbyteclkhs(hbp, bpp, lane_count, intel_dsi->burst_mode_ratio); |
4e646495 | 504 | |
e7d7cad0 JN |
505 | I915_WRITE(MIPI_HACTIVE_AREA_COUNT(port), hactive); |
506 | I915_WRITE(MIPI_HFP_COUNT(port), hfp); | |
4e646495 JN |
507 | |
508 | /* meaningful for video mode non-burst sync pulse mode only, can be zero | |
509 | * for non-burst sync events and burst modes */ | |
e7d7cad0 JN |
510 | I915_WRITE(MIPI_HSYNC_PADDING_COUNT(port), hsync); |
511 | I915_WRITE(MIPI_HBP_COUNT(port), hbp); | |
4e646495 JN |
512 | |
513 | /* vertical values are in terms of lines */ | |
e7d7cad0 JN |
514 | I915_WRITE(MIPI_VFP_COUNT(port), vfp); |
515 | I915_WRITE(MIPI_VSYNC_PADDING_COUNT(port), vsync); | |
516 | I915_WRITE(MIPI_VBP_COUNT(port), vbp); | |
4e646495 JN |
517 | } |
518 | ||
07e4fb9e | 519 | static void intel_dsi_prepare(struct intel_encoder *intel_encoder) |
4e646495 JN |
520 | { |
521 | struct drm_encoder *encoder = &intel_encoder->base; | |
522 | struct drm_device *dev = encoder->dev; | |
523 | struct drm_i915_private *dev_priv = dev->dev_private; | |
524 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); | |
525 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); | |
526 | struct drm_display_mode *adjusted_mode = | |
527 | &intel_crtc->config.adjusted_mode; | |
e7d7cad0 | 528 | enum port port = intel_dsi_pipe_to_port(intel_crtc->pipe); |
4e646495 JN |
529 | unsigned int bpp = intel_crtc->config.pipe_bpp; |
530 | u32 val, tmp; | |
531 | ||
e7d7cad0 | 532 | DRM_DEBUG_KMS("pipe %c\n", pipe_name(intel_crtc->pipe)); |
4e646495 JN |
533 | |
534 | /* escape clock divider, 20MHz, shared for A and C. device ready must be | |
535 | * off when doing this! txclkesc? */ | |
e7d7cad0 | 536 | tmp = I915_READ(MIPI_CTRL(PORT_A)); |
4e646495 | 537 | tmp &= ~ESCAPE_CLOCK_DIVIDER_MASK; |
e7d7cad0 | 538 | I915_WRITE(MIPI_CTRL(PORT_A), tmp | ESCAPE_CLOCK_DIVIDER_1); |
4e646495 JN |
539 | |
540 | /* read request priority is per pipe */ | |
e7d7cad0 | 541 | tmp = I915_READ(MIPI_CTRL(port)); |
4e646495 | 542 | tmp &= ~READ_REQUEST_PRIORITY_MASK; |
e7d7cad0 | 543 | I915_WRITE(MIPI_CTRL(port), tmp | READ_REQUEST_PRIORITY_HIGH); |
4e646495 JN |
544 | |
545 | /* XXX: why here, why like this? handling in irq handler?! */ | |
e7d7cad0 JN |
546 | I915_WRITE(MIPI_INTR_STAT(port), 0xffffffff); |
547 | I915_WRITE(MIPI_INTR_EN(port), 0xffffffff); | |
4e646495 | 548 | |
e7d7cad0 | 549 | I915_WRITE(MIPI_DPHY_PARAM(port), intel_dsi->dphy_reg); |
4e646495 | 550 | |
e7d7cad0 | 551 | I915_WRITE(MIPI_DPI_RESOLUTION(port), |
4e646495 JN |
552 | adjusted_mode->vdisplay << VERTICAL_ADDRESS_SHIFT | |
553 | adjusted_mode->hdisplay << HORIZONTAL_ADDRESS_SHIFT); | |
554 | ||
555 | set_dsi_timings(encoder, adjusted_mode); | |
556 | ||
557 | val = intel_dsi->lane_count << DATA_LANES_PRG_REG_SHIFT; | |
558 | if (is_cmd_mode(intel_dsi)) { | |
559 | val |= intel_dsi->channel << CMD_MODE_CHANNEL_NUMBER_SHIFT; | |
560 | val |= CMD_MODE_DATA_WIDTH_8_BIT; /* XXX */ | |
561 | } else { | |
562 | val |= intel_dsi->channel << VID_MODE_CHANNEL_NUMBER_SHIFT; | |
563 | ||
564 | /* XXX: cross-check bpp vs. pixel format? */ | |
565 | val |= intel_dsi->pixel_format; | |
566 | } | |
e7d7cad0 | 567 | I915_WRITE(MIPI_DSI_FUNC_PRG(port), val); |
4e646495 JN |
568 | |
569 | /* timeouts for recovery. one frame IIUC. if counter expires, EOT and | |
570 | * stop state. */ | |
571 | ||
572 | /* | |
573 | * In burst mode, value greater than one DPI line Time in byte clock | |
574 | * (txbyteclkhs) To timeout this timer 1+ of the above said value is | |
575 | * recommended. | |
576 | * | |
577 | * In non-burst mode, Value greater than one DPI frame time in byte | |
578 | * clock(txbyteclkhs) To timeout this timer 1+ of the above said value | |
579 | * is recommended. | |
580 | * | |
581 | * In DBI only mode, value greater than one DBI frame time in byte | |
582 | * clock(txbyteclkhs) To timeout this timer 1+ of the above said value | |
583 | * is recommended. | |
584 | */ | |
585 | ||
586 | if (is_vid_mode(intel_dsi) && | |
587 | intel_dsi->video_mode_format == VIDEO_MODE_BURST) { | |
e7d7cad0 | 588 | I915_WRITE(MIPI_HS_TX_TIMEOUT(port), |
4e646495 | 589 | txbyteclkhs(adjusted_mode->htotal, bpp, |
7f0c8605 SK |
590 | intel_dsi->lane_count, |
591 | intel_dsi->burst_mode_ratio) + 1); | |
4e646495 | 592 | } else { |
e7d7cad0 | 593 | I915_WRITE(MIPI_HS_TX_TIMEOUT(port), |
4e646495 JN |
594 | txbyteclkhs(adjusted_mode->vtotal * |
595 | adjusted_mode->htotal, | |
7f0c8605 SK |
596 | bpp, intel_dsi->lane_count, |
597 | intel_dsi->burst_mode_ratio) + 1); | |
4e646495 | 598 | } |
e7d7cad0 JN |
599 | I915_WRITE(MIPI_LP_RX_TIMEOUT(port), intel_dsi->lp_rx_timeout); |
600 | I915_WRITE(MIPI_TURN_AROUND_TIMEOUT(port), intel_dsi->turn_arnd_val); | |
601 | I915_WRITE(MIPI_DEVICE_RESET_TIMER(port), intel_dsi->rst_timer_val); | |
4e646495 JN |
602 | |
603 | /* dphy stuff */ | |
604 | ||
605 | /* in terms of low power clock */ | |
e7d7cad0 | 606 | I915_WRITE(MIPI_INIT_COUNT(port), txclkesc(intel_dsi->escape_clk_div, 100)); |
f1c79f16 SK |
607 | |
608 | val = 0; | |
609 | if (intel_dsi->eotp_pkt == 0) | |
610 | val |= EOT_DISABLE; | |
611 | ||
612 | if (intel_dsi->clock_stop) | |
613 | val |= CLOCKSTOP; | |
4e646495 JN |
614 | |
615 | /* recovery disables */ | |
e7d7cad0 | 616 | I915_WRITE(MIPI_EOT_DISABLE(port), val); |
4e646495 | 617 | |
cf4dbd2e | 618 | /* in terms of low power clock */ |
e7d7cad0 | 619 | I915_WRITE(MIPI_INIT_COUNT(port), intel_dsi->init_count); |
cf4dbd2e | 620 | |
4e646495 JN |
621 | /* in terms of txbyteclkhs. actual high to low switch + |
622 | * MIPI_STOP_STATE_STALL * MIPI_LP_BYTECLK. | |
623 | * | |
624 | * XXX: write MIPI_STOP_STATE_STALL? | |
625 | */ | |
e7d7cad0 | 626 | I915_WRITE(MIPI_HIGH_LOW_SWITCH_COUNT(port), |
7f3de833 | 627 | intel_dsi->hs_to_lp_count); |
4e646495 JN |
628 | |
629 | /* XXX: low power clock equivalence in terms of byte clock. the number | |
630 | * of byte clocks occupied in one low power clock. based on txbyteclkhs | |
631 | * and txclkesc. txclkesc time / txbyteclk time * (105 + | |
632 | * MIPI_STOP_STATE_STALL) / 105.??? | |
633 | */ | |
e7d7cad0 | 634 | I915_WRITE(MIPI_LP_BYTECLK(port), intel_dsi->lp_byte_clk); |
4e646495 JN |
635 | |
636 | /* the bw essential for transmitting 16 long packets containing 252 | |
637 | * bytes meant for dcs write memory command is programmed in this | |
638 | * register in terms of byte clocks. based on dsi transfer rate and the | |
639 | * number of lanes configured the time taken to transmit 16 long packets | |
640 | * in a dsi stream varies. */ | |
e7d7cad0 | 641 | I915_WRITE(MIPI_DBI_BW_CTRL(port), intel_dsi->bw_timer); |
4e646495 | 642 | |
e7d7cad0 | 643 | I915_WRITE(MIPI_CLK_LANE_SWITCH_TIME_CNT(port), |
f6da2842 SK |
644 | intel_dsi->clk_lp_to_hs_count << LP_HS_SSW_CNT_SHIFT | |
645 | intel_dsi->clk_hs_to_lp_count << HS_LP_PWR_SW_CNT_SHIFT); | |
4e646495 JN |
646 | |
647 | if (is_vid_mode(intel_dsi)) | |
24d9c401 SK |
648 | /* Some panels might have resolution which is not a multiple of |
649 | * 64 like 1366 x 768. Enable RANDOM resolution support for such | |
650 | * panels by default */ | |
e7d7cad0 | 651 | I915_WRITE(MIPI_VIDEO_MODE_FORMAT(port), |
7f3de833 DV |
652 | intel_dsi->video_frmt_cfg_bits | |
653 | intel_dsi->video_mode_format | | |
654 | IP_TG_CONFIG | | |
655 | RANDOM_DPI_DISPLAY_RESOLUTION); | |
4e646495 JN |
656 | } |
657 | ||
07e4fb9e DV |
658 | static void intel_dsi_pre_pll_enable(struct intel_encoder *encoder) |
659 | { | |
660 | DRM_DEBUG_KMS("\n"); | |
661 | ||
662 | intel_dsi_prepare(encoder); | |
663 | ||
664 | vlv_enable_dsi_pll(encoder); | |
665 | } | |
666 | ||
4e646495 JN |
667 | static enum drm_connector_status |
668 | intel_dsi_detect(struct drm_connector *connector, bool force) | |
669 | { | |
670 | struct intel_dsi *intel_dsi = intel_attached_dsi(connector); | |
671dedd2 ID |
671 | struct intel_encoder *intel_encoder = &intel_dsi->base; |
672 | enum intel_display_power_domain power_domain; | |
673 | enum drm_connector_status connector_status; | |
674 | struct drm_i915_private *dev_priv = intel_encoder->base.dev->dev_private; | |
675 | ||
4e646495 | 676 | DRM_DEBUG_KMS("\n"); |
671dedd2 ID |
677 | power_domain = intel_display_port_power_domain(intel_encoder); |
678 | ||
679 | intel_display_power_get(dev_priv, power_domain); | |
680 | connector_status = intel_dsi->dev.dev_ops->detect(&intel_dsi->dev); | |
681 | intel_display_power_put(dev_priv, power_domain); | |
682 | ||
683 | return connector_status; | |
4e646495 JN |
684 | } |
685 | ||
686 | static int intel_dsi_get_modes(struct drm_connector *connector) | |
687 | { | |
688 | struct intel_connector *intel_connector = to_intel_connector(connector); | |
689 | struct drm_display_mode *mode; | |
690 | ||
691 | DRM_DEBUG_KMS("\n"); | |
692 | ||
693 | if (!intel_connector->panel.fixed_mode) { | |
694 | DRM_DEBUG_KMS("no fixed mode\n"); | |
695 | return 0; | |
696 | } | |
697 | ||
698 | mode = drm_mode_duplicate(connector->dev, | |
699 | intel_connector->panel.fixed_mode); | |
700 | if (!mode) { | |
701 | DRM_DEBUG_KMS("drm_mode_duplicate failed\n"); | |
702 | return 0; | |
703 | } | |
704 | ||
705 | drm_mode_probed_add(connector, mode); | |
706 | return 1; | |
707 | } | |
708 | ||
709 | static void intel_dsi_destroy(struct drm_connector *connector) | |
710 | { | |
711 | struct intel_connector *intel_connector = to_intel_connector(connector); | |
712 | ||
713 | DRM_DEBUG_KMS("\n"); | |
714 | intel_panel_fini(&intel_connector->panel); | |
4e646495 JN |
715 | drm_connector_cleanup(connector); |
716 | kfree(connector); | |
717 | } | |
718 | ||
719 | static const struct drm_encoder_funcs intel_dsi_funcs = { | |
720 | .destroy = intel_encoder_destroy, | |
721 | }; | |
722 | ||
723 | static const struct drm_connector_helper_funcs intel_dsi_connector_helper_funcs = { | |
724 | .get_modes = intel_dsi_get_modes, | |
725 | .mode_valid = intel_dsi_mode_valid, | |
726 | .best_encoder = intel_best_encoder, | |
727 | }; | |
728 | ||
729 | static const struct drm_connector_funcs intel_dsi_connector_funcs = { | |
730 | .dpms = intel_connector_dpms, | |
731 | .detect = intel_dsi_detect, | |
732 | .destroy = intel_dsi_destroy, | |
733 | .fill_modes = drm_helper_probe_single_connector_modes, | |
734 | }; | |
735 | ||
4328633d | 736 | void intel_dsi_init(struct drm_device *dev) |
4e646495 JN |
737 | { |
738 | struct intel_dsi *intel_dsi; | |
739 | struct intel_encoder *intel_encoder; | |
740 | struct drm_encoder *encoder; | |
741 | struct intel_connector *intel_connector; | |
742 | struct drm_connector *connector; | |
743 | struct drm_display_mode *fixed_mode = NULL; | |
b6fdd0f2 | 744 | struct drm_i915_private *dev_priv = dev->dev_private; |
4e646495 JN |
745 | const struct intel_dsi_device *dsi; |
746 | unsigned int i; | |
747 | ||
748 | DRM_DEBUG_KMS("\n"); | |
749 | ||
3e6bd011 SK |
750 | /* There is no detection method for MIPI so rely on VBT */ |
751 | if (!dev_priv->vbt.has_mipi) | |
4328633d | 752 | return; |
3e6bd011 | 753 | |
868d665b CJ |
754 | if (IS_VALLEYVIEW(dev)) { |
755 | dev_priv->mipi_mmio_base = VLV_MIPI_BASE; | |
756 | } else { | |
757 | DRM_ERROR("Unsupported Mipi device to reg base"); | |
758 | return; | |
759 | } | |
3e6bd011 | 760 | |
4e646495 JN |
761 | intel_dsi = kzalloc(sizeof(*intel_dsi), GFP_KERNEL); |
762 | if (!intel_dsi) | |
4328633d | 763 | return; |
4e646495 JN |
764 | |
765 | intel_connector = kzalloc(sizeof(*intel_connector), GFP_KERNEL); | |
766 | if (!intel_connector) { | |
767 | kfree(intel_dsi); | |
4328633d | 768 | return; |
4e646495 JN |
769 | } |
770 | ||
771 | intel_encoder = &intel_dsi->base; | |
772 | encoder = &intel_encoder->base; | |
773 | intel_dsi->attached_connector = intel_connector; | |
774 | ||
775 | connector = &intel_connector->base; | |
776 | ||
777 | drm_encoder_init(dev, encoder, &intel_dsi_funcs, DRM_MODE_ENCODER_DSI); | |
778 | ||
779 | /* XXX: very likely not all of these are needed */ | |
780 | intel_encoder->hot_plug = intel_dsi_hot_plug; | |
781 | intel_encoder->compute_config = intel_dsi_compute_config; | |
782 | intel_encoder->pre_pll_enable = intel_dsi_pre_pll_enable; | |
783 | intel_encoder->pre_enable = intel_dsi_pre_enable; | |
2634fd7f | 784 | intel_encoder->enable = intel_dsi_enable_nop; |
c315faf8 | 785 | intel_encoder->disable = intel_dsi_pre_disable; |
4e646495 JN |
786 | intel_encoder->post_disable = intel_dsi_post_disable; |
787 | intel_encoder->get_hw_state = intel_dsi_get_hw_state; | |
788 | intel_encoder->get_config = intel_dsi_get_config; | |
789 | ||
790 | intel_connector->get_hw_state = intel_connector_get_hw_state; | |
4932e2c3 | 791 | intel_connector->unregister = intel_connector_unregister; |
4e646495 | 792 | |
e7d7cad0 | 793 | /* Pipe A maps to MIPI DSI port A, pipe B maps to MIPI DSI port C */ |
17af40a8 | 794 | if (dev_priv->vbt.dsi.port == DVO_PORT_MIPIA) { |
e7d7cad0 | 795 | intel_encoder->crtc_mask = (1 << PIPE_A); |
17af40a8 JN |
796 | intel_dsi->ports = (1 << PORT_A); |
797 | } else if (dev_priv->vbt.dsi.port == DVO_PORT_MIPIC) { | |
e7d7cad0 | 798 | intel_encoder->crtc_mask = (1 << PIPE_B); |
17af40a8 JN |
799 | intel_dsi->ports = (1 << PORT_C); |
800 | } | |
e7d7cad0 | 801 | |
4e646495 JN |
802 | for (i = 0; i < ARRAY_SIZE(intel_dsi_devices); i++) { |
803 | dsi = &intel_dsi_devices[i]; | |
804 | intel_dsi->dev = *dsi; | |
805 | ||
806 | if (dsi->dev_ops->init(&intel_dsi->dev)) | |
807 | break; | |
808 | } | |
809 | ||
810 | if (i == ARRAY_SIZE(intel_dsi_devices)) { | |
811 | DRM_DEBUG_KMS("no device found\n"); | |
812 | goto err; | |
813 | } | |
814 | ||
815 | intel_encoder->type = INTEL_OUTPUT_DSI; | |
bc079e8b | 816 | intel_encoder->cloneable = 0; |
4e646495 JN |
817 | drm_connector_init(dev, connector, &intel_dsi_connector_funcs, |
818 | DRM_MODE_CONNECTOR_DSI); | |
819 | ||
820 | drm_connector_helper_add(connector, &intel_dsi_connector_helper_funcs); | |
821 | ||
822 | connector->display_info.subpixel_order = SubPixelHorizontalRGB; /*XXX*/ | |
823 | connector->interlace_allowed = false; | |
824 | connector->doublescan_allowed = false; | |
825 | ||
826 | intel_connector_attach_encoder(intel_connector, intel_encoder); | |
827 | ||
34ea3d38 | 828 | drm_connector_register(connector); |
4e646495 JN |
829 | |
830 | fixed_mode = dsi->dev_ops->get_modes(&intel_dsi->dev); | |
831 | if (!fixed_mode) { | |
832 | DRM_DEBUG_KMS("no fixed mode\n"); | |
833 | goto err; | |
834 | } | |
835 | ||
836 | fixed_mode->type |= DRM_MODE_TYPE_PREFERRED; | |
4b6ed685 | 837 | intel_panel_init(&intel_connector->panel, fixed_mode, NULL); |
4e646495 | 838 | |
4328633d | 839 | return; |
4e646495 JN |
840 | |
841 | err: | |
842 | drm_encoder_cleanup(&intel_encoder->base); | |
843 | kfree(intel_dsi); | |
844 | kfree(intel_connector); | |
4e646495 | 845 | } |