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4e646495 JN |
1 | /* |
2 | * Copyright © 2013 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
21 | * DEALINGS IN THE SOFTWARE. | |
22 | * | |
23 | * Author: Jani Nikula <jani.nikula@intel.com> | |
24 | */ | |
25 | ||
26 | #include <drm/drmP.h> | |
c6f95f27 | 27 | #include <drm/drm_atomic_helper.h> |
4e646495 JN |
28 | #include <drm/drm_crtc.h> |
29 | #include <drm/drm_edid.h> | |
30 | #include <drm/i915_drm.h> | |
593e0622 | 31 | #include <drm/drm_panel.h> |
7e9804fd | 32 | #include <drm/drm_mipi_dsi.h> |
4e646495 | 33 | #include <linux/slab.h> |
fc45e821 | 34 | #include <linux/gpio/consumer.h> |
4e646495 JN |
35 | #include "i915_drv.h" |
36 | #include "intel_drv.h" | |
37 | #include "intel_dsi.h" | |
4e646495 | 38 | |
593e0622 JN |
39 | static const struct { |
40 | u16 panel_id; | |
41 | struct drm_panel * (*init)(struct intel_dsi *intel_dsi, u16 panel_id); | |
42 | } intel_dsi_drivers[] = { | |
2ab8b458 SK |
43 | { |
44 | .panel_id = MIPI_DSI_GENERIC_PANEL_ID, | |
593e0622 | 45 | .init = vbt_panel_init, |
2ab8b458 | 46 | }, |
4e646495 JN |
47 | }; |
48 | ||
042ab0c3 R |
49 | /* return pixels in terms of txbyteclkhs */ |
50 | static u16 txbyteclkhs(u16 pixels, int bpp, int lane_count, | |
51 | u16 burst_mode_ratio) | |
52 | { | |
53 | return DIV_ROUND_UP(DIV_ROUND_UP(pixels * bpp * burst_mode_ratio, | |
54 | 8 * 100), lane_count); | |
55 | } | |
56 | ||
cefc4e18 R |
57 | /* return pixels equvalent to txbyteclkhs */ |
58 | static u16 pixels_from_txbyteclkhs(u16 clk_hs, int bpp, int lane_count, | |
59 | u16 burst_mode_ratio) | |
60 | { | |
61 | return DIV_ROUND_UP((clk_hs * lane_count * 8 * 100), | |
62 | (bpp * burst_mode_ratio)); | |
63 | } | |
64 | ||
43367ec9 R |
65 | enum mipi_dsi_pixel_format pixel_format_from_register_bits(u32 fmt) |
66 | { | |
67 | /* It just so happens the VBT matches register contents. */ | |
68 | switch (fmt) { | |
69 | case VID_MODE_FORMAT_RGB888: | |
70 | return MIPI_DSI_FMT_RGB888; | |
71 | case VID_MODE_FORMAT_RGB666: | |
72 | return MIPI_DSI_FMT_RGB666; | |
73 | case VID_MODE_FORMAT_RGB666_PACKED: | |
74 | return MIPI_DSI_FMT_RGB666_PACKED; | |
75 | case VID_MODE_FORMAT_RGB565: | |
76 | return MIPI_DSI_FMT_RGB565; | |
77 | default: | |
78 | MISSING_CASE(fmt); | |
79 | return MIPI_DSI_FMT_RGB666; | |
80 | } | |
81 | } | |
82 | ||
3870b89a | 83 | void wait_for_dsi_fifo_empty(struct intel_dsi *intel_dsi, enum port port) |
3b1808bf JN |
84 | { |
85 | struct drm_encoder *encoder = &intel_dsi->base.base; | |
86 | struct drm_device *dev = encoder->dev; | |
fac5e23e | 87 | struct drm_i915_private *dev_priv = to_i915(dev); |
3b1808bf JN |
88 | u32 mask; |
89 | ||
90 | mask = LP_CTRL_FIFO_EMPTY | HS_CTRL_FIFO_EMPTY | | |
91 | LP_DATA_FIFO_EMPTY | HS_DATA_FIFO_EMPTY; | |
92 | ||
9b6a2d72 CW |
93 | if (intel_wait_for_register(dev_priv, |
94 | MIPI_GEN_FIFO_STAT(port), mask, mask, | |
95 | 100)) | |
3b1808bf JN |
96 | DRM_ERROR("DPI FIFOs are not empty\n"); |
97 | } | |
98 | ||
f0f59a00 VS |
99 | static void write_data(struct drm_i915_private *dev_priv, |
100 | i915_reg_t reg, | |
7e9804fd JN |
101 | const u8 *data, u32 len) |
102 | { | |
103 | u32 i, j; | |
104 | ||
105 | for (i = 0; i < len; i += 4) { | |
106 | u32 val = 0; | |
107 | ||
108 | for (j = 0; j < min_t(u32, len - i, 4); j++) | |
109 | val |= *data++ << 8 * j; | |
110 | ||
111 | I915_WRITE(reg, val); | |
112 | } | |
113 | } | |
114 | ||
f0f59a00 VS |
115 | static void read_data(struct drm_i915_private *dev_priv, |
116 | i915_reg_t reg, | |
7e9804fd JN |
117 | u8 *data, u32 len) |
118 | { | |
119 | u32 i, j; | |
120 | ||
121 | for (i = 0; i < len; i += 4) { | |
122 | u32 val = I915_READ(reg); | |
123 | ||
124 | for (j = 0; j < min_t(u32, len - i, 4); j++) | |
125 | *data++ = val >> 8 * j; | |
126 | } | |
127 | } | |
128 | ||
129 | static ssize_t intel_dsi_host_transfer(struct mipi_dsi_host *host, | |
130 | const struct mipi_dsi_msg *msg) | |
131 | { | |
132 | struct intel_dsi_host *intel_dsi_host = to_intel_dsi_host(host); | |
133 | struct drm_device *dev = intel_dsi_host->intel_dsi->base.base.dev; | |
fac5e23e | 134 | struct drm_i915_private *dev_priv = to_i915(dev); |
7e9804fd JN |
135 | enum port port = intel_dsi_host->port; |
136 | struct mipi_dsi_packet packet; | |
137 | ssize_t ret; | |
138 | const u8 *header, *data; | |
f0f59a00 VS |
139 | i915_reg_t data_reg, ctrl_reg; |
140 | u32 data_mask, ctrl_mask; | |
7e9804fd JN |
141 | |
142 | ret = mipi_dsi_create_packet(&packet, msg); | |
143 | if (ret < 0) | |
144 | return ret; | |
145 | ||
146 | header = packet.header; | |
147 | data = packet.payload; | |
148 | ||
149 | if (msg->flags & MIPI_DSI_MSG_USE_LPM) { | |
150 | data_reg = MIPI_LP_GEN_DATA(port); | |
151 | data_mask = LP_DATA_FIFO_FULL; | |
152 | ctrl_reg = MIPI_LP_GEN_CTRL(port); | |
153 | ctrl_mask = LP_CTRL_FIFO_FULL; | |
154 | } else { | |
155 | data_reg = MIPI_HS_GEN_DATA(port); | |
156 | data_mask = HS_DATA_FIFO_FULL; | |
157 | ctrl_reg = MIPI_HS_GEN_CTRL(port); | |
158 | ctrl_mask = HS_CTRL_FIFO_FULL; | |
159 | } | |
160 | ||
161 | /* note: this is never true for reads */ | |
162 | if (packet.payload_length) { | |
8c6cea0b CW |
163 | if (intel_wait_for_register(dev_priv, |
164 | MIPI_GEN_FIFO_STAT(port), | |
165 | data_mask, 0, | |
166 | 50)) | |
7e9804fd JN |
167 | DRM_ERROR("Timeout waiting for HS/LP DATA FIFO !full\n"); |
168 | ||
169 | write_data(dev_priv, data_reg, packet.payload, | |
170 | packet.payload_length); | |
171 | } | |
172 | ||
173 | if (msg->rx_len) { | |
174 | I915_WRITE(MIPI_INTR_STAT(port), GEN_READ_DATA_AVAIL); | |
175 | } | |
176 | ||
84c2aa90 CW |
177 | if (intel_wait_for_register(dev_priv, |
178 | MIPI_GEN_FIFO_STAT(port), | |
179 | ctrl_mask, 0, | |
180 | 50)) { | |
7e9804fd JN |
181 | DRM_ERROR("Timeout waiting for HS/LP CTRL FIFO !full\n"); |
182 | } | |
183 | ||
184 | I915_WRITE(ctrl_reg, header[2] << 16 | header[1] << 8 | header[0]); | |
185 | ||
186 | /* ->rx_len is set only for reads */ | |
187 | if (msg->rx_len) { | |
188 | data_mask = GEN_READ_DATA_AVAIL; | |
e7615b37 CW |
189 | if (intel_wait_for_register(dev_priv, |
190 | MIPI_INTR_STAT(port), | |
191 | data_mask, data_mask, | |
192 | 50)) | |
7e9804fd JN |
193 | DRM_ERROR("Timeout waiting for read data.\n"); |
194 | ||
195 | read_data(dev_priv, data_reg, msg->rx_buf, msg->rx_len); | |
196 | } | |
197 | ||
198 | /* XXX: fix for reads and writes */ | |
199 | return 4 + packet.payload_length; | |
200 | } | |
201 | ||
202 | static int intel_dsi_host_attach(struct mipi_dsi_host *host, | |
203 | struct mipi_dsi_device *dsi) | |
204 | { | |
205 | return 0; | |
206 | } | |
207 | ||
208 | static int intel_dsi_host_detach(struct mipi_dsi_host *host, | |
209 | struct mipi_dsi_device *dsi) | |
210 | { | |
211 | return 0; | |
212 | } | |
213 | ||
214 | static const struct mipi_dsi_host_ops intel_dsi_host_ops = { | |
215 | .attach = intel_dsi_host_attach, | |
216 | .detach = intel_dsi_host_detach, | |
217 | .transfer = intel_dsi_host_transfer, | |
218 | }; | |
219 | ||
220 | static struct intel_dsi_host *intel_dsi_host_init(struct intel_dsi *intel_dsi, | |
221 | enum port port) | |
222 | { | |
223 | struct intel_dsi_host *host; | |
224 | struct mipi_dsi_device *device; | |
225 | ||
226 | host = kzalloc(sizeof(*host), GFP_KERNEL); | |
227 | if (!host) | |
228 | return NULL; | |
229 | ||
230 | host->base.ops = &intel_dsi_host_ops; | |
231 | host->intel_dsi = intel_dsi; | |
232 | host->port = port; | |
233 | ||
234 | /* | |
235 | * We should call mipi_dsi_host_register(&host->base) here, but we don't | |
236 | * have a host->dev, and we don't have OF stuff either. So just use the | |
237 | * dsi framework as a library and hope for the best. Create the dsi | |
238 | * devices by ourselves here too. Need to be careful though, because we | |
239 | * don't initialize any of the driver model devices here. | |
240 | */ | |
241 | device = kzalloc(sizeof(*device), GFP_KERNEL); | |
242 | if (!device) { | |
243 | kfree(host); | |
244 | return NULL; | |
245 | } | |
246 | ||
247 | device->host = &host->base; | |
248 | host->device = device; | |
249 | ||
250 | return host; | |
251 | } | |
252 | ||
a2581a9e JN |
253 | /* |
254 | * send a video mode command | |
255 | * | |
256 | * XXX: commands with data in MIPI_DPI_DATA? | |
257 | */ | |
258 | static int dpi_send_cmd(struct intel_dsi *intel_dsi, u32 cmd, bool hs, | |
259 | enum port port) | |
260 | { | |
261 | struct drm_encoder *encoder = &intel_dsi->base.base; | |
262 | struct drm_device *dev = encoder->dev; | |
fac5e23e | 263 | struct drm_i915_private *dev_priv = to_i915(dev); |
a2581a9e JN |
264 | u32 mask; |
265 | ||
266 | /* XXX: pipe, hs */ | |
267 | if (hs) | |
268 | cmd &= ~DPI_LP_MODE; | |
269 | else | |
270 | cmd |= DPI_LP_MODE; | |
271 | ||
272 | /* clear bit */ | |
273 | I915_WRITE(MIPI_INTR_STAT(port), SPL_PKT_SENT_INTERRUPT); | |
274 | ||
275 | /* XXX: old code skips write if control unchanged */ | |
276 | if (cmd == I915_READ(MIPI_DPI_CONTROL(port))) | |
277 | DRM_ERROR("Same special packet %02x twice in a row.\n", cmd); | |
278 | ||
279 | I915_WRITE(MIPI_DPI_CONTROL(port), cmd); | |
280 | ||
281 | mask = SPL_PKT_SENT_INTERRUPT; | |
2af05078 CW |
282 | if (intel_wait_for_register(dev_priv, |
283 | MIPI_INTR_STAT(port), mask, mask, | |
284 | 100)) | |
a2581a9e JN |
285 | DRM_ERROR("Video mode command 0x%08x send failed.\n", cmd); |
286 | ||
287 | return 0; | |
288 | } | |
289 | ||
e9fe51c6 | 290 | static void band_gap_reset(struct drm_i915_private *dev_priv) |
4ce8c9a7 | 291 | { |
a580516d | 292 | mutex_lock(&dev_priv->sb_lock); |
4ce8c9a7 | 293 | |
e9fe51c6 SK |
294 | vlv_flisdsi_write(dev_priv, 0x08, 0x0001); |
295 | vlv_flisdsi_write(dev_priv, 0x0F, 0x0005); | |
296 | vlv_flisdsi_write(dev_priv, 0x0F, 0x0025); | |
297 | udelay(150); | |
298 | vlv_flisdsi_write(dev_priv, 0x0F, 0x0000); | |
299 | vlv_flisdsi_write(dev_priv, 0x08, 0x0000); | |
4ce8c9a7 | 300 | |
a580516d | 301 | mutex_unlock(&dev_priv->sb_lock); |
4ce8c9a7 SK |
302 | } |
303 | ||
4e646495 JN |
304 | static inline bool is_vid_mode(struct intel_dsi *intel_dsi) |
305 | { | |
dfba2e2d | 306 | return intel_dsi->operation_mode == INTEL_DSI_VIDEO_MODE; |
4e646495 JN |
307 | } |
308 | ||
309 | static inline bool is_cmd_mode(struct intel_dsi *intel_dsi) | |
310 | { | |
dfba2e2d | 311 | return intel_dsi->operation_mode == INTEL_DSI_COMMAND_MODE; |
4e646495 JN |
312 | } |
313 | ||
4e646495 | 314 | static bool intel_dsi_compute_config(struct intel_encoder *encoder, |
0a478c27 ML |
315 | struct intel_crtc_state *pipe_config, |
316 | struct drm_connector_state *conn_state) | |
4e646495 | 317 | { |
fac5e23e | 318 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
4e646495 JN |
319 | struct intel_dsi *intel_dsi = container_of(encoder, struct intel_dsi, |
320 | base); | |
321 | struct intel_connector *intel_connector = intel_dsi->attached_connector; | |
f4ee265f VS |
322 | struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc); |
323 | const struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode; | |
a65347ba | 324 | struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; |
47eacbab | 325 | int ret; |
4e646495 JN |
326 | |
327 | DRM_DEBUG_KMS("\n"); | |
328 | ||
f4ee265f | 329 | if (fixed_mode) { |
4e646495 JN |
330 | intel_fixed_panel_mode(fixed_mode, adjusted_mode); |
331 | ||
f4ee265f VS |
332 | if (HAS_GMCH_DISPLAY(dev_priv)) |
333 | intel_gmch_panel_fitting(crtc, pipe_config, | |
334 | intel_connector->panel.fitting_mode); | |
335 | else | |
336 | intel_pch_panel_fitting(crtc, pipe_config, | |
337 | intel_connector->panel.fitting_mode); | |
338 | } | |
339 | ||
f573de5a SK |
340 | /* DSI uses short packets for sync events, so clear mode flags for DSI */ |
341 | adjusted_mode->flags = 0; | |
342 | ||
cc3f90f0 | 343 | if (IS_GEN9_LP(dev_priv)) { |
4d1de975 JN |
344 | /* Dual link goes to DSI transcoder A. */ |
345 | if (intel_dsi->ports == BIT(PORT_C)) | |
346 | pipe_config->cpu_transcoder = TRANSCODER_DSI_C; | |
347 | else | |
348 | pipe_config->cpu_transcoder = TRANSCODER_DSI_A; | |
349 | } | |
350 | ||
47eacbab VS |
351 | ret = intel_compute_dsi_pll(encoder, pipe_config); |
352 | if (ret) | |
353 | return false; | |
354 | ||
cd2d34d9 VS |
355 | pipe_config->clock_set = true; |
356 | ||
4e646495 JN |
357 | return true; |
358 | } | |
359 | ||
46448483 D |
360 | static void glk_dsi_device_ready(struct intel_encoder *encoder) |
361 | { | |
362 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); | |
363 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); | |
364 | enum port port; | |
365 | u32 tmp, val; | |
366 | ||
367 | /* Set the MIPI mode | |
368 | * If MIPI_Mode is off, then writing to LP_Wake bit is not reflecting. | |
369 | * Power ON MIPI IO first and then write into IO reset and LP wake bits | |
370 | */ | |
371 | for_each_dsi_port(port, intel_dsi->ports) { | |
372 | tmp = I915_READ(MIPI_CTRL(port)); | |
373 | I915_WRITE(MIPI_CTRL(port), tmp | GLK_MIPIIO_ENABLE); | |
374 | } | |
375 | ||
376 | /* Put the IO into reset */ | |
377 | tmp = I915_READ(MIPI_CTRL(PORT_A)); | |
378 | tmp &= ~GLK_MIPIIO_RESET_RELEASED; | |
379 | I915_WRITE(MIPI_CTRL(PORT_A), tmp); | |
380 | ||
381 | /* Program LP Wake */ | |
382 | for_each_dsi_port(port, intel_dsi->ports) { | |
383 | tmp = I915_READ(MIPI_CTRL(port)); | |
384 | tmp |= GLK_LP_WAKE; | |
385 | I915_WRITE(MIPI_CTRL(port), tmp); | |
386 | } | |
387 | ||
388 | /* Wait for Pwr ACK */ | |
389 | for_each_dsi_port(port, intel_dsi->ports) { | |
390 | if (intel_wait_for_register(dev_priv, | |
391 | MIPI_CTRL(port), GLK_MIPIIO_PORT_POWERED, | |
392 | GLK_MIPIIO_PORT_POWERED, 20)) | |
393 | DRM_ERROR("MIPIO port is powergated\n"); | |
394 | } | |
395 | ||
396 | /* Wait for MIPI PHY status bit to set */ | |
397 | for_each_dsi_port(port, intel_dsi->ports) { | |
398 | if (intel_wait_for_register(dev_priv, | |
399 | MIPI_CTRL(port), GLK_PHY_STATUS_PORT_READY, | |
400 | GLK_PHY_STATUS_PORT_READY, 20)) | |
401 | DRM_ERROR("PHY is not ON\n"); | |
402 | } | |
403 | ||
404 | /* Get IO out of reset */ | |
405 | tmp = I915_READ(MIPI_CTRL(PORT_A)); | |
406 | I915_WRITE(MIPI_CTRL(PORT_A), tmp | GLK_MIPIIO_RESET_RELEASED); | |
407 | ||
408 | /* Get IO out of Low power state*/ | |
409 | for_each_dsi_port(port, intel_dsi->ports) { | |
410 | if (!(I915_READ(MIPI_DEVICE_READY(port)) & DEVICE_READY)) { | |
411 | val = I915_READ(MIPI_DEVICE_READY(port)); | |
412 | val &= ~ULPS_STATE_MASK; | |
413 | val |= DEVICE_READY; | |
414 | I915_WRITE(MIPI_DEVICE_READY(port), val); | |
415 | usleep_range(10, 15); | |
416 | } | |
417 | ||
418 | /* Enter ULPS */ | |
419 | val = I915_READ(MIPI_DEVICE_READY(port)); | |
420 | val &= ~ULPS_STATE_MASK; | |
421 | val |= (ULPS_STATE_ENTER | DEVICE_READY); | |
422 | I915_WRITE(MIPI_DEVICE_READY(port), val); | |
423 | ||
424 | /* Wait for ULPS Not active */ | |
425 | if (intel_wait_for_register(dev_priv, | |
426 | MIPI_CTRL(port), GLK_ULPS_NOT_ACTIVE, | |
427 | GLK_ULPS_NOT_ACTIVE, 20)) | |
428 | ||
429 | /* Exit ULPS */ | |
430 | val = I915_READ(MIPI_DEVICE_READY(port)); | |
431 | val &= ~ULPS_STATE_MASK; | |
432 | val |= (ULPS_STATE_EXIT | DEVICE_READY); | |
433 | I915_WRITE(MIPI_DEVICE_READY(port), val); | |
434 | ||
435 | /* Enter Normal Mode */ | |
436 | val = I915_READ(MIPI_DEVICE_READY(port)); | |
437 | val &= ~ULPS_STATE_MASK; | |
438 | val |= (ULPS_STATE_NORMAL_OPERATION | DEVICE_READY); | |
439 | I915_WRITE(MIPI_DEVICE_READY(port), val); | |
440 | ||
441 | tmp = I915_READ(MIPI_CTRL(port)); | |
442 | tmp &= ~GLK_LP_WAKE; | |
443 | I915_WRITE(MIPI_CTRL(port), tmp); | |
444 | } | |
445 | ||
446 | /* Wait for Stop state */ | |
447 | for_each_dsi_port(port, intel_dsi->ports) { | |
448 | if (intel_wait_for_register(dev_priv, | |
449 | MIPI_CTRL(port), GLK_DATA_LANE_STOP_STATE, | |
450 | GLK_DATA_LANE_STOP_STATE, 20)) | |
451 | DRM_ERROR("Date lane not in STOP state\n"); | |
452 | } | |
453 | ||
454 | /* Wait for AFE LATCH */ | |
455 | for_each_dsi_port(port, intel_dsi->ports) { | |
456 | if (intel_wait_for_register(dev_priv, | |
457 | BXT_MIPI_PORT_CTRL(port), AFE_LATCHOUT, | |
458 | AFE_LATCHOUT, 20)) | |
459 | DRM_ERROR("D-PHY not entering LP-11 state\n"); | |
460 | } | |
461 | } | |
462 | ||
37ab0810 | 463 | static void bxt_dsi_device_ready(struct intel_encoder *encoder) |
5505a244 | 464 | { |
fac5e23e | 465 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
5505a244 | 466 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); |
369602d3 | 467 | enum port port; |
37ab0810 | 468 | u32 val; |
5505a244 | 469 | |
37ab0810 | 470 | DRM_DEBUG_KMS("\n"); |
a9da9bce | 471 | |
eba4daf0 | 472 | /* Enable MIPI PHY transparent latch */ |
369602d3 | 473 | for_each_dsi_port(port, intel_dsi->ports) { |
37ab0810 SS |
474 | val = I915_READ(BXT_MIPI_PORT_CTRL(port)); |
475 | I915_WRITE(BXT_MIPI_PORT_CTRL(port), val | LP_OUTPUT_HOLD); | |
476 | usleep_range(2000, 2500); | |
eba4daf0 | 477 | } |
37ab0810 | 478 | |
eba4daf0 US |
479 | /* Clear ULPS and set device ready */ |
480 | for_each_dsi_port(port, intel_dsi->ports) { | |
37ab0810 SS |
481 | val = I915_READ(MIPI_DEVICE_READY(port)); |
482 | val &= ~ULPS_STATE_MASK; | |
37ab0810 | 483 | I915_WRITE(MIPI_DEVICE_READY(port), val); |
eba4daf0 | 484 | usleep_range(2000, 2500); |
37ab0810 SS |
485 | val |= DEVICE_READY; |
486 | I915_WRITE(MIPI_DEVICE_READY(port), val); | |
369602d3 | 487 | } |
5505a244 GS |
488 | } |
489 | ||
37ab0810 | 490 | static void vlv_dsi_device_ready(struct intel_encoder *encoder) |
4e646495 | 491 | { |
fac5e23e | 492 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
24ee0e64 GS |
493 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); |
494 | enum port port; | |
1dbd7cb2 SK |
495 | u32 val; |
496 | ||
4e646495 | 497 | DRM_DEBUG_KMS("\n"); |
4e646495 | 498 | |
a580516d | 499 | mutex_lock(&dev_priv->sb_lock); |
2095f9fc SK |
500 | /* program rcomp for compliance, reduce from 50 ohms to 45 ohms |
501 | * needed everytime after power gate */ | |
502 | vlv_flisdsi_write(dev_priv, 0x04, 0x0004); | |
a580516d | 503 | mutex_unlock(&dev_priv->sb_lock); |
2095f9fc SK |
504 | |
505 | /* bandgap reset is needed after everytime we do power gate */ | |
506 | band_gap_reset(dev_priv); | |
507 | ||
24ee0e64 | 508 | for_each_dsi_port(port, intel_dsi->ports) { |
aceb365c | 509 | |
24ee0e64 GS |
510 | I915_WRITE(MIPI_DEVICE_READY(port), ULPS_STATE_ENTER); |
511 | usleep_range(2500, 3000); | |
aceb365c | 512 | |
bf344e80 GS |
513 | /* Enable MIPI PHY transparent latch |
514 | * Common bit for both MIPI Port A & MIPI Port C | |
515 | * No similar bit in MIPI Port C reg | |
516 | */ | |
4ba7d93a | 517 | val = I915_READ(MIPI_PORT_CTRL(PORT_A)); |
bf344e80 | 518 | I915_WRITE(MIPI_PORT_CTRL(PORT_A), val | LP_OUTPUT_HOLD); |
24ee0e64 | 519 | usleep_range(1000, 1500); |
aceb365c | 520 | |
24ee0e64 GS |
521 | I915_WRITE(MIPI_DEVICE_READY(port), ULPS_STATE_EXIT); |
522 | usleep_range(2500, 3000); | |
523 | ||
524 | I915_WRITE(MIPI_DEVICE_READY(port), DEVICE_READY); | |
525 | usleep_range(2500, 3000); | |
526 | } | |
1dbd7cb2 | 527 | } |
1dbd7cb2 | 528 | |
37ab0810 SS |
529 | static void intel_dsi_device_ready(struct intel_encoder *encoder) |
530 | { | |
e2d214ae | 531 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
37ab0810 | 532 | |
e2d214ae | 533 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) |
37ab0810 | 534 | vlv_dsi_device_ready(encoder); |
46448483 | 535 | else if (IS_BROXTON(dev_priv)) |
37ab0810 | 536 | bxt_dsi_device_ready(encoder); |
46448483 D |
537 | else if (IS_GEMINILAKE(dev_priv)) |
538 | glk_dsi_device_ready(encoder); | |
37ab0810 SS |
539 | } |
540 | ||
46448483 D |
541 | static void glk_dsi_enter_low_power_mode(struct intel_encoder *encoder) |
542 | { | |
543 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); | |
544 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); | |
545 | enum port port; | |
546 | u32 val; | |
547 | ||
548 | /* Enter ULPS */ | |
549 | for_each_dsi_port(port, intel_dsi->ports) { | |
550 | val = I915_READ(MIPI_DEVICE_READY(port)); | |
551 | val &= ~ULPS_STATE_MASK; | |
552 | val |= (ULPS_STATE_ENTER | DEVICE_READY); | |
553 | I915_WRITE(MIPI_DEVICE_READY(port), val); | |
554 | } | |
555 | ||
556 | /* Wait for MIPI PHY status bit to unset */ | |
557 | for_each_dsi_port(port, intel_dsi->ports) { | |
558 | if (intel_wait_for_register(dev_priv, | |
559 | MIPI_CTRL(port), | |
560 | GLK_PHY_STATUS_PORT_READY, 0, 20)) | |
561 | DRM_ERROR("PHY is not turning OFF\n"); | |
562 | } | |
563 | ||
564 | /* Wait for Pwr ACK bit to unset */ | |
565 | for_each_dsi_port(port, intel_dsi->ports) { | |
566 | if (intel_wait_for_register(dev_priv, | |
567 | MIPI_CTRL(port), | |
568 | GLK_MIPIIO_PORT_POWERED, 0, 20)) | |
569 | DRM_ERROR("MIPI IO Port is not powergated\n"); | |
570 | } | |
571 | } | |
572 | ||
573 | static void glk_dsi_disable_mipi_io(struct intel_encoder *encoder) | |
574 | { | |
575 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); | |
576 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); | |
577 | enum port port; | |
578 | u32 tmp; | |
579 | ||
580 | /* Put the IO into reset */ | |
581 | tmp = I915_READ(MIPI_CTRL(PORT_A)); | |
582 | tmp &= ~GLK_MIPIIO_RESET_RELEASED; | |
583 | I915_WRITE(MIPI_CTRL(PORT_A), tmp); | |
584 | ||
585 | /* Wait for MIPI PHY status bit to unset */ | |
586 | for_each_dsi_port(port, intel_dsi->ports) { | |
587 | if (intel_wait_for_register(dev_priv, | |
588 | MIPI_CTRL(port), | |
589 | GLK_PHY_STATUS_PORT_READY, 0, 20)) | |
590 | DRM_ERROR("PHY is not turning OFF\n"); | |
591 | } | |
592 | ||
593 | /* Clear MIPI mode */ | |
594 | for_each_dsi_port(port, intel_dsi->ports) { | |
595 | tmp = I915_READ(MIPI_CTRL(port)); | |
596 | tmp &= ~GLK_MIPIIO_ENABLE; | |
597 | I915_WRITE(MIPI_CTRL(port), tmp); | |
598 | } | |
599 | } | |
600 | ||
601 | static void glk_dsi_clear_device_ready(struct intel_encoder *encoder) | |
602 | { | |
603 | glk_dsi_enter_low_power_mode(encoder); | |
604 | glk_dsi_disable_mipi_io(encoder); | |
605 | } | |
606 | ||
607 | static void vlv_dsi_clear_device_ready(struct intel_encoder *encoder) | |
14be7a5c HG |
608 | { |
609 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); | |
610 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); | |
611 | enum port port; | |
612 | ||
613 | DRM_DEBUG_KMS("\n"); | |
614 | for_each_dsi_port(port, intel_dsi->ports) { | |
615 | /* Common bit for both MIPI Port A & MIPI Port C on VLV/CHV */ | |
616 | i915_reg_t port_ctrl = IS_GEN9_LP(dev_priv) ? | |
617 | BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(PORT_A); | |
618 | u32 val; | |
619 | ||
620 | I915_WRITE(MIPI_DEVICE_READY(port), DEVICE_READY | | |
621 | ULPS_STATE_ENTER); | |
622 | usleep_range(2000, 2500); | |
623 | ||
624 | I915_WRITE(MIPI_DEVICE_READY(port), DEVICE_READY | | |
625 | ULPS_STATE_EXIT); | |
626 | usleep_range(2000, 2500); | |
627 | ||
628 | I915_WRITE(MIPI_DEVICE_READY(port), DEVICE_READY | | |
629 | ULPS_STATE_ENTER); | |
630 | usleep_range(2000, 2500); | |
631 | ||
1e08a260 HG |
632 | /* |
633 | * On VLV/CHV, wait till Clock lanes are in LP-00 state for MIPI | |
634 | * Port A only. MIPI Port C has no similar bit for checking. | |
14be7a5c | 635 | */ |
1e08a260 HG |
636 | if ((IS_GEN9_LP(dev_priv) || port == PORT_A) && |
637 | intel_wait_for_register(dev_priv, | |
14be7a5c HG |
638 | port_ctrl, AFE_LATCHOUT, 0, |
639 | 30)) | |
640 | DRM_ERROR("DSI LP not going Low\n"); | |
641 | ||
642 | /* Disable MIPI PHY transparent latch */ | |
643 | val = I915_READ(port_ctrl); | |
644 | I915_WRITE(port_ctrl, val & ~LP_OUTPUT_HOLD); | |
645 | usleep_range(1000, 1500); | |
646 | ||
647 | I915_WRITE(MIPI_DEVICE_READY(port), 0x00); | |
648 | usleep_range(2000, 2500); | |
649 | } | |
650 | } | |
651 | ||
37ab0810 SS |
652 | static void intel_dsi_port_enable(struct intel_encoder *encoder) |
653 | { | |
654 | struct drm_device *dev = encoder->base.dev; | |
fac5e23e | 655 | struct drm_i915_private *dev_priv = to_i915(dev); |
37ab0810 SS |
656 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); |
657 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); | |
658 | enum port port; | |
37ab0810 SS |
659 | |
660 | if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) { | |
f0f59a00 | 661 | u32 temp; |
6043801f D |
662 | if (IS_GEN9_LP(dev_priv)) { |
663 | for_each_dsi_port(port, intel_dsi->ports) { | |
664 | temp = I915_READ(MIPI_CTRL(port)); | |
665 | temp &= ~BXT_PIXEL_OVERLAP_CNT_MASK | | |
666 | intel_dsi->pixel_overlap << | |
667 | BXT_PIXEL_OVERLAP_CNT_SHIFT; | |
668 | I915_WRITE(MIPI_CTRL(port), temp); | |
669 | } | |
670 | } else { | |
671 | temp = I915_READ(VLV_CHICKEN_3); | |
672 | temp &= ~PIXEL_OVERLAP_CNT_MASK | | |
37ab0810 SS |
673 | intel_dsi->pixel_overlap << |
674 | PIXEL_OVERLAP_CNT_SHIFT; | |
6043801f D |
675 | I915_WRITE(VLV_CHICKEN_3, temp); |
676 | } | |
37ab0810 SS |
677 | } |
678 | ||
679 | for_each_dsi_port(port, intel_dsi->ports) { | |
cc3f90f0 | 680 | i915_reg_t port_ctrl = IS_GEN9_LP(dev_priv) ? |
f0f59a00 VS |
681 | BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(port); |
682 | u32 temp; | |
37ab0810 SS |
683 | |
684 | temp = I915_READ(port_ctrl); | |
685 | ||
686 | temp &= ~LANE_CONFIGURATION_MASK; | |
687 | temp &= ~DUAL_LINK_MODE_MASK; | |
688 | ||
701d25b4 | 689 | if (intel_dsi->ports == (BIT(PORT_A) | BIT(PORT_C))) { |
37ab0810 SS |
690 | temp |= (intel_dsi->dual_link - 1) |
691 | << DUAL_LINK_MODE_SHIFT; | |
812b1d2f BP |
692 | if (IS_BROXTON(dev_priv)) |
693 | temp |= LANE_CONFIGURATION_DUAL_LINK_A; | |
694 | else | |
695 | temp |= intel_crtc->pipe ? | |
37ab0810 SS |
696 | LANE_CONFIGURATION_DUAL_LINK_B : |
697 | LANE_CONFIGURATION_DUAL_LINK_A; | |
698 | } | |
699 | /* assert ip_tg_enable signal */ | |
700 | I915_WRITE(port_ctrl, temp | DPI_ENABLE); | |
701 | POSTING_READ(port_ctrl); | |
702 | } | |
703 | } | |
704 | ||
705 | static void intel_dsi_port_disable(struct intel_encoder *encoder) | |
706 | { | |
707 | struct drm_device *dev = encoder->base.dev; | |
fac5e23e | 708 | struct drm_i915_private *dev_priv = to_i915(dev); |
37ab0810 SS |
709 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); |
710 | enum port port; | |
37ab0810 SS |
711 | |
712 | for_each_dsi_port(port, intel_dsi->ports) { | |
cc3f90f0 | 713 | i915_reg_t port_ctrl = IS_GEN9_LP(dev_priv) ? |
f0f59a00 VS |
714 | BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(port); |
715 | u32 temp; | |
716 | ||
37ab0810 | 717 | /* de-assert ip_tg_enable signal */ |
b389a45c SS |
718 | temp = I915_READ(port_ctrl); |
719 | I915_WRITE(port_ctrl, temp & ~DPI_ENABLE); | |
720 | POSTING_READ(port_ctrl); | |
37ab0810 SS |
721 | } |
722 | } | |
723 | ||
5eff0edf ML |
724 | static void intel_dsi_prepare(struct intel_encoder *intel_encoder, |
725 | struct intel_crtc_state *pipe_config); | |
c7991eca | 726 | static void intel_dsi_unprepare(struct intel_encoder *encoder); |
e3488e75 | 727 | |
249f6962 HG |
728 | /* |
729 | * Panel enable/disable sequences from the VBT spec. | |
730 | * | |
731 | * Note the spec has AssertReset / DeassertReset swapped from their | |
732 | * usual naming. We use the normal names to avoid confusion (so below | |
733 | * they are swapped compared to the spec). | |
734 | * | |
735 | * Steps starting with MIPI refer to VBT sequences, note that for v2 | |
736 | * VBTs several steps which have a VBT in v2 are expected to be handled | |
737 | * directly by the driver, by directly driving gpios for example. | |
738 | * | |
739 | * v2 video mode seq v3 video mode seq command mode seq | |
740 | * - power on - MIPIPanelPowerOn - power on | |
741 | * - wait t1+t2 - wait t1+t2 | |
742 | * - MIPIDeassertResetPin - MIPIDeassertResetPin - MIPIDeassertResetPin | |
743 | * - io lines to lp-11 - io lines to lp-11 - io lines to lp-11 | |
744 | * - MIPISendInitialDcsCmds - MIPISendInitialDcsCmds - MIPISendInitialDcsCmds | |
745 | * - MIPITearOn | |
746 | * - MIPIDisplayOn | |
747 | * - turn on DPI - turn on DPI - set pipe to dsr mode | |
748 | * - MIPIDisplayOn - MIPIDisplayOn | |
749 | * - wait t5 - wait t5 | |
750 | * - backlight on - MIPIBacklightOn - backlight on | |
751 | * ... ... ... issue mem cmds ... | |
752 | * - backlight off - MIPIBacklightOff - backlight off | |
753 | * - wait t6 - wait t6 | |
754 | * - MIPIDisplayOff | |
755 | * - turn off DPI - turn off DPI - disable pipe dsr mode | |
756 | * - MIPITearOff | |
757 | * - MIPIDisplayOff - MIPIDisplayOff | |
758 | * - io lines to lp-00 - io lines to lp-00 - io lines to lp-00 | |
759 | * - MIPIAssertResetPin - MIPIAssertResetPin - MIPIAssertResetPin | |
760 | * - wait t3 - wait t3 | |
761 | * - power off - MIPIPanelPowerOff - power off | |
762 | * - wait t4 - wait t4 | |
763 | */ | |
764 | ||
fd6bbda9 ML |
765 | static void intel_dsi_pre_enable(struct intel_encoder *encoder, |
766 | struct intel_crtc_state *pipe_config, | |
767 | struct drm_connector_state *conn_state) | |
2634fd7f | 768 | { |
5eff0edf | 769 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
2634fd7f | 770 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); |
5a2e65e7 | 771 | enum port port; |
1881a423 | 772 | u32 val; |
2634fd7f SK |
773 | |
774 | DRM_DEBUG_KMS("\n"); | |
775 | ||
f00b5689 VS |
776 | /* |
777 | * The BIOS may leave the PLL in a wonky state where it doesn't | |
778 | * lock. It needs to be fully powered down to fix it. | |
779 | */ | |
780 | intel_disable_dsi_pll(encoder); | |
5eff0edf | 781 | intel_enable_dsi_pll(encoder, pipe_config); |
f00b5689 | 782 | |
1881a423 US |
783 | if (IS_BROXTON(dev_priv)) { |
784 | /* Add MIPI IO reset programming for modeset */ | |
785 | val = I915_READ(BXT_P_CR_GT_DISP_PWRON); | |
786 | I915_WRITE(BXT_P_CR_GT_DISP_PWRON, | |
787 | val | MIPIO_RST_CTRL); | |
788 | ||
789 | /* Power up DSI regulator */ | |
790 | I915_WRITE(BXT_P_DSI_REGULATOR_CFG, STAP_SELECT); | |
791 | I915_WRITE(BXT_P_DSI_REGULATOR_TX_CTRL, 0); | |
792 | } | |
793 | ||
d1877c0f VS |
794 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { |
795 | u32 val; | |
796 | ||
cd2d34d9 | 797 | /* Disable DPOunit clock gating, can stall pipe */ |
d1877c0f VS |
798 | val = I915_READ(DSPCLK_GATE_D); |
799 | val |= DPOUNIT_CLOCK_GATE_DISABLE; | |
800 | I915_WRITE(DSPCLK_GATE_D, val); | |
37ab0810 | 801 | } |
2634fd7f | 802 | |
deae2006 HG |
803 | intel_dsi_prepare(encoder, pipe_config); |
804 | ||
805 | /* Power on, try both CRC pmic gpio and VBT */ | |
806 | if (intel_dsi->gpio_panel) | |
807 | gpiod_set_value_cansleep(intel_dsi->gpio_panel, 1); | |
808 | intel_dsi_exec_vbt_sequence(intel_dsi, MIPI_SEQ_POWER_ON); | |
809 | msleep(intel_dsi->panel_on_delay); | |
810 | ||
3e40fa8a HG |
811 | /* Deassert reset */ |
812 | intel_dsi_exec_vbt_sequence(intel_dsi, MIPI_SEQ_DEASSERT_RESET); | |
813 | ||
814 | /* Put device in ready state (LP-11) */ | |
2634fd7f | 815 | intel_dsi_device_ready(encoder); |
4e646495 | 816 | |
3e40fa8a | 817 | /* Send initialization commands in LP mode */ |
18a00095 | 818 | intel_dsi_exec_vbt_sequence(intel_dsi, MIPI_SEQ_INIT_OTP); |
20e5bf66 | 819 | |
2634fd7f SK |
820 | /* Enable port in pre-enable phase itself because as per hw team |
821 | * recommendation, port should be enabled befor plane & pipe */ | |
5a2e65e7 HG |
822 | if (is_cmd_mode(intel_dsi)) { |
823 | for_each_dsi_port(port, intel_dsi->ports) | |
824 | I915_WRITE(MIPI_MAX_RETURN_PKT_SIZE(port), 8 * 4); | |
825 | } else { | |
826 | msleep(20); /* XXX */ | |
827 | for_each_dsi_port(port, intel_dsi->ports) | |
828 | dpi_send_cmd(intel_dsi, TURN_ON, false, port); | |
829 | msleep(100); | |
830 | ||
18a00095 | 831 | intel_dsi_exec_vbt_sequence(intel_dsi, MIPI_SEQ_DISPLAY_ON); |
5a2e65e7 HG |
832 | |
833 | intel_dsi_port_enable(encoder); | |
834 | } | |
835 | ||
836 | intel_panel_enable_backlight(intel_dsi->attached_connector); | |
f5bce6df | 837 | intel_dsi_exec_vbt_sequence(intel_dsi, MIPI_SEQ_BACKLIGHT_ON); |
2634fd7f SK |
838 | } |
839 | ||
fd6bbda9 ML |
840 | static void intel_dsi_enable_nop(struct intel_encoder *encoder, |
841 | struct intel_crtc_state *pipe_config, | |
842 | struct drm_connector_state *conn_state) | |
2634fd7f SK |
843 | { |
844 | DRM_DEBUG_KMS("\n"); | |
845 | ||
846 | /* for DSI port enable has to be done before pipe | |
847 | * and plane enable, so port enable is done in | |
848 | * pre_enable phase itself unlike other encoders | |
849 | */ | |
4e646495 JN |
850 | } |
851 | ||
fd6bbda9 ML |
852 | static void intel_dsi_pre_disable(struct intel_encoder *encoder, |
853 | struct intel_crtc_state *old_crtc_state, | |
854 | struct drm_connector_state *old_conn_state) | |
c315faf8 | 855 | { |
bbdf0b2f US |
856 | struct drm_device *dev = encoder->base.dev; |
857 | struct drm_i915_private *dev_priv = dev->dev_private; | |
c315faf8 | 858 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); |
f03e4179 | 859 | enum port port; |
c315faf8 ID |
860 | |
861 | DRM_DEBUG_KMS("\n"); | |
862 | ||
f5bce6df | 863 | intel_dsi_exec_vbt_sequence(intel_dsi, MIPI_SEQ_BACKLIGHT_OFF); |
b029e66f SK |
864 | intel_panel_disable_backlight(intel_dsi->attached_connector); |
865 | ||
bbdf0b2f US |
866 | /* |
867 | * Disable Device ready before the port shutdown in order | |
868 | * to avoid split screen | |
869 | */ | |
870 | if (IS_BROXTON(dev_priv)) { | |
871 | for_each_dsi_port(port, intel_dsi->ports) | |
872 | I915_WRITE(MIPI_DEVICE_READY(port), 0); | |
873 | } | |
874 | ||
39831451 HG |
875 | /* |
876 | * According to the spec we should send SHUTDOWN before | |
877 | * MIPI_SEQ_DISPLAY_OFF only for v3+ VBTs, but field testing | |
878 | * has shown that the v3 sequence works for v2 VBTs too | |
879 | */ | |
c315faf8 ID |
880 | if (is_vid_mode(intel_dsi)) { |
881 | /* Send Shutdown command to the panel in LP mode */ | |
f03e4179 | 882 | for_each_dsi_port(port, intel_dsi->ports) |
a2581a9e | 883 | dpi_send_cmd(intel_dsi, SHUTDOWN, false, port); |
c315faf8 ID |
884 | msleep(10); |
885 | } | |
886 | } | |
887 | ||
46448483 D |
888 | static void intel_dsi_clear_device_ready(struct intel_encoder *encoder) |
889 | { | |
890 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); | |
891 | ||
892 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv) || | |
893 | IS_BROXTON(dev_priv)) | |
894 | vlv_dsi_clear_device_ready(encoder); | |
895 | else if (IS_GEMINILAKE(dev_priv)) | |
896 | glk_dsi_clear_device_ready(encoder); | |
897 | } | |
898 | ||
fd6bbda9 ML |
899 | static void intel_dsi_post_disable(struct intel_encoder *encoder, |
900 | struct intel_crtc_state *pipe_config, | |
901 | struct drm_connector_state *conn_state) | |
1dbd7cb2 | 902 | { |
fac5e23e | 903 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
1dbd7cb2 | 904 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); |
5a2e65e7 | 905 | enum port port; |
1881a423 | 906 | u32 val; |
1dbd7cb2 SK |
907 | |
908 | DRM_DEBUG_KMS("\n"); | |
909 | ||
5a2e65e7 HG |
910 | if (is_vid_mode(intel_dsi)) { |
911 | for_each_dsi_port(port, intel_dsi->ports) | |
912 | wait_for_dsi_fifo_empty(intel_dsi, port); | |
913 | ||
914 | intel_dsi_port_disable(encoder); | |
915 | usleep_range(2000, 5000); | |
916 | } | |
917 | ||
c7991eca | 918 | intel_dsi_unprepare(encoder); |
5a2e65e7 HG |
919 | |
920 | /* | |
921 | * if disable packets are sent before sending shutdown packet then in | |
922 | * some next enable sequence send turn on packet error is observed | |
923 | */ | |
18a00095 | 924 | intel_dsi_exec_vbt_sequence(intel_dsi, MIPI_SEQ_DISPLAY_OFF); |
c315faf8 | 925 | |
3e40fa8a | 926 | /* Transition to LP-00 */ |
1dbd7cb2 SK |
927 | intel_dsi_clear_device_ready(encoder); |
928 | ||
1881a423 US |
929 | if (IS_BROXTON(dev_priv)) { |
930 | /* Power down DSI regulator to save power */ | |
931 | I915_WRITE(BXT_P_DSI_REGULATOR_CFG, STAP_SELECT); | |
932 | I915_WRITE(BXT_P_DSI_REGULATOR_TX_CTRL, HS_IO_CTRL_SELECT); | |
933 | ||
934 | /* Add MIPI IO reset programming for modeset */ | |
935 | val = I915_READ(BXT_P_CR_GT_DISP_PWRON); | |
936 | I915_WRITE(BXT_P_CR_GT_DISP_PWRON, | |
937 | val & ~MIPIO_RST_CTRL); | |
938 | } | |
939 | ||
e840fd31 HG |
940 | intel_disable_dsi_pll(encoder); |
941 | ||
d1877c0f | 942 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { |
d6e3af54 US |
943 | u32 val; |
944 | ||
945 | val = I915_READ(DSPCLK_GATE_D); | |
946 | val &= ~DPOUNIT_CLOCK_GATE_DISABLE; | |
947 | I915_WRITE(DSPCLK_GATE_D, val); | |
948 | } | |
20e5bf66 | 949 | |
3e40fa8a | 950 | /* Assert reset */ |
18a00095 | 951 | intel_dsi_exec_vbt_sequence(intel_dsi, MIPI_SEQ_ASSERT_RESET); |
df38e655 | 952 | |
c7dc5275 | 953 | /* Power off, try both CRC pmic gpio and VBT */ |
df38e655 | 954 | msleep(intel_dsi->panel_off_delay); |
c7dc5275 | 955 | intel_dsi_exec_vbt_sequence(intel_dsi, MIPI_SEQ_POWER_OFF); |
fc45e821 SK |
956 | if (intel_dsi->gpio_panel) |
957 | gpiod_set_value_cansleep(intel_dsi->gpio_panel, 0); | |
1d5c65ed VS |
958 | |
959 | /* | |
960 | * FIXME As we do with eDP, just make a note of the time here | |
961 | * and perform the wait before the next panel power on. | |
962 | */ | |
963 | msleep(intel_dsi->panel_pwr_cycle_delay); | |
1dbd7cb2 | 964 | } |
4e646495 JN |
965 | |
966 | static bool intel_dsi_get_hw_state(struct intel_encoder *encoder, | |
967 | enum pipe *pipe) | |
968 | { | |
fac5e23e | 969 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
c0beefd2 | 970 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); |
e7d7cad0 | 971 | enum port port; |
1dcec2f3 | 972 | bool active = false; |
4e646495 JN |
973 | |
974 | DRM_DEBUG_KMS("\n"); | |
975 | ||
79f255a0 ACO |
976 | if (!intel_display_power_get_if_enabled(dev_priv, |
977 | encoder->power_domain)) | |
6d129bea ID |
978 | return false; |
979 | ||
db18b6a6 ID |
980 | /* |
981 | * On Broxton the PLL needs to be enabled with a valid divider | |
982 | * configuration, otherwise accessing DSI registers will hang the | |
983 | * machine. See BSpec North Display Engine registers/MIPI[BXT]. | |
984 | */ | |
cc3f90f0 | 985 | if (IS_GEN9_LP(dev_priv) && !intel_dsi_pll_is_enabled(dev_priv)) |
db18b6a6 ID |
986 | goto out_put_power; |
987 | ||
4e646495 | 988 | /* XXX: this only works for one DSI output */ |
c0beefd2 | 989 | for_each_dsi_port(port, intel_dsi->ports) { |
cc3f90f0 | 990 | i915_reg_t ctrl_reg = IS_GEN9_LP(dev_priv) ? |
f0f59a00 | 991 | BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(port); |
1dcec2f3 | 992 | bool enabled = I915_READ(ctrl_reg) & DPI_ENABLE; |
c0beefd2 | 993 | |
e6f57789 JN |
994 | /* |
995 | * Due to some hardware limitations on VLV/CHV, the DPI enable | |
996 | * bit in port C control register does not get set. As a | |
997 | * workaround, check pipe B conf instead. | |
c0beefd2 | 998 | */ |
920a14b2 TU |
999 | if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && |
1000 | port == PORT_C) | |
1dcec2f3 | 1001 | enabled = I915_READ(PIPECONF(PIPE_B)) & PIPECONF_ENABLE; |
4e646495 | 1002 | |
1dcec2f3 JN |
1003 | /* Try command mode if video mode not enabled */ |
1004 | if (!enabled) { | |
1005 | u32 tmp = I915_READ(MIPI_DSI_FUNC_PRG(port)); | |
1006 | enabled = tmp & CMD_MODE_DATA_WIDTH_MASK; | |
4e646495 | 1007 | } |
1dcec2f3 JN |
1008 | |
1009 | if (!enabled) | |
1010 | continue; | |
1011 | ||
1012 | if (!(I915_READ(MIPI_DEVICE_READY(port)) & DEVICE_READY)) | |
1013 | continue; | |
1014 | ||
cc3f90f0 | 1015 | if (IS_GEN9_LP(dev_priv)) { |
6b93e9c8 JN |
1016 | u32 tmp = I915_READ(MIPI_CTRL(port)); |
1017 | tmp &= BXT_PIPE_SELECT_MASK; | |
1018 | tmp >>= BXT_PIPE_SELECT_SHIFT; | |
1019 | ||
1020 | if (WARN_ON(tmp > PIPE_C)) | |
1021 | continue; | |
1022 | ||
1023 | *pipe = tmp; | |
1024 | } else { | |
1025 | *pipe = port == PORT_A ? PIPE_A : PIPE_B; | |
1026 | } | |
1027 | ||
1dcec2f3 JN |
1028 | active = true; |
1029 | break; | |
4e646495 | 1030 | } |
1dcec2f3 | 1031 | |
db18b6a6 | 1032 | out_put_power: |
79f255a0 | 1033 | intel_display_power_put(dev_priv, encoder->power_domain); |
4e646495 | 1034 | |
1dcec2f3 | 1035 | return active; |
4e646495 JN |
1036 | } |
1037 | ||
6f0e7535 R |
1038 | static void bxt_dsi_get_pipe_config(struct intel_encoder *encoder, |
1039 | struct intel_crtc_state *pipe_config) | |
1040 | { | |
1041 | struct drm_device *dev = encoder->base.dev; | |
fac5e23e | 1042 | struct drm_i915_private *dev_priv = to_i915(dev); |
6f0e7535 R |
1043 | struct drm_display_mode *adjusted_mode = |
1044 | &pipe_config->base.adjusted_mode; | |
042ab0c3 R |
1045 | struct drm_display_mode *adjusted_mode_sw; |
1046 | struct intel_crtc *intel_crtc; | |
6f0e7535 | 1047 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); |
cefc4e18 | 1048 | unsigned int lane_count = intel_dsi->lane_count; |
6f0e7535 R |
1049 | unsigned int bpp, fmt; |
1050 | enum port port; | |
cefc4e18 | 1051 | u16 hactive, hfp, hsync, hbp, vfp, vsync, vbp; |
042ab0c3 R |
1052 | u16 hfp_sw, hsync_sw, hbp_sw; |
1053 | u16 crtc_htotal_sw, crtc_hsync_start_sw, crtc_hsync_end_sw, | |
1054 | crtc_hblank_start_sw, crtc_hblank_end_sw; | |
1055 | ||
5eff0edf | 1056 | /* FIXME: hw readout should not depend on SW state */ |
042ab0c3 R |
1057 | intel_crtc = to_intel_crtc(encoder->base.crtc); |
1058 | adjusted_mode_sw = &intel_crtc->config->base.adjusted_mode; | |
6f0e7535 R |
1059 | |
1060 | /* | |
1061 | * Atleast one port is active as encoder->get_config called only if | |
1062 | * encoder->get_hw_state() returns true. | |
1063 | */ | |
1064 | for_each_dsi_port(port, intel_dsi->ports) { | |
1065 | if (I915_READ(BXT_MIPI_PORT_CTRL(port)) & DPI_ENABLE) | |
1066 | break; | |
1067 | } | |
1068 | ||
1069 | fmt = I915_READ(MIPI_DSI_FUNC_PRG(port)) & VID_MODE_FORMAT_MASK; | |
1070 | pipe_config->pipe_bpp = | |
1071 | mipi_dsi_pixel_format_to_bpp( | |
1072 | pixel_format_from_register_bits(fmt)); | |
1073 | bpp = pipe_config->pipe_bpp; | |
1074 | ||
1075 | /* In terms of pixels */ | |
1076 | adjusted_mode->crtc_hdisplay = | |
1077 | I915_READ(BXT_MIPI_TRANS_HACTIVE(port)); | |
1078 | adjusted_mode->crtc_vdisplay = | |
1079 | I915_READ(BXT_MIPI_TRANS_VACTIVE(port)); | |
1080 | adjusted_mode->crtc_vtotal = | |
1081 | I915_READ(BXT_MIPI_TRANS_VTOTAL(port)); | |
1082 | ||
cefc4e18 R |
1083 | hactive = adjusted_mode->crtc_hdisplay; |
1084 | hfp = I915_READ(MIPI_HFP_COUNT(port)); | |
1085 | ||
6f0e7535 | 1086 | /* |
cefc4e18 R |
1087 | * Meaningful for video mode non-burst sync pulse mode only, |
1088 | * can be zero for non-burst sync events and burst modes | |
6f0e7535 | 1089 | */ |
cefc4e18 R |
1090 | hsync = I915_READ(MIPI_HSYNC_PADDING_COUNT(port)); |
1091 | hbp = I915_READ(MIPI_HBP_COUNT(port)); | |
1092 | ||
1093 | /* harizontal values are in terms of high speed byte clock */ | |
1094 | hfp = pixels_from_txbyteclkhs(hfp, bpp, lane_count, | |
1095 | intel_dsi->burst_mode_ratio); | |
1096 | hsync = pixels_from_txbyteclkhs(hsync, bpp, lane_count, | |
1097 | intel_dsi->burst_mode_ratio); | |
1098 | hbp = pixels_from_txbyteclkhs(hbp, bpp, lane_count, | |
1099 | intel_dsi->burst_mode_ratio); | |
1100 | ||
1101 | if (intel_dsi->dual_link) { | |
1102 | hfp *= 2; | |
1103 | hsync *= 2; | |
1104 | hbp *= 2; | |
1105 | } | |
6f0e7535 R |
1106 | |
1107 | /* vertical values are in terms of lines */ | |
1108 | vfp = I915_READ(MIPI_VFP_COUNT(port)); | |
1109 | vsync = I915_READ(MIPI_VSYNC_PADDING_COUNT(port)); | |
1110 | vbp = I915_READ(MIPI_VBP_COUNT(port)); | |
1111 | ||
cefc4e18 R |
1112 | adjusted_mode->crtc_htotal = hactive + hfp + hsync + hbp; |
1113 | adjusted_mode->crtc_hsync_start = hfp + adjusted_mode->crtc_hdisplay; | |
1114 | adjusted_mode->crtc_hsync_end = hsync + adjusted_mode->crtc_hsync_start; | |
6f0e7535 | 1115 | adjusted_mode->crtc_hblank_start = adjusted_mode->crtc_hdisplay; |
cefc4e18 | 1116 | adjusted_mode->crtc_hblank_end = adjusted_mode->crtc_htotal; |
6f0e7535 | 1117 | |
cefc4e18 R |
1118 | adjusted_mode->crtc_vsync_start = vfp + adjusted_mode->crtc_vdisplay; |
1119 | adjusted_mode->crtc_vsync_end = vsync + adjusted_mode->crtc_vsync_start; | |
6f0e7535 R |
1120 | adjusted_mode->crtc_vblank_start = adjusted_mode->crtc_vdisplay; |
1121 | adjusted_mode->crtc_vblank_end = adjusted_mode->crtc_vtotal; | |
6f0e7535 | 1122 | |
042ab0c3 R |
1123 | /* |
1124 | * In BXT DSI there is no regs programmed with few horizontal timings | |
1125 | * in Pixels but txbyteclkhs.. So retrieval process adds some | |
1126 | * ROUND_UP ERRORS in the process of PIXELS<==>txbyteclkhs. | |
1127 | * Actually here for the given adjusted_mode, we are calculating the | |
1128 | * value programmed to the port and then back to the horizontal timing | |
1129 | * param in pixels. This is the expected value, including roundup errors | |
1130 | * And if that is same as retrieved value from port, then | |
1131 | * (HW state) adjusted_mode's horizontal timings are corrected to | |
1132 | * match with SW state to nullify the errors. | |
1133 | */ | |
1134 | /* Calculating the value programmed to the Port register */ | |
1135 | hfp_sw = adjusted_mode_sw->crtc_hsync_start - | |
1136 | adjusted_mode_sw->crtc_hdisplay; | |
1137 | hsync_sw = adjusted_mode_sw->crtc_hsync_end - | |
1138 | adjusted_mode_sw->crtc_hsync_start; | |
1139 | hbp_sw = adjusted_mode_sw->crtc_htotal - | |
1140 | adjusted_mode_sw->crtc_hsync_end; | |
1141 | ||
1142 | if (intel_dsi->dual_link) { | |
1143 | hfp_sw /= 2; | |
1144 | hsync_sw /= 2; | |
1145 | hbp_sw /= 2; | |
1146 | } | |
1147 | ||
1148 | hfp_sw = txbyteclkhs(hfp_sw, bpp, lane_count, | |
1149 | intel_dsi->burst_mode_ratio); | |
1150 | hsync_sw = txbyteclkhs(hsync_sw, bpp, lane_count, | |
1151 | intel_dsi->burst_mode_ratio); | |
1152 | hbp_sw = txbyteclkhs(hbp_sw, bpp, lane_count, | |
1153 | intel_dsi->burst_mode_ratio); | |
1154 | ||
1155 | /* Reverse calculating the adjusted mode parameters from port reg vals*/ | |
1156 | hfp_sw = pixels_from_txbyteclkhs(hfp_sw, bpp, lane_count, | |
1157 | intel_dsi->burst_mode_ratio); | |
1158 | hsync_sw = pixels_from_txbyteclkhs(hsync_sw, bpp, lane_count, | |
1159 | intel_dsi->burst_mode_ratio); | |
1160 | hbp_sw = pixels_from_txbyteclkhs(hbp_sw, bpp, lane_count, | |
1161 | intel_dsi->burst_mode_ratio); | |
1162 | ||
1163 | if (intel_dsi->dual_link) { | |
1164 | hfp_sw *= 2; | |
1165 | hsync_sw *= 2; | |
1166 | hbp_sw *= 2; | |
1167 | } | |
1168 | ||
1169 | crtc_htotal_sw = adjusted_mode_sw->crtc_hdisplay + hfp_sw + | |
1170 | hsync_sw + hbp_sw; | |
1171 | crtc_hsync_start_sw = hfp_sw + adjusted_mode_sw->crtc_hdisplay; | |
1172 | crtc_hsync_end_sw = hsync_sw + crtc_hsync_start_sw; | |
1173 | crtc_hblank_start_sw = adjusted_mode_sw->crtc_hdisplay; | |
1174 | crtc_hblank_end_sw = crtc_htotal_sw; | |
1175 | ||
1176 | if (adjusted_mode->crtc_htotal == crtc_htotal_sw) | |
1177 | adjusted_mode->crtc_htotal = adjusted_mode_sw->crtc_htotal; | |
1178 | ||
1179 | if (adjusted_mode->crtc_hsync_start == crtc_hsync_start_sw) | |
1180 | adjusted_mode->crtc_hsync_start = | |
1181 | adjusted_mode_sw->crtc_hsync_start; | |
1182 | ||
1183 | if (adjusted_mode->crtc_hsync_end == crtc_hsync_end_sw) | |
1184 | adjusted_mode->crtc_hsync_end = | |
1185 | adjusted_mode_sw->crtc_hsync_end; | |
1186 | ||
1187 | if (adjusted_mode->crtc_hblank_start == crtc_hblank_start_sw) | |
1188 | adjusted_mode->crtc_hblank_start = | |
1189 | adjusted_mode_sw->crtc_hblank_start; | |
1190 | ||
1191 | if (adjusted_mode->crtc_hblank_end == crtc_hblank_end_sw) | |
1192 | adjusted_mode->crtc_hblank_end = | |
1193 | adjusted_mode_sw->crtc_hblank_end; | |
1194 | } | |
6f0e7535 | 1195 | |
4e646495 | 1196 | static void intel_dsi_get_config(struct intel_encoder *encoder, |
5cec258b | 1197 | struct intel_crtc_state *pipe_config) |
4e646495 | 1198 | { |
e2d214ae | 1199 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
d7d85d85 | 1200 | u32 pclk; |
4e646495 JN |
1201 | DRM_DEBUG_KMS("\n"); |
1202 | ||
cc3f90f0 | 1203 | if (IS_GEN9_LP(dev_priv)) |
6f0e7535 R |
1204 | bxt_dsi_get_pipe_config(encoder, pipe_config); |
1205 | ||
47eacbab VS |
1206 | pclk = intel_dsi_get_pclk(encoder, pipe_config->pipe_bpp, |
1207 | pipe_config); | |
f573de5a SK |
1208 | if (!pclk) |
1209 | return; | |
1210 | ||
2d112de7 | 1211 | pipe_config->base.adjusted_mode.crtc_clock = pclk; |
f573de5a | 1212 | pipe_config->port_clock = pclk; |
4e646495 JN |
1213 | } |
1214 | ||
c19de8eb DL |
1215 | static enum drm_mode_status |
1216 | intel_dsi_mode_valid(struct drm_connector *connector, | |
1217 | struct drm_display_mode *mode) | |
4e646495 JN |
1218 | { |
1219 | struct intel_connector *intel_connector = to_intel_connector(connector); | |
f4ee265f | 1220 | const struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode; |
759a1e98 | 1221 | int max_dotclk = to_i915(connector->dev)->max_dotclk_freq; |
4e646495 JN |
1222 | |
1223 | DRM_DEBUG_KMS("\n"); | |
1224 | ||
1225 | if (mode->flags & DRM_MODE_FLAG_DBLSCAN) { | |
1226 | DRM_DEBUG_KMS("MODE_NO_DBLESCAN\n"); | |
1227 | return MODE_NO_DBLESCAN; | |
1228 | } | |
1229 | ||
1230 | if (fixed_mode) { | |
1231 | if (mode->hdisplay > fixed_mode->hdisplay) | |
1232 | return MODE_PANEL; | |
1233 | if (mode->vdisplay > fixed_mode->vdisplay) | |
1234 | return MODE_PANEL; | |
759a1e98 MK |
1235 | if (fixed_mode->clock > max_dotclk) |
1236 | return MODE_CLOCK_HIGH; | |
4e646495 JN |
1237 | } |
1238 | ||
36d21f4c | 1239 | return MODE_OK; |
4e646495 JN |
1240 | } |
1241 | ||
1242 | /* return txclkesc cycles in terms of divider and duration in us */ | |
1243 | static u16 txclkesc(u32 divider, unsigned int us) | |
1244 | { | |
1245 | switch (divider) { | |
1246 | case ESCAPE_CLOCK_DIVIDER_1: | |
1247 | default: | |
1248 | return 20 * us; | |
1249 | case ESCAPE_CLOCK_DIVIDER_2: | |
1250 | return 10 * us; | |
1251 | case ESCAPE_CLOCK_DIVIDER_4: | |
1252 | return 5 * us; | |
1253 | } | |
1254 | } | |
1255 | ||
4e646495 | 1256 | static void set_dsi_timings(struct drm_encoder *encoder, |
5e7234c9 | 1257 | const struct drm_display_mode *adjusted_mode) |
4e646495 JN |
1258 | { |
1259 | struct drm_device *dev = encoder->dev; | |
fac5e23e | 1260 | struct drm_i915_private *dev_priv = to_i915(dev); |
4e646495 | 1261 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); |
aa102d28 | 1262 | enum port port; |
1e78aa01 | 1263 | unsigned int bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format); |
4e646495 JN |
1264 | unsigned int lane_count = intel_dsi->lane_count; |
1265 | ||
1266 | u16 hactive, hfp, hsync, hbp, vfp, vsync, vbp; | |
1267 | ||
aad941d5 VS |
1268 | hactive = adjusted_mode->crtc_hdisplay; |
1269 | hfp = adjusted_mode->crtc_hsync_start - adjusted_mode->crtc_hdisplay; | |
1270 | hsync = adjusted_mode->crtc_hsync_end - adjusted_mode->crtc_hsync_start; | |
1271 | hbp = adjusted_mode->crtc_htotal - adjusted_mode->crtc_hsync_end; | |
4e646495 | 1272 | |
aa102d28 GS |
1273 | if (intel_dsi->dual_link) { |
1274 | hactive /= 2; | |
1275 | if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) | |
1276 | hactive += intel_dsi->pixel_overlap; | |
1277 | hfp /= 2; | |
1278 | hsync /= 2; | |
1279 | hbp /= 2; | |
1280 | } | |
1281 | ||
aad941d5 VS |
1282 | vfp = adjusted_mode->crtc_vsync_start - adjusted_mode->crtc_vdisplay; |
1283 | vsync = adjusted_mode->crtc_vsync_end - adjusted_mode->crtc_vsync_start; | |
1284 | vbp = adjusted_mode->crtc_vtotal - adjusted_mode->crtc_vsync_end; | |
4e646495 JN |
1285 | |
1286 | /* horizontal values are in terms of high speed byte clock */ | |
7f0c8605 | 1287 | hactive = txbyteclkhs(hactive, bpp, lane_count, |
7f3de833 | 1288 | intel_dsi->burst_mode_ratio); |
7f0c8605 SK |
1289 | hfp = txbyteclkhs(hfp, bpp, lane_count, intel_dsi->burst_mode_ratio); |
1290 | hsync = txbyteclkhs(hsync, bpp, lane_count, | |
7f3de833 | 1291 | intel_dsi->burst_mode_ratio); |
7f0c8605 | 1292 | hbp = txbyteclkhs(hbp, bpp, lane_count, intel_dsi->burst_mode_ratio); |
4e646495 | 1293 | |
aa102d28 | 1294 | for_each_dsi_port(port, intel_dsi->ports) { |
cc3f90f0 | 1295 | if (IS_GEN9_LP(dev_priv)) { |
d2e08c0f SS |
1296 | /* |
1297 | * Program hdisplay and vdisplay on MIPI transcoder. | |
1298 | * This is different from calculated hactive and | |
1299 | * vactive, as they are calculated per channel basis, | |
1300 | * whereas these values should be based on resolution. | |
1301 | */ | |
1302 | I915_WRITE(BXT_MIPI_TRANS_HACTIVE(port), | |
aad941d5 | 1303 | adjusted_mode->crtc_hdisplay); |
d2e08c0f | 1304 | I915_WRITE(BXT_MIPI_TRANS_VACTIVE(port), |
aad941d5 | 1305 | adjusted_mode->crtc_vdisplay); |
d2e08c0f | 1306 | I915_WRITE(BXT_MIPI_TRANS_VTOTAL(port), |
aad941d5 | 1307 | adjusted_mode->crtc_vtotal); |
d2e08c0f SS |
1308 | } |
1309 | ||
aa102d28 GS |
1310 | I915_WRITE(MIPI_HACTIVE_AREA_COUNT(port), hactive); |
1311 | I915_WRITE(MIPI_HFP_COUNT(port), hfp); | |
1312 | ||
1313 | /* meaningful for video mode non-burst sync pulse mode only, | |
1314 | * can be zero for non-burst sync events and burst modes */ | |
1315 | I915_WRITE(MIPI_HSYNC_PADDING_COUNT(port), hsync); | |
1316 | I915_WRITE(MIPI_HBP_COUNT(port), hbp); | |
1317 | ||
1318 | /* vertical values are in terms of lines */ | |
1319 | I915_WRITE(MIPI_VFP_COUNT(port), vfp); | |
1320 | I915_WRITE(MIPI_VSYNC_PADDING_COUNT(port), vsync); | |
1321 | I915_WRITE(MIPI_VBP_COUNT(port), vbp); | |
1322 | } | |
4e646495 JN |
1323 | } |
1324 | ||
1e78aa01 JN |
1325 | static u32 pixel_format_to_reg(enum mipi_dsi_pixel_format fmt) |
1326 | { | |
1327 | switch (fmt) { | |
1328 | case MIPI_DSI_FMT_RGB888: | |
1329 | return VID_MODE_FORMAT_RGB888; | |
1330 | case MIPI_DSI_FMT_RGB666: | |
1331 | return VID_MODE_FORMAT_RGB666; | |
1332 | case MIPI_DSI_FMT_RGB666_PACKED: | |
1333 | return VID_MODE_FORMAT_RGB666_PACKED; | |
1334 | case MIPI_DSI_FMT_RGB565: | |
1335 | return VID_MODE_FORMAT_RGB565; | |
1336 | default: | |
1337 | MISSING_CASE(fmt); | |
1338 | return VID_MODE_FORMAT_RGB666; | |
1339 | } | |
1340 | } | |
1341 | ||
5eff0edf ML |
1342 | static void intel_dsi_prepare(struct intel_encoder *intel_encoder, |
1343 | struct intel_crtc_state *pipe_config) | |
4e646495 JN |
1344 | { |
1345 | struct drm_encoder *encoder = &intel_encoder->base; | |
1346 | struct drm_device *dev = encoder->dev; | |
fac5e23e | 1347 | struct drm_i915_private *dev_priv = to_i915(dev); |
5eff0edf | 1348 | struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc); |
4e646495 | 1349 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); |
5eff0edf | 1350 | const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; |
24ee0e64 | 1351 | enum port port; |
1e78aa01 | 1352 | unsigned int bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format); |
4e646495 | 1353 | u32 val, tmp; |
24ee0e64 | 1354 | u16 mode_hdisplay; |
4e646495 | 1355 | |
e7d7cad0 | 1356 | DRM_DEBUG_KMS("pipe %c\n", pipe_name(intel_crtc->pipe)); |
4e646495 | 1357 | |
aad941d5 | 1358 | mode_hdisplay = adjusted_mode->crtc_hdisplay; |
4e646495 | 1359 | |
24ee0e64 GS |
1360 | if (intel_dsi->dual_link) { |
1361 | mode_hdisplay /= 2; | |
1362 | if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) | |
1363 | mode_hdisplay += intel_dsi->pixel_overlap; | |
1364 | } | |
4e646495 | 1365 | |
24ee0e64 | 1366 | for_each_dsi_port(port, intel_dsi->ports) { |
920a14b2 | 1367 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { |
d2e08c0f SS |
1368 | /* |
1369 | * escape clock divider, 20MHz, shared for A and C. | |
1370 | * device ready must be off when doing this! txclkesc? | |
1371 | */ | |
1372 | tmp = I915_READ(MIPI_CTRL(PORT_A)); | |
1373 | tmp &= ~ESCAPE_CLOCK_DIVIDER_MASK; | |
1374 | I915_WRITE(MIPI_CTRL(PORT_A), tmp | | |
1375 | ESCAPE_CLOCK_DIVIDER_1); | |
1376 | ||
1377 | /* read request priority is per pipe */ | |
1378 | tmp = I915_READ(MIPI_CTRL(port)); | |
1379 | tmp &= ~READ_REQUEST_PRIORITY_MASK; | |
1380 | I915_WRITE(MIPI_CTRL(port), tmp | | |
1381 | READ_REQUEST_PRIORITY_HIGH); | |
cc3f90f0 | 1382 | } else if (IS_GEN9_LP(dev_priv)) { |
56c48978 D |
1383 | enum pipe pipe = intel_crtc->pipe; |
1384 | ||
d2e08c0f SS |
1385 | tmp = I915_READ(MIPI_CTRL(port)); |
1386 | tmp &= ~BXT_PIPE_SELECT_MASK; | |
1387 | ||
56c48978 | 1388 | tmp |= BXT_PIPE_SELECT(pipe); |
d2e08c0f SS |
1389 | I915_WRITE(MIPI_CTRL(port), tmp); |
1390 | } | |
24ee0e64 GS |
1391 | |
1392 | /* XXX: why here, why like this? handling in irq handler?! */ | |
1393 | I915_WRITE(MIPI_INTR_STAT(port), 0xffffffff); | |
1394 | I915_WRITE(MIPI_INTR_EN(port), 0xffffffff); | |
1395 | ||
1396 | I915_WRITE(MIPI_DPHY_PARAM(port), intel_dsi->dphy_reg); | |
1397 | ||
1398 | I915_WRITE(MIPI_DPI_RESOLUTION(port), | |
aad941d5 | 1399 | adjusted_mode->crtc_vdisplay << VERTICAL_ADDRESS_SHIFT | |
24ee0e64 GS |
1400 | mode_hdisplay << HORIZONTAL_ADDRESS_SHIFT); |
1401 | } | |
4e646495 JN |
1402 | |
1403 | set_dsi_timings(encoder, adjusted_mode); | |
1404 | ||
1405 | val = intel_dsi->lane_count << DATA_LANES_PRG_REG_SHIFT; | |
1406 | if (is_cmd_mode(intel_dsi)) { | |
1407 | val |= intel_dsi->channel << CMD_MODE_CHANNEL_NUMBER_SHIFT; | |
1408 | val |= CMD_MODE_DATA_WIDTH_8_BIT; /* XXX */ | |
1409 | } else { | |
1410 | val |= intel_dsi->channel << VID_MODE_CHANNEL_NUMBER_SHIFT; | |
1e78aa01 | 1411 | val |= pixel_format_to_reg(intel_dsi->pixel_format); |
4e646495 | 1412 | } |
4e646495 | 1413 | |
24ee0e64 GS |
1414 | tmp = 0; |
1415 | if (intel_dsi->eotp_pkt == 0) | |
1416 | tmp |= EOT_DISABLE; | |
1417 | if (intel_dsi->clock_stop) | |
1418 | tmp |= CLOCKSTOP; | |
4e646495 | 1419 | |
cc3f90f0 | 1420 | if (IS_GEN9_LP(dev_priv)) { |
f90e8c36 JN |
1421 | tmp |= BXT_DPHY_DEFEATURE_EN; |
1422 | if (!is_cmd_mode(intel_dsi)) | |
1423 | tmp |= BXT_DEFEATURE_DPI_FIFO_CTR; | |
1424 | } | |
1425 | ||
24ee0e64 GS |
1426 | for_each_dsi_port(port, intel_dsi->ports) { |
1427 | I915_WRITE(MIPI_DSI_FUNC_PRG(port), val); | |
1428 | ||
1429 | /* timeouts for recovery. one frame IIUC. if counter expires, | |
1430 | * EOT and stop state. */ | |
1431 | ||
1432 | /* | |
1433 | * In burst mode, value greater than one DPI line Time in byte | |
1434 | * clock (txbyteclkhs) To timeout this timer 1+ of the above | |
1435 | * said value is recommended. | |
1436 | * | |
1437 | * In non-burst mode, Value greater than one DPI frame time in | |
1438 | * byte clock(txbyteclkhs) To timeout this timer 1+ of the above | |
1439 | * said value is recommended. | |
1440 | * | |
1441 | * In DBI only mode, value greater than one DBI frame time in | |
1442 | * byte clock(txbyteclkhs) To timeout this timer 1+ of the above | |
1443 | * said value is recommended. | |
1444 | */ | |
4e646495 | 1445 | |
24ee0e64 GS |
1446 | if (is_vid_mode(intel_dsi) && |
1447 | intel_dsi->video_mode_format == VIDEO_MODE_BURST) { | |
1448 | I915_WRITE(MIPI_HS_TX_TIMEOUT(port), | |
aad941d5 | 1449 | txbyteclkhs(adjusted_mode->crtc_htotal, bpp, |
124abe07 VS |
1450 | intel_dsi->lane_count, |
1451 | intel_dsi->burst_mode_ratio) + 1); | |
24ee0e64 GS |
1452 | } else { |
1453 | I915_WRITE(MIPI_HS_TX_TIMEOUT(port), | |
aad941d5 VS |
1454 | txbyteclkhs(adjusted_mode->crtc_vtotal * |
1455 | adjusted_mode->crtc_htotal, | |
124abe07 VS |
1456 | bpp, intel_dsi->lane_count, |
1457 | intel_dsi->burst_mode_ratio) + 1); | |
24ee0e64 GS |
1458 | } |
1459 | I915_WRITE(MIPI_LP_RX_TIMEOUT(port), intel_dsi->lp_rx_timeout); | |
1460 | I915_WRITE(MIPI_TURN_AROUND_TIMEOUT(port), | |
1461 | intel_dsi->turn_arnd_val); | |
1462 | I915_WRITE(MIPI_DEVICE_RESET_TIMER(port), | |
1463 | intel_dsi->rst_timer_val); | |
f1c79f16 | 1464 | |
24ee0e64 | 1465 | /* dphy stuff */ |
f1c79f16 | 1466 | |
24ee0e64 GS |
1467 | /* in terms of low power clock */ |
1468 | I915_WRITE(MIPI_INIT_COUNT(port), | |
1469 | txclkesc(intel_dsi->escape_clk_div, 100)); | |
4e646495 | 1470 | |
cc3f90f0 | 1471 | if (IS_GEN9_LP(dev_priv) && (!intel_dsi->dual_link)) { |
d2e08c0f SS |
1472 | /* |
1473 | * BXT spec says write MIPI_INIT_COUNT for | |
1474 | * both the ports, even if only one is | |
1475 | * getting used. So write the other port | |
1476 | * if not in dual link mode. | |
1477 | */ | |
1478 | I915_WRITE(MIPI_INIT_COUNT(port == | |
1479 | PORT_A ? PORT_C : PORT_A), | |
1480 | intel_dsi->init_count); | |
1481 | } | |
4e646495 | 1482 | |
24ee0e64 | 1483 | /* recovery disables */ |
87c54d0e | 1484 | I915_WRITE(MIPI_EOT_DISABLE(port), tmp); |
cf4dbd2e | 1485 | |
24ee0e64 GS |
1486 | /* in terms of low power clock */ |
1487 | I915_WRITE(MIPI_INIT_COUNT(port), intel_dsi->init_count); | |
4e646495 | 1488 | |
24ee0e64 GS |
1489 | /* in terms of txbyteclkhs. actual high to low switch + |
1490 | * MIPI_STOP_STATE_STALL * MIPI_LP_BYTECLK. | |
1491 | * | |
1492 | * XXX: write MIPI_STOP_STATE_STALL? | |
1493 | */ | |
1494 | I915_WRITE(MIPI_HIGH_LOW_SWITCH_COUNT(port), | |
1495 | intel_dsi->hs_to_lp_count); | |
1496 | ||
1497 | /* XXX: low power clock equivalence in terms of byte clock. | |
1498 | * the number of byte clocks occupied in one low power clock. | |
1499 | * based on txbyteclkhs and txclkesc. | |
1500 | * txclkesc time / txbyteclk time * (105 + MIPI_STOP_STATE_STALL | |
1501 | * ) / 105.??? | |
1502 | */ | |
1503 | I915_WRITE(MIPI_LP_BYTECLK(port), intel_dsi->lp_byte_clk); | |
1504 | ||
b426f985 D |
1505 | if (IS_GEMINILAKE(dev_priv)) { |
1506 | I915_WRITE(MIPI_TLPX_TIME_COUNT(port), | |
1507 | intel_dsi->lp_byte_clk); | |
1508 | /* Shadow of DPHY reg */ | |
1509 | I915_WRITE(MIPI_CLK_LANE_TIMING(port), | |
1510 | intel_dsi->dphy_reg); | |
1511 | } | |
1512 | ||
24ee0e64 GS |
1513 | /* the bw essential for transmitting 16 long packets containing |
1514 | * 252 bytes meant for dcs write memory command is programmed in | |
1515 | * this register in terms of byte clocks. based on dsi transfer | |
1516 | * rate and the number of lanes configured the time taken to | |
1517 | * transmit 16 long packets in a dsi stream varies. */ | |
1518 | I915_WRITE(MIPI_DBI_BW_CTRL(port), intel_dsi->bw_timer); | |
1519 | ||
1520 | I915_WRITE(MIPI_CLK_LANE_SWITCH_TIME_CNT(port), | |
1521 | intel_dsi->clk_lp_to_hs_count << LP_HS_SSW_CNT_SHIFT | | |
1522 | intel_dsi->clk_hs_to_lp_count << HS_LP_PWR_SW_CNT_SHIFT); | |
1523 | ||
1524 | if (is_vid_mode(intel_dsi)) | |
1525 | /* Some panels might have resolution which is not a | |
1526 | * multiple of 64 like 1366 x 768. Enable RANDOM | |
1527 | * resolution support for such panels by default */ | |
1528 | I915_WRITE(MIPI_VIDEO_MODE_FORMAT(port), | |
1529 | intel_dsi->video_frmt_cfg_bits | | |
1530 | intel_dsi->video_mode_format | | |
1531 | IP_TG_CONFIG | | |
1532 | RANDOM_DPI_DISPLAY_RESOLUTION); | |
1533 | } | |
4e646495 JN |
1534 | } |
1535 | ||
c7991eca HG |
1536 | static void intel_dsi_unprepare(struct intel_encoder *encoder) |
1537 | { | |
1538 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); | |
1539 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); | |
1540 | enum port port; | |
1541 | u32 val; | |
1542 | ||
46448483 D |
1543 | if (!IS_GEMINILAKE(dev_priv)) { |
1544 | for_each_dsi_port(port, intel_dsi->ports) { | |
1545 | /* Panel commands can be sent when clock is in LP11 */ | |
1546 | I915_WRITE(MIPI_DEVICE_READY(port), 0x0); | |
c7991eca | 1547 | |
46448483 D |
1548 | intel_dsi_reset_clocks(encoder, port); |
1549 | I915_WRITE(MIPI_EOT_DISABLE(port), CLOCKSTOP); | |
c7991eca | 1550 | |
46448483 D |
1551 | val = I915_READ(MIPI_DSI_FUNC_PRG(port)); |
1552 | val &= ~VID_MODE_FORMAT_MASK; | |
1553 | I915_WRITE(MIPI_DSI_FUNC_PRG(port), val); | |
c7991eca | 1554 | |
46448483 D |
1555 | I915_WRITE(MIPI_DEVICE_READY(port), 0x1); |
1556 | } | |
c7991eca HG |
1557 | } |
1558 | } | |
1559 | ||
4e646495 JN |
1560 | static int intel_dsi_get_modes(struct drm_connector *connector) |
1561 | { | |
1562 | struct intel_connector *intel_connector = to_intel_connector(connector); | |
1563 | struct drm_display_mode *mode; | |
1564 | ||
1565 | DRM_DEBUG_KMS("\n"); | |
1566 | ||
1567 | if (!intel_connector->panel.fixed_mode) { | |
1568 | DRM_DEBUG_KMS("no fixed mode\n"); | |
1569 | return 0; | |
1570 | } | |
1571 | ||
1572 | mode = drm_mode_duplicate(connector->dev, | |
1573 | intel_connector->panel.fixed_mode); | |
1574 | if (!mode) { | |
1575 | DRM_DEBUG_KMS("drm_mode_duplicate failed\n"); | |
1576 | return 0; | |
1577 | } | |
1578 | ||
1579 | drm_mode_probed_add(connector, mode); | |
1580 | return 1; | |
1581 | } | |
1582 | ||
f4ee265f VS |
1583 | static int intel_dsi_set_property(struct drm_connector *connector, |
1584 | struct drm_property *property, | |
1585 | uint64_t val) | |
1586 | { | |
1587 | struct drm_device *dev = connector->dev; | |
1588 | struct intel_connector *intel_connector = to_intel_connector(connector); | |
1589 | struct drm_crtc *crtc; | |
1590 | int ret; | |
1591 | ||
1592 | ret = drm_object_property_set_value(&connector->base, property, val); | |
1593 | if (ret) | |
1594 | return ret; | |
1595 | ||
1596 | if (property == dev->mode_config.scaling_mode_property) { | |
1597 | if (val == DRM_MODE_SCALE_NONE) { | |
1598 | DRM_DEBUG_KMS("no scaling not supported\n"); | |
1599 | return -EINVAL; | |
1600 | } | |
49cff963 | 1601 | if (HAS_GMCH_DISPLAY(to_i915(dev)) && |
234126c6 VS |
1602 | val == DRM_MODE_SCALE_CENTER) { |
1603 | DRM_DEBUG_KMS("centering not supported\n"); | |
1604 | return -EINVAL; | |
1605 | } | |
f4ee265f VS |
1606 | |
1607 | if (intel_connector->panel.fitting_mode == val) | |
1608 | return 0; | |
1609 | ||
1610 | intel_connector->panel.fitting_mode = val; | |
1611 | } | |
1612 | ||
5eff0edf | 1613 | crtc = connector->state->crtc; |
f4ee265f VS |
1614 | if (crtc && crtc->state->enable) { |
1615 | /* | |
1616 | * If the CRTC is enabled, the display will be changed | |
1617 | * according to the new panel fitting mode. | |
1618 | */ | |
1619 | intel_crtc_restore_mode(crtc); | |
1620 | } | |
1621 | ||
1622 | return 0; | |
1623 | } | |
1624 | ||
593e0622 | 1625 | static void intel_dsi_connector_destroy(struct drm_connector *connector) |
4e646495 JN |
1626 | { |
1627 | struct intel_connector *intel_connector = to_intel_connector(connector); | |
1628 | ||
1629 | DRM_DEBUG_KMS("\n"); | |
1630 | intel_panel_fini(&intel_connector->panel); | |
4e646495 JN |
1631 | drm_connector_cleanup(connector); |
1632 | kfree(connector); | |
1633 | } | |
1634 | ||
593e0622 JN |
1635 | static void intel_dsi_encoder_destroy(struct drm_encoder *encoder) |
1636 | { | |
1637 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); | |
1638 | ||
1639 | if (intel_dsi->panel) { | |
1640 | drm_panel_detach(intel_dsi->panel); | |
1641 | /* XXX: Logically this call belongs in the panel driver. */ | |
1642 | drm_panel_remove(intel_dsi->panel); | |
1643 | } | |
fc45e821 SK |
1644 | |
1645 | /* dispose of the gpios */ | |
1646 | if (intel_dsi->gpio_panel) | |
1647 | gpiod_put(intel_dsi->gpio_panel); | |
1648 | ||
593e0622 JN |
1649 | intel_encoder_destroy(encoder); |
1650 | } | |
1651 | ||
4e646495 | 1652 | static const struct drm_encoder_funcs intel_dsi_funcs = { |
593e0622 | 1653 | .destroy = intel_dsi_encoder_destroy, |
4e646495 JN |
1654 | }; |
1655 | ||
1656 | static const struct drm_connector_helper_funcs intel_dsi_connector_helper_funcs = { | |
1657 | .get_modes = intel_dsi_get_modes, | |
1658 | .mode_valid = intel_dsi_mode_valid, | |
4e646495 JN |
1659 | }; |
1660 | ||
1661 | static const struct drm_connector_funcs intel_dsi_connector_funcs = { | |
4d688a2a | 1662 | .dpms = drm_atomic_helper_connector_dpms, |
1ebaa0b9 | 1663 | .late_register = intel_connector_register, |
c191eca1 | 1664 | .early_unregister = intel_connector_unregister, |
593e0622 | 1665 | .destroy = intel_dsi_connector_destroy, |
4e646495 | 1666 | .fill_modes = drm_helper_probe_single_connector_modes, |
f4ee265f | 1667 | .set_property = intel_dsi_set_property, |
2545e4a6 | 1668 | .atomic_get_property = intel_connector_atomic_get_property, |
c6f95f27 | 1669 | .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, |
98969725 | 1670 | .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, |
4e646495 JN |
1671 | }; |
1672 | ||
f4ee265f VS |
1673 | static void intel_dsi_add_properties(struct intel_connector *connector) |
1674 | { | |
1675 | struct drm_device *dev = connector->base.dev; | |
1676 | ||
1677 | if (connector->panel.fixed_mode) { | |
1678 | drm_mode_create_scaling_mode_property(dev); | |
1679 | drm_object_attach_property(&connector->base.base, | |
1680 | dev->mode_config.scaling_mode_property, | |
1681 | DRM_MODE_SCALE_ASPECT); | |
1682 | connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT; | |
1683 | } | |
1684 | } | |
1685 | ||
c39055b0 | 1686 | void intel_dsi_init(struct drm_i915_private *dev_priv) |
4e646495 | 1687 | { |
c39055b0 | 1688 | struct drm_device *dev = &dev_priv->drm; |
4e646495 JN |
1689 | struct intel_dsi *intel_dsi; |
1690 | struct intel_encoder *intel_encoder; | |
1691 | struct drm_encoder *encoder; | |
1692 | struct intel_connector *intel_connector; | |
1693 | struct drm_connector *connector; | |
593e0622 | 1694 | struct drm_display_mode *scan, *fixed_mode = NULL; |
7e9804fd | 1695 | enum port port; |
4e646495 JN |
1696 | unsigned int i; |
1697 | ||
1698 | DRM_DEBUG_KMS("\n"); | |
1699 | ||
3e6bd011 | 1700 | /* There is no detection method for MIPI so rely on VBT */ |
7137aec1 | 1701 | if (!intel_bios_is_dsi_present(dev_priv, &port)) |
4328633d | 1702 | return; |
3e6bd011 | 1703 | |
920a14b2 | 1704 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { |
868d665b | 1705 | dev_priv->mipi_mmio_base = VLV_MIPI_BASE; |
cc3f90f0 | 1706 | } else if (IS_GEN9_LP(dev_priv)) { |
c6c794a2 | 1707 | dev_priv->mipi_mmio_base = BXT_MIPI_BASE; |
868d665b CJ |
1708 | } else { |
1709 | DRM_ERROR("Unsupported Mipi device to reg base"); | |
1710 | return; | |
1711 | } | |
3e6bd011 | 1712 | |
4e646495 JN |
1713 | intel_dsi = kzalloc(sizeof(*intel_dsi), GFP_KERNEL); |
1714 | if (!intel_dsi) | |
4328633d | 1715 | return; |
4e646495 | 1716 | |
08d9bc92 | 1717 | intel_connector = intel_connector_alloc(); |
4e646495 JN |
1718 | if (!intel_connector) { |
1719 | kfree(intel_dsi); | |
4328633d | 1720 | return; |
4e646495 JN |
1721 | } |
1722 | ||
1723 | intel_encoder = &intel_dsi->base; | |
1724 | encoder = &intel_encoder->base; | |
1725 | intel_dsi->attached_connector = intel_connector; | |
1726 | ||
1727 | connector = &intel_connector->base; | |
1728 | ||
13a3d91f | 1729 | drm_encoder_init(dev, encoder, &intel_dsi_funcs, DRM_MODE_ENCODER_DSI, |
580d8ed5 | 1730 | "DSI %c", port_name(port)); |
4e646495 | 1731 | |
4e646495 | 1732 | intel_encoder->compute_config = intel_dsi_compute_config; |
4e646495 | 1733 | intel_encoder->pre_enable = intel_dsi_pre_enable; |
2634fd7f | 1734 | intel_encoder->enable = intel_dsi_enable_nop; |
c315faf8 | 1735 | intel_encoder->disable = intel_dsi_pre_disable; |
4e646495 JN |
1736 | intel_encoder->post_disable = intel_dsi_post_disable; |
1737 | intel_encoder->get_hw_state = intel_dsi_get_hw_state; | |
1738 | intel_encoder->get_config = intel_dsi_get_config; | |
1739 | ||
1740 | intel_connector->get_hw_state = intel_connector_get_hw_state; | |
1741 | ||
03cdc1d4 | 1742 | intel_encoder->port = port; |
79f255a0 | 1743 | |
2e85ab4f JN |
1744 | /* |
1745 | * On BYT/CHV, pipe A maps to MIPI DSI port A, pipe B maps to MIPI DSI | |
1746 | * port C. BXT isn't limited like this. | |
1747 | */ | |
cc3f90f0 | 1748 | if (IS_GEN9_LP(dev_priv)) |
2e85ab4f JN |
1749 | intel_encoder->crtc_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C); |
1750 | else if (port == PORT_A) | |
701d25b4 | 1751 | intel_encoder->crtc_mask = BIT(PIPE_A); |
7137aec1 | 1752 | else |
701d25b4 | 1753 | intel_encoder->crtc_mask = BIT(PIPE_B); |
e7d7cad0 | 1754 | |
90198355 | 1755 | if (dev_priv->vbt.dsi.config->dual_link) { |
701d25b4 | 1756 | intel_dsi->ports = BIT(PORT_A) | BIT(PORT_C); |
90198355 JN |
1757 | |
1758 | switch (dev_priv->vbt.dsi.config->dl_dcs_backlight_ports) { | |
1759 | case DL_DCS_PORT_A: | |
1760 | intel_dsi->dcs_backlight_ports = BIT(PORT_A); | |
1761 | break; | |
1762 | case DL_DCS_PORT_C: | |
1763 | intel_dsi->dcs_backlight_ports = BIT(PORT_C); | |
1764 | break; | |
1765 | default: | |
1766 | case DL_DCS_PORT_A_AND_C: | |
1767 | intel_dsi->dcs_backlight_ports = BIT(PORT_A) | BIT(PORT_C); | |
1768 | break; | |
1769 | } | |
1ecc1c6c D |
1770 | |
1771 | switch (dev_priv->vbt.dsi.config->dl_dcs_cabc_ports) { | |
1772 | case DL_DCS_PORT_A: | |
1773 | intel_dsi->dcs_cabc_ports = BIT(PORT_A); | |
1774 | break; | |
1775 | case DL_DCS_PORT_C: | |
1776 | intel_dsi->dcs_cabc_ports = BIT(PORT_C); | |
1777 | break; | |
1778 | default: | |
1779 | case DL_DCS_PORT_A_AND_C: | |
1780 | intel_dsi->dcs_cabc_ports = BIT(PORT_A) | BIT(PORT_C); | |
1781 | break; | |
1782 | } | |
90198355 | 1783 | } else { |
701d25b4 | 1784 | intel_dsi->ports = BIT(port); |
90198355 | 1785 | intel_dsi->dcs_backlight_ports = BIT(port); |
1ecc1c6c | 1786 | intel_dsi->dcs_cabc_ports = BIT(port); |
90198355 | 1787 | } |
82425785 | 1788 | |
1ecc1c6c D |
1789 | if (!dev_priv->vbt.dsi.config->cabc_supported) |
1790 | intel_dsi->dcs_cabc_ports = 0; | |
1791 | ||
7e9804fd JN |
1792 | /* Create a DSI host (and a device) for each port. */ |
1793 | for_each_dsi_port(port, intel_dsi->ports) { | |
1794 | struct intel_dsi_host *host; | |
1795 | ||
1796 | host = intel_dsi_host_init(intel_dsi, port); | |
1797 | if (!host) | |
1798 | goto err; | |
1799 | ||
1800 | intel_dsi->dsi_hosts[port] = host; | |
1801 | } | |
1802 | ||
593e0622 JN |
1803 | for (i = 0; i < ARRAY_SIZE(intel_dsi_drivers); i++) { |
1804 | intel_dsi->panel = intel_dsi_drivers[i].init(intel_dsi, | |
1805 | intel_dsi_drivers[i].panel_id); | |
1806 | if (intel_dsi->panel) | |
4e646495 JN |
1807 | break; |
1808 | } | |
1809 | ||
593e0622 | 1810 | if (!intel_dsi->panel) { |
4e646495 JN |
1811 | DRM_DEBUG_KMS("no device found\n"); |
1812 | goto err; | |
1813 | } | |
1814 | ||
fc45e821 SK |
1815 | /* |
1816 | * In case of BYT with CRC PMIC, we need to use GPIO for | |
1817 | * Panel control. | |
1818 | */ | |
645a2f6e US |
1819 | if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && |
1820 | (dev_priv->vbt.dsi.config->pwm_blc == PPS_BLC_PMIC)) { | |
fc45e821 SK |
1821 | intel_dsi->gpio_panel = |
1822 | gpiod_get(dev->dev, "panel", GPIOD_OUT_HIGH); | |
1823 | ||
1824 | if (IS_ERR(intel_dsi->gpio_panel)) { | |
1825 | DRM_ERROR("Failed to own gpio for panel control\n"); | |
1826 | intel_dsi->gpio_panel = NULL; | |
1827 | } | |
1828 | } | |
1829 | ||
4e646495 | 1830 | intel_encoder->type = INTEL_OUTPUT_DSI; |
79f255a0 | 1831 | intel_encoder->power_domain = POWER_DOMAIN_PORT_DSI; |
bc079e8b | 1832 | intel_encoder->cloneable = 0; |
4e646495 JN |
1833 | drm_connector_init(dev, connector, &intel_dsi_connector_funcs, |
1834 | DRM_MODE_CONNECTOR_DSI); | |
1835 | ||
1836 | drm_connector_helper_add(connector, &intel_dsi_connector_helper_funcs); | |
1837 | ||
1838 | connector->display_info.subpixel_order = SubPixelHorizontalRGB; /*XXX*/ | |
1839 | connector->interlace_allowed = false; | |
1840 | connector->doublescan_allowed = false; | |
1841 | ||
1842 | intel_connector_attach_encoder(intel_connector, intel_encoder); | |
1843 | ||
593e0622 JN |
1844 | drm_panel_attach(intel_dsi->panel, connector); |
1845 | ||
1846 | mutex_lock(&dev->mode_config.mutex); | |
1847 | drm_panel_get_modes(intel_dsi->panel); | |
1848 | list_for_each_entry(scan, &connector->probed_modes, head) { | |
1849 | if ((scan->type & DRM_MODE_TYPE_PREFERRED)) { | |
1850 | fixed_mode = drm_mode_duplicate(dev, scan); | |
1851 | break; | |
1852 | } | |
1853 | } | |
1854 | mutex_unlock(&dev->mode_config.mutex); | |
1855 | ||
4e646495 JN |
1856 | if (!fixed_mode) { |
1857 | DRM_DEBUG_KMS("no fixed mode\n"); | |
1858 | goto err; | |
1859 | } | |
1860 | ||
df457245 VS |
1861 | connector->display_info.width_mm = fixed_mode->width_mm; |
1862 | connector->display_info.height_mm = fixed_mode->height_mm; | |
1863 | ||
4b6ed685 | 1864 | intel_panel_init(&intel_connector->panel, fixed_mode, NULL); |
fda9ee98 | 1865 | intel_panel_setup_backlight(connector, INVALID_PIPE); |
f4ee265f VS |
1866 | |
1867 | intel_dsi_add_properties(intel_connector); | |
1868 | ||
4328633d | 1869 | return; |
4e646495 JN |
1870 | |
1871 | err: | |
1872 | drm_encoder_cleanup(&intel_encoder->base); | |
1873 | kfree(intel_dsi); | |
1874 | kfree(intel_connector); | |
4e646495 | 1875 | } |