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4e646495 JN |
1 | /* |
2 | * Copyright © 2013 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
21 | * DEALINGS IN THE SOFTWARE. | |
22 | * | |
23 | * Author: Jani Nikula <jani.nikula@intel.com> | |
24 | */ | |
25 | ||
26 | #include <drm/drmP.h> | |
c6f95f27 | 27 | #include <drm/drm_atomic_helper.h> |
4e646495 JN |
28 | #include <drm/drm_crtc.h> |
29 | #include <drm/drm_edid.h> | |
30 | #include <drm/i915_drm.h> | |
593e0622 | 31 | #include <drm/drm_panel.h> |
7e9804fd | 32 | #include <drm/drm_mipi_dsi.h> |
4e646495 | 33 | #include <linux/slab.h> |
fc45e821 | 34 | #include <linux/gpio/consumer.h> |
4e646495 JN |
35 | #include "i915_drv.h" |
36 | #include "intel_drv.h" | |
37 | #include "intel_dsi.h" | |
4e646495 | 38 | |
593e0622 JN |
39 | static const struct { |
40 | u16 panel_id; | |
41 | struct drm_panel * (*init)(struct intel_dsi *intel_dsi, u16 panel_id); | |
42 | } intel_dsi_drivers[] = { | |
2ab8b458 SK |
43 | { |
44 | .panel_id = MIPI_DSI_GENERIC_PANEL_ID, | |
593e0622 | 45 | .init = vbt_panel_init, |
2ab8b458 | 46 | }, |
4e646495 JN |
47 | }; |
48 | ||
042ab0c3 R |
49 | /* return pixels in terms of txbyteclkhs */ |
50 | static u16 txbyteclkhs(u16 pixels, int bpp, int lane_count, | |
51 | u16 burst_mode_ratio) | |
52 | { | |
53 | return DIV_ROUND_UP(DIV_ROUND_UP(pixels * bpp * burst_mode_ratio, | |
54 | 8 * 100), lane_count); | |
55 | } | |
56 | ||
cefc4e18 R |
57 | /* return pixels equvalent to txbyteclkhs */ |
58 | static u16 pixels_from_txbyteclkhs(u16 clk_hs, int bpp, int lane_count, | |
59 | u16 burst_mode_ratio) | |
60 | { | |
61 | return DIV_ROUND_UP((clk_hs * lane_count * 8 * 100), | |
62 | (bpp * burst_mode_ratio)); | |
63 | } | |
64 | ||
43367ec9 R |
65 | enum mipi_dsi_pixel_format pixel_format_from_register_bits(u32 fmt) |
66 | { | |
67 | /* It just so happens the VBT matches register contents. */ | |
68 | switch (fmt) { | |
69 | case VID_MODE_FORMAT_RGB888: | |
70 | return MIPI_DSI_FMT_RGB888; | |
71 | case VID_MODE_FORMAT_RGB666: | |
72 | return MIPI_DSI_FMT_RGB666; | |
73 | case VID_MODE_FORMAT_RGB666_PACKED: | |
74 | return MIPI_DSI_FMT_RGB666_PACKED; | |
75 | case VID_MODE_FORMAT_RGB565: | |
76 | return MIPI_DSI_FMT_RGB565; | |
77 | default: | |
78 | MISSING_CASE(fmt); | |
79 | return MIPI_DSI_FMT_RGB666; | |
80 | } | |
81 | } | |
82 | ||
7f6a6a4a | 83 | static void wait_for_dsi_fifo_empty(struct intel_dsi *intel_dsi, enum port port) |
3b1808bf JN |
84 | { |
85 | struct drm_encoder *encoder = &intel_dsi->base.base; | |
86 | struct drm_device *dev = encoder->dev; | |
fac5e23e | 87 | struct drm_i915_private *dev_priv = to_i915(dev); |
3b1808bf JN |
88 | u32 mask; |
89 | ||
90 | mask = LP_CTRL_FIFO_EMPTY | HS_CTRL_FIFO_EMPTY | | |
91 | LP_DATA_FIFO_EMPTY | HS_DATA_FIFO_EMPTY; | |
92 | ||
9b6a2d72 CW |
93 | if (intel_wait_for_register(dev_priv, |
94 | MIPI_GEN_FIFO_STAT(port), mask, mask, | |
95 | 100)) | |
3b1808bf JN |
96 | DRM_ERROR("DPI FIFOs are not empty\n"); |
97 | } | |
98 | ||
f0f59a00 VS |
99 | static void write_data(struct drm_i915_private *dev_priv, |
100 | i915_reg_t reg, | |
7e9804fd JN |
101 | const u8 *data, u32 len) |
102 | { | |
103 | u32 i, j; | |
104 | ||
105 | for (i = 0; i < len; i += 4) { | |
106 | u32 val = 0; | |
107 | ||
108 | for (j = 0; j < min_t(u32, len - i, 4); j++) | |
109 | val |= *data++ << 8 * j; | |
110 | ||
111 | I915_WRITE(reg, val); | |
112 | } | |
113 | } | |
114 | ||
f0f59a00 VS |
115 | static void read_data(struct drm_i915_private *dev_priv, |
116 | i915_reg_t reg, | |
7e9804fd JN |
117 | u8 *data, u32 len) |
118 | { | |
119 | u32 i, j; | |
120 | ||
121 | for (i = 0; i < len; i += 4) { | |
122 | u32 val = I915_READ(reg); | |
123 | ||
124 | for (j = 0; j < min_t(u32, len - i, 4); j++) | |
125 | *data++ = val >> 8 * j; | |
126 | } | |
127 | } | |
128 | ||
129 | static ssize_t intel_dsi_host_transfer(struct mipi_dsi_host *host, | |
130 | const struct mipi_dsi_msg *msg) | |
131 | { | |
132 | struct intel_dsi_host *intel_dsi_host = to_intel_dsi_host(host); | |
133 | struct drm_device *dev = intel_dsi_host->intel_dsi->base.base.dev; | |
fac5e23e | 134 | struct drm_i915_private *dev_priv = to_i915(dev); |
7e9804fd JN |
135 | enum port port = intel_dsi_host->port; |
136 | struct mipi_dsi_packet packet; | |
137 | ssize_t ret; | |
138 | const u8 *header, *data; | |
f0f59a00 VS |
139 | i915_reg_t data_reg, ctrl_reg; |
140 | u32 data_mask, ctrl_mask; | |
7e9804fd JN |
141 | |
142 | ret = mipi_dsi_create_packet(&packet, msg); | |
143 | if (ret < 0) | |
144 | return ret; | |
145 | ||
146 | header = packet.header; | |
147 | data = packet.payload; | |
148 | ||
149 | if (msg->flags & MIPI_DSI_MSG_USE_LPM) { | |
150 | data_reg = MIPI_LP_GEN_DATA(port); | |
151 | data_mask = LP_DATA_FIFO_FULL; | |
152 | ctrl_reg = MIPI_LP_GEN_CTRL(port); | |
153 | ctrl_mask = LP_CTRL_FIFO_FULL; | |
154 | } else { | |
155 | data_reg = MIPI_HS_GEN_DATA(port); | |
156 | data_mask = HS_DATA_FIFO_FULL; | |
157 | ctrl_reg = MIPI_HS_GEN_CTRL(port); | |
158 | ctrl_mask = HS_CTRL_FIFO_FULL; | |
159 | } | |
160 | ||
161 | /* note: this is never true for reads */ | |
162 | if (packet.payload_length) { | |
8c6cea0b CW |
163 | if (intel_wait_for_register(dev_priv, |
164 | MIPI_GEN_FIFO_STAT(port), | |
165 | data_mask, 0, | |
166 | 50)) | |
7e9804fd JN |
167 | DRM_ERROR("Timeout waiting for HS/LP DATA FIFO !full\n"); |
168 | ||
169 | write_data(dev_priv, data_reg, packet.payload, | |
170 | packet.payload_length); | |
171 | } | |
172 | ||
173 | if (msg->rx_len) { | |
174 | I915_WRITE(MIPI_INTR_STAT(port), GEN_READ_DATA_AVAIL); | |
175 | } | |
176 | ||
84c2aa90 CW |
177 | if (intel_wait_for_register(dev_priv, |
178 | MIPI_GEN_FIFO_STAT(port), | |
179 | ctrl_mask, 0, | |
180 | 50)) { | |
7e9804fd JN |
181 | DRM_ERROR("Timeout waiting for HS/LP CTRL FIFO !full\n"); |
182 | } | |
183 | ||
184 | I915_WRITE(ctrl_reg, header[2] << 16 | header[1] << 8 | header[0]); | |
185 | ||
186 | /* ->rx_len is set only for reads */ | |
187 | if (msg->rx_len) { | |
188 | data_mask = GEN_READ_DATA_AVAIL; | |
e7615b37 CW |
189 | if (intel_wait_for_register(dev_priv, |
190 | MIPI_INTR_STAT(port), | |
191 | data_mask, data_mask, | |
192 | 50)) | |
7e9804fd JN |
193 | DRM_ERROR("Timeout waiting for read data.\n"); |
194 | ||
195 | read_data(dev_priv, data_reg, msg->rx_buf, msg->rx_len); | |
196 | } | |
197 | ||
198 | /* XXX: fix for reads and writes */ | |
199 | return 4 + packet.payload_length; | |
200 | } | |
201 | ||
202 | static int intel_dsi_host_attach(struct mipi_dsi_host *host, | |
203 | struct mipi_dsi_device *dsi) | |
204 | { | |
205 | return 0; | |
206 | } | |
207 | ||
208 | static int intel_dsi_host_detach(struct mipi_dsi_host *host, | |
209 | struct mipi_dsi_device *dsi) | |
210 | { | |
211 | return 0; | |
212 | } | |
213 | ||
214 | static const struct mipi_dsi_host_ops intel_dsi_host_ops = { | |
215 | .attach = intel_dsi_host_attach, | |
216 | .detach = intel_dsi_host_detach, | |
217 | .transfer = intel_dsi_host_transfer, | |
218 | }; | |
219 | ||
220 | static struct intel_dsi_host *intel_dsi_host_init(struct intel_dsi *intel_dsi, | |
221 | enum port port) | |
222 | { | |
223 | struct intel_dsi_host *host; | |
224 | struct mipi_dsi_device *device; | |
225 | ||
226 | host = kzalloc(sizeof(*host), GFP_KERNEL); | |
227 | if (!host) | |
228 | return NULL; | |
229 | ||
230 | host->base.ops = &intel_dsi_host_ops; | |
231 | host->intel_dsi = intel_dsi; | |
232 | host->port = port; | |
233 | ||
234 | /* | |
235 | * We should call mipi_dsi_host_register(&host->base) here, but we don't | |
236 | * have a host->dev, and we don't have OF stuff either. So just use the | |
237 | * dsi framework as a library and hope for the best. Create the dsi | |
238 | * devices by ourselves here too. Need to be careful though, because we | |
239 | * don't initialize any of the driver model devices here. | |
240 | */ | |
241 | device = kzalloc(sizeof(*device), GFP_KERNEL); | |
242 | if (!device) { | |
243 | kfree(host); | |
244 | return NULL; | |
245 | } | |
246 | ||
247 | device->host = &host->base; | |
248 | host->device = device; | |
249 | ||
250 | return host; | |
251 | } | |
252 | ||
a2581a9e JN |
253 | /* |
254 | * send a video mode command | |
255 | * | |
256 | * XXX: commands with data in MIPI_DPI_DATA? | |
257 | */ | |
258 | static int dpi_send_cmd(struct intel_dsi *intel_dsi, u32 cmd, bool hs, | |
259 | enum port port) | |
260 | { | |
261 | struct drm_encoder *encoder = &intel_dsi->base.base; | |
262 | struct drm_device *dev = encoder->dev; | |
fac5e23e | 263 | struct drm_i915_private *dev_priv = to_i915(dev); |
a2581a9e JN |
264 | u32 mask; |
265 | ||
266 | /* XXX: pipe, hs */ | |
267 | if (hs) | |
268 | cmd &= ~DPI_LP_MODE; | |
269 | else | |
270 | cmd |= DPI_LP_MODE; | |
271 | ||
272 | /* clear bit */ | |
273 | I915_WRITE(MIPI_INTR_STAT(port), SPL_PKT_SENT_INTERRUPT); | |
274 | ||
275 | /* XXX: old code skips write if control unchanged */ | |
276 | if (cmd == I915_READ(MIPI_DPI_CONTROL(port))) | |
277 | DRM_ERROR("Same special packet %02x twice in a row.\n", cmd); | |
278 | ||
279 | I915_WRITE(MIPI_DPI_CONTROL(port), cmd); | |
280 | ||
281 | mask = SPL_PKT_SENT_INTERRUPT; | |
2af05078 CW |
282 | if (intel_wait_for_register(dev_priv, |
283 | MIPI_INTR_STAT(port), mask, mask, | |
284 | 100)) | |
a2581a9e JN |
285 | DRM_ERROR("Video mode command 0x%08x send failed.\n", cmd); |
286 | ||
287 | return 0; | |
288 | } | |
289 | ||
e9fe51c6 | 290 | static void band_gap_reset(struct drm_i915_private *dev_priv) |
4ce8c9a7 | 291 | { |
a580516d | 292 | mutex_lock(&dev_priv->sb_lock); |
4ce8c9a7 | 293 | |
e9fe51c6 SK |
294 | vlv_flisdsi_write(dev_priv, 0x08, 0x0001); |
295 | vlv_flisdsi_write(dev_priv, 0x0F, 0x0005); | |
296 | vlv_flisdsi_write(dev_priv, 0x0F, 0x0025); | |
297 | udelay(150); | |
298 | vlv_flisdsi_write(dev_priv, 0x0F, 0x0000); | |
299 | vlv_flisdsi_write(dev_priv, 0x08, 0x0000); | |
4ce8c9a7 | 300 | |
a580516d | 301 | mutex_unlock(&dev_priv->sb_lock); |
4ce8c9a7 SK |
302 | } |
303 | ||
4e646495 JN |
304 | static inline bool is_vid_mode(struct intel_dsi *intel_dsi) |
305 | { | |
dfba2e2d | 306 | return intel_dsi->operation_mode == INTEL_DSI_VIDEO_MODE; |
4e646495 JN |
307 | } |
308 | ||
309 | static inline bool is_cmd_mode(struct intel_dsi *intel_dsi) | |
310 | { | |
dfba2e2d | 311 | return intel_dsi->operation_mode == INTEL_DSI_COMMAND_MODE; |
4e646495 JN |
312 | } |
313 | ||
4e646495 | 314 | static bool intel_dsi_compute_config(struct intel_encoder *encoder, |
0a478c27 ML |
315 | struct intel_crtc_state *pipe_config, |
316 | struct drm_connector_state *conn_state) | |
4e646495 | 317 | { |
fac5e23e | 318 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
4e646495 JN |
319 | struct intel_dsi *intel_dsi = container_of(encoder, struct intel_dsi, |
320 | base); | |
321 | struct intel_connector *intel_connector = intel_dsi->attached_connector; | |
f4ee265f VS |
322 | struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc); |
323 | const struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode; | |
a65347ba | 324 | struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; |
47eacbab | 325 | int ret; |
4e646495 JN |
326 | |
327 | DRM_DEBUG_KMS("\n"); | |
328 | ||
f4ee265f | 329 | if (fixed_mode) { |
4e646495 JN |
330 | intel_fixed_panel_mode(fixed_mode, adjusted_mode); |
331 | ||
f4ee265f VS |
332 | if (HAS_GMCH_DISPLAY(dev_priv)) |
333 | intel_gmch_panel_fitting(crtc, pipe_config, | |
334 | intel_connector->panel.fitting_mode); | |
335 | else | |
336 | intel_pch_panel_fitting(crtc, pipe_config, | |
337 | intel_connector->panel.fitting_mode); | |
338 | } | |
339 | ||
f573de5a SK |
340 | /* DSI uses short packets for sync events, so clear mode flags for DSI */ |
341 | adjusted_mode->flags = 0; | |
342 | ||
cc3f90f0 | 343 | if (IS_GEN9_LP(dev_priv)) { |
4d1de975 JN |
344 | /* Dual link goes to DSI transcoder A. */ |
345 | if (intel_dsi->ports == BIT(PORT_C)) | |
346 | pipe_config->cpu_transcoder = TRANSCODER_DSI_C; | |
347 | else | |
348 | pipe_config->cpu_transcoder = TRANSCODER_DSI_A; | |
349 | } | |
350 | ||
47eacbab VS |
351 | ret = intel_compute_dsi_pll(encoder, pipe_config); |
352 | if (ret) | |
353 | return false; | |
354 | ||
cd2d34d9 VS |
355 | pipe_config->clock_set = true; |
356 | ||
4e646495 JN |
357 | return true; |
358 | } | |
359 | ||
37ab0810 | 360 | static void bxt_dsi_device_ready(struct intel_encoder *encoder) |
5505a244 | 361 | { |
fac5e23e | 362 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
5505a244 | 363 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); |
369602d3 | 364 | enum port port; |
37ab0810 | 365 | u32 val; |
5505a244 | 366 | |
37ab0810 | 367 | DRM_DEBUG_KMS("\n"); |
a9da9bce | 368 | |
37ab0810 | 369 | /* Exit Low power state in 4 steps*/ |
369602d3 | 370 | for_each_dsi_port(port, intel_dsi->ports) { |
5505a244 | 371 | |
37ab0810 SS |
372 | /* 1. Enable MIPI PHY transparent latch */ |
373 | val = I915_READ(BXT_MIPI_PORT_CTRL(port)); | |
374 | I915_WRITE(BXT_MIPI_PORT_CTRL(port), val | LP_OUTPUT_HOLD); | |
375 | usleep_range(2000, 2500); | |
376 | ||
377 | /* 2. Enter ULPS */ | |
378 | val = I915_READ(MIPI_DEVICE_READY(port)); | |
379 | val &= ~ULPS_STATE_MASK; | |
380 | val |= (ULPS_STATE_ENTER | DEVICE_READY); | |
381 | I915_WRITE(MIPI_DEVICE_READY(port), val); | |
0a7b35ce NMG |
382 | /* at least 2us - relaxed for hrtimer subsystem optimization */ |
383 | usleep_range(10, 50); | |
37ab0810 SS |
384 | |
385 | /* 3. Exit ULPS */ | |
386 | val = I915_READ(MIPI_DEVICE_READY(port)); | |
387 | val &= ~ULPS_STATE_MASK; | |
388 | val |= (ULPS_STATE_EXIT | DEVICE_READY); | |
389 | I915_WRITE(MIPI_DEVICE_READY(port), val); | |
390 | usleep_range(1000, 1500); | |
5505a244 | 391 | |
37ab0810 SS |
392 | /* Clear ULPS and set device ready */ |
393 | val = I915_READ(MIPI_DEVICE_READY(port)); | |
394 | val &= ~ULPS_STATE_MASK; | |
395 | val |= DEVICE_READY; | |
396 | I915_WRITE(MIPI_DEVICE_READY(port), val); | |
369602d3 | 397 | } |
5505a244 GS |
398 | } |
399 | ||
37ab0810 | 400 | static void vlv_dsi_device_ready(struct intel_encoder *encoder) |
4e646495 | 401 | { |
fac5e23e | 402 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
24ee0e64 GS |
403 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); |
404 | enum port port; | |
1dbd7cb2 SK |
405 | u32 val; |
406 | ||
4e646495 | 407 | DRM_DEBUG_KMS("\n"); |
4e646495 | 408 | |
a580516d | 409 | mutex_lock(&dev_priv->sb_lock); |
2095f9fc SK |
410 | /* program rcomp for compliance, reduce from 50 ohms to 45 ohms |
411 | * needed everytime after power gate */ | |
412 | vlv_flisdsi_write(dev_priv, 0x04, 0x0004); | |
a580516d | 413 | mutex_unlock(&dev_priv->sb_lock); |
2095f9fc SK |
414 | |
415 | /* bandgap reset is needed after everytime we do power gate */ | |
416 | band_gap_reset(dev_priv); | |
417 | ||
24ee0e64 | 418 | for_each_dsi_port(port, intel_dsi->ports) { |
aceb365c | 419 | |
24ee0e64 GS |
420 | I915_WRITE(MIPI_DEVICE_READY(port), ULPS_STATE_ENTER); |
421 | usleep_range(2500, 3000); | |
aceb365c | 422 | |
bf344e80 GS |
423 | /* Enable MIPI PHY transparent latch |
424 | * Common bit for both MIPI Port A & MIPI Port C | |
425 | * No similar bit in MIPI Port C reg | |
426 | */ | |
4ba7d93a | 427 | val = I915_READ(MIPI_PORT_CTRL(PORT_A)); |
bf344e80 | 428 | I915_WRITE(MIPI_PORT_CTRL(PORT_A), val | LP_OUTPUT_HOLD); |
24ee0e64 | 429 | usleep_range(1000, 1500); |
aceb365c | 430 | |
24ee0e64 GS |
431 | I915_WRITE(MIPI_DEVICE_READY(port), ULPS_STATE_EXIT); |
432 | usleep_range(2500, 3000); | |
433 | ||
434 | I915_WRITE(MIPI_DEVICE_READY(port), DEVICE_READY); | |
435 | usleep_range(2500, 3000); | |
436 | } | |
1dbd7cb2 | 437 | } |
1dbd7cb2 | 438 | |
37ab0810 SS |
439 | static void intel_dsi_device_ready(struct intel_encoder *encoder) |
440 | { | |
e2d214ae | 441 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
37ab0810 | 442 | |
e2d214ae | 443 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) |
37ab0810 | 444 | vlv_dsi_device_ready(encoder); |
cc3f90f0 | 445 | else if (IS_GEN9_LP(dev_priv)) |
37ab0810 SS |
446 | bxt_dsi_device_ready(encoder); |
447 | } | |
448 | ||
449 | static void intel_dsi_port_enable(struct intel_encoder *encoder) | |
450 | { | |
451 | struct drm_device *dev = encoder->base.dev; | |
fac5e23e | 452 | struct drm_i915_private *dev_priv = to_i915(dev); |
37ab0810 SS |
453 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); |
454 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); | |
455 | enum port port; | |
37ab0810 SS |
456 | |
457 | if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) { | |
f0f59a00 VS |
458 | u32 temp; |
459 | ||
37ab0810 SS |
460 | temp = I915_READ(VLV_CHICKEN_3); |
461 | temp &= ~PIXEL_OVERLAP_CNT_MASK | | |
462 | intel_dsi->pixel_overlap << | |
463 | PIXEL_OVERLAP_CNT_SHIFT; | |
464 | I915_WRITE(VLV_CHICKEN_3, temp); | |
465 | } | |
466 | ||
467 | for_each_dsi_port(port, intel_dsi->ports) { | |
cc3f90f0 | 468 | i915_reg_t port_ctrl = IS_GEN9_LP(dev_priv) ? |
f0f59a00 VS |
469 | BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(port); |
470 | u32 temp; | |
37ab0810 SS |
471 | |
472 | temp = I915_READ(port_ctrl); | |
473 | ||
474 | temp &= ~LANE_CONFIGURATION_MASK; | |
475 | temp &= ~DUAL_LINK_MODE_MASK; | |
476 | ||
701d25b4 | 477 | if (intel_dsi->ports == (BIT(PORT_A) | BIT(PORT_C))) { |
37ab0810 SS |
478 | temp |= (intel_dsi->dual_link - 1) |
479 | << DUAL_LINK_MODE_SHIFT; | |
812b1d2f BP |
480 | if (IS_BROXTON(dev_priv)) |
481 | temp |= LANE_CONFIGURATION_DUAL_LINK_A; | |
482 | else | |
483 | temp |= intel_crtc->pipe ? | |
37ab0810 SS |
484 | LANE_CONFIGURATION_DUAL_LINK_B : |
485 | LANE_CONFIGURATION_DUAL_LINK_A; | |
486 | } | |
487 | /* assert ip_tg_enable signal */ | |
488 | I915_WRITE(port_ctrl, temp | DPI_ENABLE); | |
489 | POSTING_READ(port_ctrl); | |
490 | } | |
491 | } | |
492 | ||
493 | static void intel_dsi_port_disable(struct intel_encoder *encoder) | |
494 | { | |
495 | struct drm_device *dev = encoder->base.dev; | |
fac5e23e | 496 | struct drm_i915_private *dev_priv = to_i915(dev); |
37ab0810 SS |
497 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); |
498 | enum port port; | |
37ab0810 SS |
499 | |
500 | for_each_dsi_port(port, intel_dsi->ports) { | |
cc3f90f0 | 501 | i915_reg_t port_ctrl = IS_GEN9_LP(dev_priv) ? |
f0f59a00 VS |
502 | BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(port); |
503 | u32 temp; | |
504 | ||
37ab0810 | 505 | /* de-assert ip_tg_enable signal */ |
b389a45c SS |
506 | temp = I915_READ(port_ctrl); |
507 | I915_WRITE(port_ctrl, temp & ~DPI_ENABLE); | |
508 | POSTING_READ(port_ctrl); | |
37ab0810 SS |
509 | } |
510 | } | |
511 | ||
1dbd7cb2 SK |
512 | static void intel_dsi_enable(struct intel_encoder *encoder) |
513 | { | |
514 | struct drm_device *dev = encoder->base.dev; | |
fac5e23e | 515 | struct drm_i915_private *dev_priv = to_i915(dev); |
1dbd7cb2 | 516 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); |
4934b656 | 517 | enum port port; |
1dbd7cb2 SK |
518 | |
519 | DRM_DEBUG_KMS("\n"); | |
b9f5e07d | 520 | |
4934b656 JN |
521 | if (is_cmd_mode(intel_dsi)) { |
522 | for_each_dsi_port(port, intel_dsi->ports) | |
523 | I915_WRITE(MIPI_MAX_RETURN_PKT_SIZE(port), 8 * 4); | |
524 | } else { | |
4e646495 | 525 | msleep(20); /* XXX */ |
f03e4179 | 526 | for_each_dsi_port(port, intel_dsi->ports) |
a2581a9e | 527 | dpi_send_cmd(intel_dsi, TURN_ON, false, port); |
4e646495 JN |
528 | msleep(100); |
529 | ||
593e0622 | 530 | drm_panel_enable(intel_dsi->panel); |
2634fd7f | 531 | |
7f6a6a4a JN |
532 | for_each_dsi_port(port, intel_dsi->ports) |
533 | wait_for_dsi_fifo_empty(intel_dsi, port); | |
1381308b | 534 | |
5505a244 | 535 | intel_dsi_port_enable(encoder); |
4e646495 | 536 | } |
b029e66f SK |
537 | |
538 | intel_panel_enable_backlight(intel_dsi->attached_connector); | |
2634fd7f SK |
539 | } |
540 | ||
5eff0edf ML |
541 | static void intel_dsi_prepare(struct intel_encoder *intel_encoder, |
542 | struct intel_crtc_state *pipe_config); | |
e3488e75 | 543 | |
fd6bbda9 ML |
544 | static void intel_dsi_pre_enable(struct intel_encoder *encoder, |
545 | struct intel_crtc_state *pipe_config, | |
546 | struct drm_connector_state *conn_state) | |
2634fd7f | 547 | { |
5eff0edf | 548 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
2634fd7f | 549 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); |
7f6a6a4a | 550 | enum port port; |
2634fd7f SK |
551 | |
552 | DRM_DEBUG_KMS("\n"); | |
553 | ||
f00b5689 VS |
554 | /* |
555 | * The BIOS may leave the PLL in a wonky state where it doesn't | |
556 | * lock. It needs to be fully powered down to fix it. | |
557 | */ | |
558 | intel_disable_dsi_pll(encoder); | |
5eff0edf | 559 | intel_enable_dsi_pll(encoder, pipe_config); |
f00b5689 | 560 | |
5eff0edf | 561 | intel_dsi_prepare(encoder, pipe_config); |
e3488e75 | 562 | |
fc45e821 SK |
563 | /* Panel Enable over CRC PMIC */ |
564 | if (intel_dsi->gpio_panel) | |
565 | gpiod_set_value_cansleep(intel_dsi->gpio_panel, 1); | |
566 | ||
567 | msleep(intel_dsi->panel_on_delay); | |
568 | ||
d1877c0f VS |
569 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { |
570 | u32 val; | |
571 | ||
cd2d34d9 | 572 | /* Disable DPOunit clock gating, can stall pipe */ |
d1877c0f VS |
573 | val = I915_READ(DSPCLK_GATE_D); |
574 | val |= DPOUNIT_CLOCK_GATE_DISABLE; | |
575 | I915_WRITE(DSPCLK_GATE_D, val); | |
37ab0810 | 576 | } |
2634fd7f SK |
577 | |
578 | /* put device in ready state */ | |
579 | intel_dsi_device_ready(encoder); | |
4e646495 | 580 | |
593e0622 | 581 | drm_panel_prepare(intel_dsi->panel); |
20e5bf66 | 582 | |
7f6a6a4a JN |
583 | for_each_dsi_port(port, intel_dsi->ports) |
584 | wait_for_dsi_fifo_empty(intel_dsi, port); | |
1381308b | 585 | |
2634fd7f SK |
586 | /* Enable port in pre-enable phase itself because as per hw team |
587 | * recommendation, port should be enabled befor plane & pipe */ | |
588 | intel_dsi_enable(encoder); | |
589 | } | |
590 | ||
fd6bbda9 ML |
591 | static void intel_dsi_enable_nop(struct intel_encoder *encoder, |
592 | struct intel_crtc_state *pipe_config, | |
593 | struct drm_connector_state *conn_state) | |
2634fd7f SK |
594 | { |
595 | DRM_DEBUG_KMS("\n"); | |
596 | ||
597 | /* for DSI port enable has to be done before pipe | |
598 | * and plane enable, so port enable is done in | |
599 | * pre_enable phase itself unlike other encoders | |
600 | */ | |
4e646495 JN |
601 | } |
602 | ||
fd6bbda9 ML |
603 | static void intel_dsi_pre_disable(struct intel_encoder *encoder, |
604 | struct intel_crtc_state *old_crtc_state, | |
605 | struct drm_connector_state *old_conn_state) | |
c315faf8 ID |
606 | { |
607 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); | |
f03e4179 | 608 | enum port port; |
c315faf8 ID |
609 | |
610 | DRM_DEBUG_KMS("\n"); | |
611 | ||
b029e66f SK |
612 | intel_panel_disable_backlight(intel_dsi->attached_connector); |
613 | ||
c315faf8 ID |
614 | if (is_vid_mode(intel_dsi)) { |
615 | /* Send Shutdown command to the panel in LP mode */ | |
f03e4179 | 616 | for_each_dsi_port(port, intel_dsi->ports) |
a2581a9e | 617 | dpi_send_cmd(intel_dsi, SHUTDOWN, false, port); |
c315faf8 ID |
618 | msleep(10); |
619 | } | |
620 | } | |
621 | ||
4e646495 JN |
622 | static void intel_dsi_disable(struct intel_encoder *encoder) |
623 | { | |
1dbd7cb2 | 624 | struct drm_device *dev = encoder->base.dev; |
fac5e23e | 625 | struct drm_i915_private *dev_priv = to_i915(dev); |
4e646495 | 626 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); |
384f02a2 | 627 | enum port port; |
4e646495 JN |
628 | u32 temp; |
629 | ||
630 | DRM_DEBUG_KMS("\n"); | |
631 | ||
4e646495 | 632 | if (is_vid_mode(intel_dsi)) { |
7f6a6a4a JN |
633 | for_each_dsi_port(port, intel_dsi->ports) |
634 | wait_for_dsi_fifo_empty(intel_dsi, port); | |
1381308b | 635 | |
5505a244 | 636 | intel_dsi_port_disable(encoder); |
4e646495 JN |
637 | msleep(2); |
638 | } | |
639 | ||
384f02a2 GS |
640 | for_each_dsi_port(port, intel_dsi->ports) { |
641 | /* Panel commands can be sent when clock is in LP11 */ | |
642 | I915_WRITE(MIPI_DEVICE_READY(port), 0x0); | |
339023ec | 643 | |
b389a45c | 644 | intel_dsi_reset_clocks(encoder, port); |
384f02a2 | 645 | I915_WRITE(MIPI_EOT_DISABLE(port), CLOCKSTOP); |
339023ec | 646 | |
384f02a2 GS |
647 | temp = I915_READ(MIPI_DSI_FUNC_PRG(port)); |
648 | temp &= ~VID_MODE_FORMAT_MASK; | |
649 | I915_WRITE(MIPI_DSI_FUNC_PRG(port), temp); | |
339023ec | 650 | |
384f02a2 GS |
651 | I915_WRITE(MIPI_DEVICE_READY(port), 0x1); |
652 | } | |
1dbd7cb2 SK |
653 | /* if disable packets are sent before sending shutdown packet then in |
654 | * some next enable sequence send turn on packet error is observed */ | |
593e0622 | 655 | drm_panel_disable(intel_dsi->panel); |
1381308b | 656 | |
7f6a6a4a JN |
657 | for_each_dsi_port(port, intel_dsi->ports) |
658 | wait_for_dsi_fifo_empty(intel_dsi, port); | |
4e646495 JN |
659 | } |
660 | ||
1dbd7cb2 | 661 | static void intel_dsi_clear_device_ready(struct intel_encoder *encoder) |
4e646495 | 662 | { |
fac5e23e | 663 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
384f02a2 GS |
664 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); |
665 | enum port port; | |
1dbd7cb2 | 666 | |
4e646495 | 667 | DRM_DEBUG_KMS("\n"); |
384f02a2 | 668 | for_each_dsi_port(port, intel_dsi->ports) { |
f0f59a00 | 669 | /* Common bit for both MIPI Port A & MIPI Port C on VLV/CHV */ |
cc3f90f0 | 670 | i915_reg_t port_ctrl = IS_GEN9_LP(dev_priv) ? |
f0f59a00 VS |
671 | BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(PORT_A); |
672 | u32 val; | |
be4fc046 | 673 | |
384f02a2 GS |
674 | I915_WRITE(MIPI_DEVICE_READY(port), DEVICE_READY | |
675 | ULPS_STATE_ENTER); | |
676 | usleep_range(2000, 2500); | |
677 | ||
678 | I915_WRITE(MIPI_DEVICE_READY(port), DEVICE_READY | | |
679 | ULPS_STATE_EXIT); | |
680 | usleep_range(2000, 2500); | |
681 | ||
682 | I915_WRITE(MIPI_DEVICE_READY(port), DEVICE_READY | | |
683 | ULPS_STATE_ENTER); | |
684 | usleep_range(2000, 2500); | |
685 | ||
686 | /* Wait till Clock lanes are in LP-00 state for MIPI Port A | |
687 | * only. MIPI Port C has no similar bit for checking | |
688 | */ | |
0698cf60 CW |
689 | if (intel_wait_for_register(dev_priv, |
690 | port_ctrl, AFE_LATCHOUT, 0, | |
691 | 30)) | |
384f02a2 GS |
692 | DRM_ERROR("DSI LP not going Low\n"); |
693 | ||
b389a45c SS |
694 | /* Disable MIPI PHY transparent latch */ |
695 | val = I915_READ(port_ctrl); | |
696 | I915_WRITE(port_ctrl, val & ~LP_OUTPUT_HOLD); | |
384f02a2 GS |
697 | usleep_range(1000, 1500); |
698 | ||
699 | I915_WRITE(MIPI_DEVICE_READY(port), 0x00); | |
700 | usleep_range(2000, 2500); | |
701 | } | |
4e646495 | 702 | } |
20e5bf66 | 703 | |
fd6bbda9 ML |
704 | static void intel_dsi_post_disable(struct intel_encoder *encoder, |
705 | struct intel_crtc_state *pipe_config, | |
706 | struct drm_connector_state *conn_state) | |
1dbd7cb2 | 707 | { |
fac5e23e | 708 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
1dbd7cb2 SK |
709 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); |
710 | ||
711 | DRM_DEBUG_KMS("\n"); | |
712 | ||
c315faf8 ID |
713 | intel_dsi_disable(encoder); |
714 | ||
1dbd7cb2 SK |
715 | intel_dsi_clear_device_ready(encoder); |
716 | ||
e840fd31 HG |
717 | intel_disable_dsi_pll(encoder); |
718 | ||
d1877c0f | 719 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { |
d6e3af54 US |
720 | u32 val; |
721 | ||
722 | val = I915_READ(DSPCLK_GATE_D); | |
723 | val &= ~DPOUNIT_CLOCK_GATE_DISABLE; | |
724 | I915_WRITE(DSPCLK_GATE_D, val); | |
725 | } | |
20e5bf66 | 726 | |
593e0622 | 727 | drm_panel_unprepare(intel_dsi->panel); |
df38e655 SK |
728 | |
729 | msleep(intel_dsi->panel_off_delay); | |
fc45e821 SK |
730 | |
731 | /* Panel Disable over CRC PMIC */ | |
732 | if (intel_dsi->gpio_panel) | |
733 | gpiod_set_value_cansleep(intel_dsi->gpio_panel, 0); | |
1d5c65ed VS |
734 | |
735 | /* | |
736 | * FIXME As we do with eDP, just make a note of the time here | |
737 | * and perform the wait before the next panel power on. | |
738 | */ | |
739 | msleep(intel_dsi->panel_pwr_cycle_delay); | |
1dbd7cb2 | 740 | } |
4e646495 JN |
741 | |
742 | static bool intel_dsi_get_hw_state(struct intel_encoder *encoder, | |
743 | enum pipe *pipe) | |
744 | { | |
fac5e23e | 745 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
c0beefd2 | 746 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); |
6d129bea | 747 | enum intel_display_power_domain power_domain; |
e7d7cad0 | 748 | enum port port; |
1dcec2f3 | 749 | bool active = false; |
4e646495 JN |
750 | |
751 | DRM_DEBUG_KMS("\n"); | |
752 | ||
6d129bea | 753 | power_domain = intel_display_port_power_domain(encoder); |
3f3f42b8 | 754 | if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) |
6d129bea ID |
755 | return false; |
756 | ||
db18b6a6 ID |
757 | /* |
758 | * On Broxton the PLL needs to be enabled with a valid divider | |
759 | * configuration, otherwise accessing DSI registers will hang the | |
760 | * machine. See BSpec North Display Engine registers/MIPI[BXT]. | |
761 | */ | |
cc3f90f0 | 762 | if (IS_GEN9_LP(dev_priv) && !intel_dsi_pll_is_enabled(dev_priv)) |
db18b6a6 ID |
763 | goto out_put_power; |
764 | ||
4e646495 | 765 | /* XXX: this only works for one DSI output */ |
c0beefd2 | 766 | for_each_dsi_port(port, intel_dsi->ports) { |
cc3f90f0 | 767 | i915_reg_t ctrl_reg = IS_GEN9_LP(dev_priv) ? |
f0f59a00 | 768 | BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(port); |
1dcec2f3 | 769 | bool enabled = I915_READ(ctrl_reg) & DPI_ENABLE; |
c0beefd2 | 770 | |
e6f57789 JN |
771 | /* |
772 | * Due to some hardware limitations on VLV/CHV, the DPI enable | |
773 | * bit in port C control register does not get set. As a | |
774 | * workaround, check pipe B conf instead. | |
c0beefd2 | 775 | */ |
920a14b2 TU |
776 | if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && |
777 | port == PORT_C) | |
1dcec2f3 | 778 | enabled = I915_READ(PIPECONF(PIPE_B)) & PIPECONF_ENABLE; |
4e646495 | 779 | |
1dcec2f3 JN |
780 | /* Try command mode if video mode not enabled */ |
781 | if (!enabled) { | |
782 | u32 tmp = I915_READ(MIPI_DSI_FUNC_PRG(port)); | |
783 | enabled = tmp & CMD_MODE_DATA_WIDTH_MASK; | |
4e646495 | 784 | } |
1dcec2f3 JN |
785 | |
786 | if (!enabled) | |
787 | continue; | |
788 | ||
789 | if (!(I915_READ(MIPI_DEVICE_READY(port)) & DEVICE_READY)) | |
790 | continue; | |
791 | ||
cc3f90f0 | 792 | if (IS_GEN9_LP(dev_priv)) { |
6b93e9c8 JN |
793 | u32 tmp = I915_READ(MIPI_CTRL(port)); |
794 | tmp &= BXT_PIPE_SELECT_MASK; | |
795 | tmp >>= BXT_PIPE_SELECT_SHIFT; | |
796 | ||
797 | if (WARN_ON(tmp > PIPE_C)) | |
798 | continue; | |
799 | ||
800 | *pipe = tmp; | |
801 | } else { | |
802 | *pipe = port == PORT_A ? PIPE_A : PIPE_B; | |
803 | } | |
804 | ||
1dcec2f3 JN |
805 | active = true; |
806 | break; | |
4e646495 | 807 | } |
1dcec2f3 | 808 | |
db18b6a6 | 809 | out_put_power: |
3f3f42b8 | 810 | intel_display_power_put(dev_priv, power_domain); |
4e646495 | 811 | |
1dcec2f3 | 812 | return active; |
4e646495 JN |
813 | } |
814 | ||
6f0e7535 R |
815 | static void bxt_dsi_get_pipe_config(struct intel_encoder *encoder, |
816 | struct intel_crtc_state *pipe_config) | |
817 | { | |
818 | struct drm_device *dev = encoder->base.dev; | |
fac5e23e | 819 | struct drm_i915_private *dev_priv = to_i915(dev); |
6f0e7535 R |
820 | struct drm_display_mode *adjusted_mode = |
821 | &pipe_config->base.adjusted_mode; | |
042ab0c3 R |
822 | struct drm_display_mode *adjusted_mode_sw; |
823 | struct intel_crtc *intel_crtc; | |
6f0e7535 | 824 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); |
cefc4e18 | 825 | unsigned int lane_count = intel_dsi->lane_count; |
6f0e7535 R |
826 | unsigned int bpp, fmt; |
827 | enum port port; | |
cefc4e18 | 828 | u16 hactive, hfp, hsync, hbp, vfp, vsync, vbp; |
042ab0c3 R |
829 | u16 hfp_sw, hsync_sw, hbp_sw; |
830 | u16 crtc_htotal_sw, crtc_hsync_start_sw, crtc_hsync_end_sw, | |
831 | crtc_hblank_start_sw, crtc_hblank_end_sw; | |
832 | ||
5eff0edf | 833 | /* FIXME: hw readout should not depend on SW state */ |
042ab0c3 R |
834 | intel_crtc = to_intel_crtc(encoder->base.crtc); |
835 | adjusted_mode_sw = &intel_crtc->config->base.adjusted_mode; | |
6f0e7535 R |
836 | |
837 | /* | |
838 | * Atleast one port is active as encoder->get_config called only if | |
839 | * encoder->get_hw_state() returns true. | |
840 | */ | |
841 | for_each_dsi_port(port, intel_dsi->ports) { | |
842 | if (I915_READ(BXT_MIPI_PORT_CTRL(port)) & DPI_ENABLE) | |
843 | break; | |
844 | } | |
845 | ||
846 | fmt = I915_READ(MIPI_DSI_FUNC_PRG(port)) & VID_MODE_FORMAT_MASK; | |
847 | pipe_config->pipe_bpp = | |
848 | mipi_dsi_pixel_format_to_bpp( | |
849 | pixel_format_from_register_bits(fmt)); | |
850 | bpp = pipe_config->pipe_bpp; | |
851 | ||
852 | /* In terms of pixels */ | |
853 | adjusted_mode->crtc_hdisplay = | |
854 | I915_READ(BXT_MIPI_TRANS_HACTIVE(port)); | |
855 | adjusted_mode->crtc_vdisplay = | |
856 | I915_READ(BXT_MIPI_TRANS_VACTIVE(port)); | |
857 | adjusted_mode->crtc_vtotal = | |
858 | I915_READ(BXT_MIPI_TRANS_VTOTAL(port)); | |
859 | ||
cefc4e18 R |
860 | hactive = adjusted_mode->crtc_hdisplay; |
861 | hfp = I915_READ(MIPI_HFP_COUNT(port)); | |
862 | ||
6f0e7535 | 863 | /* |
cefc4e18 R |
864 | * Meaningful for video mode non-burst sync pulse mode only, |
865 | * can be zero for non-burst sync events and burst modes | |
6f0e7535 | 866 | */ |
cefc4e18 R |
867 | hsync = I915_READ(MIPI_HSYNC_PADDING_COUNT(port)); |
868 | hbp = I915_READ(MIPI_HBP_COUNT(port)); | |
869 | ||
870 | /* harizontal values are in terms of high speed byte clock */ | |
871 | hfp = pixels_from_txbyteclkhs(hfp, bpp, lane_count, | |
872 | intel_dsi->burst_mode_ratio); | |
873 | hsync = pixels_from_txbyteclkhs(hsync, bpp, lane_count, | |
874 | intel_dsi->burst_mode_ratio); | |
875 | hbp = pixels_from_txbyteclkhs(hbp, bpp, lane_count, | |
876 | intel_dsi->burst_mode_ratio); | |
877 | ||
878 | if (intel_dsi->dual_link) { | |
879 | hfp *= 2; | |
880 | hsync *= 2; | |
881 | hbp *= 2; | |
882 | } | |
6f0e7535 R |
883 | |
884 | /* vertical values are in terms of lines */ | |
885 | vfp = I915_READ(MIPI_VFP_COUNT(port)); | |
886 | vsync = I915_READ(MIPI_VSYNC_PADDING_COUNT(port)); | |
887 | vbp = I915_READ(MIPI_VBP_COUNT(port)); | |
888 | ||
cefc4e18 R |
889 | adjusted_mode->crtc_htotal = hactive + hfp + hsync + hbp; |
890 | adjusted_mode->crtc_hsync_start = hfp + adjusted_mode->crtc_hdisplay; | |
891 | adjusted_mode->crtc_hsync_end = hsync + adjusted_mode->crtc_hsync_start; | |
6f0e7535 | 892 | adjusted_mode->crtc_hblank_start = adjusted_mode->crtc_hdisplay; |
cefc4e18 | 893 | adjusted_mode->crtc_hblank_end = adjusted_mode->crtc_htotal; |
6f0e7535 | 894 | |
cefc4e18 R |
895 | adjusted_mode->crtc_vsync_start = vfp + adjusted_mode->crtc_vdisplay; |
896 | adjusted_mode->crtc_vsync_end = vsync + adjusted_mode->crtc_vsync_start; | |
6f0e7535 R |
897 | adjusted_mode->crtc_vblank_start = adjusted_mode->crtc_vdisplay; |
898 | adjusted_mode->crtc_vblank_end = adjusted_mode->crtc_vtotal; | |
6f0e7535 | 899 | |
042ab0c3 R |
900 | /* |
901 | * In BXT DSI there is no regs programmed with few horizontal timings | |
902 | * in Pixels but txbyteclkhs.. So retrieval process adds some | |
903 | * ROUND_UP ERRORS in the process of PIXELS<==>txbyteclkhs. | |
904 | * Actually here for the given adjusted_mode, we are calculating the | |
905 | * value programmed to the port and then back to the horizontal timing | |
906 | * param in pixels. This is the expected value, including roundup errors | |
907 | * And if that is same as retrieved value from port, then | |
908 | * (HW state) adjusted_mode's horizontal timings are corrected to | |
909 | * match with SW state to nullify the errors. | |
910 | */ | |
911 | /* Calculating the value programmed to the Port register */ | |
912 | hfp_sw = adjusted_mode_sw->crtc_hsync_start - | |
913 | adjusted_mode_sw->crtc_hdisplay; | |
914 | hsync_sw = adjusted_mode_sw->crtc_hsync_end - | |
915 | adjusted_mode_sw->crtc_hsync_start; | |
916 | hbp_sw = adjusted_mode_sw->crtc_htotal - | |
917 | adjusted_mode_sw->crtc_hsync_end; | |
918 | ||
919 | if (intel_dsi->dual_link) { | |
920 | hfp_sw /= 2; | |
921 | hsync_sw /= 2; | |
922 | hbp_sw /= 2; | |
923 | } | |
924 | ||
925 | hfp_sw = txbyteclkhs(hfp_sw, bpp, lane_count, | |
926 | intel_dsi->burst_mode_ratio); | |
927 | hsync_sw = txbyteclkhs(hsync_sw, bpp, lane_count, | |
928 | intel_dsi->burst_mode_ratio); | |
929 | hbp_sw = txbyteclkhs(hbp_sw, bpp, lane_count, | |
930 | intel_dsi->burst_mode_ratio); | |
931 | ||
932 | /* Reverse calculating the adjusted mode parameters from port reg vals*/ | |
933 | hfp_sw = pixels_from_txbyteclkhs(hfp_sw, bpp, lane_count, | |
934 | intel_dsi->burst_mode_ratio); | |
935 | hsync_sw = pixels_from_txbyteclkhs(hsync_sw, bpp, lane_count, | |
936 | intel_dsi->burst_mode_ratio); | |
937 | hbp_sw = pixels_from_txbyteclkhs(hbp_sw, bpp, lane_count, | |
938 | intel_dsi->burst_mode_ratio); | |
939 | ||
940 | if (intel_dsi->dual_link) { | |
941 | hfp_sw *= 2; | |
942 | hsync_sw *= 2; | |
943 | hbp_sw *= 2; | |
944 | } | |
945 | ||
946 | crtc_htotal_sw = adjusted_mode_sw->crtc_hdisplay + hfp_sw + | |
947 | hsync_sw + hbp_sw; | |
948 | crtc_hsync_start_sw = hfp_sw + adjusted_mode_sw->crtc_hdisplay; | |
949 | crtc_hsync_end_sw = hsync_sw + crtc_hsync_start_sw; | |
950 | crtc_hblank_start_sw = adjusted_mode_sw->crtc_hdisplay; | |
951 | crtc_hblank_end_sw = crtc_htotal_sw; | |
952 | ||
953 | if (adjusted_mode->crtc_htotal == crtc_htotal_sw) | |
954 | adjusted_mode->crtc_htotal = adjusted_mode_sw->crtc_htotal; | |
955 | ||
956 | if (adjusted_mode->crtc_hsync_start == crtc_hsync_start_sw) | |
957 | adjusted_mode->crtc_hsync_start = | |
958 | adjusted_mode_sw->crtc_hsync_start; | |
959 | ||
960 | if (adjusted_mode->crtc_hsync_end == crtc_hsync_end_sw) | |
961 | adjusted_mode->crtc_hsync_end = | |
962 | adjusted_mode_sw->crtc_hsync_end; | |
963 | ||
964 | if (adjusted_mode->crtc_hblank_start == crtc_hblank_start_sw) | |
965 | adjusted_mode->crtc_hblank_start = | |
966 | adjusted_mode_sw->crtc_hblank_start; | |
967 | ||
968 | if (adjusted_mode->crtc_hblank_end == crtc_hblank_end_sw) | |
969 | adjusted_mode->crtc_hblank_end = | |
970 | adjusted_mode_sw->crtc_hblank_end; | |
971 | } | |
6f0e7535 | 972 | |
4e646495 | 973 | static void intel_dsi_get_config(struct intel_encoder *encoder, |
5cec258b | 974 | struct intel_crtc_state *pipe_config) |
4e646495 | 975 | { |
e2d214ae | 976 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
d7d85d85 | 977 | u32 pclk; |
4e646495 JN |
978 | DRM_DEBUG_KMS("\n"); |
979 | ||
cc3f90f0 | 980 | if (IS_GEN9_LP(dev_priv)) |
6f0e7535 R |
981 | bxt_dsi_get_pipe_config(encoder, pipe_config); |
982 | ||
47eacbab VS |
983 | pclk = intel_dsi_get_pclk(encoder, pipe_config->pipe_bpp, |
984 | pipe_config); | |
f573de5a SK |
985 | if (!pclk) |
986 | return; | |
987 | ||
2d112de7 | 988 | pipe_config->base.adjusted_mode.crtc_clock = pclk; |
f573de5a | 989 | pipe_config->port_clock = pclk; |
4e646495 JN |
990 | } |
991 | ||
c19de8eb DL |
992 | static enum drm_mode_status |
993 | intel_dsi_mode_valid(struct drm_connector *connector, | |
994 | struct drm_display_mode *mode) | |
4e646495 JN |
995 | { |
996 | struct intel_connector *intel_connector = to_intel_connector(connector); | |
f4ee265f | 997 | const struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode; |
759a1e98 | 998 | int max_dotclk = to_i915(connector->dev)->max_dotclk_freq; |
4e646495 JN |
999 | |
1000 | DRM_DEBUG_KMS("\n"); | |
1001 | ||
1002 | if (mode->flags & DRM_MODE_FLAG_DBLSCAN) { | |
1003 | DRM_DEBUG_KMS("MODE_NO_DBLESCAN\n"); | |
1004 | return MODE_NO_DBLESCAN; | |
1005 | } | |
1006 | ||
1007 | if (fixed_mode) { | |
1008 | if (mode->hdisplay > fixed_mode->hdisplay) | |
1009 | return MODE_PANEL; | |
1010 | if (mode->vdisplay > fixed_mode->vdisplay) | |
1011 | return MODE_PANEL; | |
759a1e98 MK |
1012 | if (fixed_mode->clock > max_dotclk) |
1013 | return MODE_CLOCK_HIGH; | |
4e646495 JN |
1014 | } |
1015 | ||
36d21f4c | 1016 | return MODE_OK; |
4e646495 JN |
1017 | } |
1018 | ||
1019 | /* return txclkesc cycles in terms of divider and duration in us */ | |
1020 | static u16 txclkesc(u32 divider, unsigned int us) | |
1021 | { | |
1022 | switch (divider) { | |
1023 | case ESCAPE_CLOCK_DIVIDER_1: | |
1024 | default: | |
1025 | return 20 * us; | |
1026 | case ESCAPE_CLOCK_DIVIDER_2: | |
1027 | return 10 * us; | |
1028 | case ESCAPE_CLOCK_DIVIDER_4: | |
1029 | return 5 * us; | |
1030 | } | |
1031 | } | |
1032 | ||
4e646495 | 1033 | static void set_dsi_timings(struct drm_encoder *encoder, |
5e7234c9 | 1034 | const struct drm_display_mode *adjusted_mode) |
4e646495 JN |
1035 | { |
1036 | struct drm_device *dev = encoder->dev; | |
fac5e23e | 1037 | struct drm_i915_private *dev_priv = to_i915(dev); |
4e646495 | 1038 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); |
aa102d28 | 1039 | enum port port; |
1e78aa01 | 1040 | unsigned int bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format); |
4e646495 JN |
1041 | unsigned int lane_count = intel_dsi->lane_count; |
1042 | ||
1043 | u16 hactive, hfp, hsync, hbp, vfp, vsync, vbp; | |
1044 | ||
aad941d5 VS |
1045 | hactive = adjusted_mode->crtc_hdisplay; |
1046 | hfp = adjusted_mode->crtc_hsync_start - adjusted_mode->crtc_hdisplay; | |
1047 | hsync = adjusted_mode->crtc_hsync_end - adjusted_mode->crtc_hsync_start; | |
1048 | hbp = adjusted_mode->crtc_htotal - adjusted_mode->crtc_hsync_end; | |
4e646495 | 1049 | |
aa102d28 GS |
1050 | if (intel_dsi->dual_link) { |
1051 | hactive /= 2; | |
1052 | if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) | |
1053 | hactive += intel_dsi->pixel_overlap; | |
1054 | hfp /= 2; | |
1055 | hsync /= 2; | |
1056 | hbp /= 2; | |
1057 | } | |
1058 | ||
aad941d5 VS |
1059 | vfp = adjusted_mode->crtc_vsync_start - adjusted_mode->crtc_vdisplay; |
1060 | vsync = adjusted_mode->crtc_vsync_end - adjusted_mode->crtc_vsync_start; | |
1061 | vbp = adjusted_mode->crtc_vtotal - adjusted_mode->crtc_vsync_end; | |
4e646495 JN |
1062 | |
1063 | /* horizontal values are in terms of high speed byte clock */ | |
7f0c8605 | 1064 | hactive = txbyteclkhs(hactive, bpp, lane_count, |
7f3de833 | 1065 | intel_dsi->burst_mode_ratio); |
7f0c8605 SK |
1066 | hfp = txbyteclkhs(hfp, bpp, lane_count, intel_dsi->burst_mode_ratio); |
1067 | hsync = txbyteclkhs(hsync, bpp, lane_count, | |
7f3de833 | 1068 | intel_dsi->burst_mode_ratio); |
7f0c8605 | 1069 | hbp = txbyteclkhs(hbp, bpp, lane_count, intel_dsi->burst_mode_ratio); |
4e646495 | 1070 | |
aa102d28 | 1071 | for_each_dsi_port(port, intel_dsi->ports) { |
cc3f90f0 | 1072 | if (IS_GEN9_LP(dev_priv)) { |
d2e08c0f SS |
1073 | /* |
1074 | * Program hdisplay and vdisplay on MIPI transcoder. | |
1075 | * This is different from calculated hactive and | |
1076 | * vactive, as they are calculated per channel basis, | |
1077 | * whereas these values should be based on resolution. | |
1078 | */ | |
1079 | I915_WRITE(BXT_MIPI_TRANS_HACTIVE(port), | |
aad941d5 | 1080 | adjusted_mode->crtc_hdisplay); |
d2e08c0f | 1081 | I915_WRITE(BXT_MIPI_TRANS_VACTIVE(port), |
aad941d5 | 1082 | adjusted_mode->crtc_vdisplay); |
d2e08c0f | 1083 | I915_WRITE(BXT_MIPI_TRANS_VTOTAL(port), |
aad941d5 | 1084 | adjusted_mode->crtc_vtotal); |
d2e08c0f SS |
1085 | } |
1086 | ||
aa102d28 GS |
1087 | I915_WRITE(MIPI_HACTIVE_AREA_COUNT(port), hactive); |
1088 | I915_WRITE(MIPI_HFP_COUNT(port), hfp); | |
1089 | ||
1090 | /* meaningful for video mode non-burst sync pulse mode only, | |
1091 | * can be zero for non-burst sync events and burst modes */ | |
1092 | I915_WRITE(MIPI_HSYNC_PADDING_COUNT(port), hsync); | |
1093 | I915_WRITE(MIPI_HBP_COUNT(port), hbp); | |
1094 | ||
1095 | /* vertical values are in terms of lines */ | |
1096 | I915_WRITE(MIPI_VFP_COUNT(port), vfp); | |
1097 | I915_WRITE(MIPI_VSYNC_PADDING_COUNT(port), vsync); | |
1098 | I915_WRITE(MIPI_VBP_COUNT(port), vbp); | |
1099 | } | |
4e646495 JN |
1100 | } |
1101 | ||
1e78aa01 JN |
1102 | static u32 pixel_format_to_reg(enum mipi_dsi_pixel_format fmt) |
1103 | { | |
1104 | switch (fmt) { | |
1105 | case MIPI_DSI_FMT_RGB888: | |
1106 | return VID_MODE_FORMAT_RGB888; | |
1107 | case MIPI_DSI_FMT_RGB666: | |
1108 | return VID_MODE_FORMAT_RGB666; | |
1109 | case MIPI_DSI_FMT_RGB666_PACKED: | |
1110 | return VID_MODE_FORMAT_RGB666_PACKED; | |
1111 | case MIPI_DSI_FMT_RGB565: | |
1112 | return VID_MODE_FORMAT_RGB565; | |
1113 | default: | |
1114 | MISSING_CASE(fmt); | |
1115 | return VID_MODE_FORMAT_RGB666; | |
1116 | } | |
1117 | } | |
1118 | ||
5eff0edf ML |
1119 | static void intel_dsi_prepare(struct intel_encoder *intel_encoder, |
1120 | struct intel_crtc_state *pipe_config) | |
4e646495 JN |
1121 | { |
1122 | struct drm_encoder *encoder = &intel_encoder->base; | |
1123 | struct drm_device *dev = encoder->dev; | |
fac5e23e | 1124 | struct drm_i915_private *dev_priv = to_i915(dev); |
5eff0edf | 1125 | struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc); |
4e646495 | 1126 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); |
5eff0edf | 1127 | const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; |
24ee0e64 | 1128 | enum port port; |
1e78aa01 | 1129 | unsigned int bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format); |
4e646495 | 1130 | u32 val, tmp; |
24ee0e64 | 1131 | u16 mode_hdisplay; |
4e646495 | 1132 | |
e7d7cad0 | 1133 | DRM_DEBUG_KMS("pipe %c\n", pipe_name(intel_crtc->pipe)); |
4e646495 | 1134 | |
aad941d5 | 1135 | mode_hdisplay = adjusted_mode->crtc_hdisplay; |
4e646495 | 1136 | |
24ee0e64 GS |
1137 | if (intel_dsi->dual_link) { |
1138 | mode_hdisplay /= 2; | |
1139 | if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) | |
1140 | mode_hdisplay += intel_dsi->pixel_overlap; | |
1141 | } | |
4e646495 | 1142 | |
24ee0e64 | 1143 | for_each_dsi_port(port, intel_dsi->ports) { |
920a14b2 | 1144 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { |
d2e08c0f SS |
1145 | /* |
1146 | * escape clock divider, 20MHz, shared for A and C. | |
1147 | * device ready must be off when doing this! txclkesc? | |
1148 | */ | |
1149 | tmp = I915_READ(MIPI_CTRL(PORT_A)); | |
1150 | tmp &= ~ESCAPE_CLOCK_DIVIDER_MASK; | |
1151 | I915_WRITE(MIPI_CTRL(PORT_A), tmp | | |
1152 | ESCAPE_CLOCK_DIVIDER_1); | |
1153 | ||
1154 | /* read request priority is per pipe */ | |
1155 | tmp = I915_READ(MIPI_CTRL(port)); | |
1156 | tmp &= ~READ_REQUEST_PRIORITY_MASK; | |
1157 | I915_WRITE(MIPI_CTRL(port), tmp | | |
1158 | READ_REQUEST_PRIORITY_HIGH); | |
cc3f90f0 | 1159 | } else if (IS_GEN9_LP(dev_priv)) { |
56c48978 D |
1160 | enum pipe pipe = intel_crtc->pipe; |
1161 | ||
d2e08c0f SS |
1162 | tmp = I915_READ(MIPI_CTRL(port)); |
1163 | tmp &= ~BXT_PIPE_SELECT_MASK; | |
1164 | ||
56c48978 | 1165 | tmp |= BXT_PIPE_SELECT(pipe); |
d2e08c0f SS |
1166 | I915_WRITE(MIPI_CTRL(port), tmp); |
1167 | } | |
24ee0e64 GS |
1168 | |
1169 | /* XXX: why here, why like this? handling in irq handler?! */ | |
1170 | I915_WRITE(MIPI_INTR_STAT(port), 0xffffffff); | |
1171 | I915_WRITE(MIPI_INTR_EN(port), 0xffffffff); | |
1172 | ||
1173 | I915_WRITE(MIPI_DPHY_PARAM(port), intel_dsi->dphy_reg); | |
1174 | ||
1175 | I915_WRITE(MIPI_DPI_RESOLUTION(port), | |
aad941d5 | 1176 | adjusted_mode->crtc_vdisplay << VERTICAL_ADDRESS_SHIFT | |
24ee0e64 GS |
1177 | mode_hdisplay << HORIZONTAL_ADDRESS_SHIFT); |
1178 | } | |
4e646495 JN |
1179 | |
1180 | set_dsi_timings(encoder, adjusted_mode); | |
1181 | ||
1182 | val = intel_dsi->lane_count << DATA_LANES_PRG_REG_SHIFT; | |
1183 | if (is_cmd_mode(intel_dsi)) { | |
1184 | val |= intel_dsi->channel << CMD_MODE_CHANNEL_NUMBER_SHIFT; | |
1185 | val |= CMD_MODE_DATA_WIDTH_8_BIT; /* XXX */ | |
1186 | } else { | |
1187 | val |= intel_dsi->channel << VID_MODE_CHANNEL_NUMBER_SHIFT; | |
1e78aa01 | 1188 | val |= pixel_format_to_reg(intel_dsi->pixel_format); |
4e646495 | 1189 | } |
4e646495 | 1190 | |
24ee0e64 GS |
1191 | tmp = 0; |
1192 | if (intel_dsi->eotp_pkt == 0) | |
1193 | tmp |= EOT_DISABLE; | |
1194 | if (intel_dsi->clock_stop) | |
1195 | tmp |= CLOCKSTOP; | |
4e646495 | 1196 | |
cc3f90f0 | 1197 | if (IS_GEN9_LP(dev_priv)) { |
f90e8c36 JN |
1198 | tmp |= BXT_DPHY_DEFEATURE_EN; |
1199 | if (!is_cmd_mode(intel_dsi)) | |
1200 | tmp |= BXT_DEFEATURE_DPI_FIFO_CTR; | |
1201 | } | |
1202 | ||
24ee0e64 GS |
1203 | for_each_dsi_port(port, intel_dsi->ports) { |
1204 | I915_WRITE(MIPI_DSI_FUNC_PRG(port), val); | |
1205 | ||
1206 | /* timeouts for recovery. one frame IIUC. if counter expires, | |
1207 | * EOT and stop state. */ | |
1208 | ||
1209 | /* | |
1210 | * In burst mode, value greater than one DPI line Time in byte | |
1211 | * clock (txbyteclkhs) To timeout this timer 1+ of the above | |
1212 | * said value is recommended. | |
1213 | * | |
1214 | * In non-burst mode, Value greater than one DPI frame time in | |
1215 | * byte clock(txbyteclkhs) To timeout this timer 1+ of the above | |
1216 | * said value is recommended. | |
1217 | * | |
1218 | * In DBI only mode, value greater than one DBI frame time in | |
1219 | * byte clock(txbyteclkhs) To timeout this timer 1+ of the above | |
1220 | * said value is recommended. | |
1221 | */ | |
4e646495 | 1222 | |
24ee0e64 GS |
1223 | if (is_vid_mode(intel_dsi) && |
1224 | intel_dsi->video_mode_format == VIDEO_MODE_BURST) { | |
1225 | I915_WRITE(MIPI_HS_TX_TIMEOUT(port), | |
aad941d5 | 1226 | txbyteclkhs(adjusted_mode->crtc_htotal, bpp, |
124abe07 VS |
1227 | intel_dsi->lane_count, |
1228 | intel_dsi->burst_mode_ratio) + 1); | |
24ee0e64 GS |
1229 | } else { |
1230 | I915_WRITE(MIPI_HS_TX_TIMEOUT(port), | |
aad941d5 VS |
1231 | txbyteclkhs(adjusted_mode->crtc_vtotal * |
1232 | adjusted_mode->crtc_htotal, | |
124abe07 VS |
1233 | bpp, intel_dsi->lane_count, |
1234 | intel_dsi->burst_mode_ratio) + 1); | |
24ee0e64 GS |
1235 | } |
1236 | I915_WRITE(MIPI_LP_RX_TIMEOUT(port), intel_dsi->lp_rx_timeout); | |
1237 | I915_WRITE(MIPI_TURN_AROUND_TIMEOUT(port), | |
1238 | intel_dsi->turn_arnd_val); | |
1239 | I915_WRITE(MIPI_DEVICE_RESET_TIMER(port), | |
1240 | intel_dsi->rst_timer_val); | |
f1c79f16 | 1241 | |
24ee0e64 | 1242 | /* dphy stuff */ |
f1c79f16 | 1243 | |
24ee0e64 GS |
1244 | /* in terms of low power clock */ |
1245 | I915_WRITE(MIPI_INIT_COUNT(port), | |
1246 | txclkesc(intel_dsi->escape_clk_div, 100)); | |
4e646495 | 1247 | |
cc3f90f0 | 1248 | if (IS_GEN9_LP(dev_priv) && (!intel_dsi->dual_link)) { |
d2e08c0f SS |
1249 | /* |
1250 | * BXT spec says write MIPI_INIT_COUNT for | |
1251 | * both the ports, even if only one is | |
1252 | * getting used. So write the other port | |
1253 | * if not in dual link mode. | |
1254 | */ | |
1255 | I915_WRITE(MIPI_INIT_COUNT(port == | |
1256 | PORT_A ? PORT_C : PORT_A), | |
1257 | intel_dsi->init_count); | |
1258 | } | |
4e646495 | 1259 | |
24ee0e64 | 1260 | /* recovery disables */ |
87c54d0e | 1261 | I915_WRITE(MIPI_EOT_DISABLE(port), tmp); |
cf4dbd2e | 1262 | |
24ee0e64 GS |
1263 | /* in terms of low power clock */ |
1264 | I915_WRITE(MIPI_INIT_COUNT(port), intel_dsi->init_count); | |
4e646495 | 1265 | |
24ee0e64 GS |
1266 | /* in terms of txbyteclkhs. actual high to low switch + |
1267 | * MIPI_STOP_STATE_STALL * MIPI_LP_BYTECLK. | |
1268 | * | |
1269 | * XXX: write MIPI_STOP_STATE_STALL? | |
1270 | */ | |
1271 | I915_WRITE(MIPI_HIGH_LOW_SWITCH_COUNT(port), | |
1272 | intel_dsi->hs_to_lp_count); | |
1273 | ||
1274 | /* XXX: low power clock equivalence in terms of byte clock. | |
1275 | * the number of byte clocks occupied in one low power clock. | |
1276 | * based on txbyteclkhs and txclkesc. | |
1277 | * txclkesc time / txbyteclk time * (105 + MIPI_STOP_STATE_STALL | |
1278 | * ) / 105.??? | |
1279 | */ | |
1280 | I915_WRITE(MIPI_LP_BYTECLK(port), intel_dsi->lp_byte_clk); | |
1281 | ||
1282 | /* the bw essential for transmitting 16 long packets containing | |
1283 | * 252 bytes meant for dcs write memory command is programmed in | |
1284 | * this register in terms of byte clocks. based on dsi transfer | |
1285 | * rate and the number of lanes configured the time taken to | |
1286 | * transmit 16 long packets in a dsi stream varies. */ | |
1287 | I915_WRITE(MIPI_DBI_BW_CTRL(port), intel_dsi->bw_timer); | |
1288 | ||
1289 | I915_WRITE(MIPI_CLK_LANE_SWITCH_TIME_CNT(port), | |
1290 | intel_dsi->clk_lp_to_hs_count << LP_HS_SSW_CNT_SHIFT | | |
1291 | intel_dsi->clk_hs_to_lp_count << HS_LP_PWR_SW_CNT_SHIFT); | |
1292 | ||
1293 | if (is_vid_mode(intel_dsi)) | |
1294 | /* Some panels might have resolution which is not a | |
1295 | * multiple of 64 like 1366 x 768. Enable RANDOM | |
1296 | * resolution support for such panels by default */ | |
1297 | I915_WRITE(MIPI_VIDEO_MODE_FORMAT(port), | |
1298 | intel_dsi->video_frmt_cfg_bits | | |
1299 | intel_dsi->video_mode_format | | |
1300 | IP_TG_CONFIG | | |
1301 | RANDOM_DPI_DISPLAY_RESOLUTION); | |
1302 | } | |
4e646495 JN |
1303 | } |
1304 | ||
4e646495 JN |
1305 | static int intel_dsi_get_modes(struct drm_connector *connector) |
1306 | { | |
1307 | struct intel_connector *intel_connector = to_intel_connector(connector); | |
1308 | struct drm_display_mode *mode; | |
1309 | ||
1310 | DRM_DEBUG_KMS("\n"); | |
1311 | ||
1312 | if (!intel_connector->panel.fixed_mode) { | |
1313 | DRM_DEBUG_KMS("no fixed mode\n"); | |
1314 | return 0; | |
1315 | } | |
1316 | ||
1317 | mode = drm_mode_duplicate(connector->dev, | |
1318 | intel_connector->panel.fixed_mode); | |
1319 | if (!mode) { | |
1320 | DRM_DEBUG_KMS("drm_mode_duplicate failed\n"); | |
1321 | return 0; | |
1322 | } | |
1323 | ||
1324 | drm_mode_probed_add(connector, mode); | |
1325 | return 1; | |
1326 | } | |
1327 | ||
f4ee265f VS |
1328 | static int intel_dsi_set_property(struct drm_connector *connector, |
1329 | struct drm_property *property, | |
1330 | uint64_t val) | |
1331 | { | |
1332 | struct drm_device *dev = connector->dev; | |
1333 | struct intel_connector *intel_connector = to_intel_connector(connector); | |
1334 | struct drm_crtc *crtc; | |
1335 | int ret; | |
1336 | ||
1337 | ret = drm_object_property_set_value(&connector->base, property, val); | |
1338 | if (ret) | |
1339 | return ret; | |
1340 | ||
1341 | if (property == dev->mode_config.scaling_mode_property) { | |
1342 | if (val == DRM_MODE_SCALE_NONE) { | |
1343 | DRM_DEBUG_KMS("no scaling not supported\n"); | |
1344 | return -EINVAL; | |
1345 | } | |
49cff963 | 1346 | if (HAS_GMCH_DISPLAY(to_i915(dev)) && |
234126c6 VS |
1347 | val == DRM_MODE_SCALE_CENTER) { |
1348 | DRM_DEBUG_KMS("centering not supported\n"); | |
1349 | return -EINVAL; | |
1350 | } | |
f4ee265f VS |
1351 | |
1352 | if (intel_connector->panel.fitting_mode == val) | |
1353 | return 0; | |
1354 | ||
1355 | intel_connector->panel.fitting_mode = val; | |
1356 | } | |
1357 | ||
5eff0edf | 1358 | crtc = connector->state->crtc; |
f4ee265f VS |
1359 | if (crtc && crtc->state->enable) { |
1360 | /* | |
1361 | * If the CRTC is enabled, the display will be changed | |
1362 | * according to the new panel fitting mode. | |
1363 | */ | |
1364 | intel_crtc_restore_mode(crtc); | |
1365 | } | |
1366 | ||
1367 | return 0; | |
1368 | } | |
1369 | ||
593e0622 | 1370 | static void intel_dsi_connector_destroy(struct drm_connector *connector) |
4e646495 JN |
1371 | { |
1372 | struct intel_connector *intel_connector = to_intel_connector(connector); | |
1373 | ||
1374 | DRM_DEBUG_KMS("\n"); | |
1375 | intel_panel_fini(&intel_connector->panel); | |
4e646495 JN |
1376 | drm_connector_cleanup(connector); |
1377 | kfree(connector); | |
1378 | } | |
1379 | ||
593e0622 JN |
1380 | static void intel_dsi_encoder_destroy(struct drm_encoder *encoder) |
1381 | { | |
1382 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); | |
1383 | ||
1384 | if (intel_dsi->panel) { | |
1385 | drm_panel_detach(intel_dsi->panel); | |
1386 | /* XXX: Logically this call belongs in the panel driver. */ | |
1387 | drm_panel_remove(intel_dsi->panel); | |
1388 | } | |
fc45e821 SK |
1389 | |
1390 | /* dispose of the gpios */ | |
1391 | if (intel_dsi->gpio_panel) | |
1392 | gpiod_put(intel_dsi->gpio_panel); | |
1393 | ||
593e0622 JN |
1394 | intel_encoder_destroy(encoder); |
1395 | } | |
1396 | ||
4e646495 | 1397 | static const struct drm_encoder_funcs intel_dsi_funcs = { |
593e0622 | 1398 | .destroy = intel_dsi_encoder_destroy, |
4e646495 JN |
1399 | }; |
1400 | ||
1401 | static const struct drm_connector_helper_funcs intel_dsi_connector_helper_funcs = { | |
1402 | .get_modes = intel_dsi_get_modes, | |
1403 | .mode_valid = intel_dsi_mode_valid, | |
4e646495 JN |
1404 | }; |
1405 | ||
1406 | static const struct drm_connector_funcs intel_dsi_connector_funcs = { | |
4d688a2a | 1407 | .dpms = drm_atomic_helper_connector_dpms, |
1ebaa0b9 | 1408 | .late_register = intel_connector_register, |
c191eca1 | 1409 | .early_unregister = intel_connector_unregister, |
593e0622 | 1410 | .destroy = intel_dsi_connector_destroy, |
4e646495 | 1411 | .fill_modes = drm_helper_probe_single_connector_modes, |
f4ee265f | 1412 | .set_property = intel_dsi_set_property, |
2545e4a6 | 1413 | .atomic_get_property = intel_connector_atomic_get_property, |
c6f95f27 | 1414 | .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, |
98969725 | 1415 | .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, |
4e646495 JN |
1416 | }; |
1417 | ||
f4ee265f VS |
1418 | static void intel_dsi_add_properties(struct intel_connector *connector) |
1419 | { | |
1420 | struct drm_device *dev = connector->base.dev; | |
1421 | ||
1422 | if (connector->panel.fixed_mode) { | |
1423 | drm_mode_create_scaling_mode_property(dev); | |
1424 | drm_object_attach_property(&connector->base.base, | |
1425 | dev->mode_config.scaling_mode_property, | |
1426 | DRM_MODE_SCALE_ASPECT); | |
1427 | connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT; | |
1428 | } | |
1429 | } | |
1430 | ||
c39055b0 | 1431 | void intel_dsi_init(struct drm_i915_private *dev_priv) |
4e646495 | 1432 | { |
c39055b0 | 1433 | struct drm_device *dev = &dev_priv->drm; |
4e646495 JN |
1434 | struct intel_dsi *intel_dsi; |
1435 | struct intel_encoder *intel_encoder; | |
1436 | struct drm_encoder *encoder; | |
1437 | struct intel_connector *intel_connector; | |
1438 | struct drm_connector *connector; | |
593e0622 | 1439 | struct drm_display_mode *scan, *fixed_mode = NULL; |
7e9804fd | 1440 | enum port port; |
4e646495 JN |
1441 | unsigned int i; |
1442 | ||
1443 | DRM_DEBUG_KMS("\n"); | |
1444 | ||
3e6bd011 | 1445 | /* There is no detection method for MIPI so rely on VBT */ |
7137aec1 | 1446 | if (!intel_bios_is_dsi_present(dev_priv, &port)) |
4328633d | 1447 | return; |
3e6bd011 | 1448 | |
920a14b2 | 1449 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { |
868d665b | 1450 | dev_priv->mipi_mmio_base = VLV_MIPI_BASE; |
cc3f90f0 | 1451 | } else if (IS_GEN9_LP(dev_priv)) { |
c6c794a2 | 1452 | dev_priv->mipi_mmio_base = BXT_MIPI_BASE; |
868d665b CJ |
1453 | } else { |
1454 | DRM_ERROR("Unsupported Mipi device to reg base"); | |
1455 | return; | |
1456 | } | |
3e6bd011 | 1457 | |
4e646495 JN |
1458 | intel_dsi = kzalloc(sizeof(*intel_dsi), GFP_KERNEL); |
1459 | if (!intel_dsi) | |
4328633d | 1460 | return; |
4e646495 | 1461 | |
08d9bc92 | 1462 | intel_connector = intel_connector_alloc(); |
4e646495 JN |
1463 | if (!intel_connector) { |
1464 | kfree(intel_dsi); | |
4328633d | 1465 | return; |
4e646495 JN |
1466 | } |
1467 | ||
1468 | intel_encoder = &intel_dsi->base; | |
1469 | encoder = &intel_encoder->base; | |
1470 | intel_dsi->attached_connector = intel_connector; | |
1471 | ||
1472 | connector = &intel_connector->base; | |
1473 | ||
13a3d91f | 1474 | drm_encoder_init(dev, encoder, &intel_dsi_funcs, DRM_MODE_ENCODER_DSI, |
580d8ed5 | 1475 | "DSI %c", port_name(port)); |
4e646495 | 1476 | |
4e646495 | 1477 | intel_encoder->compute_config = intel_dsi_compute_config; |
4e646495 | 1478 | intel_encoder->pre_enable = intel_dsi_pre_enable; |
2634fd7f | 1479 | intel_encoder->enable = intel_dsi_enable_nop; |
c315faf8 | 1480 | intel_encoder->disable = intel_dsi_pre_disable; |
4e646495 JN |
1481 | intel_encoder->post_disable = intel_dsi_post_disable; |
1482 | intel_encoder->get_hw_state = intel_dsi_get_hw_state; | |
1483 | intel_encoder->get_config = intel_dsi_get_config; | |
1484 | ||
1485 | intel_connector->get_hw_state = intel_connector_get_hw_state; | |
1486 | ||
03cdc1d4 | 1487 | intel_encoder->port = port; |
2e85ab4f JN |
1488 | /* |
1489 | * On BYT/CHV, pipe A maps to MIPI DSI port A, pipe B maps to MIPI DSI | |
1490 | * port C. BXT isn't limited like this. | |
1491 | */ | |
cc3f90f0 | 1492 | if (IS_GEN9_LP(dev_priv)) |
2e85ab4f JN |
1493 | intel_encoder->crtc_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C); |
1494 | else if (port == PORT_A) | |
701d25b4 | 1495 | intel_encoder->crtc_mask = BIT(PIPE_A); |
7137aec1 | 1496 | else |
701d25b4 | 1497 | intel_encoder->crtc_mask = BIT(PIPE_B); |
e7d7cad0 | 1498 | |
90198355 | 1499 | if (dev_priv->vbt.dsi.config->dual_link) { |
701d25b4 | 1500 | intel_dsi->ports = BIT(PORT_A) | BIT(PORT_C); |
90198355 JN |
1501 | |
1502 | switch (dev_priv->vbt.dsi.config->dl_dcs_backlight_ports) { | |
1503 | case DL_DCS_PORT_A: | |
1504 | intel_dsi->dcs_backlight_ports = BIT(PORT_A); | |
1505 | break; | |
1506 | case DL_DCS_PORT_C: | |
1507 | intel_dsi->dcs_backlight_ports = BIT(PORT_C); | |
1508 | break; | |
1509 | default: | |
1510 | case DL_DCS_PORT_A_AND_C: | |
1511 | intel_dsi->dcs_backlight_ports = BIT(PORT_A) | BIT(PORT_C); | |
1512 | break; | |
1513 | } | |
1ecc1c6c D |
1514 | |
1515 | switch (dev_priv->vbt.dsi.config->dl_dcs_cabc_ports) { | |
1516 | case DL_DCS_PORT_A: | |
1517 | intel_dsi->dcs_cabc_ports = BIT(PORT_A); | |
1518 | break; | |
1519 | case DL_DCS_PORT_C: | |
1520 | intel_dsi->dcs_cabc_ports = BIT(PORT_C); | |
1521 | break; | |
1522 | default: | |
1523 | case DL_DCS_PORT_A_AND_C: | |
1524 | intel_dsi->dcs_cabc_ports = BIT(PORT_A) | BIT(PORT_C); | |
1525 | break; | |
1526 | } | |
90198355 | 1527 | } else { |
701d25b4 | 1528 | intel_dsi->ports = BIT(port); |
90198355 | 1529 | intel_dsi->dcs_backlight_ports = BIT(port); |
1ecc1c6c | 1530 | intel_dsi->dcs_cabc_ports = BIT(port); |
90198355 | 1531 | } |
82425785 | 1532 | |
1ecc1c6c D |
1533 | if (!dev_priv->vbt.dsi.config->cabc_supported) |
1534 | intel_dsi->dcs_cabc_ports = 0; | |
1535 | ||
7e9804fd JN |
1536 | /* Create a DSI host (and a device) for each port. */ |
1537 | for_each_dsi_port(port, intel_dsi->ports) { | |
1538 | struct intel_dsi_host *host; | |
1539 | ||
1540 | host = intel_dsi_host_init(intel_dsi, port); | |
1541 | if (!host) | |
1542 | goto err; | |
1543 | ||
1544 | intel_dsi->dsi_hosts[port] = host; | |
1545 | } | |
1546 | ||
593e0622 JN |
1547 | for (i = 0; i < ARRAY_SIZE(intel_dsi_drivers); i++) { |
1548 | intel_dsi->panel = intel_dsi_drivers[i].init(intel_dsi, | |
1549 | intel_dsi_drivers[i].panel_id); | |
1550 | if (intel_dsi->panel) | |
4e646495 JN |
1551 | break; |
1552 | } | |
1553 | ||
593e0622 | 1554 | if (!intel_dsi->panel) { |
4e646495 JN |
1555 | DRM_DEBUG_KMS("no device found\n"); |
1556 | goto err; | |
1557 | } | |
1558 | ||
fc45e821 SK |
1559 | /* |
1560 | * In case of BYT with CRC PMIC, we need to use GPIO for | |
1561 | * Panel control. | |
1562 | */ | |
1563 | if (dev_priv->vbt.dsi.config->pwm_blc == PPS_BLC_PMIC) { | |
1564 | intel_dsi->gpio_panel = | |
1565 | gpiod_get(dev->dev, "panel", GPIOD_OUT_HIGH); | |
1566 | ||
1567 | if (IS_ERR(intel_dsi->gpio_panel)) { | |
1568 | DRM_ERROR("Failed to own gpio for panel control\n"); | |
1569 | intel_dsi->gpio_panel = NULL; | |
1570 | } | |
1571 | } | |
1572 | ||
4e646495 | 1573 | intel_encoder->type = INTEL_OUTPUT_DSI; |
bc079e8b | 1574 | intel_encoder->cloneable = 0; |
4e646495 JN |
1575 | drm_connector_init(dev, connector, &intel_dsi_connector_funcs, |
1576 | DRM_MODE_CONNECTOR_DSI); | |
1577 | ||
1578 | drm_connector_helper_add(connector, &intel_dsi_connector_helper_funcs); | |
1579 | ||
1580 | connector->display_info.subpixel_order = SubPixelHorizontalRGB; /*XXX*/ | |
1581 | connector->interlace_allowed = false; | |
1582 | connector->doublescan_allowed = false; | |
1583 | ||
1584 | intel_connector_attach_encoder(intel_connector, intel_encoder); | |
1585 | ||
593e0622 JN |
1586 | drm_panel_attach(intel_dsi->panel, connector); |
1587 | ||
1588 | mutex_lock(&dev->mode_config.mutex); | |
1589 | drm_panel_get_modes(intel_dsi->panel); | |
1590 | list_for_each_entry(scan, &connector->probed_modes, head) { | |
1591 | if ((scan->type & DRM_MODE_TYPE_PREFERRED)) { | |
1592 | fixed_mode = drm_mode_duplicate(dev, scan); | |
1593 | break; | |
1594 | } | |
1595 | } | |
1596 | mutex_unlock(&dev->mode_config.mutex); | |
1597 | ||
4e646495 JN |
1598 | if (!fixed_mode) { |
1599 | DRM_DEBUG_KMS("no fixed mode\n"); | |
1600 | goto err; | |
1601 | } | |
1602 | ||
df457245 VS |
1603 | connector->display_info.width_mm = fixed_mode->width_mm; |
1604 | connector->display_info.height_mm = fixed_mode->height_mm; | |
1605 | ||
4b6ed685 | 1606 | intel_panel_init(&intel_connector->panel, fixed_mode, NULL); |
fda9ee98 | 1607 | intel_panel_setup_backlight(connector, INVALID_PIPE); |
f4ee265f VS |
1608 | |
1609 | intel_dsi_add_properties(intel_connector); | |
1610 | ||
4328633d | 1611 | return; |
4e646495 JN |
1612 | |
1613 | err: | |
1614 | drm_encoder_cleanup(&intel_encoder->base); | |
1615 | kfree(intel_dsi); | |
1616 | kfree(intel_connector); | |
4e646495 | 1617 | } |