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4e646495 JN |
1 | /* |
2 | * Copyright © 2013 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
21 | * DEALINGS IN THE SOFTWARE. | |
22 | * | |
23 | * Author: Jani Nikula <jani.nikula@intel.com> | |
24 | */ | |
25 | ||
26 | #include <drm/drmP.h> | |
c6f95f27 | 27 | #include <drm/drm_atomic_helper.h> |
4e646495 JN |
28 | #include <drm/drm_crtc.h> |
29 | #include <drm/drm_edid.h> | |
30 | #include <drm/i915_drm.h> | |
593e0622 | 31 | #include <drm/drm_panel.h> |
7e9804fd | 32 | #include <drm/drm_mipi_dsi.h> |
4e646495 | 33 | #include <linux/slab.h> |
fc45e821 | 34 | #include <linux/gpio/consumer.h> |
4e646495 JN |
35 | #include "i915_drv.h" |
36 | #include "intel_drv.h" | |
37 | #include "intel_dsi.h" | |
4e646495 | 38 | |
593e0622 JN |
39 | static const struct { |
40 | u16 panel_id; | |
41 | struct drm_panel * (*init)(struct intel_dsi *intel_dsi, u16 panel_id); | |
42 | } intel_dsi_drivers[] = { | |
2ab8b458 SK |
43 | { |
44 | .panel_id = MIPI_DSI_GENERIC_PANEL_ID, | |
593e0622 | 45 | .init = vbt_panel_init, |
2ab8b458 | 46 | }, |
4e646495 JN |
47 | }; |
48 | ||
7f6a6a4a | 49 | static void wait_for_dsi_fifo_empty(struct intel_dsi *intel_dsi, enum port port) |
3b1808bf JN |
50 | { |
51 | struct drm_encoder *encoder = &intel_dsi->base.base; | |
52 | struct drm_device *dev = encoder->dev; | |
53 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3b1808bf JN |
54 | u32 mask; |
55 | ||
56 | mask = LP_CTRL_FIFO_EMPTY | HS_CTRL_FIFO_EMPTY | | |
57 | LP_DATA_FIFO_EMPTY | HS_DATA_FIFO_EMPTY; | |
58 | ||
59 | if (wait_for((I915_READ(MIPI_GEN_FIFO_STAT(port)) & mask) == mask, 100)) | |
60 | DRM_ERROR("DPI FIFOs are not empty\n"); | |
61 | } | |
62 | ||
7e9804fd JN |
63 | static void write_data(struct drm_i915_private *dev_priv, u32 reg, |
64 | const u8 *data, u32 len) | |
65 | { | |
66 | u32 i, j; | |
67 | ||
68 | for (i = 0; i < len; i += 4) { | |
69 | u32 val = 0; | |
70 | ||
71 | for (j = 0; j < min_t(u32, len - i, 4); j++) | |
72 | val |= *data++ << 8 * j; | |
73 | ||
74 | I915_WRITE(reg, val); | |
75 | } | |
76 | } | |
77 | ||
78 | static void read_data(struct drm_i915_private *dev_priv, u32 reg, | |
79 | u8 *data, u32 len) | |
80 | { | |
81 | u32 i, j; | |
82 | ||
83 | for (i = 0; i < len; i += 4) { | |
84 | u32 val = I915_READ(reg); | |
85 | ||
86 | for (j = 0; j < min_t(u32, len - i, 4); j++) | |
87 | *data++ = val >> 8 * j; | |
88 | } | |
89 | } | |
90 | ||
91 | static ssize_t intel_dsi_host_transfer(struct mipi_dsi_host *host, | |
92 | const struct mipi_dsi_msg *msg) | |
93 | { | |
94 | struct intel_dsi_host *intel_dsi_host = to_intel_dsi_host(host); | |
95 | struct drm_device *dev = intel_dsi_host->intel_dsi->base.base.dev; | |
96 | struct drm_i915_private *dev_priv = dev->dev_private; | |
97 | enum port port = intel_dsi_host->port; | |
98 | struct mipi_dsi_packet packet; | |
99 | ssize_t ret; | |
100 | const u8 *header, *data; | |
101 | u32 data_reg, data_mask, ctrl_reg, ctrl_mask; | |
102 | ||
103 | ret = mipi_dsi_create_packet(&packet, msg); | |
104 | if (ret < 0) | |
105 | return ret; | |
106 | ||
107 | header = packet.header; | |
108 | data = packet.payload; | |
109 | ||
110 | if (msg->flags & MIPI_DSI_MSG_USE_LPM) { | |
111 | data_reg = MIPI_LP_GEN_DATA(port); | |
112 | data_mask = LP_DATA_FIFO_FULL; | |
113 | ctrl_reg = MIPI_LP_GEN_CTRL(port); | |
114 | ctrl_mask = LP_CTRL_FIFO_FULL; | |
115 | } else { | |
116 | data_reg = MIPI_HS_GEN_DATA(port); | |
117 | data_mask = HS_DATA_FIFO_FULL; | |
118 | ctrl_reg = MIPI_HS_GEN_CTRL(port); | |
119 | ctrl_mask = HS_CTRL_FIFO_FULL; | |
120 | } | |
121 | ||
122 | /* note: this is never true for reads */ | |
123 | if (packet.payload_length) { | |
124 | ||
125 | if (wait_for((I915_READ(MIPI_GEN_FIFO_STAT(port)) & data_mask) == 0, 50)) | |
126 | DRM_ERROR("Timeout waiting for HS/LP DATA FIFO !full\n"); | |
127 | ||
128 | write_data(dev_priv, data_reg, packet.payload, | |
129 | packet.payload_length); | |
130 | } | |
131 | ||
132 | if (msg->rx_len) { | |
133 | I915_WRITE(MIPI_INTR_STAT(port), GEN_READ_DATA_AVAIL); | |
134 | } | |
135 | ||
136 | if (wait_for((I915_READ(MIPI_GEN_FIFO_STAT(port)) & ctrl_mask) == 0, 50)) { | |
137 | DRM_ERROR("Timeout waiting for HS/LP CTRL FIFO !full\n"); | |
138 | } | |
139 | ||
140 | I915_WRITE(ctrl_reg, header[2] << 16 | header[1] << 8 | header[0]); | |
141 | ||
142 | /* ->rx_len is set only for reads */ | |
143 | if (msg->rx_len) { | |
144 | data_mask = GEN_READ_DATA_AVAIL; | |
145 | if (wait_for((I915_READ(MIPI_INTR_STAT(port)) & data_mask) == data_mask, 50)) | |
146 | DRM_ERROR("Timeout waiting for read data.\n"); | |
147 | ||
148 | read_data(dev_priv, data_reg, msg->rx_buf, msg->rx_len); | |
149 | } | |
150 | ||
151 | /* XXX: fix for reads and writes */ | |
152 | return 4 + packet.payload_length; | |
153 | } | |
154 | ||
155 | static int intel_dsi_host_attach(struct mipi_dsi_host *host, | |
156 | struct mipi_dsi_device *dsi) | |
157 | { | |
158 | return 0; | |
159 | } | |
160 | ||
161 | static int intel_dsi_host_detach(struct mipi_dsi_host *host, | |
162 | struct mipi_dsi_device *dsi) | |
163 | { | |
164 | return 0; | |
165 | } | |
166 | ||
167 | static const struct mipi_dsi_host_ops intel_dsi_host_ops = { | |
168 | .attach = intel_dsi_host_attach, | |
169 | .detach = intel_dsi_host_detach, | |
170 | .transfer = intel_dsi_host_transfer, | |
171 | }; | |
172 | ||
173 | static struct intel_dsi_host *intel_dsi_host_init(struct intel_dsi *intel_dsi, | |
174 | enum port port) | |
175 | { | |
176 | struct intel_dsi_host *host; | |
177 | struct mipi_dsi_device *device; | |
178 | ||
179 | host = kzalloc(sizeof(*host), GFP_KERNEL); | |
180 | if (!host) | |
181 | return NULL; | |
182 | ||
183 | host->base.ops = &intel_dsi_host_ops; | |
184 | host->intel_dsi = intel_dsi; | |
185 | host->port = port; | |
186 | ||
187 | /* | |
188 | * We should call mipi_dsi_host_register(&host->base) here, but we don't | |
189 | * have a host->dev, and we don't have OF stuff either. So just use the | |
190 | * dsi framework as a library and hope for the best. Create the dsi | |
191 | * devices by ourselves here too. Need to be careful though, because we | |
192 | * don't initialize any of the driver model devices here. | |
193 | */ | |
194 | device = kzalloc(sizeof(*device), GFP_KERNEL); | |
195 | if (!device) { | |
196 | kfree(host); | |
197 | return NULL; | |
198 | } | |
199 | ||
200 | device->host = &host->base; | |
201 | host->device = device; | |
202 | ||
203 | return host; | |
204 | } | |
205 | ||
a2581a9e JN |
206 | /* |
207 | * send a video mode command | |
208 | * | |
209 | * XXX: commands with data in MIPI_DPI_DATA? | |
210 | */ | |
211 | static int dpi_send_cmd(struct intel_dsi *intel_dsi, u32 cmd, bool hs, | |
212 | enum port port) | |
213 | { | |
214 | struct drm_encoder *encoder = &intel_dsi->base.base; | |
215 | struct drm_device *dev = encoder->dev; | |
216 | struct drm_i915_private *dev_priv = dev->dev_private; | |
217 | u32 mask; | |
218 | ||
219 | /* XXX: pipe, hs */ | |
220 | if (hs) | |
221 | cmd &= ~DPI_LP_MODE; | |
222 | else | |
223 | cmd |= DPI_LP_MODE; | |
224 | ||
225 | /* clear bit */ | |
226 | I915_WRITE(MIPI_INTR_STAT(port), SPL_PKT_SENT_INTERRUPT); | |
227 | ||
228 | /* XXX: old code skips write if control unchanged */ | |
229 | if (cmd == I915_READ(MIPI_DPI_CONTROL(port))) | |
230 | DRM_ERROR("Same special packet %02x twice in a row.\n", cmd); | |
231 | ||
232 | I915_WRITE(MIPI_DPI_CONTROL(port), cmd); | |
233 | ||
234 | mask = SPL_PKT_SENT_INTERRUPT; | |
235 | if (wait_for((I915_READ(MIPI_INTR_STAT(port)) & mask) == mask, 100)) | |
236 | DRM_ERROR("Video mode command 0x%08x send failed.\n", cmd); | |
237 | ||
238 | return 0; | |
239 | } | |
240 | ||
e9fe51c6 | 241 | static void band_gap_reset(struct drm_i915_private *dev_priv) |
4ce8c9a7 | 242 | { |
a580516d | 243 | mutex_lock(&dev_priv->sb_lock); |
4ce8c9a7 | 244 | |
e9fe51c6 SK |
245 | vlv_flisdsi_write(dev_priv, 0x08, 0x0001); |
246 | vlv_flisdsi_write(dev_priv, 0x0F, 0x0005); | |
247 | vlv_flisdsi_write(dev_priv, 0x0F, 0x0025); | |
248 | udelay(150); | |
249 | vlv_flisdsi_write(dev_priv, 0x0F, 0x0000); | |
250 | vlv_flisdsi_write(dev_priv, 0x08, 0x0000); | |
4ce8c9a7 | 251 | |
a580516d | 252 | mutex_unlock(&dev_priv->sb_lock); |
4ce8c9a7 SK |
253 | } |
254 | ||
4e646495 JN |
255 | static inline bool is_vid_mode(struct intel_dsi *intel_dsi) |
256 | { | |
dfba2e2d | 257 | return intel_dsi->operation_mode == INTEL_DSI_VIDEO_MODE; |
4e646495 JN |
258 | } |
259 | ||
260 | static inline bool is_cmd_mode(struct intel_dsi *intel_dsi) | |
261 | { | |
dfba2e2d | 262 | return intel_dsi->operation_mode == INTEL_DSI_COMMAND_MODE; |
4e646495 JN |
263 | } |
264 | ||
4e646495 | 265 | static bool intel_dsi_compute_config(struct intel_encoder *encoder, |
5cec258b | 266 | struct intel_crtc_state *config) |
4e646495 JN |
267 | { |
268 | struct intel_dsi *intel_dsi = container_of(encoder, struct intel_dsi, | |
269 | base); | |
270 | struct intel_connector *intel_connector = intel_dsi->attached_connector; | |
271 | struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode; | |
2d112de7 | 272 | struct drm_display_mode *adjusted_mode = &config->base.adjusted_mode; |
4e646495 JN |
273 | |
274 | DRM_DEBUG_KMS("\n"); | |
275 | ||
276 | if (fixed_mode) | |
277 | intel_fixed_panel_mode(fixed_mode, adjusted_mode); | |
278 | ||
f573de5a SK |
279 | /* DSI uses short packets for sync events, so clear mode flags for DSI */ |
280 | adjusted_mode->flags = 0; | |
281 | ||
4e646495 JN |
282 | return true; |
283 | } | |
284 | ||
5505a244 GS |
285 | static void intel_dsi_port_enable(struct intel_encoder *encoder) |
286 | { | |
287 | struct drm_device *dev = encoder->base.dev; | |
288 | struct drm_i915_private *dev_priv = dev->dev_private; | |
289 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); | |
290 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); | |
369602d3 | 291 | enum port port; |
5505a244 GS |
292 | u32 temp; |
293 | ||
a9da9bce GS |
294 | if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) { |
295 | temp = I915_READ(VLV_CHICKEN_3); | |
296 | temp &= ~PIXEL_OVERLAP_CNT_MASK | | |
297 | intel_dsi->pixel_overlap << | |
298 | PIXEL_OVERLAP_CNT_SHIFT; | |
299 | I915_WRITE(VLV_CHICKEN_3, temp); | |
300 | } | |
301 | ||
369602d3 GS |
302 | for_each_dsi_port(port, intel_dsi->ports) { |
303 | temp = I915_READ(MIPI_PORT_CTRL(port)); | |
304 | temp &= ~LANE_CONFIGURATION_MASK; | |
305 | temp &= ~DUAL_LINK_MODE_MASK; | |
306 | ||
307 | if (intel_dsi->ports == ((1 << PORT_A) | (1 << PORT_C))) { | |
308 | temp |= (intel_dsi->dual_link - 1) | |
309 | << DUAL_LINK_MODE_SHIFT; | |
310 | temp |= intel_crtc->pipe ? | |
311 | LANE_CONFIGURATION_DUAL_LINK_B : | |
312 | LANE_CONFIGURATION_DUAL_LINK_A; | |
313 | } | |
314 | /* assert ip_tg_enable signal */ | |
315 | I915_WRITE(MIPI_PORT_CTRL(port), temp | DPI_ENABLE); | |
316 | POSTING_READ(MIPI_PORT_CTRL(port)); | |
317 | } | |
5505a244 GS |
318 | } |
319 | ||
320 | static void intel_dsi_port_disable(struct intel_encoder *encoder) | |
321 | { | |
322 | struct drm_device *dev = encoder->base.dev; | |
323 | struct drm_i915_private *dev_priv = dev->dev_private; | |
369602d3 GS |
324 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); |
325 | enum port port; | |
5505a244 GS |
326 | u32 temp; |
327 | ||
369602d3 GS |
328 | for_each_dsi_port(port, intel_dsi->ports) { |
329 | /* de-assert ip_tg_enable signal */ | |
330 | temp = I915_READ(MIPI_PORT_CTRL(port)); | |
331 | I915_WRITE(MIPI_PORT_CTRL(port), temp & ~DPI_ENABLE); | |
332 | POSTING_READ(MIPI_PORT_CTRL(port)); | |
333 | } | |
5505a244 GS |
334 | } |
335 | ||
1dbd7cb2 | 336 | static void intel_dsi_device_ready(struct intel_encoder *encoder) |
4e646495 | 337 | { |
1dbd7cb2 | 338 | struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; |
24ee0e64 GS |
339 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); |
340 | enum port port; | |
1dbd7cb2 SK |
341 | u32 val; |
342 | ||
4e646495 | 343 | DRM_DEBUG_KMS("\n"); |
4e646495 | 344 | |
a580516d | 345 | mutex_lock(&dev_priv->sb_lock); |
2095f9fc SK |
346 | /* program rcomp for compliance, reduce from 50 ohms to 45 ohms |
347 | * needed everytime after power gate */ | |
348 | vlv_flisdsi_write(dev_priv, 0x04, 0x0004); | |
a580516d | 349 | mutex_unlock(&dev_priv->sb_lock); |
2095f9fc SK |
350 | |
351 | /* bandgap reset is needed after everytime we do power gate */ | |
352 | band_gap_reset(dev_priv); | |
353 | ||
24ee0e64 | 354 | for_each_dsi_port(port, intel_dsi->ports) { |
aceb365c | 355 | |
24ee0e64 GS |
356 | I915_WRITE(MIPI_DEVICE_READY(port), ULPS_STATE_ENTER); |
357 | usleep_range(2500, 3000); | |
aceb365c | 358 | |
bf344e80 GS |
359 | /* Enable MIPI PHY transparent latch |
360 | * Common bit for both MIPI Port A & MIPI Port C | |
361 | * No similar bit in MIPI Port C reg | |
362 | */ | |
4ba7d93a | 363 | val = I915_READ(MIPI_PORT_CTRL(PORT_A)); |
bf344e80 | 364 | I915_WRITE(MIPI_PORT_CTRL(PORT_A), val | LP_OUTPUT_HOLD); |
24ee0e64 | 365 | usleep_range(1000, 1500); |
aceb365c | 366 | |
24ee0e64 GS |
367 | I915_WRITE(MIPI_DEVICE_READY(port), ULPS_STATE_EXIT); |
368 | usleep_range(2500, 3000); | |
369 | ||
370 | I915_WRITE(MIPI_DEVICE_READY(port), DEVICE_READY); | |
371 | usleep_range(2500, 3000); | |
372 | } | |
1dbd7cb2 | 373 | } |
1dbd7cb2 SK |
374 | |
375 | static void intel_dsi_enable(struct intel_encoder *encoder) | |
376 | { | |
377 | struct drm_device *dev = encoder->base.dev; | |
378 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1dbd7cb2 | 379 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); |
4934b656 | 380 | enum port port; |
1dbd7cb2 SK |
381 | |
382 | DRM_DEBUG_KMS("\n"); | |
b9f5e07d | 383 | |
4934b656 JN |
384 | if (is_cmd_mode(intel_dsi)) { |
385 | for_each_dsi_port(port, intel_dsi->ports) | |
386 | I915_WRITE(MIPI_MAX_RETURN_PKT_SIZE(port), 8 * 4); | |
387 | } else { | |
4e646495 | 388 | msleep(20); /* XXX */ |
f03e4179 | 389 | for_each_dsi_port(port, intel_dsi->ports) |
a2581a9e | 390 | dpi_send_cmd(intel_dsi, TURN_ON, false, port); |
4e646495 JN |
391 | msleep(100); |
392 | ||
593e0622 | 393 | drm_panel_enable(intel_dsi->panel); |
2634fd7f | 394 | |
7f6a6a4a JN |
395 | for_each_dsi_port(port, intel_dsi->ports) |
396 | wait_for_dsi_fifo_empty(intel_dsi, port); | |
1381308b | 397 | |
5505a244 | 398 | intel_dsi_port_enable(encoder); |
4e646495 | 399 | } |
b029e66f SK |
400 | |
401 | intel_panel_enable_backlight(intel_dsi->attached_connector); | |
2634fd7f SK |
402 | } |
403 | ||
404 | static void intel_dsi_pre_enable(struct intel_encoder *encoder) | |
405 | { | |
20e5bf66 SK |
406 | struct drm_device *dev = encoder->base.dev; |
407 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2634fd7f | 408 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); |
20e5bf66 SK |
409 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); |
410 | enum pipe pipe = intel_crtc->pipe; | |
7f6a6a4a | 411 | enum port port; |
20e5bf66 | 412 | u32 tmp; |
2634fd7f SK |
413 | |
414 | DRM_DEBUG_KMS("\n"); | |
415 | ||
fc45e821 SK |
416 | /* Panel Enable over CRC PMIC */ |
417 | if (intel_dsi->gpio_panel) | |
418 | gpiod_set_value_cansleep(intel_dsi->gpio_panel, 1); | |
419 | ||
420 | msleep(intel_dsi->panel_on_delay); | |
421 | ||
20e5bf66 SK |
422 | /* Disable DPOunit clock gating, can stall pipe |
423 | * and we need DPLL REFA always enabled */ | |
424 | tmp = I915_READ(DPLL(pipe)); | |
60bfe44f | 425 | tmp |= DPLL_REF_CLK_ENABLE_VLV; |
20e5bf66 SK |
426 | I915_WRITE(DPLL(pipe), tmp); |
427 | ||
f573de5a | 428 | /* update the hw state for DPLL */ |
60bfe44f VS |
429 | intel_crtc->config->dpll_hw_state.dpll = DPLL_INTEGRATED_REF_CLK_VLV | |
430 | DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS; | |
f573de5a | 431 | |
20e5bf66 SK |
432 | tmp = I915_READ(DSPCLK_GATE_D); |
433 | tmp |= DPOUNIT_CLOCK_GATE_DISABLE; | |
434 | I915_WRITE(DSPCLK_GATE_D, tmp); | |
2634fd7f SK |
435 | |
436 | /* put device in ready state */ | |
437 | intel_dsi_device_ready(encoder); | |
4e646495 | 438 | |
593e0622 | 439 | drm_panel_prepare(intel_dsi->panel); |
20e5bf66 | 440 | |
7f6a6a4a JN |
441 | for_each_dsi_port(port, intel_dsi->ports) |
442 | wait_for_dsi_fifo_empty(intel_dsi, port); | |
1381308b | 443 | |
2634fd7f SK |
444 | /* Enable port in pre-enable phase itself because as per hw team |
445 | * recommendation, port should be enabled befor plane & pipe */ | |
446 | intel_dsi_enable(encoder); | |
447 | } | |
448 | ||
449 | static void intel_dsi_enable_nop(struct intel_encoder *encoder) | |
450 | { | |
451 | DRM_DEBUG_KMS("\n"); | |
452 | ||
453 | /* for DSI port enable has to be done before pipe | |
454 | * and plane enable, so port enable is done in | |
455 | * pre_enable phase itself unlike other encoders | |
456 | */ | |
4e646495 JN |
457 | } |
458 | ||
c315faf8 ID |
459 | static void intel_dsi_pre_disable(struct intel_encoder *encoder) |
460 | { | |
461 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); | |
f03e4179 | 462 | enum port port; |
c315faf8 ID |
463 | |
464 | DRM_DEBUG_KMS("\n"); | |
465 | ||
b029e66f SK |
466 | intel_panel_disable_backlight(intel_dsi->attached_connector); |
467 | ||
c315faf8 ID |
468 | if (is_vid_mode(intel_dsi)) { |
469 | /* Send Shutdown command to the panel in LP mode */ | |
f03e4179 | 470 | for_each_dsi_port(port, intel_dsi->ports) |
a2581a9e | 471 | dpi_send_cmd(intel_dsi, SHUTDOWN, false, port); |
c315faf8 ID |
472 | msleep(10); |
473 | } | |
474 | } | |
475 | ||
4e646495 JN |
476 | static void intel_dsi_disable(struct intel_encoder *encoder) |
477 | { | |
1dbd7cb2 SK |
478 | struct drm_device *dev = encoder->base.dev; |
479 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4e646495 | 480 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); |
384f02a2 | 481 | enum port port; |
4e646495 JN |
482 | u32 temp; |
483 | ||
484 | DRM_DEBUG_KMS("\n"); | |
485 | ||
4e646495 | 486 | if (is_vid_mode(intel_dsi)) { |
7f6a6a4a JN |
487 | for_each_dsi_port(port, intel_dsi->ports) |
488 | wait_for_dsi_fifo_empty(intel_dsi, port); | |
1381308b | 489 | |
5505a244 | 490 | intel_dsi_port_disable(encoder); |
4e646495 JN |
491 | msleep(2); |
492 | } | |
493 | ||
384f02a2 GS |
494 | for_each_dsi_port(port, intel_dsi->ports) { |
495 | /* Panel commands can be sent when clock is in LP11 */ | |
496 | I915_WRITE(MIPI_DEVICE_READY(port), 0x0); | |
339023ec | 497 | |
384f02a2 GS |
498 | temp = I915_READ(MIPI_CTRL(port)); |
499 | temp &= ~ESCAPE_CLOCK_DIVIDER_MASK; | |
500 | I915_WRITE(MIPI_CTRL(port), temp | | |
501 | intel_dsi->escape_clk_div << | |
502 | ESCAPE_CLOCK_DIVIDER_SHIFT); | |
339023ec | 503 | |
384f02a2 | 504 | I915_WRITE(MIPI_EOT_DISABLE(port), CLOCKSTOP); |
339023ec | 505 | |
384f02a2 GS |
506 | temp = I915_READ(MIPI_DSI_FUNC_PRG(port)); |
507 | temp &= ~VID_MODE_FORMAT_MASK; | |
508 | I915_WRITE(MIPI_DSI_FUNC_PRG(port), temp); | |
339023ec | 509 | |
384f02a2 GS |
510 | I915_WRITE(MIPI_DEVICE_READY(port), 0x1); |
511 | } | |
1dbd7cb2 SK |
512 | /* if disable packets are sent before sending shutdown packet then in |
513 | * some next enable sequence send turn on packet error is observed */ | |
593e0622 | 514 | drm_panel_disable(intel_dsi->panel); |
1381308b | 515 | |
7f6a6a4a JN |
516 | for_each_dsi_port(port, intel_dsi->ports) |
517 | wait_for_dsi_fifo_empty(intel_dsi, port); | |
4e646495 JN |
518 | } |
519 | ||
1dbd7cb2 | 520 | static void intel_dsi_clear_device_ready(struct intel_encoder *encoder) |
4e646495 | 521 | { |
1dbd7cb2 | 522 | struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; |
384f02a2 GS |
523 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); |
524 | enum port port; | |
1dbd7cb2 SK |
525 | u32 val; |
526 | ||
4e646495 | 527 | DRM_DEBUG_KMS("\n"); |
384f02a2 | 528 | for_each_dsi_port(port, intel_dsi->ports) { |
be4fc046 | 529 | |
384f02a2 GS |
530 | I915_WRITE(MIPI_DEVICE_READY(port), DEVICE_READY | |
531 | ULPS_STATE_ENTER); | |
532 | usleep_range(2000, 2500); | |
533 | ||
534 | I915_WRITE(MIPI_DEVICE_READY(port), DEVICE_READY | | |
535 | ULPS_STATE_EXIT); | |
536 | usleep_range(2000, 2500); | |
537 | ||
538 | I915_WRITE(MIPI_DEVICE_READY(port), DEVICE_READY | | |
539 | ULPS_STATE_ENTER); | |
540 | usleep_range(2000, 2500); | |
541 | ||
542 | /* Wait till Clock lanes are in LP-00 state for MIPI Port A | |
543 | * only. MIPI Port C has no similar bit for checking | |
544 | */ | |
545 | if (wait_for(((I915_READ(MIPI_PORT_CTRL(PORT_A)) & AFE_LATCHOUT) | |
546 | == 0x00000), 30)) | |
547 | DRM_ERROR("DSI LP not going Low\n"); | |
548 | ||
384f02a2 GS |
549 | /* Disable MIPI PHY transparent latch |
550 | * Common bit for both MIPI Port A & MIPI Port C | |
551 | */ | |
4ba7d93a | 552 | val = I915_READ(MIPI_PORT_CTRL(PORT_A)); |
384f02a2 GS |
553 | I915_WRITE(MIPI_PORT_CTRL(PORT_A), val & ~LP_OUTPUT_HOLD); |
554 | usleep_range(1000, 1500); | |
555 | ||
556 | I915_WRITE(MIPI_DEVICE_READY(port), 0x00); | |
557 | usleep_range(2000, 2500); | |
558 | } | |
1dbd7cb2 | 559 | |
fe88fc68 | 560 | intel_disable_dsi_pll(encoder); |
4e646495 | 561 | } |
20e5bf66 | 562 | |
1dbd7cb2 SK |
563 | static void intel_dsi_post_disable(struct intel_encoder *encoder) |
564 | { | |
20e5bf66 | 565 | struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; |
1dbd7cb2 | 566 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); |
20e5bf66 | 567 | u32 val; |
1dbd7cb2 SK |
568 | |
569 | DRM_DEBUG_KMS("\n"); | |
570 | ||
c315faf8 ID |
571 | intel_dsi_disable(encoder); |
572 | ||
1dbd7cb2 SK |
573 | intel_dsi_clear_device_ready(encoder); |
574 | ||
20e5bf66 SK |
575 | val = I915_READ(DSPCLK_GATE_D); |
576 | val &= ~DPOUNIT_CLOCK_GATE_DISABLE; | |
577 | I915_WRITE(DSPCLK_GATE_D, val); | |
578 | ||
593e0622 | 579 | drm_panel_unprepare(intel_dsi->panel); |
df38e655 SK |
580 | |
581 | msleep(intel_dsi->panel_off_delay); | |
582 | msleep(intel_dsi->panel_pwr_cycle_delay); | |
fc45e821 SK |
583 | |
584 | /* Panel Disable over CRC PMIC */ | |
585 | if (intel_dsi->gpio_panel) | |
586 | gpiod_set_value_cansleep(intel_dsi->gpio_panel, 0); | |
1dbd7cb2 | 587 | } |
4e646495 JN |
588 | |
589 | static bool intel_dsi_get_hw_state(struct intel_encoder *encoder, | |
590 | enum pipe *pipe) | |
591 | { | |
592 | struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; | |
c0beefd2 GS |
593 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); |
594 | struct drm_device *dev = encoder->base.dev; | |
6d129bea | 595 | enum intel_display_power_domain power_domain; |
c0beefd2 | 596 | u32 dpi_enabled, func; |
e7d7cad0 | 597 | enum port port; |
4e646495 JN |
598 | |
599 | DRM_DEBUG_KMS("\n"); | |
600 | ||
6d129bea | 601 | power_domain = intel_display_port_power_domain(encoder); |
f458ebbc | 602 | if (!intel_display_power_is_enabled(dev_priv, power_domain)) |
6d129bea ID |
603 | return false; |
604 | ||
4e646495 | 605 | /* XXX: this only works for one DSI output */ |
c0beefd2 | 606 | for_each_dsi_port(port, intel_dsi->ports) { |
e7d7cad0 | 607 | func = I915_READ(MIPI_DSI_FUNC_PRG(port)); |
c0beefd2 GS |
608 | dpi_enabled = I915_READ(MIPI_PORT_CTRL(port)) & |
609 | DPI_ENABLE; | |
610 | ||
611 | /* Due to some hardware limitations on BYT, MIPI Port C DPI | |
612 | * Enable bit does not get set. To check whether DSI Port C | |
613 | * was enabled in BIOS, check the Pipe B enable bit | |
614 | */ | |
615 | if (IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) && | |
616 | (port == PORT_C)) | |
617 | dpi_enabled = I915_READ(PIPECONF(PIPE_B)) & | |
618 | PIPECONF_ENABLE; | |
4e646495 | 619 | |
c0beefd2 | 620 | if (dpi_enabled || (func & CMD_MODE_DATA_WIDTH_MASK)) { |
e7d7cad0 | 621 | if (I915_READ(MIPI_DEVICE_READY(port)) & DEVICE_READY) { |
c0beefd2 | 622 | *pipe = port == PORT_A ? PIPE_A : PIPE_B; |
4e646495 JN |
623 | return true; |
624 | } | |
625 | } | |
626 | } | |
627 | ||
628 | return false; | |
629 | } | |
630 | ||
631 | static void intel_dsi_get_config(struct intel_encoder *encoder, | |
5cec258b | 632 | struct intel_crtc_state *pipe_config) |
4e646495 | 633 | { |
f573de5a | 634 | u32 pclk; |
4e646495 JN |
635 | DRM_DEBUG_KMS("\n"); |
636 | ||
f573de5a SK |
637 | /* |
638 | * DPLL_MD is not used in case of DSI, reading will get some default value | |
639 | * set dpll_md = 0 | |
640 | */ | |
641 | pipe_config->dpll_hw_state.dpll_md = 0; | |
642 | ||
643 | pclk = vlv_get_dsi_pclk(encoder, pipe_config->pipe_bpp); | |
644 | if (!pclk) | |
645 | return; | |
646 | ||
2d112de7 | 647 | pipe_config->base.adjusted_mode.crtc_clock = pclk; |
f573de5a | 648 | pipe_config->port_clock = pclk; |
4e646495 JN |
649 | } |
650 | ||
c19de8eb DL |
651 | static enum drm_mode_status |
652 | intel_dsi_mode_valid(struct drm_connector *connector, | |
653 | struct drm_display_mode *mode) | |
4e646495 JN |
654 | { |
655 | struct intel_connector *intel_connector = to_intel_connector(connector); | |
656 | struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode; | |
759a1e98 | 657 | int max_dotclk = to_i915(connector->dev)->max_dotclk_freq; |
4e646495 JN |
658 | |
659 | DRM_DEBUG_KMS("\n"); | |
660 | ||
661 | if (mode->flags & DRM_MODE_FLAG_DBLSCAN) { | |
662 | DRM_DEBUG_KMS("MODE_NO_DBLESCAN\n"); | |
663 | return MODE_NO_DBLESCAN; | |
664 | } | |
665 | ||
666 | if (fixed_mode) { | |
667 | if (mode->hdisplay > fixed_mode->hdisplay) | |
668 | return MODE_PANEL; | |
669 | if (mode->vdisplay > fixed_mode->vdisplay) | |
670 | return MODE_PANEL; | |
759a1e98 MK |
671 | if (fixed_mode->clock > max_dotclk) |
672 | return MODE_CLOCK_HIGH; | |
4e646495 JN |
673 | } |
674 | ||
36d21f4c | 675 | return MODE_OK; |
4e646495 JN |
676 | } |
677 | ||
678 | /* return txclkesc cycles in terms of divider and duration in us */ | |
679 | static u16 txclkesc(u32 divider, unsigned int us) | |
680 | { | |
681 | switch (divider) { | |
682 | case ESCAPE_CLOCK_DIVIDER_1: | |
683 | default: | |
684 | return 20 * us; | |
685 | case ESCAPE_CLOCK_DIVIDER_2: | |
686 | return 10 * us; | |
687 | case ESCAPE_CLOCK_DIVIDER_4: | |
688 | return 5 * us; | |
689 | } | |
690 | } | |
691 | ||
692 | /* return pixels in terms of txbyteclkhs */ | |
7f0c8605 SK |
693 | static u16 txbyteclkhs(u16 pixels, int bpp, int lane_count, |
694 | u16 burst_mode_ratio) | |
4e646495 | 695 | { |
7f0c8605 | 696 | return DIV_ROUND_UP(DIV_ROUND_UP(pixels * bpp * burst_mode_ratio, |
7f3de833 | 697 | 8 * 100), lane_count); |
4e646495 JN |
698 | } |
699 | ||
700 | static void set_dsi_timings(struct drm_encoder *encoder, | |
5e7234c9 | 701 | const struct drm_display_mode *adjusted_mode) |
4e646495 JN |
702 | { |
703 | struct drm_device *dev = encoder->dev; | |
704 | struct drm_i915_private *dev_priv = dev->dev_private; | |
705 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); | |
706 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); | |
aa102d28 | 707 | enum port port; |
6e3c9717 | 708 | unsigned int bpp = intel_crtc->config->pipe_bpp; |
4e646495 JN |
709 | unsigned int lane_count = intel_dsi->lane_count; |
710 | ||
711 | u16 hactive, hfp, hsync, hbp, vfp, vsync, vbp; | |
712 | ||
aad941d5 VS |
713 | hactive = adjusted_mode->crtc_hdisplay; |
714 | hfp = adjusted_mode->crtc_hsync_start - adjusted_mode->crtc_hdisplay; | |
715 | hsync = adjusted_mode->crtc_hsync_end - adjusted_mode->crtc_hsync_start; | |
716 | hbp = adjusted_mode->crtc_htotal - adjusted_mode->crtc_hsync_end; | |
4e646495 | 717 | |
aa102d28 GS |
718 | if (intel_dsi->dual_link) { |
719 | hactive /= 2; | |
720 | if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) | |
721 | hactive += intel_dsi->pixel_overlap; | |
722 | hfp /= 2; | |
723 | hsync /= 2; | |
724 | hbp /= 2; | |
725 | } | |
726 | ||
aad941d5 VS |
727 | vfp = adjusted_mode->crtc_vsync_start - adjusted_mode->crtc_vdisplay; |
728 | vsync = adjusted_mode->crtc_vsync_end - adjusted_mode->crtc_vsync_start; | |
729 | vbp = adjusted_mode->crtc_vtotal - adjusted_mode->crtc_vsync_end; | |
4e646495 JN |
730 | |
731 | /* horizontal values are in terms of high speed byte clock */ | |
7f0c8605 | 732 | hactive = txbyteclkhs(hactive, bpp, lane_count, |
7f3de833 | 733 | intel_dsi->burst_mode_ratio); |
7f0c8605 SK |
734 | hfp = txbyteclkhs(hfp, bpp, lane_count, intel_dsi->burst_mode_ratio); |
735 | hsync = txbyteclkhs(hsync, bpp, lane_count, | |
7f3de833 | 736 | intel_dsi->burst_mode_ratio); |
7f0c8605 | 737 | hbp = txbyteclkhs(hbp, bpp, lane_count, intel_dsi->burst_mode_ratio); |
4e646495 | 738 | |
aa102d28 | 739 | for_each_dsi_port(port, intel_dsi->ports) { |
d2e08c0f SS |
740 | if (IS_BROXTON(dev)) { |
741 | /* | |
742 | * Program hdisplay and vdisplay on MIPI transcoder. | |
743 | * This is different from calculated hactive and | |
744 | * vactive, as they are calculated per channel basis, | |
745 | * whereas these values should be based on resolution. | |
746 | */ | |
747 | I915_WRITE(BXT_MIPI_TRANS_HACTIVE(port), | |
aad941d5 | 748 | adjusted_mode->crtc_hdisplay); |
d2e08c0f | 749 | I915_WRITE(BXT_MIPI_TRANS_VACTIVE(port), |
aad941d5 | 750 | adjusted_mode->crtc_vdisplay); |
d2e08c0f | 751 | I915_WRITE(BXT_MIPI_TRANS_VTOTAL(port), |
aad941d5 | 752 | adjusted_mode->crtc_vtotal); |
d2e08c0f SS |
753 | } |
754 | ||
aa102d28 GS |
755 | I915_WRITE(MIPI_HACTIVE_AREA_COUNT(port), hactive); |
756 | I915_WRITE(MIPI_HFP_COUNT(port), hfp); | |
757 | ||
758 | /* meaningful for video mode non-burst sync pulse mode only, | |
759 | * can be zero for non-burst sync events and burst modes */ | |
760 | I915_WRITE(MIPI_HSYNC_PADDING_COUNT(port), hsync); | |
761 | I915_WRITE(MIPI_HBP_COUNT(port), hbp); | |
762 | ||
763 | /* vertical values are in terms of lines */ | |
764 | I915_WRITE(MIPI_VFP_COUNT(port), vfp); | |
765 | I915_WRITE(MIPI_VSYNC_PADDING_COUNT(port), vsync); | |
766 | I915_WRITE(MIPI_VBP_COUNT(port), vbp); | |
767 | } | |
4e646495 JN |
768 | } |
769 | ||
07e4fb9e | 770 | static void intel_dsi_prepare(struct intel_encoder *intel_encoder) |
4e646495 JN |
771 | { |
772 | struct drm_encoder *encoder = &intel_encoder->base; | |
773 | struct drm_device *dev = encoder->dev; | |
774 | struct drm_i915_private *dev_priv = dev->dev_private; | |
775 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); | |
776 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); | |
7c5f93b0 | 777 | const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode; |
24ee0e64 | 778 | enum port port; |
6e3c9717 | 779 | unsigned int bpp = intel_crtc->config->pipe_bpp; |
4e646495 | 780 | u32 val, tmp; |
24ee0e64 | 781 | u16 mode_hdisplay; |
4e646495 | 782 | |
e7d7cad0 | 783 | DRM_DEBUG_KMS("pipe %c\n", pipe_name(intel_crtc->pipe)); |
4e646495 | 784 | |
aad941d5 | 785 | mode_hdisplay = adjusted_mode->crtc_hdisplay; |
4e646495 | 786 | |
24ee0e64 GS |
787 | if (intel_dsi->dual_link) { |
788 | mode_hdisplay /= 2; | |
789 | if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) | |
790 | mode_hdisplay += intel_dsi->pixel_overlap; | |
791 | } | |
4e646495 | 792 | |
24ee0e64 | 793 | for_each_dsi_port(port, intel_dsi->ports) { |
d2e08c0f SS |
794 | if (IS_VALLEYVIEW(dev)) { |
795 | /* | |
796 | * escape clock divider, 20MHz, shared for A and C. | |
797 | * device ready must be off when doing this! txclkesc? | |
798 | */ | |
799 | tmp = I915_READ(MIPI_CTRL(PORT_A)); | |
800 | tmp &= ~ESCAPE_CLOCK_DIVIDER_MASK; | |
801 | I915_WRITE(MIPI_CTRL(PORT_A), tmp | | |
802 | ESCAPE_CLOCK_DIVIDER_1); | |
803 | ||
804 | /* read request priority is per pipe */ | |
805 | tmp = I915_READ(MIPI_CTRL(port)); | |
806 | tmp &= ~READ_REQUEST_PRIORITY_MASK; | |
807 | I915_WRITE(MIPI_CTRL(port), tmp | | |
808 | READ_REQUEST_PRIORITY_HIGH); | |
809 | } else if (IS_BROXTON(dev)) { | |
810 | /* | |
811 | * FIXME: | |
812 | * BXT can connect any PIPE to any MIPI port. | |
813 | * Select the pipe based on the MIPI port read from | |
814 | * VBT for now. Pick PIPE A for MIPI port A and C | |
815 | * for port C. | |
816 | */ | |
817 | tmp = I915_READ(MIPI_CTRL(port)); | |
818 | tmp &= ~BXT_PIPE_SELECT_MASK; | |
819 | ||
820 | if (port == PORT_A) | |
821 | tmp |= BXT_PIPE_SELECT_A; | |
822 | else if (port == PORT_C) | |
823 | tmp |= BXT_PIPE_SELECT_C; | |
824 | ||
825 | I915_WRITE(MIPI_CTRL(port), tmp); | |
826 | } | |
24ee0e64 GS |
827 | |
828 | /* XXX: why here, why like this? handling in irq handler?! */ | |
829 | I915_WRITE(MIPI_INTR_STAT(port), 0xffffffff); | |
830 | I915_WRITE(MIPI_INTR_EN(port), 0xffffffff); | |
831 | ||
832 | I915_WRITE(MIPI_DPHY_PARAM(port), intel_dsi->dphy_reg); | |
833 | ||
834 | I915_WRITE(MIPI_DPI_RESOLUTION(port), | |
aad941d5 | 835 | adjusted_mode->crtc_vdisplay << VERTICAL_ADDRESS_SHIFT | |
24ee0e64 GS |
836 | mode_hdisplay << HORIZONTAL_ADDRESS_SHIFT); |
837 | } | |
4e646495 JN |
838 | |
839 | set_dsi_timings(encoder, adjusted_mode); | |
840 | ||
841 | val = intel_dsi->lane_count << DATA_LANES_PRG_REG_SHIFT; | |
842 | if (is_cmd_mode(intel_dsi)) { | |
843 | val |= intel_dsi->channel << CMD_MODE_CHANNEL_NUMBER_SHIFT; | |
844 | val |= CMD_MODE_DATA_WIDTH_8_BIT; /* XXX */ | |
845 | } else { | |
846 | val |= intel_dsi->channel << VID_MODE_CHANNEL_NUMBER_SHIFT; | |
847 | ||
848 | /* XXX: cross-check bpp vs. pixel format? */ | |
849 | val |= intel_dsi->pixel_format; | |
850 | } | |
4e646495 | 851 | |
24ee0e64 GS |
852 | tmp = 0; |
853 | if (intel_dsi->eotp_pkt == 0) | |
854 | tmp |= EOT_DISABLE; | |
855 | if (intel_dsi->clock_stop) | |
856 | tmp |= CLOCKSTOP; | |
4e646495 | 857 | |
24ee0e64 GS |
858 | for_each_dsi_port(port, intel_dsi->ports) { |
859 | I915_WRITE(MIPI_DSI_FUNC_PRG(port), val); | |
860 | ||
861 | /* timeouts for recovery. one frame IIUC. if counter expires, | |
862 | * EOT and stop state. */ | |
863 | ||
864 | /* | |
865 | * In burst mode, value greater than one DPI line Time in byte | |
866 | * clock (txbyteclkhs) To timeout this timer 1+ of the above | |
867 | * said value is recommended. | |
868 | * | |
869 | * In non-burst mode, Value greater than one DPI frame time in | |
870 | * byte clock(txbyteclkhs) To timeout this timer 1+ of the above | |
871 | * said value is recommended. | |
872 | * | |
873 | * In DBI only mode, value greater than one DBI frame time in | |
874 | * byte clock(txbyteclkhs) To timeout this timer 1+ of the above | |
875 | * said value is recommended. | |
876 | */ | |
4e646495 | 877 | |
24ee0e64 GS |
878 | if (is_vid_mode(intel_dsi) && |
879 | intel_dsi->video_mode_format == VIDEO_MODE_BURST) { | |
880 | I915_WRITE(MIPI_HS_TX_TIMEOUT(port), | |
aad941d5 | 881 | txbyteclkhs(adjusted_mode->crtc_htotal, bpp, |
124abe07 VS |
882 | intel_dsi->lane_count, |
883 | intel_dsi->burst_mode_ratio) + 1); | |
24ee0e64 GS |
884 | } else { |
885 | I915_WRITE(MIPI_HS_TX_TIMEOUT(port), | |
aad941d5 VS |
886 | txbyteclkhs(adjusted_mode->crtc_vtotal * |
887 | adjusted_mode->crtc_htotal, | |
124abe07 VS |
888 | bpp, intel_dsi->lane_count, |
889 | intel_dsi->burst_mode_ratio) + 1); | |
24ee0e64 GS |
890 | } |
891 | I915_WRITE(MIPI_LP_RX_TIMEOUT(port), intel_dsi->lp_rx_timeout); | |
892 | I915_WRITE(MIPI_TURN_AROUND_TIMEOUT(port), | |
893 | intel_dsi->turn_arnd_val); | |
894 | I915_WRITE(MIPI_DEVICE_RESET_TIMER(port), | |
895 | intel_dsi->rst_timer_val); | |
f1c79f16 | 896 | |
24ee0e64 | 897 | /* dphy stuff */ |
f1c79f16 | 898 | |
24ee0e64 GS |
899 | /* in terms of low power clock */ |
900 | I915_WRITE(MIPI_INIT_COUNT(port), | |
901 | txclkesc(intel_dsi->escape_clk_div, 100)); | |
4e646495 | 902 | |
d2e08c0f SS |
903 | if (IS_BROXTON(dev) && (!intel_dsi->dual_link)) { |
904 | /* | |
905 | * BXT spec says write MIPI_INIT_COUNT for | |
906 | * both the ports, even if only one is | |
907 | * getting used. So write the other port | |
908 | * if not in dual link mode. | |
909 | */ | |
910 | I915_WRITE(MIPI_INIT_COUNT(port == | |
911 | PORT_A ? PORT_C : PORT_A), | |
912 | intel_dsi->init_count); | |
913 | } | |
4e646495 | 914 | |
24ee0e64 | 915 | /* recovery disables */ |
87c54d0e | 916 | I915_WRITE(MIPI_EOT_DISABLE(port), tmp); |
cf4dbd2e | 917 | |
24ee0e64 GS |
918 | /* in terms of low power clock */ |
919 | I915_WRITE(MIPI_INIT_COUNT(port), intel_dsi->init_count); | |
4e646495 | 920 | |
24ee0e64 GS |
921 | /* in terms of txbyteclkhs. actual high to low switch + |
922 | * MIPI_STOP_STATE_STALL * MIPI_LP_BYTECLK. | |
923 | * | |
924 | * XXX: write MIPI_STOP_STATE_STALL? | |
925 | */ | |
926 | I915_WRITE(MIPI_HIGH_LOW_SWITCH_COUNT(port), | |
927 | intel_dsi->hs_to_lp_count); | |
928 | ||
929 | /* XXX: low power clock equivalence in terms of byte clock. | |
930 | * the number of byte clocks occupied in one low power clock. | |
931 | * based on txbyteclkhs and txclkesc. | |
932 | * txclkesc time / txbyteclk time * (105 + MIPI_STOP_STATE_STALL | |
933 | * ) / 105.??? | |
934 | */ | |
935 | I915_WRITE(MIPI_LP_BYTECLK(port), intel_dsi->lp_byte_clk); | |
936 | ||
937 | /* the bw essential for transmitting 16 long packets containing | |
938 | * 252 bytes meant for dcs write memory command is programmed in | |
939 | * this register in terms of byte clocks. based on dsi transfer | |
940 | * rate and the number of lanes configured the time taken to | |
941 | * transmit 16 long packets in a dsi stream varies. */ | |
942 | I915_WRITE(MIPI_DBI_BW_CTRL(port), intel_dsi->bw_timer); | |
943 | ||
944 | I915_WRITE(MIPI_CLK_LANE_SWITCH_TIME_CNT(port), | |
945 | intel_dsi->clk_lp_to_hs_count << LP_HS_SSW_CNT_SHIFT | | |
946 | intel_dsi->clk_hs_to_lp_count << HS_LP_PWR_SW_CNT_SHIFT); | |
947 | ||
948 | if (is_vid_mode(intel_dsi)) | |
949 | /* Some panels might have resolution which is not a | |
950 | * multiple of 64 like 1366 x 768. Enable RANDOM | |
951 | * resolution support for such panels by default */ | |
952 | I915_WRITE(MIPI_VIDEO_MODE_FORMAT(port), | |
953 | intel_dsi->video_frmt_cfg_bits | | |
954 | intel_dsi->video_mode_format | | |
955 | IP_TG_CONFIG | | |
956 | RANDOM_DPI_DISPLAY_RESOLUTION); | |
957 | } | |
4e646495 JN |
958 | } |
959 | ||
07e4fb9e DV |
960 | static void intel_dsi_pre_pll_enable(struct intel_encoder *encoder) |
961 | { | |
962 | DRM_DEBUG_KMS("\n"); | |
963 | ||
964 | intel_dsi_prepare(encoder); | |
cfe01a5e | 965 | intel_enable_dsi_pll(encoder); |
07e4fb9e | 966 | |
07e4fb9e DV |
967 | } |
968 | ||
4e646495 JN |
969 | static enum drm_connector_status |
970 | intel_dsi_detect(struct drm_connector *connector, bool force) | |
971 | { | |
36d21f4c | 972 | return connector_status_connected; |
4e646495 JN |
973 | } |
974 | ||
975 | static int intel_dsi_get_modes(struct drm_connector *connector) | |
976 | { | |
977 | struct intel_connector *intel_connector = to_intel_connector(connector); | |
978 | struct drm_display_mode *mode; | |
979 | ||
980 | DRM_DEBUG_KMS("\n"); | |
981 | ||
982 | if (!intel_connector->panel.fixed_mode) { | |
983 | DRM_DEBUG_KMS("no fixed mode\n"); | |
984 | return 0; | |
985 | } | |
986 | ||
987 | mode = drm_mode_duplicate(connector->dev, | |
988 | intel_connector->panel.fixed_mode); | |
989 | if (!mode) { | |
990 | DRM_DEBUG_KMS("drm_mode_duplicate failed\n"); | |
991 | return 0; | |
992 | } | |
993 | ||
994 | drm_mode_probed_add(connector, mode); | |
995 | return 1; | |
996 | } | |
997 | ||
593e0622 | 998 | static void intel_dsi_connector_destroy(struct drm_connector *connector) |
4e646495 JN |
999 | { |
1000 | struct intel_connector *intel_connector = to_intel_connector(connector); | |
1001 | ||
1002 | DRM_DEBUG_KMS("\n"); | |
1003 | intel_panel_fini(&intel_connector->panel); | |
4e646495 JN |
1004 | drm_connector_cleanup(connector); |
1005 | kfree(connector); | |
1006 | } | |
1007 | ||
593e0622 JN |
1008 | static void intel_dsi_encoder_destroy(struct drm_encoder *encoder) |
1009 | { | |
1010 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); | |
1011 | ||
1012 | if (intel_dsi->panel) { | |
1013 | drm_panel_detach(intel_dsi->panel); | |
1014 | /* XXX: Logically this call belongs in the panel driver. */ | |
1015 | drm_panel_remove(intel_dsi->panel); | |
1016 | } | |
fc45e821 SK |
1017 | |
1018 | /* dispose of the gpios */ | |
1019 | if (intel_dsi->gpio_panel) | |
1020 | gpiod_put(intel_dsi->gpio_panel); | |
1021 | ||
593e0622 JN |
1022 | intel_encoder_destroy(encoder); |
1023 | } | |
1024 | ||
4e646495 | 1025 | static const struct drm_encoder_funcs intel_dsi_funcs = { |
593e0622 | 1026 | .destroy = intel_dsi_encoder_destroy, |
4e646495 JN |
1027 | }; |
1028 | ||
1029 | static const struct drm_connector_helper_funcs intel_dsi_connector_helper_funcs = { | |
1030 | .get_modes = intel_dsi_get_modes, | |
1031 | .mode_valid = intel_dsi_mode_valid, | |
1032 | .best_encoder = intel_best_encoder, | |
1033 | }; | |
1034 | ||
1035 | static const struct drm_connector_funcs intel_dsi_connector_funcs = { | |
4d688a2a | 1036 | .dpms = drm_atomic_helper_connector_dpms, |
4e646495 | 1037 | .detect = intel_dsi_detect, |
593e0622 | 1038 | .destroy = intel_dsi_connector_destroy, |
4e646495 | 1039 | .fill_modes = drm_helper_probe_single_connector_modes, |
2545e4a6 | 1040 | .atomic_get_property = intel_connector_atomic_get_property, |
c6f95f27 | 1041 | .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, |
98969725 | 1042 | .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, |
4e646495 JN |
1043 | }; |
1044 | ||
4328633d | 1045 | void intel_dsi_init(struct drm_device *dev) |
4e646495 JN |
1046 | { |
1047 | struct intel_dsi *intel_dsi; | |
1048 | struct intel_encoder *intel_encoder; | |
1049 | struct drm_encoder *encoder; | |
1050 | struct intel_connector *intel_connector; | |
1051 | struct drm_connector *connector; | |
593e0622 | 1052 | struct drm_display_mode *scan, *fixed_mode = NULL; |
b6fdd0f2 | 1053 | struct drm_i915_private *dev_priv = dev->dev_private; |
7e9804fd | 1054 | enum port port; |
4e646495 JN |
1055 | unsigned int i; |
1056 | ||
1057 | DRM_DEBUG_KMS("\n"); | |
1058 | ||
3e6bd011 SK |
1059 | /* There is no detection method for MIPI so rely on VBT */ |
1060 | if (!dev_priv->vbt.has_mipi) | |
4328633d | 1061 | return; |
3e6bd011 | 1062 | |
868d665b CJ |
1063 | if (IS_VALLEYVIEW(dev)) { |
1064 | dev_priv->mipi_mmio_base = VLV_MIPI_BASE; | |
1065 | } else { | |
1066 | DRM_ERROR("Unsupported Mipi device to reg base"); | |
1067 | return; | |
1068 | } | |
3e6bd011 | 1069 | |
4e646495 JN |
1070 | intel_dsi = kzalloc(sizeof(*intel_dsi), GFP_KERNEL); |
1071 | if (!intel_dsi) | |
4328633d | 1072 | return; |
4e646495 | 1073 | |
08d9bc92 | 1074 | intel_connector = intel_connector_alloc(); |
4e646495 JN |
1075 | if (!intel_connector) { |
1076 | kfree(intel_dsi); | |
4328633d | 1077 | return; |
4e646495 JN |
1078 | } |
1079 | ||
1080 | intel_encoder = &intel_dsi->base; | |
1081 | encoder = &intel_encoder->base; | |
1082 | intel_dsi->attached_connector = intel_connector; | |
1083 | ||
1084 | connector = &intel_connector->base; | |
1085 | ||
1086 | drm_encoder_init(dev, encoder, &intel_dsi_funcs, DRM_MODE_ENCODER_DSI); | |
1087 | ||
1088 | /* XXX: very likely not all of these are needed */ | |
4e646495 JN |
1089 | intel_encoder->compute_config = intel_dsi_compute_config; |
1090 | intel_encoder->pre_pll_enable = intel_dsi_pre_pll_enable; | |
1091 | intel_encoder->pre_enable = intel_dsi_pre_enable; | |
2634fd7f | 1092 | intel_encoder->enable = intel_dsi_enable_nop; |
c315faf8 | 1093 | intel_encoder->disable = intel_dsi_pre_disable; |
4e646495 JN |
1094 | intel_encoder->post_disable = intel_dsi_post_disable; |
1095 | intel_encoder->get_hw_state = intel_dsi_get_hw_state; | |
1096 | intel_encoder->get_config = intel_dsi_get_config; | |
1097 | ||
1098 | intel_connector->get_hw_state = intel_connector_get_hw_state; | |
4932e2c3 | 1099 | intel_connector->unregister = intel_connector_unregister; |
4e646495 | 1100 | |
e7d7cad0 | 1101 | /* Pipe A maps to MIPI DSI port A, pipe B maps to MIPI DSI port C */ |
82425785 | 1102 | if (dev_priv->vbt.dsi.port == DVO_PORT_MIPIA) { |
e7d7cad0 | 1103 | intel_encoder->crtc_mask = (1 << PIPE_A); |
17af40a8 JN |
1104 | intel_dsi->ports = (1 << PORT_A); |
1105 | } else if (dev_priv->vbt.dsi.port == DVO_PORT_MIPIC) { | |
e7d7cad0 | 1106 | intel_encoder->crtc_mask = (1 << PIPE_B); |
17af40a8 JN |
1107 | intel_dsi->ports = (1 << PORT_C); |
1108 | } | |
e7d7cad0 | 1109 | |
82425785 GS |
1110 | if (dev_priv->vbt.dsi.config->dual_link) |
1111 | intel_dsi->ports = ((1 << PORT_A) | (1 << PORT_C)); | |
1112 | ||
7e9804fd JN |
1113 | /* Create a DSI host (and a device) for each port. */ |
1114 | for_each_dsi_port(port, intel_dsi->ports) { | |
1115 | struct intel_dsi_host *host; | |
1116 | ||
1117 | host = intel_dsi_host_init(intel_dsi, port); | |
1118 | if (!host) | |
1119 | goto err; | |
1120 | ||
1121 | intel_dsi->dsi_hosts[port] = host; | |
1122 | } | |
1123 | ||
593e0622 JN |
1124 | for (i = 0; i < ARRAY_SIZE(intel_dsi_drivers); i++) { |
1125 | intel_dsi->panel = intel_dsi_drivers[i].init(intel_dsi, | |
1126 | intel_dsi_drivers[i].panel_id); | |
1127 | if (intel_dsi->panel) | |
4e646495 JN |
1128 | break; |
1129 | } | |
1130 | ||
593e0622 | 1131 | if (!intel_dsi->panel) { |
4e646495 JN |
1132 | DRM_DEBUG_KMS("no device found\n"); |
1133 | goto err; | |
1134 | } | |
1135 | ||
fc45e821 SK |
1136 | /* |
1137 | * In case of BYT with CRC PMIC, we need to use GPIO for | |
1138 | * Panel control. | |
1139 | */ | |
1140 | if (dev_priv->vbt.dsi.config->pwm_blc == PPS_BLC_PMIC) { | |
1141 | intel_dsi->gpio_panel = | |
1142 | gpiod_get(dev->dev, "panel", GPIOD_OUT_HIGH); | |
1143 | ||
1144 | if (IS_ERR(intel_dsi->gpio_panel)) { | |
1145 | DRM_ERROR("Failed to own gpio for panel control\n"); | |
1146 | intel_dsi->gpio_panel = NULL; | |
1147 | } | |
1148 | } | |
1149 | ||
4e646495 | 1150 | intel_encoder->type = INTEL_OUTPUT_DSI; |
bc079e8b | 1151 | intel_encoder->cloneable = 0; |
4e646495 JN |
1152 | drm_connector_init(dev, connector, &intel_dsi_connector_funcs, |
1153 | DRM_MODE_CONNECTOR_DSI); | |
1154 | ||
1155 | drm_connector_helper_add(connector, &intel_dsi_connector_helper_funcs); | |
1156 | ||
1157 | connector->display_info.subpixel_order = SubPixelHorizontalRGB; /*XXX*/ | |
1158 | connector->interlace_allowed = false; | |
1159 | connector->doublescan_allowed = false; | |
1160 | ||
1161 | intel_connector_attach_encoder(intel_connector, intel_encoder); | |
1162 | ||
34ea3d38 | 1163 | drm_connector_register(connector); |
4e646495 | 1164 | |
593e0622 JN |
1165 | drm_panel_attach(intel_dsi->panel, connector); |
1166 | ||
1167 | mutex_lock(&dev->mode_config.mutex); | |
1168 | drm_panel_get_modes(intel_dsi->panel); | |
1169 | list_for_each_entry(scan, &connector->probed_modes, head) { | |
1170 | if ((scan->type & DRM_MODE_TYPE_PREFERRED)) { | |
1171 | fixed_mode = drm_mode_duplicate(dev, scan); | |
1172 | break; | |
1173 | } | |
1174 | } | |
1175 | mutex_unlock(&dev->mode_config.mutex); | |
1176 | ||
4e646495 JN |
1177 | if (!fixed_mode) { |
1178 | DRM_DEBUG_KMS("no fixed mode\n"); | |
1179 | goto err; | |
1180 | } | |
1181 | ||
4b6ed685 | 1182 | intel_panel_init(&intel_connector->panel, fixed_mode, NULL); |
b029e66f | 1183 | intel_panel_setup_backlight(connector, INVALID_PIPE); |
4e646495 | 1184 | |
4328633d | 1185 | return; |
4e646495 JN |
1186 | |
1187 | err: | |
1188 | drm_encoder_cleanup(&intel_encoder->base); | |
1189 | kfree(intel_dsi); | |
1190 | kfree(intel_connector); | |
4e646495 | 1191 | } |