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4e646495 JN |
1 | /* |
2 | * Copyright © 2013 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
21 | * DEALINGS IN THE SOFTWARE. | |
22 | * | |
23 | * Author: Jani Nikula <jani.nikula@intel.com> | |
24 | */ | |
25 | ||
26 | #include <drm/drmP.h> | |
27 | #include <drm/drm_crtc.h> | |
28 | #include <drm/drm_edid.h> | |
29 | #include <drm/i915_drm.h> | |
30 | #include <linux/slab.h> | |
31 | #include "i915_drv.h" | |
32 | #include "intel_drv.h" | |
33 | #include "intel_dsi.h" | |
34 | #include "intel_dsi_cmd.h" | |
35 | ||
36 | /* the sub-encoders aka panel drivers */ | |
37 | static const struct intel_dsi_device intel_dsi_devices[] = { | |
2ab8b458 SK |
38 | { |
39 | .panel_id = MIPI_DSI_GENERIC_PANEL_ID, | |
40 | .name = "vbt-generic-dsi-vid-mode-display", | |
41 | .dev_ops = &vbt_generic_dsi_display_ops, | |
42 | }, | |
4e646495 JN |
43 | }; |
44 | ||
7f6a6a4a | 45 | static void wait_for_dsi_fifo_empty(struct intel_dsi *intel_dsi, enum port port) |
3b1808bf JN |
46 | { |
47 | struct drm_encoder *encoder = &intel_dsi->base.base; | |
48 | struct drm_device *dev = encoder->dev; | |
49 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3b1808bf JN |
50 | u32 mask; |
51 | ||
52 | mask = LP_CTRL_FIFO_EMPTY | HS_CTRL_FIFO_EMPTY | | |
53 | LP_DATA_FIFO_EMPTY | HS_DATA_FIFO_EMPTY; | |
54 | ||
55 | if (wait_for((I915_READ(MIPI_GEN_FIFO_STAT(port)) & mask) == mask, 100)) | |
56 | DRM_ERROR("DPI FIFOs are not empty\n"); | |
57 | } | |
58 | ||
e9fe51c6 | 59 | static void band_gap_reset(struct drm_i915_private *dev_priv) |
4ce8c9a7 SK |
60 | { |
61 | mutex_lock(&dev_priv->dpio_lock); | |
62 | ||
e9fe51c6 SK |
63 | vlv_flisdsi_write(dev_priv, 0x08, 0x0001); |
64 | vlv_flisdsi_write(dev_priv, 0x0F, 0x0005); | |
65 | vlv_flisdsi_write(dev_priv, 0x0F, 0x0025); | |
66 | udelay(150); | |
67 | vlv_flisdsi_write(dev_priv, 0x0F, 0x0000); | |
68 | vlv_flisdsi_write(dev_priv, 0x08, 0x0000); | |
4ce8c9a7 SK |
69 | |
70 | mutex_unlock(&dev_priv->dpio_lock); | |
4ce8c9a7 SK |
71 | } |
72 | ||
4e646495 JN |
73 | static struct intel_dsi *intel_attached_dsi(struct drm_connector *connector) |
74 | { | |
75 | return container_of(intel_attached_encoder(connector), | |
76 | struct intel_dsi, base); | |
77 | } | |
78 | ||
79 | static inline bool is_vid_mode(struct intel_dsi *intel_dsi) | |
80 | { | |
dfba2e2d | 81 | return intel_dsi->operation_mode == INTEL_DSI_VIDEO_MODE; |
4e646495 JN |
82 | } |
83 | ||
84 | static inline bool is_cmd_mode(struct intel_dsi *intel_dsi) | |
85 | { | |
dfba2e2d | 86 | return intel_dsi->operation_mode == INTEL_DSI_COMMAND_MODE; |
4e646495 JN |
87 | } |
88 | ||
89 | static void intel_dsi_hot_plug(struct intel_encoder *encoder) | |
90 | { | |
91 | DRM_DEBUG_KMS("\n"); | |
92 | } | |
93 | ||
94 | static bool intel_dsi_compute_config(struct intel_encoder *encoder, | |
5cec258b | 95 | struct intel_crtc_state *config) |
4e646495 JN |
96 | { |
97 | struct intel_dsi *intel_dsi = container_of(encoder, struct intel_dsi, | |
98 | base); | |
99 | struct intel_connector *intel_connector = intel_dsi->attached_connector; | |
100 | struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode; | |
2d112de7 ACO |
101 | struct drm_display_mode *adjusted_mode = &config->base.adjusted_mode; |
102 | struct drm_display_mode *mode = &config->base.mode; | |
4e646495 JN |
103 | |
104 | DRM_DEBUG_KMS("\n"); | |
105 | ||
106 | if (fixed_mode) | |
107 | intel_fixed_panel_mode(fixed_mode, adjusted_mode); | |
108 | ||
f573de5a SK |
109 | /* DSI uses short packets for sync events, so clear mode flags for DSI */ |
110 | adjusted_mode->flags = 0; | |
111 | ||
4e646495 JN |
112 | if (intel_dsi->dev.dev_ops->mode_fixup) |
113 | return intel_dsi->dev.dev_ops->mode_fixup(&intel_dsi->dev, | |
114 | mode, adjusted_mode); | |
115 | ||
116 | return true; | |
117 | } | |
118 | ||
5505a244 GS |
119 | static void intel_dsi_port_enable(struct intel_encoder *encoder) |
120 | { | |
121 | struct drm_device *dev = encoder->base.dev; | |
122 | struct drm_i915_private *dev_priv = dev->dev_private; | |
123 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); | |
124 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); | |
369602d3 | 125 | enum port port; |
5505a244 GS |
126 | u32 temp; |
127 | ||
a9da9bce GS |
128 | if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) { |
129 | temp = I915_READ(VLV_CHICKEN_3); | |
130 | temp &= ~PIXEL_OVERLAP_CNT_MASK | | |
131 | intel_dsi->pixel_overlap << | |
132 | PIXEL_OVERLAP_CNT_SHIFT; | |
133 | I915_WRITE(VLV_CHICKEN_3, temp); | |
134 | } | |
135 | ||
369602d3 GS |
136 | for_each_dsi_port(port, intel_dsi->ports) { |
137 | temp = I915_READ(MIPI_PORT_CTRL(port)); | |
138 | temp &= ~LANE_CONFIGURATION_MASK; | |
139 | temp &= ~DUAL_LINK_MODE_MASK; | |
140 | ||
141 | if (intel_dsi->ports == ((1 << PORT_A) | (1 << PORT_C))) { | |
142 | temp |= (intel_dsi->dual_link - 1) | |
143 | << DUAL_LINK_MODE_SHIFT; | |
144 | temp |= intel_crtc->pipe ? | |
145 | LANE_CONFIGURATION_DUAL_LINK_B : | |
146 | LANE_CONFIGURATION_DUAL_LINK_A; | |
147 | } | |
148 | /* assert ip_tg_enable signal */ | |
149 | I915_WRITE(MIPI_PORT_CTRL(port), temp | DPI_ENABLE); | |
150 | POSTING_READ(MIPI_PORT_CTRL(port)); | |
151 | } | |
5505a244 GS |
152 | } |
153 | ||
154 | static void intel_dsi_port_disable(struct intel_encoder *encoder) | |
155 | { | |
156 | struct drm_device *dev = encoder->base.dev; | |
157 | struct drm_i915_private *dev_priv = dev->dev_private; | |
369602d3 GS |
158 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); |
159 | enum port port; | |
5505a244 GS |
160 | u32 temp; |
161 | ||
369602d3 GS |
162 | for_each_dsi_port(port, intel_dsi->ports) { |
163 | /* de-assert ip_tg_enable signal */ | |
164 | temp = I915_READ(MIPI_PORT_CTRL(port)); | |
165 | I915_WRITE(MIPI_PORT_CTRL(port), temp & ~DPI_ENABLE); | |
166 | POSTING_READ(MIPI_PORT_CTRL(port)); | |
167 | } | |
5505a244 GS |
168 | } |
169 | ||
1dbd7cb2 | 170 | static void intel_dsi_device_ready(struct intel_encoder *encoder) |
4e646495 | 171 | { |
1dbd7cb2 | 172 | struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; |
24ee0e64 GS |
173 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); |
174 | enum port port; | |
1dbd7cb2 SK |
175 | u32 val; |
176 | ||
4e646495 | 177 | DRM_DEBUG_KMS("\n"); |
4e646495 | 178 | |
2095f9fc SK |
179 | mutex_lock(&dev_priv->dpio_lock); |
180 | /* program rcomp for compliance, reduce from 50 ohms to 45 ohms | |
181 | * needed everytime after power gate */ | |
182 | vlv_flisdsi_write(dev_priv, 0x04, 0x0004); | |
183 | mutex_unlock(&dev_priv->dpio_lock); | |
184 | ||
185 | /* bandgap reset is needed after everytime we do power gate */ | |
186 | band_gap_reset(dev_priv); | |
187 | ||
24ee0e64 | 188 | for_each_dsi_port(port, intel_dsi->ports) { |
aceb365c | 189 | |
24ee0e64 GS |
190 | I915_WRITE(MIPI_DEVICE_READY(port), ULPS_STATE_ENTER); |
191 | usleep_range(2500, 3000); | |
aceb365c | 192 | |
24ee0e64 | 193 | val = I915_READ(MIPI_PORT_CTRL(port)); |
bf344e80 GS |
194 | |
195 | /* Enable MIPI PHY transparent latch | |
196 | * Common bit for both MIPI Port A & MIPI Port C | |
197 | * No similar bit in MIPI Port C reg | |
198 | */ | |
199 | I915_WRITE(MIPI_PORT_CTRL(PORT_A), val | LP_OUTPUT_HOLD); | |
24ee0e64 | 200 | usleep_range(1000, 1500); |
aceb365c | 201 | |
24ee0e64 GS |
202 | I915_WRITE(MIPI_DEVICE_READY(port), ULPS_STATE_EXIT); |
203 | usleep_range(2500, 3000); | |
204 | ||
205 | I915_WRITE(MIPI_DEVICE_READY(port), DEVICE_READY); | |
206 | usleep_range(2500, 3000); | |
207 | } | |
1dbd7cb2 | 208 | } |
1dbd7cb2 SK |
209 | |
210 | static void intel_dsi_enable(struct intel_encoder *encoder) | |
211 | { | |
212 | struct drm_device *dev = encoder->base.dev; | |
213 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1dbd7cb2 | 214 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); |
4934b656 | 215 | enum port port; |
1dbd7cb2 SK |
216 | |
217 | DRM_DEBUG_KMS("\n"); | |
b9f5e07d | 218 | |
4934b656 JN |
219 | if (is_cmd_mode(intel_dsi)) { |
220 | for_each_dsi_port(port, intel_dsi->ports) | |
221 | I915_WRITE(MIPI_MAX_RETURN_PKT_SIZE(port), 8 * 4); | |
222 | } else { | |
4e646495 | 223 | msleep(20); /* XXX */ |
f03e4179 JN |
224 | for_each_dsi_port(port, intel_dsi->ports) |
225 | dpi_send_cmd(intel_dsi, TURN_ON, DPI_LP_MODE_EN, port); | |
4e646495 JN |
226 | msleep(100); |
227 | ||
2634fd7f SK |
228 | if (intel_dsi->dev.dev_ops->enable) |
229 | intel_dsi->dev.dev_ops->enable(&intel_dsi->dev); | |
230 | ||
7f6a6a4a JN |
231 | for_each_dsi_port(port, intel_dsi->ports) |
232 | wait_for_dsi_fifo_empty(intel_dsi, port); | |
1381308b | 233 | |
5505a244 | 234 | intel_dsi_port_enable(encoder); |
4e646495 | 235 | } |
2634fd7f SK |
236 | } |
237 | ||
238 | static void intel_dsi_pre_enable(struct intel_encoder *encoder) | |
239 | { | |
20e5bf66 SK |
240 | struct drm_device *dev = encoder->base.dev; |
241 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2634fd7f | 242 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); |
20e5bf66 SK |
243 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); |
244 | enum pipe pipe = intel_crtc->pipe; | |
7f6a6a4a | 245 | enum port port; |
20e5bf66 | 246 | u32 tmp; |
2634fd7f SK |
247 | |
248 | DRM_DEBUG_KMS("\n"); | |
249 | ||
20e5bf66 SK |
250 | /* Disable DPOunit clock gating, can stall pipe |
251 | * and we need DPLL REFA always enabled */ | |
252 | tmp = I915_READ(DPLL(pipe)); | |
253 | tmp |= DPLL_REFA_CLK_ENABLE_VLV; | |
254 | I915_WRITE(DPLL(pipe), tmp); | |
255 | ||
f573de5a | 256 | /* update the hw state for DPLL */ |
6e3c9717 | 257 | intel_crtc->config->dpll_hw_state.dpll = DPLL_INTEGRATED_CLOCK_VLV | |
7f3de833 | 258 | DPLL_REFA_CLK_ENABLE_VLV; |
f573de5a | 259 | |
20e5bf66 SK |
260 | tmp = I915_READ(DSPCLK_GATE_D); |
261 | tmp |= DPOUNIT_CLOCK_GATE_DISABLE; | |
262 | I915_WRITE(DSPCLK_GATE_D, tmp); | |
2634fd7f SK |
263 | |
264 | /* put device in ready state */ | |
265 | intel_dsi_device_ready(encoder); | |
4e646495 | 266 | |
df38e655 SK |
267 | msleep(intel_dsi->panel_on_delay); |
268 | ||
20e5bf66 SK |
269 | if (intel_dsi->dev.dev_ops->panel_reset) |
270 | intel_dsi->dev.dev_ops->panel_reset(&intel_dsi->dev); | |
271 | ||
2634fd7f SK |
272 | if (intel_dsi->dev.dev_ops->send_otp_cmds) |
273 | intel_dsi->dev.dev_ops->send_otp_cmds(&intel_dsi->dev); | |
274 | ||
7f6a6a4a JN |
275 | for_each_dsi_port(port, intel_dsi->ports) |
276 | wait_for_dsi_fifo_empty(intel_dsi, port); | |
1381308b | 277 | |
2634fd7f SK |
278 | /* Enable port in pre-enable phase itself because as per hw team |
279 | * recommendation, port should be enabled befor plane & pipe */ | |
280 | intel_dsi_enable(encoder); | |
281 | } | |
282 | ||
283 | static void intel_dsi_enable_nop(struct intel_encoder *encoder) | |
284 | { | |
285 | DRM_DEBUG_KMS("\n"); | |
286 | ||
287 | /* for DSI port enable has to be done before pipe | |
288 | * and plane enable, so port enable is done in | |
289 | * pre_enable phase itself unlike other encoders | |
290 | */ | |
4e646495 JN |
291 | } |
292 | ||
c315faf8 ID |
293 | static void intel_dsi_pre_disable(struct intel_encoder *encoder) |
294 | { | |
295 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); | |
f03e4179 | 296 | enum port port; |
c315faf8 ID |
297 | |
298 | DRM_DEBUG_KMS("\n"); | |
299 | ||
300 | if (is_vid_mode(intel_dsi)) { | |
301 | /* Send Shutdown command to the panel in LP mode */ | |
f03e4179 JN |
302 | for_each_dsi_port(port, intel_dsi->ports) |
303 | dpi_send_cmd(intel_dsi, SHUTDOWN, DPI_LP_MODE_EN, port); | |
c315faf8 ID |
304 | msleep(10); |
305 | } | |
306 | } | |
307 | ||
4e646495 JN |
308 | static void intel_dsi_disable(struct intel_encoder *encoder) |
309 | { | |
1dbd7cb2 SK |
310 | struct drm_device *dev = encoder->base.dev; |
311 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4e646495 | 312 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); |
384f02a2 | 313 | enum port port; |
4e646495 JN |
314 | u32 temp; |
315 | ||
316 | DRM_DEBUG_KMS("\n"); | |
317 | ||
4e646495 | 318 | if (is_vid_mode(intel_dsi)) { |
7f6a6a4a JN |
319 | for_each_dsi_port(port, intel_dsi->ports) |
320 | wait_for_dsi_fifo_empty(intel_dsi, port); | |
1381308b | 321 | |
5505a244 | 322 | intel_dsi_port_disable(encoder); |
4e646495 JN |
323 | msleep(2); |
324 | } | |
325 | ||
384f02a2 GS |
326 | for_each_dsi_port(port, intel_dsi->ports) { |
327 | /* Panel commands can be sent when clock is in LP11 */ | |
328 | I915_WRITE(MIPI_DEVICE_READY(port), 0x0); | |
339023ec | 329 | |
384f02a2 GS |
330 | temp = I915_READ(MIPI_CTRL(port)); |
331 | temp &= ~ESCAPE_CLOCK_DIVIDER_MASK; | |
332 | I915_WRITE(MIPI_CTRL(port), temp | | |
333 | intel_dsi->escape_clk_div << | |
334 | ESCAPE_CLOCK_DIVIDER_SHIFT); | |
339023ec | 335 | |
384f02a2 | 336 | I915_WRITE(MIPI_EOT_DISABLE(port), CLOCKSTOP); |
339023ec | 337 | |
384f02a2 GS |
338 | temp = I915_READ(MIPI_DSI_FUNC_PRG(port)); |
339 | temp &= ~VID_MODE_FORMAT_MASK; | |
340 | I915_WRITE(MIPI_DSI_FUNC_PRG(port), temp); | |
339023ec | 341 | |
384f02a2 GS |
342 | I915_WRITE(MIPI_DEVICE_READY(port), 0x1); |
343 | } | |
1dbd7cb2 SK |
344 | /* if disable packets are sent before sending shutdown packet then in |
345 | * some next enable sequence send turn on packet error is observed */ | |
346 | if (intel_dsi->dev.dev_ops->disable) | |
347 | intel_dsi->dev.dev_ops->disable(&intel_dsi->dev); | |
1381308b | 348 | |
7f6a6a4a JN |
349 | for_each_dsi_port(port, intel_dsi->ports) |
350 | wait_for_dsi_fifo_empty(intel_dsi, port); | |
4e646495 JN |
351 | } |
352 | ||
1dbd7cb2 | 353 | static void intel_dsi_clear_device_ready(struct intel_encoder *encoder) |
4e646495 | 354 | { |
1dbd7cb2 | 355 | struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; |
384f02a2 GS |
356 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); |
357 | enum port port; | |
1dbd7cb2 SK |
358 | u32 val; |
359 | ||
4e646495 | 360 | DRM_DEBUG_KMS("\n"); |
384f02a2 | 361 | for_each_dsi_port(port, intel_dsi->ports) { |
be4fc046 | 362 | |
384f02a2 GS |
363 | I915_WRITE(MIPI_DEVICE_READY(port), DEVICE_READY | |
364 | ULPS_STATE_ENTER); | |
365 | usleep_range(2000, 2500); | |
366 | ||
367 | I915_WRITE(MIPI_DEVICE_READY(port), DEVICE_READY | | |
368 | ULPS_STATE_EXIT); | |
369 | usleep_range(2000, 2500); | |
370 | ||
371 | I915_WRITE(MIPI_DEVICE_READY(port), DEVICE_READY | | |
372 | ULPS_STATE_ENTER); | |
373 | usleep_range(2000, 2500); | |
374 | ||
375 | /* Wait till Clock lanes are in LP-00 state for MIPI Port A | |
376 | * only. MIPI Port C has no similar bit for checking | |
377 | */ | |
378 | if (wait_for(((I915_READ(MIPI_PORT_CTRL(PORT_A)) & AFE_LATCHOUT) | |
379 | == 0x00000), 30)) | |
380 | DRM_ERROR("DSI LP not going Low\n"); | |
381 | ||
382 | val = I915_READ(MIPI_PORT_CTRL(port)); | |
383 | /* Disable MIPI PHY transparent latch | |
384 | * Common bit for both MIPI Port A & MIPI Port C | |
385 | */ | |
386 | I915_WRITE(MIPI_PORT_CTRL(PORT_A), val & ~LP_OUTPUT_HOLD); | |
387 | usleep_range(1000, 1500); | |
388 | ||
389 | I915_WRITE(MIPI_DEVICE_READY(port), 0x00); | |
390 | usleep_range(2000, 2500); | |
391 | } | |
1dbd7cb2 | 392 | |
be4fc046 | 393 | vlv_disable_dsi_pll(encoder); |
4e646495 | 394 | } |
20e5bf66 | 395 | |
1dbd7cb2 SK |
396 | static void intel_dsi_post_disable(struct intel_encoder *encoder) |
397 | { | |
20e5bf66 | 398 | struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; |
1dbd7cb2 | 399 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); |
20e5bf66 | 400 | u32 val; |
1dbd7cb2 SK |
401 | |
402 | DRM_DEBUG_KMS("\n"); | |
403 | ||
c315faf8 ID |
404 | intel_dsi_disable(encoder); |
405 | ||
1dbd7cb2 SK |
406 | intel_dsi_clear_device_ready(encoder); |
407 | ||
20e5bf66 SK |
408 | val = I915_READ(DSPCLK_GATE_D); |
409 | val &= ~DPOUNIT_CLOCK_GATE_DISABLE; | |
410 | I915_WRITE(DSPCLK_GATE_D, val); | |
411 | ||
1dbd7cb2 SK |
412 | if (intel_dsi->dev.dev_ops->disable_panel_power) |
413 | intel_dsi->dev.dev_ops->disable_panel_power(&intel_dsi->dev); | |
df38e655 SK |
414 | |
415 | msleep(intel_dsi->panel_off_delay); | |
416 | msleep(intel_dsi->panel_pwr_cycle_delay); | |
1dbd7cb2 | 417 | } |
4e646495 JN |
418 | |
419 | static bool intel_dsi_get_hw_state(struct intel_encoder *encoder, | |
420 | enum pipe *pipe) | |
421 | { | |
422 | struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; | |
c0beefd2 GS |
423 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); |
424 | struct drm_device *dev = encoder->base.dev; | |
6d129bea | 425 | enum intel_display_power_domain power_domain; |
c0beefd2 | 426 | u32 dpi_enabled, func; |
e7d7cad0 | 427 | enum port port; |
4e646495 JN |
428 | |
429 | DRM_DEBUG_KMS("\n"); | |
430 | ||
6d129bea | 431 | power_domain = intel_display_port_power_domain(encoder); |
f458ebbc | 432 | if (!intel_display_power_is_enabled(dev_priv, power_domain)) |
6d129bea ID |
433 | return false; |
434 | ||
4e646495 | 435 | /* XXX: this only works for one DSI output */ |
c0beefd2 | 436 | for_each_dsi_port(port, intel_dsi->ports) { |
e7d7cad0 | 437 | func = I915_READ(MIPI_DSI_FUNC_PRG(port)); |
c0beefd2 GS |
438 | dpi_enabled = I915_READ(MIPI_PORT_CTRL(port)) & |
439 | DPI_ENABLE; | |
440 | ||
441 | /* Due to some hardware limitations on BYT, MIPI Port C DPI | |
442 | * Enable bit does not get set. To check whether DSI Port C | |
443 | * was enabled in BIOS, check the Pipe B enable bit | |
444 | */ | |
445 | if (IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) && | |
446 | (port == PORT_C)) | |
447 | dpi_enabled = I915_READ(PIPECONF(PIPE_B)) & | |
448 | PIPECONF_ENABLE; | |
4e646495 | 449 | |
c0beefd2 | 450 | if (dpi_enabled || (func & CMD_MODE_DATA_WIDTH_MASK)) { |
e7d7cad0 | 451 | if (I915_READ(MIPI_DEVICE_READY(port)) & DEVICE_READY) { |
c0beefd2 | 452 | *pipe = port == PORT_A ? PIPE_A : PIPE_B; |
4e646495 JN |
453 | return true; |
454 | } | |
455 | } | |
456 | } | |
457 | ||
458 | return false; | |
459 | } | |
460 | ||
461 | static void intel_dsi_get_config(struct intel_encoder *encoder, | |
5cec258b | 462 | struct intel_crtc_state *pipe_config) |
4e646495 | 463 | { |
f573de5a | 464 | u32 pclk; |
4e646495 JN |
465 | DRM_DEBUG_KMS("\n"); |
466 | ||
f573de5a SK |
467 | /* |
468 | * DPLL_MD is not used in case of DSI, reading will get some default value | |
469 | * set dpll_md = 0 | |
470 | */ | |
471 | pipe_config->dpll_hw_state.dpll_md = 0; | |
472 | ||
473 | pclk = vlv_get_dsi_pclk(encoder, pipe_config->pipe_bpp); | |
474 | if (!pclk) | |
475 | return; | |
476 | ||
2d112de7 | 477 | pipe_config->base.adjusted_mode.crtc_clock = pclk; |
f573de5a | 478 | pipe_config->port_clock = pclk; |
4e646495 JN |
479 | } |
480 | ||
c19de8eb DL |
481 | static enum drm_mode_status |
482 | intel_dsi_mode_valid(struct drm_connector *connector, | |
483 | struct drm_display_mode *mode) | |
4e646495 JN |
484 | { |
485 | struct intel_connector *intel_connector = to_intel_connector(connector); | |
486 | struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode; | |
487 | struct intel_dsi *intel_dsi = intel_attached_dsi(connector); | |
488 | ||
489 | DRM_DEBUG_KMS("\n"); | |
490 | ||
491 | if (mode->flags & DRM_MODE_FLAG_DBLSCAN) { | |
492 | DRM_DEBUG_KMS("MODE_NO_DBLESCAN\n"); | |
493 | return MODE_NO_DBLESCAN; | |
494 | } | |
495 | ||
496 | if (fixed_mode) { | |
497 | if (mode->hdisplay > fixed_mode->hdisplay) | |
498 | return MODE_PANEL; | |
499 | if (mode->vdisplay > fixed_mode->vdisplay) | |
500 | return MODE_PANEL; | |
501 | } | |
502 | ||
503 | return intel_dsi->dev.dev_ops->mode_valid(&intel_dsi->dev, mode); | |
504 | } | |
505 | ||
506 | /* return txclkesc cycles in terms of divider and duration in us */ | |
507 | static u16 txclkesc(u32 divider, unsigned int us) | |
508 | { | |
509 | switch (divider) { | |
510 | case ESCAPE_CLOCK_DIVIDER_1: | |
511 | default: | |
512 | return 20 * us; | |
513 | case ESCAPE_CLOCK_DIVIDER_2: | |
514 | return 10 * us; | |
515 | case ESCAPE_CLOCK_DIVIDER_4: | |
516 | return 5 * us; | |
517 | } | |
518 | } | |
519 | ||
520 | /* return pixels in terms of txbyteclkhs */ | |
7f0c8605 SK |
521 | static u16 txbyteclkhs(u16 pixels, int bpp, int lane_count, |
522 | u16 burst_mode_ratio) | |
4e646495 | 523 | { |
7f0c8605 | 524 | return DIV_ROUND_UP(DIV_ROUND_UP(pixels * bpp * burst_mode_ratio, |
7f3de833 | 525 | 8 * 100), lane_count); |
4e646495 JN |
526 | } |
527 | ||
528 | static void set_dsi_timings(struct drm_encoder *encoder, | |
529 | const struct drm_display_mode *mode) | |
530 | { | |
531 | struct drm_device *dev = encoder->dev; | |
532 | struct drm_i915_private *dev_priv = dev->dev_private; | |
533 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); | |
534 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); | |
aa102d28 | 535 | enum port port; |
6e3c9717 | 536 | unsigned int bpp = intel_crtc->config->pipe_bpp; |
4e646495 JN |
537 | unsigned int lane_count = intel_dsi->lane_count; |
538 | ||
539 | u16 hactive, hfp, hsync, hbp, vfp, vsync, vbp; | |
540 | ||
541 | hactive = mode->hdisplay; | |
542 | hfp = mode->hsync_start - mode->hdisplay; | |
543 | hsync = mode->hsync_end - mode->hsync_start; | |
544 | hbp = mode->htotal - mode->hsync_end; | |
545 | ||
aa102d28 GS |
546 | if (intel_dsi->dual_link) { |
547 | hactive /= 2; | |
548 | if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) | |
549 | hactive += intel_dsi->pixel_overlap; | |
550 | hfp /= 2; | |
551 | hsync /= 2; | |
552 | hbp /= 2; | |
553 | } | |
554 | ||
4e646495 JN |
555 | vfp = mode->vsync_start - mode->vdisplay; |
556 | vsync = mode->vsync_end - mode->vsync_start; | |
557 | vbp = mode->vtotal - mode->vsync_end; | |
558 | ||
559 | /* horizontal values are in terms of high speed byte clock */ | |
7f0c8605 | 560 | hactive = txbyteclkhs(hactive, bpp, lane_count, |
7f3de833 | 561 | intel_dsi->burst_mode_ratio); |
7f0c8605 SK |
562 | hfp = txbyteclkhs(hfp, bpp, lane_count, intel_dsi->burst_mode_ratio); |
563 | hsync = txbyteclkhs(hsync, bpp, lane_count, | |
7f3de833 | 564 | intel_dsi->burst_mode_ratio); |
7f0c8605 | 565 | hbp = txbyteclkhs(hbp, bpp, lane_count, intel_dsi->burst_mode_ratio); |
4e646495 | 566 | |
aa102d28 GS |
567 | for_each_dsi_port(port, intel_dsi->ports) { |
568 | I915_WRITE(MIPI_HACTIVE_AREA_COUNT(port), hactive); | |
569 | I915_WRITE(MIPI_HFP_COUNT(port), hfp); | |
570 | ||
571 | /* meaningful for video mode non-burst sync pulse mode only, | |
572 | * can be zero for non-burst sync events and burst modes */ | |
573 | I915_WRITE(MIPI_HSYNC_PADDING_COUNT(port), hsync); | |
574 | I915_WRITE(MIPI_HBP_COUNT(port), hbp); | |
575 | ||
576 | /* vertical values are in terms of lines */ | |
577 | I915_WRITE(MIPI_VFP_COUNT(port), vfp); | |
578 | I915_WRITE(MIPI_VSYNC_PADDING_COUNT(port), vsync); | |
579 | I915_WRITE(MIPI_VBP_COUNT(port), vbp); | |
580 | } | |
4e646495 JN |
581 | } |
582 | ||
07e4fb9e | 583 | static void intel_dsi_prepare(struct intel_encoder *intel_encoder) |
4e646495 JN |
584 | { |
585 | struct drm_encoder *encoder = &intel_encoder->base; | |
586 | struct drm_device *dev = encoder->dev; | |
587 | struct drm_i915_private *dev_priv = dev->dev_private; | |
588 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); | |
589 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); | |
590 | struct drm_display_mode *adjusted_mode = | |
6e3c9717 | 591 | &intel_crtc->config->base.adjusted_mode; |
24ee0e64 | 592 | enum port port; |
6e3c9717 | 593 | unsigned int bpp = intel_crtc->config->pipe_bpp; |
4e646495 | 594 | u32 val, tmp; |
24ee0e64 | 595 | u16 mode_hdisplay; |
4e646495 | 596 | |
e7d7cad0 | 597 | DRM_DEBUG_KMS("pipe %c\n", pipe_name(intel_crtc->pipe)); |
4e646495 | 598 | |
24ee0e64 | 599 | mode_hdisplay = adjusted_mode->hdisplay; |
4e646495 | 600 | |
24ee0e64 GS |
601 | if (intel_dsi->dual_link) { |
602 | mode_hdisplay /= 2; | |
603 | if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) | |
604 | mode_hdisplay += intel_dsi->pixel_overlap; | |
605 | } | |
4e646495 | 606 | |
24ee0e64 GS |
607 | for_each_dsi_port(port, intel_dsi->ports) { |
608 | /* escape clock divider, 20MHz, shared for A and C. | |
609 | * device ready must be off when doing this! txclkesc? */ | |
610 | tmp = I915_READ(MIPI_CTRL(PORT_A)); | |
611 | tmp &= ~ESCAPE_CLOCK_DIVIDER_MASK; | |
612 | I915_WRITE(MIPI_CTRL(PORT_A), tmp | ESCAPE_CLOCK_DIVIDER_1); | |
613 | ||
614 | /* read request priority is per pipe */ | |
615 | tmp = I915_READ(MIPI_CTRL(port)); | |
616 | tmp &= ~READ_REQUEST_PRIORITY_MASK; | |
617 | I915_WRITE(MIPI_CTRL(port), tmp | READ_REQUEST_PRIORITY_HIGH); | |
618 | ||
619 | /* XXX: why here, why like this? handling in irq handler?! */ | |
620 | I915_WRITE(MIPI_INTR_STAT(port), 0xffffffff); | |
621 | I915_WRITE(MIPI_INTR_EN(port), 0xffffffff); | |
622 | ||
623 | I915_WRITE(MIPI_DPHY_PARAM(port), intel_dsi->dphy_reg); | |
624 | ||
625 | I915_WRITE(MIPI_DPI_RESOLUTION(port), | |
626 | adjusted_mode->vdisplay << VERTICAL_ADDRESS_SHIFT | | |
627 | mode_hdisplay << HORIZONTAL_ADDRESS_SHIFT); | |
628 | } | |
4e646495 JN |
629 | |
630 | set_dsi_timings(encoder, adjusted_mode); | |
631 | ||
632 | val = intel_dsi->lane_count << DATA_LANES_PRG_REG_SHIFT; | |
633 | if (is_cmd_mode(intel_dsi)) { | |
634 | val |= intel_dsi->channel << CMD_MODE_CHANNEL_NUMBER_SHIFT; | |
635 | val |= CMD_MODE_DATA_WIDTH_8_BIT; /* XXX */ | |
636 | } else { | |
637 | val |= intel_dsi->channel << VID_MODE_CHANNEL_NUMBER_SHIFT; | |
638 | ||
639 | /* XXX: cross-check bpp vs. pixel format? */ | |
640 | val |= intel_dsi->pixel_format; | |
641 | } | |
4e646495 | 642 | |
24ee0e64 GS |
643 | tmp = 0; |
644 | if (intel_dsi->eotp_pkt == 0) | |
645 | tmp |= EOT_DISABLE; | |
646 | if (intel_dsi->clock_stop) | |
647 | tmp |= CLOCKSTOP; | |
4e646495 | 648 | |
24ee0e64 GS |
649 | for_each_dsi_port(port, intel_dsi->ports) { |
650 | I915_WRITE(MIPI_DSI_FUNC_PRG(port), val); | |
651 | ||
652 | /* timeouts for recovery. one frame IIUC. if counter expires, | |
653 | * EOT and stop state. */ | |
654 | ||
655 | /* | |
656 | * In burst mode, value greater than one DPI line Time in byte | |
657 | * clock (txbyteclkhs) To timeout this timer 1+ of the above | |
658 | * said value is recommended. | |
659 | * | |
660 | * In non-burst mode, Value greater than one DPI frame time in | |
661 | * byte clock(txbyteclkhs) To timeout this timer 1+ of the above | |
662 | * said value is recommended. | |
663 | * | |
664 | * In DBI only mode, value greater than one DBI frame time in | |
665 | * byte clock(txbyteclkhs) To timeout this timer 1+ of the above | |
666 | * said value is recommended. | |
667 | */ | |
4e646495 | 668 | |
24ee0e64 GS |
669 | if (is_vid_mode(intel_dsi) && |
670 | intel_dsi->video_mode_format == VIDEO_MODE_BURST) { | |
671 | I915_WRITE(MIPI_HS_TX_TIMEOUT(port), | |
672 | txbyteclkhs(adjusted_mode->htotal, bpp, | |
673 | intel_dsi->lane_count, | |
674 | intel_dsi->burst_mode_ratio) + 1); | |
675 | } else { | |
676 | I915_WRITE(MIPI_HS_TX_TIMEOUT(port), | |
677 | txbyteclkhs(adjusted_mode->vtotal * | |
678 | adjusted_mode->htotal, | |
679 | bpp, intel_dsi->lane_count, | |
680 | intel_dsi->burst_mode_ratio) + 1); | |
681 | } | |
682 | I915_WRITE(MIPI_LP_RX_TIMEOUT(port), intel_dsi->lp_rx_timeout); | |
683 | I915_WRITE(MIPI_TURN_AROUND_TIMEOUT(port), | |
684 | intel_dsi->turn_arnd_val); | |
685 | I915_WRITE(MIPI_DEVICE_RESET_TIMER(port), | |
686 | intel_dsi->rst_timer_val); | |
f1c79f16 | 687 | |
24ee0e64 | 688 | /* dphy stuff */ |
f1c79f16 | 689 | |
24ee0e64 GS |
690 | /* in terms of low power clock */ |
691 | I915_WRITE(MIPI_INIT_COUNT(port), | |
692 | txclkesc(intel_dsi->escape_clk_div, 100)); | |
4e646495 | 693 | |
4e646495 | 694 | |
24ee0e64 GS |
695 | /* recovery disables */ |
696 | I915_WRITE(MIPI_EOT_DISABLE(port), val); | |
cf4dbd2e | 697 | |
24ee0e64 GS |
698 | /* in terms of low power clock */ |
699 | I915_WRITE(MIPI_INIT_COUNT(port), intel_dsi->init_count); | |
4e646495 | 700 | |
24ee0e64 GS |
701 | /* in terms of txbyteclkhs. actual high to low switch + |
702 | * MIPI_STOP_STATE_STALL * MIPI_LP_BYTECLK. | |
703 | * | |
704 | * XXX: write MIPI_STOP_STATE_STALL? | |
705 | */ | |
706 | I915_WRITE(MIPI_HIGH_LOW_SWITCH_COUNT(port), | |
707 | intel_dsi->hs_to_lp_count); | |
708 | ||
709 | /* XXX: low power clock equivalence in terms of byte clock. | |
710 | * the number of byte clocks occupied in one low power clock. | |
711 | * based on txbyteclkhs and txclkesc. | |
712 | * txclkesc time / txbyteclk time * (105 + MIPI_STOP_STATE_STALL | |
713 | * ) / 105.??? | |
714 | */ | |
715 | I915_WRITE(MIPI_LP_BYTECLK(port), intel_dsi->lp_byte_clk); | |
716 | ||
717 | /* the bw essential for transmitting 16 long packets containing | |
718 | * 252 bytes meant for dcs write memory command is programmed in | |
719 | * this register in terms of byte clocks. based on dsi transfer | |
720 | * rate and the number of lanes configured the time taken to | |
721 | * transmit 16 long packets in a dsi stream varies. */ | |
722 | I915_WRITE(MIPI_DBI_BW_CTRL(port), intel_dsi->bw_timer); | |
723 | ||
724 | I915_WRITE(MIPI_CLK_LANE_SWITCH_TIME_CNT(port), | |
725 | intel_dsi->clk_lp_to_hs_count << LP_HS_SSW_CNT_SHIFT | | |
726 | intel_dsi->clk_hs_to_lp_count << HS_LP_PWR_SW_CNT_SHIFT); | |
727 | ||
728 | if (is_vid_mode(intel_dsi)) | |
729 | /* Some panels might have resolution which is not a | |
730 | * multiple of 64 like 1366 x 768. Enable RANDOM | |
731 | * resolution support for such panels by default */ | |
732 | I915_WRITE(MIPI_VIDEO_MODE_FORMAT(port), | |
733 | intel_dsi->video_frmt_cfg_bits | | |
734 | intel_dsi->video_mode_format | | |
735 | IP_TG_CONFIG | | |
736 | RANDOM_DPI_DISPLAY_RESOLUTION); | |
737 | } | |
4e646495 JN |
738 | } |
739 | ||
07e4fb9e DV |
740 | static void intel_dsi_pre_pll_enable(struct intel_encoder *encoder) |
741 | { | |
742 | DRM_DEBUG_KMS("\n"); | |
743 | ||
744 | intel_dsi_prepare(encoder); | |
745 | ||
746 | vlv_enable_dsi_pll(encoder); | |
747 | } | |
748 | ||
4e646495 JN |
749 | static enum drm_connector_status |
750 | intel_dsi_detect(struct drm_connector *connector, bool force) | |
751 | { | |
752 | struct intel_dsi *intel_dsi = intel_attached_dsi(connector); | |
671dedd2 ID |
753 | struct intel_encoder *intel_encoder = &intel_dsi->base; |
754 | enum intel_display_power_domain power_domain; | |
755 | enum drm_connector_status connector_status; | |
756 | struct drm_i915_private *dev_priv = intel_encoder->base.dev->dev_private; | |
757 | ||
4e646495 | 758 | DRM_DEBUG_KMS("\n"); |
671dedd2 ID |
759 | power_domain = intel_display_port_power_domain(intel_encoder); |
760 | ||
761 | intel_display_power_get(dev_priv, power_domain); | |
762 | connector_status = intel_dsi->dev.dev_ops->detect(&intel_dsi->dev); | |
763 | intel_display_power_put(dev_priv, power_domain); | |
764 | ||
765 | return connector_status; | |
4e646495 JN |
766 | } |
767 | ||
768 | static int intel_dsi_get_modes(struct drm_connector *connector) | |
769 | { | |
770 | struct intel_connector *intel_connector = to_intel_connector(connector); | |
771 | struct drm_display_mode *mode; | |
772 | ||
773 | DRM_DEBUG_KMS("\n"); | |
774 | ||
775 | if (!intel_connector->panel.fixed_mode) { | |
776 | DRM_DEBUG_KMS("no fixed mode\n"); | |
777 | return 0; | |
778 | } | |
779 | ||
780 | mode = drm_mode_duplicate(connector->dev, | |
781 | intel_connector->panel.fixed_mode); | |
782 | if (!mode) { | |
783 | DRM_DEBUG_KMS("drm_mode_duplicate failed\n"); | |
784 | return 0; | |
785 | } | |
786 | ||
787 | drm_mode_probed_add(connector, mode); | |
788 | return 1; | |
789 | } | |
790 | ||
791 | static void intel_dsi_destroy(struct drm_connector *connector) | |
792 | { | |
793 | struct intel_connector *intel_connector = to_intel_connector(connector); | |
794 | ||
795 | DRM_DEBUG_KMS("\n"); | |
796 | intel_panel_fini(&intel_connector->panel); | |
4e646495 JN |
797 | drm_connector_cleanup(connector); |
798 | kfree(connector); | |
799 | } | |
800 | ||
801 | static const struct drm_encoder_funcs intel_dsi_funcs = { | |
802 | .destroy = intel_encoder_destroy, | |
803 | }; | |
804 | ||
805 | static const struct drm_connector_helper_funcs intel_dsi_connector_helper_funcs = { | |
806 | .get_modes = intel_dsi_get_modes, | |
807 | .mode_valid = intel_dsi_mode_valid, | |
808 | .best_encoder = intel_best_encoder, | |
809 | }; | |
810 | ||
811 | static const struct drm_connector_funcs intel_dsi_connector_funcs = { | |
812 | .dpms = intel_connector_dpms, | |
813 | .detect = intel_dsi_detect, | |
814 | .destroy = intel_dsi_destroy, | |
815 | .fill_modes = drm_helper_probe_single_connector_modes, | |
816 | }; | |
817 | ||
4328633d | 818 | void intel_dsi_init(struct drm_device *dev) |
4e646495 JN |
819 | { |
820 | struct intel_dsi *intel_dsi; | |
821 | struct intel_encoder *intel_encoder; | |
822 | struct drm_encoder *encoder; | |
823 | struct intel_connector *intel_connector; | |
824 | struct drm_connector *connector; | |
825 | struct drm_display_mode *fixed_mode = NULL; | |
b6fdd0f2 | 826 | struct drm_i915_private *dev_priv = dev->dev_private; |
4e646495 JN |
827 | const struct intel_dsi_device *dsi; |
828 | unsigned int i; | |
829 | ||
830 | DRM_DEBUG_KMS("\n"); | |
831 | ||
3e6bd011 SK |
832 | /* There is no detection method for MIPI so rely on VBT */ |
833 | if (!dev_priv->vbt.has_mipi) | |
4328633d | 834 | return; |
3e6bd011 | 835 | |
868d665b CJ |
836 | if (IS_VALLEYVIEW(dev)) { |
837 | dev_priv->mipi_mmio_base = VLV_MIPI_BASE; | |
838 | } else { | |
839 | DRM_ERROR("Unsupported Mipi device to reg base"); | |
840 | return; | |
841 | } | |
3e6bd011 | 842 | |
4e646495 JN |
843 | intel_dsi = kzalloc(sizeof(*intel_dsi), GFP_KERNEL); |
844 | if (!intel_dsi) | |
4328633d | 845 | return; |
4e646495 JN |
846 | |
847 | intel_connector = kzalloc(sizeof(*intel_connector), GFP_KERNEL); | |
848 | if (!intel_connector) { | |
849 | kfree(intel_dsi); | |
4328633d | 850 | return; |
4e646495 JN |
851 | } |
852 | ||
853 | intel_encoder = &intel_dsi->base; | |
854 | encoder = &intel_encoder->base; | |
855 | intel_dsi->attached_connector = intel_connector; | |
856 | ||
857 | connector = &intel_connector->base; | |
858 | ||
859 | drm_encoder_init(dev, encoder, &intel_dsi_funcs, DRM_MODE_ENCODER_DSI); | |
860 | ||
861 | /* XXX: very likely not all of these are needed */ | |
862 | intel_encoder->hot_plug = intel_dsi_hot_plug; | |
863 | intel_encoder->compute_config = intel_dsi_compute_config; | |
864 | intel_encoder->pre_pll_enable = intel_dsi_pre_pll_enable; | |
865 | intel_encoder->pre_enable = intel_dsi_pre_enable; | |
2634fd7f | 866 | intel_encoder->enable = intel_dsi_enable_nop; |
c315faf8 | 867 | intel_encoder->disable = intel_dsi_pre_disable; |
4e646495 JN |
868 | intel_encoder->post_disable = intel_dsi_post_disable; |
869 | intel_encoder->get_hw_state = intel_dsi_get_hw_state; | |
870 | intel_encoder->get_config = intel_dsi_get_config; | |
871 | ||
872 | intel_connector->get_hw_state = intel_connector_get_hw_state; | |
4932e2c3 | 873 | intel_connector->unregister = intel_connector_unregister; |
4e646495 | 874 | |
e7d7cad0 | 875 | /* Pipe A maps to MIPI DSI port A, pipe B maps to MIPI DSI port C */ |
17af40a8 | 876 | if (dev_priv->vbt.dsi.port == DVO_PORT_MIPIA) { |
e7d7cad0 | 877 | intel_encoder->crtc_mask = (1 << PIPE_A); |
17af40a8 JN |
878 | intel_dsi->ports = (1 << PORT_A); |
879 | } else if (dev_priv->vbt.dsi.port == DVO_PORT_MIPIC) { | |
e7d7cad0 | 880 | intel_encoder->crtc_mask = (1 << PIPE_B); |
17af40a8 JN |
881 | intel_dsi->ports = (1 << PORT_C); |
882 | } | |
e7d7cad0 | 883 | |
4e646495 JN |
884 | for (i = 0; i < ARRAY_SIZE(intel_dsi_devices); i++) { |
885 | dsi = &intel_dsi_devices[i]; | |
886 | intel_dsi->dev = *dsi; | |
887 | ||
888 | if (dsi->dev_ops->init(&intel_dsi->dev)) | |
889 | break; | |
890 | } | |
891 | ||
892 | if (i == ARRAY_SIZE(intel_dsi_devices)) { | |
893 | DRM_DEBUG_KMS("no device found\n"); | |
894 | goto err; | |
895 | } | |
896 | ||
897 | intel_encoder->type = INTEL_OUTPUT_DSI; | |
bc079e8b | 898 | intel_encoder->cloneable = 0; |
4e646495 JN |
899 | drm_connector_init(dev, connector, &intel_dsi_connector_funcs, |
900 | DRM_MODE_CONNECTOR_DSI); | |
901 | ||
902 | drm_connector_helper_add(connector, &intel_dsi_connector_helper_funcs); | |
903 | ||
904 | connector->display_info.subpixel_order = SubPixelHorizontalRGB; /*XXX*/ | |
905 | connector->interlace_allowed = false; | |
906 | connector->doublescan_allowed = false; | |
907 | ||
908 | intel_connector_attach_encoder(intel_connector, intel_encoder); | |
909 | ||
34ea3d38 | 910 | drm_connector_register(connector); |
4e646495 JN |
911 | |
912 | fixed_mode = dsi->dev_ops->get_modes(&intel_dsi->dev); | |
913 | if (!fixed_mode) { | |
914 | DRM_DEBUG_KMS("no fixed mode\n"); | |
915 | goto err; | |
916 | } | |
917 | ||
918 | fixed_mode->type |= DRM_MODE_TYPE_PREFERRED; | |
4b6ed685 | 919 | intel_panel_init(&intel_connector->panel, fixed_mode, NULL); |
4e646495 | 920 | |
4328633d | 921 | return; |
4e646495 JN |
922 | |
923 | err: | |
924 | drm_encoder_cleanup(&intel_encoder->base); | |
925 | kfree(intel_dsi); | |
926 | kfree(intel_connector); | |
4e646495 | 927 | } |