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4e646495 JN |
1 | /* |
2 | * Copyright © 2013 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
21 | * DEALINGS IN THE SOFTWARE. | |
22 | * | |
23 | * Author: Jani Nikula <jani.nikula@intel.com> | |
24 | */ | |
25 | ||
26 | #include <drm/drmP.h> | |
27 | #include <drm/drm_crtc.h> | |
28 | #include <drm/drm_edid.h> | |
29 | #include <drm/i915_drm.h> | |
30 | #include <linux/slab.h> | |
31 | #include "i915_drv.h" | |
32 | #include "intel_drv.h" | |
33 | #include "intel_dsi.h" | |
34 | #include "intel_dsi_cmd.h" | |
35 | ||
36 | /* the sub-encoders aka panel drivers */ | |
37 | static const struct intel_dsi_device intel_dsi_devices[] = { | |
38 | }; | |
39 | ||
e9fe51c6 | 40 | static void band_gap_reset(struct drm_i915_private *dev_priv) |
4ce8c9a7 SK |
41 | { |
42 | mutex_lock(&dev_priv->dpio_lock); | |
43 | ||
e9fe51c6 SK |
44 | vlv_flisdsi_write(dev_priv, 0x08, 0x0001); |
45 | vlv_flisdsi_write(dev_priv, 0x0F, 0x0005); | |
46 | vlv_flisdsi_write(dev_priv, 0x0F, 0x0025); | |
47 | udelay(150); | |
48 | vlv_flisdsi_write(dev_priv, 0x0F, 0x0000); | |
49 | vlv_flisdsi_write(dev_priv, 0x08, 0x0000); | |
4ce8c9a7 SK |
50 | |
51 | mutex_unlock(&dev_priv->dpio_lock); | |
4ce8c9a7 SK |
52 | } |
53 | ||
4e646495 JN |
54 | static struct intel_dsi *intel_attached_dsi(struct drm_connector *connector) |
55 | { | |
56 | return container_of(intel_attached_encoder(connector), | |
57 | struct intel_dsi, base); | |
58 | } | |
59 | ||
60 | static inline bool is_vid_mode(struct intel_dsi *intel_dsi) | |
61 | { | |
62 | return intel_dsi->dev.type == INTEL_DSI_VIDEO_MODE; | |
63 | } | |
64 | ||
65 | static inline bool is_cmd_mode(struct intel_dsi *intel_dsi) | |
66 | { | |
67 | return intel_dsi->dev.type == INTEL_DSI_COMMAND_MODE; | |
68 | } | |
69 | ||
70 | static void intel_dsi_hot_plug(struct intel_encoder *encoder) | |
71 | { | |
72 | DRM_DEBUG_KMS("\n"); | |
73 | } | |
74 | ||
75 | static bool intel_dsi_compute_config(struct intel_encoder *encoder, | |
76 | struct intel_crtc_config *config) | |
77 | { | |
78 | struct intel_dsi *intel_dsi = container_of(encoder, struct intel_dsi, | |
79 | base); | |
80 | struct intel_connector *intel_connector = intel_dsi->attached_connector; | |
81 | struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode; | |
82 | struct drm_display_mode *adjusted_mode = &config->adjusted_mode; | |
83 | struct drm_display_mode *mode = &config->requested_mode; | |
84 | ||
85 | DRM_DEBUG_KMS("\n"); | |
86 | ||
87 | if (fixed_mode) | |
88 | intel_fixed_panel_mode(fixed_mode, adjusted_mode); | |
89 | ||
90 | if (intel_dsi->dev.dev_ops->mode_fixup) | |
91 | return intel_dsi->dev.dev_ops->mode_fixup(&intel_dsi->dev, | |
92 | mode, adjusted_mode); | |
93 | ||
94 | return true; | |
95 | } | |
96 | ||
97 | static void intel_dsi_pre_pll_enable(struct intel_encoder *encoder) | |
98 | { | |
99 | DRM_DEBUG_KMS("\n"); | |
be4fc046 | 100 | |
101 | vlv_enable_dsi_pll(encoder); | |
4e646495 JN |
102 | } |
103 | ||
104 | static void intel_dsi_pre_enable(struct intel_encoder *encoder) | |
105 | { | |
106 | DRM_DEBUG_KMS("\n"); | |
107 | } | |
108 | ||
109 | static void intel_dsi_enable(struct intel_encoder *encoder) | |
110 | { | |
111 | struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; | |
112 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); | |
113 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); | |
114 | int pipe = intel_crtc->pipe; | |
115 | u32 temp; | |
116 | ||
117 | DRM_DEBUG_KMS("\n"); | |
118 | ||
b9f5e07d SK |
119 | if (intel_dsi->dev.dev_ops->panel_reset) |
120 | intel_dsi->dev.dev_ops->panel_reset(&intel_dsi->dev); | |
121 | ||
4e646495 JN |
122 | temp = I915_READ(MIPI_DEVICE_READY(pipe)); |
123 | if ((temp & DEVICE_READY) == 0) { | |
124 | temp &= ~ULPS_STATE_MASK; | |
125 | I915_WRITE(MIPI_DEVICE_READY(pipe), temp | DEVICE_READY); | |
126 | } else if (temp & ULPS_STATE_MASK) { | |
127 | temp &= ~ULPS_STATE_MASK; | |
128 | I915_WRITE(MIPI_DEVICE_READY(pipe), temp | ULPS_STATE_EXIT); | |
129 | /* | |
130 | * We need to ensure that there is a minimum of 1 ms time | |
131 | * available before clearing the UPLS exit state. | |
132 | */ | |
133 | msleep(2); | |
134 | I915_WRITE(MIPI_DEVICE_READY(pipe), temp); | |
135 | } | |
136 | ||
b9f5e07d SK |
137 | if (intel_dsi->dev.dev_ops->send_otp_cmds) |
138 | intel_dsi->dev.dev_ops->send_otp_cmds(&intel_dsi->dev); | |
139 | ||
4e646495 JN |
140 | if (is_cmd_mode(intel_dsi)) |
141 | I915_WRITE(MIPI_MAX_RETURN_PKT_SIZE(pipe), 8 * 4); | |
142 | ||
143 | if (is_vid_mode(intel_dsi)) { | |
144 | msleep(20); /* XXX */ | |
145 | dpi_send_cmd(intel_dsi, TURN_ON); | |
146 | msleep(100); | |
147 | ||
148 | /* assert ip_tg_enable signal */ | |
149 | temp = I915_READ(MIPI_PORT_CTRL(pipe)); | |
150 | I915_WRITE(MIPI_PORT_CTRL(pipe), temp | DPI_ENABLE); | |
151 | POSTING_READ(MIPI_PORT_CTRL(pipe)); | |
152 | } | |
153 | ||
b9f5e07d SK |
154 | if (intel_dsi->dev.dev_ops->enable) |
155 | intel_dsi->dev.dev_ops->enable(&intel_dsi->dev); | |
4e646495 JN |
156 | } |
157 | ||
158 | static void intel_dsi_disable(struct intel_encoder *encoder) | |
159 | { | |
160 | struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; | |
161 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); | |
162 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); | |
163 | int pipe = intel_crtc->pipe; | |
164 | u32 temp; | |
165 | ||
166 | DRM_DEBUG_KMS("\n"); | |
167 | ||
168 | intel_dsi->dev.dev_ops->disable(&intel_dsi->dev); | |
169 | ||
170 | if (is_vid_mode(intel_dsi)) { | |
171 | dpi_send_cmd(intel_dsi, SHUTDOWN); | |
172 | msleep(10); | |
173 | ||
174 | /* de-assert ip_tg_enable signal */ | |
175 | temp = I915_READ(MIPI_PORT_CTRL(pipe)); | |
176 | I915_WRITE(MIPI_PORT_CTRL(pipe), temp & ~DPI_ENABLE); | |
177 | POSTING_READ(MIPI_PORT_CTRL(pipe)); | |
178 | ||
179 | msleep(2); | |
180 | } | |
181 | ||
182 | temp = I915_READ(MIPI_DEVICE_READY(pipe)); | |
183 | if (temp & DEVICE_READY) { | |
184 | temp &= ~DEVICE_READY; | |
185 | temp &= ~ULPS_STATE_MASK; | |
186 | I915_WRITE(MIPI_DEVICE_READY(pipe), temp); | |
187 | } | |
188 | } | |
189 | ||
190 | static void intel_dsi_post_disable(struct intel_encoder *encoder) | |
191 | { | |
192 | DRM_DEBUG_KMS("\n"); | |
be4fc046 | 193 | |
194 | vlv_disable_dsi_pll(encoder); | |
4e646495 JN |
195 | } |
196 | ||
197 | static bool intel_dsi_get_hw_state(struct intel_encoder *encoder, | |
198 | enum pipe *pipe) | |
199 | { | |
200 | struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; | |
201 | u32 port, func; | |
202 | enum pipe p; | |
203 | ||
204 | DRM_DEBUG_KMS("\n"); | |
205 | ||
206 | /* XXX: this only works for one DSI output */ | |
207 | for (p = PIPE_A; p <= PIPE_B; p++) { | |
208 | port = I915_READ(MIPI_PORT_CTRL(p)); | |
209 | func = I915_READ(MIPI_DSI_FUNC_PRG(p)); | |
210 | ||
211 | if ((port & DPI_ENABLE) || (func & CMD_MODE_DATA_WIDTH_MASK)) { | |
212 | if (I915_READ(MIPI_DEVICE_READY(p)) & DEVICE_READY) { | |
213 | *pipe = p; | |
214 | return true; | |
215 | } | |
216 | } | |
217 | } | |
218 | ||
219 | return false; | |
220 | } | |
221 | ||
222 | static void intel_dsi_get_config(struct intel_encoder *encoder, | |
223 | struct intel_crtc_config *pipe_config) | |
224 | { | |
225 | DRM_DEBUG_KMS("\n"); | |
226 | ||
227 | /* XXX: read flags, set to adjusted_mode */ | |
228 | } | |
229 | ||
c19de8eb DL |
230 | static enum drm_mode_status |
231 | intel_dsi_mode_valid(struct drm_connector *connector, | |
232 | struct drm_display_mode *mode) | |
4e646495 JN |
233 | { |
234 | struct intel_connector *intel_connector = to_intel_connector(connector); | |
235 | struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode; | |
236 | struct intel_dsi *intel_dsi = intel_attached_dsi(connector); | |
237 | ||
238 | DRM_DEBUG_KMS("\n"); | |
239 | ||
240 | if (mode->flags & DRM_MODE_FLAG_DBLSCAN) { | |
241 | DRM_DEBUG_KMS("MODE_NO_DBLESCAN\n"); | |
242 | return MODE_NO_DBLESCAN; | |
243 | } | |
244 | ||
245 | if (fixed_mode) { | |
246 | if (mode->hdisplay > fixed_mode->hdisplay) | |
247 | return MODE_PANEL; | |
248 | if (mode->vdisplay > fixed_mode->vdisplay) | |
249 | return MODE_PANEL; | |
250 | } | |
251 | ||
252 | return intel_dsi->dev.dev_ops->mode_valid(&intel_dsi->dev, mode); | |
253 | } | |
254 | ||
255 | /* return txclkesc cycles in terms of divider and duration in us */ | |
256 | static u16 txclkesc(u32 divider, unsigned int us) | |
257 | { | |
258 | switch (divider) { | |
259 | case ESCAPE_CLOCK_DIVIDER_1: | |
260 | default: | |
261 | return 20 * us; | |
262 | case ESCAPE_CLOCK_DIVIDER_2: | |
263 | return 10 * us; | |
264 | case ESCAPE_CLOCK_DIVIDER_4: | |
265 | return 5 * us; | |
266 | } | |
267 | } | |
268 | ||
269 | /* return pixels in terms of txbyteclkhs */ | |
270 | static u16 txbyteclkhs(u16 pixels, int bpp, int lane_count) | |
271 | { | |
272 | return DIV_ROUND_UP(DIV_ROUND_UP(pixels * bpp, 8), lane_count); | |
273 | } | |
274 | ||
275 | static void set_dsi_timings(struct drm_encoder *encoder, | |
276 | const struct drm_display_mode *mode) | |
277 | { | |
278 | struct drm_device *dev = encoder->dev; | |
279 | struct drm_i915_private *dev_priv = dev->dev_private; | |
280 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); | |
281 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); | |
282 | int pipe = intel_crtc->pipe; | |
283 | unsigned int bpp = intel_crtc->config.pipe_bpp; | |
284 | unsigned int lane_count = intel_dsi->lane_count; | |
285 | ||
286 | u16 hactive, hfp, hsync, hbp, vfp, vsync, vbp; | |
287 | ||
288 | hactive = mode->hdisplay; | |
289 | hfp = mode->hsync_start - mode->hdisplay; | |
290 | hsync = mode->hsync_end - mode->hsync_start; | |
291 | hbp = mode->htotal - mode->hsync_end; | |
292 | ||
293 | vfp = mode->vsync_start - mode->vdisplay; | |
294 | vsync = mode->vsync_end - mode->vsync_start; | |
295 | vbp = mode->vtotal - mode->vsync_end; | |
296 | ||
297 | /* horizontal values are in terms of high speed byte clock */ | |
298 | hactive = txbyteclkhs(hactive, bpp, lane_count); | |
299 | hfp = txbyteclkhs(hfp, bpp, lane_count); | |
300 | hsync = txbyteclkhs(hsync, bpp, lane_count); | |
301 | hbp = txbyteclkhs(hbp, bpp, lane_count); | |
302 | ||
303 | I915_WRITE(MIPI_HACTIVE_AREA_COUNT(pipe), hactive); | |
304 | I915_WRITE(MIPI_HFP_COUNT(pipe), hfp); | |
305 | ||
306 | /* meaningful for video mode non-burst sync pulse mode only, can be zero | |
307 | * for non-burst sync events and burst modes */ | |
308 | I915_WRITE(MIPI_HSYNC_PADDING_COUNT(pipe), hsync); | |
309 | I915_WRITE(MIPI_HBP_COUNT(pipe), hbp); | |
310 | ||
311 | /* vertical values are in terms of lines */ | |
312 | I915_WRITE(MIPI_VFP_COUNT(pipe), vfp); | |
313 | I915_WRITE(MIPI_VSYNC_PADDING_COUNT(pipe), vsync); | |
314 | I915_WRITE(MIPI_VBP_COUNT(pipe), vbp); | |
315 | } | |
316 | ||
317 | static void intel_dsi_mode_set(struct intel_encoder *intel_encoder) | |
318 | { | |
319 | struct drm_encoder *encoder = &intel_encoder->base; | |
320 | struct drm_device *dev = encoder->dev; | |
321 | struct drm_i915_private *dev_priv = dev->dev_private; | |
322 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); | |
323 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); | |
324 | struct drm_display_mode *adjusted_mode = | |
325 | &intel_crtc->config.adjusted_mode; | |
326 | int pipe = intel_crtc->pipe; | |
327 | unsigned int bpp = intel_crtc->config.pipe_bpp; | |
328 | u32 val, tmp; | |
329 | ||
6f2bcceb | 330 | DRM_DEBUG_KMS("pipe %c\n", pipe_name(pipe)); |
4e646495 | 331 | |
be4fc046 | 332 | /* Update the DSI PLL */ |
333 | vlv_enable_dsi_pll(intel_encoder); | |
334 | ||
4ce8c9a7 | 335 | /* XXX: Location of the call */ |
e9fe51c6 | 336 | band_gap_reset(dev_priv); |
4ce8c9a7 | 337 | |
4e646495 JN |
338 | /* escape clock divider, 20MHz, shared for A and C. device ready must be |
339 | * off when doing this! txclkesc? */ | |
340 | tmp = I915_READ(MIPI_CTRL(0)); | |
341 | tmp &= ~ESCAPE_CLOCK_DIVIDER_MASK; | |
342 | I915_WRITE(MIPI_CTRL(0), tmp | ESCAPE_CLOCK_DIVIDER_1); | |
343 | ||
344 | /* read request priority is per pipe */ | |
345 | tmp = I915_READ(MIPI_CTRL(pipe)); | |
346 | tmp &= ~READ_REQUEST_PRIORITY_MASK; | |
347 | I915_WRITE(MIPI_CTRL(pipe), tmp | READ_REQUEST_PRIORITY_HIGH); | |
348 | ||
349 | /* XXX: why here, why like this? handling in irq handler?! */ | |
350 | I915_WRITE(MIPI_INTR_STAT(pipe), 0xffffffff); | |
351 | I915_WRITE(MIPI_INTR_EN(pipe), 0xffffffff); | |
352 | ||
353 | I915_WRITE(MIPI_DPHY_PARAM(pipe), | |
354 | 0x3c << EXIT_ZERO_COUNT_SHIFT | | |
355 | 0x1f << TRAIL_COUNT_SHIFT | | |
356 | 0xc5 << CLK_ZERO_COUNT_SHIFT | | |
357 | 0x1f << PREPARE_COUNT_SHIFT); | |
358 | ||
359 | I915_WRITE(MIPI_DPI_RESOLUTION(pipe), | |
360 | adjusted_mode->vdisplay << VERTICAL_ADDRESS_SHIFT | | |
361 | adjusted_mode->hdisplay << HORIZONTAL_ADDRESS_SHIFT); | |
362 | ||
363 | set_dsi_timings(encoder, adjusted_mode); | |
364 | ||
365 | val = intel_dsi->lane_count << DATA_LANES_PRG_REG_SHIFT; | |
366 | if (is_cmd_mode(intel_dsi)) { | |
367 | val |= intel_dsi->channel << CMD_MODE_CHANNEL_NUMBER_SHIFT; | |
368 | val |= CMD_MODE_DATA_WIDTH_8_BIT; /* XXX */ | |
369 | } else { | |
370 | val |= intel_dsi->channel << VID_MODE_CHANNEL_NUMBER_SHIFT; | |
371 | ||
372 | /* XXX: cross-check bpp vs. pixel format? */ | |
373 | val |= intel_dsi->pixel_format; | |
374 | } | |
375 | I915_WRITE(MIPI_DSI_FUNC_PRG(pipe), val); | |
376 | ||
377 | /* timeouts for recovery. one frame IIUC. if counter expires, EOT and | |
378 | * stop state. */ | |
379 | ||
380 | /* | |
381 | * In burst mode, value greater than one DPI line Time in byte clock | |
382 | * (txbyteclkhs) To timeout this timer 1+ of the above said value is | |
383 | * recommended. | |
384 | * | |
385 | * In non-burst mode, Value greater than one DPI frame time in byte | |
386 | * clock(txbyteclkhs) To timeout this timer 1+ of the above said value | |
387 | * is recommended. | |
388 | * | |
389 | * In DBI only mode, value greater than one DBI frame time in byte | |
390 | * clock(txbyteclkhs) To timeout this timer 1+ of the above said value | |
391 | * is recommended. | |
392 | */ | |
393 | ||
394 | if (is_vid_mode(intel_dsi) && | |
395 | intel_dsi->video_mode_format == VIDEO_MODE_BURST) { | |
396 | I915_WRITE(MIPI_HS_TX_TIMEOUT(pipe), | |
397 | txbyteclkhs(adjusted_mode->htotal, bpp, | |
398 | intel_dsi->lane_count) + 1); | |
399 | } else { | |
400 | I915_WRITE(MIPI_HS_TX_TIMEOUT(pipe), | |
401 | txbyteclkhs(adjusted_mode->vtotal * | |
402 | adjusted_mode->htotal, | |
403 | bpp, intel_dsi->lane_count) + 1); | |
404 | } | |
405 | I915_WRITE(MIPI_LP_RX_TIMEOUT(pipe), 8309); /* max */ | |
406 | I915_WRITE(MIPI_TURN_AROUND_TIMEOUT(pipe), 0x14); /* max */ | |
407 | I915_WRITE(MIPI_DEVICE_RESET_TIMER(pipe), 0xffff); /* max */ | |
408 | ||
409 | /* dphy stuff */ | |
410 | ||
411 | /* in terms of low power clock */ | |
412 | I915_WRITE(MIPI_INIT_COUNT(pipe), txclkesc(ESCAPE_CLOCK_DIVIDER_1, 100)); | |
413 | ||
414 | /* recovery disables */ | |
415 | I915_WRITE(MIPI_EOT_DISABLE(pipe), intel_dsi->eot_disable); | |
416 | ||
417 | /* in terms of txbyteclkhs. actual high to low switch + | |
418 | * MIPI_STOP_STATE_STALL * MIPI_LP_BYTECLK. | |
419 | * | |
420 | * XXX: write MIPI_STOP_STATE_STALL? | |
421 | */ | |
422 | I915_WRITE(MIPI_HIGH_LOW_SWITCH_COUNT(pipe), 0x46); | |
423 | ||
424 | /* XXX: low power clock equivalence in terms of byte clock. the number | |
425 | * of byte clocks occupied in one low power clock. based on txbyteclkhs | |
426 | * and txclkesc. txclkesc time / txbyteclk time * (105 + | |
427 | * MIPI_STOP_STATE_STALL) / 105.??? | |
428 | */ | |
429 | I915_WRITE(MIPI_LP_BYTECLK(pipe), 4); | |
430 | ||
431 | /* the bw essential for transmitting 16 long packets containing 252 | |
432 | * bytes meant for dcs write memory command is programmed in this | |
433 | * register in terms of byte clocks. based on dsi transfer rate and the | |
434 | * number of lanes configured the time taken to transmit 16 long packets | |
435 | * in a dsi stream varies. */ | |
436 | I915_WRITE(MIPI_DBI_BW_CTRL(pipe), 0x820); | |
437 | ||
438 | I915_WRITE(MIPI_CLK_LANE_SWITCH_TIME_CNT(pipe), | |
439 | 0xa << LP_HS_SSW_CNT_SHIFT | | |
440 | 0x14 << HS_LP_PWR_SW_CNT_SHIFT); | |
441 | ||
442 | if (is_vid_mode(intel_dsi)) | |
443 | I915_WRITE(MIPI_VIDEO_MODE_FORMAT(pipe), | |
444 | intel_dsi->video_mode_format); | |
445 | } | |
446 | ||
447 | static enum drm_connector_status | |
448 | intel_dsi_detect(struct drm_connector *connector, bool force) | |
449 | { | |
450 | struct intel_dsi *intel_dsi = intel_attached_dsi(connector); | |
451 | DRM_DEBUG_KMS("\n"); | |
452 | return intel_dsi->dev.dev_ops->detect(&intel_dsi->dev); | |
453 | } | |
454 | ||
455 | static int intel_dsi_get_modes(struct drm_connector *connector) | |
456 | { | |
457 | struct intel_connector *intel_connector = to_intel_connector(connector); | |
458 | struct drm_display_mode *mode; | |
459 | ||
460 | DRM_DEBUG_KMS("\n"); | |
461 | ||
462 | if (!intel_connector->panel.fixed_mode) { | |
463 | DRM_DEBUG_KMS("no fixed mode\n"); | |
464 | return 0; | |
465 | } | |
466 | ||
467 | mode = drm_mode_duplicate(connector->dev, | |
468 | intel_connector->panel.fixed_mode); | |
469 | if (!mode) { | |
470 | DRM_DEBUG_KMS("drm_mode_duplicate failed\n"); | |
471 | return 0; | |
472 | } | |
473 | ||
474 | drm_mode_probed_add(connector, mode); | |
475 | return 1; | |
476 | } | |
477 | ||
478 | static void intel_dsi_destroy(struct drm_connector *connector) | |
479 | { | |
480 | struct intel_connector *intel_connector = to_intel_connector(connector); | |
481 | ||
482 | DRM_DEBUG_KMS("\n"); | |
483 | intel_panel_fini(&intel_connector->panel); | |
4e646495 JN |
484 | drm_connector_cleanup(connector); |
485 | kfree(connector); | |
486 | } | |
487 | ||
488 | static const struct drm_encoder_funcs intel_dsi_funcs = { | |
489 | .destroy = intel_encoder_destroy, | |
490 | }; | |
491 | ||
492 | static const struct drm_connector_helper_funcs intel_dsi_connector_helper_funcs = { | |
493 | .get_modes = intel_dsi_get_modes, | |
494 | .mode_valid = intel_dsi_mode_valid, | |
495 | .best_encoder = intel_best_encoder, | |
496 | }; | |
497 | ||
498 | static const struct drm_connector_funcs intel_dsi_connector_funcs = { | |
499 | .dpms = intel_connector_dpms, | |
500 | .detect = intel_dsi_detect, | |
501 | .destroy = intel_dsi_destroy, | |
502 | .fill_modes = drm_helper_probe_single_connector_modes, | |
503 | }; | |
504 | ||
505 | bool intel_dsi_init(struct drm_device *dev) | |
506 | { | |
507 | struct intel_dsi *intel_dsi; | |
508 | struct intel_encoder *intel_encoder; | |
509 | struct drm_encoder *encoder; | |
510 | struct intel_connector *intel_connector; | |
511 | struct drm_connector *connector; | |
512 | struct drm_display_mode *fixed_mode = NULL; | |
513 | const struct intel_dsi_device *dsi; | |
514 | unsigned int i; | |
515 | ||
516 | DRM_DEBUG_KMS("\n"); | |
517 | ||
518 | intel_dsi = kzalloc(sizeof(*intel_dsi), GFP_KERNEL); | |
519 | if (!intel_dsi) | |
520 | return false; | |
521 | ||
522 | intel_connector = kzalloc(sizeof(*intel_connector), GFP_KERNEL); | |
523 | if (!intel_connector) { | |
524 | kfree(intel_dsi); | |
525 | return false; | |
526 | } | |
527 | ||
528 | intel_encoder = &intel_dsi->base; | |
529 | encoder = &intel_encoder->base; | |
530 | intel_dsi->attached_connector = intel_connector; | |
531 | ||
532 | connector = &intel_connector->base; | |
533 | ||
534 | drm_encoder_init(dev, encoder, &intel_dsi_funcs, DRM_MODE_ENCODER_DSI); | |
535 | ||
536 | /* XXX: very likely not all of these are needed */ | |
537 | intel_encoder->hot_plug = intel_dsi_hot_plug; | |
538 | intel_encoder->compute_config = intel_dsi_compute_config; | |
539 | intel_encoder->pre_pll_enable = intel_dsi_pre_pll_enable; | |
540 | intel_encoder->pre_enable = intel_dsi_pre_enable; | |
541 | intel_encoder->enable = intel_dsi_enable; | |
542 | intel_encoder->mode_set = intel_dsi_mode_set; | |
543 | intel_encoder->disable = intel_dsi_disable; | |
544 | intel_encoder->post_disable = intel_dsi_post_disable; | |
545 | intel_encoder->get_hw_state = intel_dsi_get_hw_state; | |
546 | intel_encoder->get_config = intel_dsi_get_config; | |
547 | ||
548 | intel_connector->get_hw_state = intel_connector_get_hw_state; | |
549 | ||
550 | for (i = 0; i < ARRAY_SIZE(intel_dsi_devices); i++) { | |
551 | dsi = &intel_dsi_devices[i]; | |
552 | intel_dsi->dev = *dsi; | |
553 | ||
554 | if (dsi->dev_ops->init(&intel_dsi->dev)) | |
555 | break; | |
556 | } | |
557 | ||
558 | if (i == ARRAY_SIZE(intel_dsi_devices)) { | |
559 | DRM_DEBUG_KMS("no device found\n"); | |
560 | goto err; | |
561 | } | |
562 | ||
563 | intel_encoder->type = INTEL_OUTPUT_DSI; | |
564 | intel_encoder->crtc_mask = (1 << 0); /* XXX */ | |
565 | ||
566 | intel_encoder->cloneable = false; | |
567 | drm_connector_init(dev, connector, &intel_dsi_connector_funcs, | |
568 | DRM_MODE_CONNECTOR_DSI); | |
569 | ||
570 | drm_connector_helper_add(connector, &intel_dsi_connector_helper_funcs); | |
571 | ||
572 | connector->display_info.subpixel_order = SubPixelHorizontalRGB; /*XXX*/ | |
573 | connector->interlace_allowed = false; | |
574 | connector->doublescan_allowed = false; | |
575 | ||
576 | intel_connector_attach_encoder(intel_connector, intel_encoder); | |
577 | ||
578 | drm_sysfs_connector_add(connector); | |
579 | ||
580 | fixed_mode = dsi->dev_ops->get_modes(&intel_dsi->dev); | |
581 | if (!fixed_mode) { | |
582 | DRM_DEBUG_KMS("no fixed mode\n"); | |
583 | goto err; | |
584 | } | |
585 | ||
586 | fixed_mode->type |= DRM_MODE_TYPE_PREFERRED; | |
587 | intel_panel_init(&intel_connector->panel, fixed_mode); | |
588 | ||
589 | return true; | |
590 | ||
591 | err: | |
592 | drm_encoder_cleanup(&intel_encoder->base); | |
593 | kfree(intel_dsi); | |
594 | kfree(intel_connector); | |
595 | ||
596 | return false; | |
597 | } |