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4e646495 JN |
1 | /* |
2 | * Copyright © 2013 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
21 | * DEALINGS IN THE SOFTWARE. | |
22 | * | |
23 | * Author: Jani Nikula <jani.nikula@intel.com> | |
24 | */ | |
25 | ||
26 | #include <drm/drmP.h> | |
27 | #include <drm/drm_crtc.h> | |
28 | #include <drm/drm_edid.h> | |
29 | #include <drm/i915_drm.h> | |
30 | #include <linux/slab.h> | |
31 | #include "i915_drv.h" | |
32 | #include "intel_drv.h" | |
33 | #include "intel_dsi.h" | |
34 | #include "intel_dsi_cmd.h" | |
35 | ||
36 | /* the sub-encoders aka panel drivers */ | |
37 | static const struct intel_dsi_device intel_dsi_devices[] = { | |
2ab8b458 SK |
38 | { |
39 | .panel_id = MIPI_DSI_GENERIC_PANEL_ID, | |
40 | .name = "vbt-generic-dsi-vid-mode-display", | |
41 | .dev_ops = &vbt_generic_dsi_display_ops, | |
42 | }, | |
4e646495 JN |
43 | }; |
44 | ||
e9fe51c6 | 45 | static void band_gap_reset(struct drm_i915_private *dev_priv) |
4ce8c9a7 SK |
46 | { |
47 | mutex_lock(&dev_priv->dpio_lock); | |
48 | ||
e9fe51c6 SK |
49 | vlv_flisdsi_write(dev_priv, 0x08, 0x0001); |
50 | vlv_flisdsi_write(dev_priv, 0x0F, 0x0005); | |
51 | vlv_flisdsi_write(dev_priv, 0x0F, 0x0025); | |
52 | udelay(150); | |
53 | vlv_flisdsi_write(dev_priv, 0x0F, 0x0000); | |
54 | vlv_flisdsi_write(dev_priv, 0x08, 0x0000); | |
4ce8c9a7 SK |
55 | |
56 | mutex_unlock(&dev_priv->dpio_lock); | |
4ce8c9a7 SK |
57 | } |
58 | ||
4e646495 JN |
59 | static struct intel_dsi *intel_attached_dsi(struct drm_connector *connector) |
60 | { | |
61 | return container_of(intel_attached_encoder(connector), | |
62 | struct intel_dsi, base); | |
63 | } | |
64 | ||
65 | static inline bool is_vid_mode(struct intel_dsi *intel_dsi) | |
66 | { | |
dfba2e2d | 67 | return intel_dsi->operation_mode == INTEL_DSI_VIDEO_MODE; |
4e646495 JN |
68 | } |
69 | ||
70 | static inline bool is_cmd_mode(struct intel_dsi *intel_dsi) | |
71 | { | |
dfba2e2d | 72 | return intel_dsi->operation_mode == INTEL_DSI_COMMAND_MODE; |
4e646495 JN |
73 | } |
74 | ||
75 | static void intel_dsi_hot_plug(struct intel_encoder *encoder) | |
76 | { | |
77 | DRM_DEBUG_KMS("\n"); | |
78 | } | |
79 | ||
80 | static bool intel_dsi_compute_config(struct intel_encoder *encoder, | |
81 | struct intel_crtc_config *config) | |
82 | { | |
83 | struct intel_dsi *intel_dsi = container_of(encoder, struct intel_dsi, | |
84 | base); | |
85 | struct intel_connector *intel_connector = intel_dsi->attached_connector; | |
86 | struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode; | |
87 | struct drm_display_mode *adjusted_mode = &config->adjusted_mode; | |
88 | struct drm_display_mode *mode = &config->requested_mode; | |
89 | ||
90 | DRM_DEBUG_KMS("\n"); | |
91 | ||
92 | if (fixed_mode) | |
93 | intel_fixed_panel_mode(fixed_mode, adjusted_mode); | |
94 | ||
95 | if (intel_dsi->dev.dev_ops->mode_fixup) | |
96 | return intel_dsi->dev.dev_ops->mode_fixup(&intel_dsi->dev, | |
97 | mode, adjusted_mode); | |
98 | ||
99 | return true; | |
100 | } | |
101 | ||
1dbd7cb2 | 102 | static void intel_dsi_device_ready(struct intel_encoder *encoder) |
4e646495 | 103 | { |
1dbd7cb2 SK |
104 | struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; |
105 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); | |
106 | int pipe = intel_crtc->pipe; | |
107 | u32 val; | |
108 | ||
4e646495 | 109 | DRM_DEBUG_KMS("\n"); |
4e646495 | 110 | |
2095f9fc SK |
111 | mutex_lock(&dev_priv->dpio_lock); |
112 | /* program rcomp for compliance, reduce from 50 ohms to 45 ohms | |
113 | * needed everytime after power gate */ | |
114 | vlv_flisdsi_write(dev_priv, 0x04, 0x0004); | |
115 | mutex_unlock(&dev_priv->dpio_lock); | |
116 | ||
117 | /* bandgap reset is needed after everytime we do power gate */ | |
118 | band_gap_reset(dev_priv); | |
119 | ||
aceb365c SK |
120 | I915_WRITE(MIPI_DEVICE_READY(pipe), ULPS_STATE_ENTER); |
121 | usleep_range(2500, 3000); | |
122 | ||
1dbd7cb2 SK |
123 | val = I915_READ(MIPI_PORT_CTRL(pipe)); |
124 | I915_WRITE(MIPI_PORT_CTRL(pipe), val | LP_OUTPUT_HOLD); | |
125 | usleep_range(1000, 1500); | |
aceb365c SK |
126 | |
127 | I915_WRITE(MIPI_DEVICE_READY(pipe), ULPS_STATE_EXIT); | |
128 | usleep_range(2500, 3000); | |
129 | ||
1dbd7cb2 | 130 | I915_WRITE(MIPI_DEVICE_READY(pipe), DEVICE_READY); |
aceb365c | 131 | usleep_range(2500, 3000); |
1dbd7cb2 | 132 | } |
1dbd7cb2 SK |
133 | |
134 | static void intel_dsi_enable(struct intel_encoder *encoder) | |
135 | { | |
136 | struct drm_device *dev = encoder->base.dev; | |
137 | struct drm_i915_private *dev_priv = dev->dev_private; | |
138 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); | |
139 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); | |
140 | int pipe = intel_crtc->pipe; | |
141 | u32 temp; | |
142 | ||
143 | DRM_DEBUG_KMS("\n"); | |
b9f5e07d | 144 | |
4e646495 JN |
145 | if (is_cmd_mode(intel_dsi)) |
146 | I915_WRITE(MIPI_MAX_RETURN_PKT_SIZE(pipe), 8 * 4); | |
1dbd7cb2 | 147 | else { |
4e646495 | 148 | msleep(20); /* XXX */ |
e1047028 | 149 | dpi_send_cmd(intel_dsi, TURN_ON, DPI_LP_MODE_EN); |
4e646495 JN |
150 | msleep(100); |
151 | ||
2634fd7f SK |
152 | if (intel_dsi->dev.dev_ops->enable) |
153 | intel_dsi->dev.dev_ops->enable(&intel_dsi->dev); | |
154 | ||
1381308b SK |
155 | wait_for_dsi_fifo_empty(intel_dsi); |
156 | ||
4e646495 | 157 | /* assert ip_tg_enable signal */ |
f6da2842 SK |
158 | temp = I915_READ(MIPI_PORT_CTRL(pipe)) & ~LANE_CONFIGURATION_MASK; |
159 | temp = temp | intel_dsi->port_bits; | |
4e646495 JN |
160 | I915_WRITE(MIPI_PORT_CTRL(pipe), temp | DPI_ENABLE); |
161 | POSTING_READ(MIPI_PORT_CTRL(pipe)); | |
162 | } | |
2634fd7f SK |
163 | } |
164 | ||
165 | static void intel_dsi_pre_enable(struct intel_encoder *encoder) | |
166 | { | |
20e5bf66 SK |
167 | struct drm_device *dev = encoder->base.dev; |
168 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2634fd7f | 169 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); |
20e5bf66 SK |
170 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); |
171 | enum pipe pipe = intel_crtc->pipe; | |
172 | u32 tmp; | |
2634fd7f SK |
173 | |
174 | DRM_DEBUG_KMS("\n"); | |
175 | ||
20e5bf66 SK |
176 | /* Disable DPOunit clock gating, can stall pipe |
177 | * and we need DPLL REFA always enabled */ | |
178 | tmp = I915_READ(DPLL(pipe)); | |
179 | tmp |= DPLL_REFA_CLK_ENABLE_VLV; | |
180 | I915_WRITE(DPLL(pipe), tmp); | |
181 | ||
182 | tmp = I915_READ(DSPCLK_GATE_D); | |
183 | tmp |= DPOUNIT_CLOCK_GATE_DISABLE; | |
184 | I915_WRITE(DSPCLK_GATE_D, tmp); | |
2634fd7f SK |
185 | |
186 | /* put device in ready state */ | |
187 | intel_dsi_device_ready(encoder); | |
4e646495 | 188 | |
df38e655 SK |
189 | msleep(intel_dsi->panel_on_delay); |
190 | ||
20e5bf66 SK |
191 | if (intel_dsi->dev.dev_ops->panel_reset) |
192 | intel_dsi->dev.dev_ops->panel_reset(&intel_dsi->dev); | |
193 | ||
2634fd7f SK |
194 | if (intel_dsi->dev.dev_ops->send_otp_cmds) |
195 | intel_dsi->dev.dev_ops->send_otp_cmds(&intel_dsi->dev); | |
196 | ||
1381308b SK |
197 | wait_for_dsi_fifo_empty(intel_dsi); |
198 | ||
2634fd7f SK |
199 | /* Enable port in pre-enable phase itself because as per hw team |
200 | * recommendation, port should be enabled befor plane & pipe */ | |
201 | intel_dsi_enable(encoder); | |
202 | } | |
203 | ||
204 | static void intel_dsi_enable_nop(struct intel_encoder *encoder) | |
205 | { | |
206 | DRM_DEBUG_KMS("\n"); | |
207 | ||
208 | /* for DSI port enable has to be done before pipe | |
209 | * and plane enable, so port enable is done in | |
210 | * pre_enable phase itself unlike other encoders | |
211 | */ | |
4e646495 JN |
212 | } |
213 | ||
c315faf8 ID |
214 | static void intel_dsi_pre_disable(struct intel_encoder *encoder) |
215 | { | |
216 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); | |
217 | ||
218 | DRM_DEBUG_KMS("\n"); | |
219 | ||
220 | if (is_vid_mode(intel_dsi)) { | |
221 | /* Send Shutdown command to the panel in LP mode */ | |
222 | dpi_send_cmd(intel_dsi, SHUTDOWN, DPI_LP_MODE_EN); | |
223 | msleep(10); | |
224 | } | |
225 | } | |
226 | ||
4e646495 JN |
227 | static void intel_dsi_disable(struct intel_encoder *encoder) |
228 | { | |
1dbd7cb2 SK |
229 | struct drm_device *dev = encoder->base.dev; |
230 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4e646495 JN |
231 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); |
232 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); | |
233 | int pipe = intel_crtc->pipe; | |
234 | u32 temp; | |
235 | ||
236 | DRM_DEBUG_KMS("\n"); | |
237 | ||
4e646495 | 238 | if (is_vid_mode(intel_dsi)) { |
1381308b SK |
239 | wait_for_dsi_fifo_empty(intel_dsi); |
240 | ||
4e646495 JN |
241 | /* de-assert ip_tg_enable signal */ |
242 | temp = I915_READ(MIPI_PORT_CTRL(pipe)); | |
243 | I915_WRITE(MIPI_PORT_CTRL(pipe), temp & ~DPI_ENABLE); | |
244 | POSTING_READ(MIPI_PORT_CTRL(pipe)); | |
245 | ||
246 | msleep(2); | |
247 | } | |
248 | ||
339023ec SK |
249 | /* Panel commands can be sent when clock is in LP11 */ |
250 | I915_WRITE(MIPI_DEVICE_READY(pipe), 0x0); | |
251 | ||
252 | temp = I915_READ(MIPI_CTRL(pipe)); | |
253 | temp &= ~ESCAPE_CLOCK_DIVIDER_MASK; | |
254 | I915_WRITE(MIPI_CTRL(pipe), temp | | |
255 | intel_dsi->escape_clk_div << | |
256 | ESCAPE_CLOCK_DIVIDER_SHIFT); | |
257 | ||
258 | I915_WRITE(MIPI_EOT_DISABLE(pipe), CLOCKSTOP); | |
259 | ||
260 | temp = I915_READ(MIPI_DSI_FUNC_PRG(pipe)); | |
261 | temp &= ~VID_MODE_FORMAT_MASK; | |
262 | I915_WRITE(MIPI_DSI_FUNC_PRG(pipe), temp); | |
263 | ||
264 | I915_WRITE(MIPI_DEVICE_READY(pipe), 0x1); | |
265 | ||
1dbd7cb2 SK |
266 | /* if disable packets are sent before sending shutdown packet then in |
267 | * some next enable sequence send turn on packet error is observed */ | |
268 | if (intel_dsi->dev.dev_ops->disable) | |
269 | intel_dsi->dev.dev_ops->disable(&intel_dsi->dev); | |
1381308b SK |
270 | |
271 | wait_for_dsi_fifo_empty(intel_dsi); | |
4e646495 JN |
272 | } |
273 | ||
1dbd7cb2 | 274 | static void intel_dsi_clear_device_ready(struct intel_encoder *encoder) |
4e646495 | 275 | { |
1dbd7cb2 SK |
276 | struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; |
277 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); | |
278 | int pipe = intel_crtc->pipe; | |
279 | u32 val; | |
280 | ||
4e646495 | 281 | DRM_DEBUG_KMS("\n"); |
be4fc046 | 282 | |
aceb365c | 283 | I915_WRITE(MIPI_DEVICE_READY(pipe), DEVICE_READY | ULPS_STATE_ENTER); |
1dbd7cb2 SK |
284 | usleep_range(2000, 2500); |
285 | ||
aceb365c | 286 | I915_WRITE(MIPI_DEVICE_READY(pipe), DEVICE_READY | ULPS_STATE_EXIT); |
1dbd7cb2 SK |
287 | usleep_range(2000, 2500); |
288 | ||
aceb365c | 289 | I915_WRITE(MIPI_DEVICE_READY(pipe), DEVICE_READY | ULPS_STATE_ENTER); |
1dbd7cb2 SK |
290 | usleep_range(2000, 2500); |
291 | ||
1dbd7cb2 SK |
292 | if (wait_for(((I915_READ(MIPI_PORT_CTRL(pipe)) & AFE_LATCHOUT) |
293 | == 0x00000), 30)) | |
294 | DRM_ERROR("DSI LP not going Low\n"); | |
295 | ||
aceb365c SK |
296 | val = I915_READ(MIPI_PORT_CTRL(pipe)); |
297 | I915_WRITE(MIPI_PORT_CTRL(pipe), val & ~LP_OUTPUT_HOLD); | |
298 | usleep_range(1000, 1500); | |
299 | ||
1dbd7cb2 SK |
300 | I915_WRITE(MIPI_DEVICE_READY(pipe), 0x00); |
301 | usleep_range(2000, 2500); | |
302 | ||
be4fc046 | 303 | vlv_disable_dsi_pll(encoder); |
4e646495 | 304 | } |
20e5bf66 | 305 | |
1dbd7cb2 SK |
306 | static void intel_dsi_post_disable(struct intel_encoder *encoder) |
307 | { | |
20e5bf66 | 308 | struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; |
1dbd7cb2 | 309 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); |
20e5bf66 | 310 | u32 val; |
1dbd7cb2 SK |
311 | |
312 | DRM_DEBUG_KMS("\n"); | |
313 | ||
c315faf8 ID |
314 | intel_dsi_disable(encoder); |
315 | ||
1dbd7cb2 SK |
316 | intel_dsi_clear_device_ready(encoder); |
317 | ||
20e5bf66 SK |
318 | val = I915_READ(DSPCLK_GATE_D); |
319 | val &= ~DPOUNIT_CLOCK_GATE_DISABLE; | |
320 | I915_WRITE(DSPCLK_GATE_D, val); | |
321 | ||
1dbd7cb2 SK |
322 | if (intel_dsi->dev.dev_ops->disable_panel_power) |
323 | intel_dsi->dev.dev_ops->disable_panel_power(&intel_dsi->dev); | |
df38e655 SK |
324 | |
325 | msleep(intel_dsi->panel_off_delay); | |
326 | msleep(intel_dsi->panel_pwr_cycle_delay); | |
1dbd7cb2 | 327 | } |
4e646495 JN |
328 | |
329 | static bool intel_dsi_get_hw_state(struct intel_encoder *encoder, | |
330 | enum pipe *pipe) | |
331 | { | |
332 | struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; | |
6d129bea | 333 | enum intel_display_power_domain power_domain; |
4e646495 JN |
334 | u32 port, func; |
335 | enum pipe p; | |
336 | ||
337 | DRM_DEBUG_KMS("\n"); | |
338 | ||
6d129bea ID |
339 | power_domain = intel_display_port_power_domain(encoder); |
340 | if (!intel_display_power_enabled(dev_priv, power_domain)) | |
341 | return false; | |
342 | ||
4e646495 JN |
343 | /* XXX: this only works for one DSI output */ |
344 | for (p = PIPE_A; p <= PIPE_B; p++) { | |
345 | port = I915_READ(MIPI_PORT_CTRL(p)); | |
346 | func = I915_READ(MIPI_DSI_FUNC_PRG(p)); | |
347 | ||
348 | if ((port & DPI_ENABLE) || (func & CMD_MODE_DATA_WIDTH_MASK)) { | |
349 | if (I915_READ(MIPI_DEVICE_READY(p)) & DEVICE_READY) { | |
350 | *pipe = p; | |
351 | return true; | |
352 | } | |
353 | } | |
354 | } | |
355 | ||
356 | return false; | |
357 | } | |
358 | ||
359 | static void intel_dsi_get_config(struct intel_encoder *encoder, | |
360 | struct intel_crtc_config *pipe_config) | |
361 | { | |
362 | DRM_DEBUG_KMS("\n"); | |
363 | ||
364 | /* XXX: read flags, set to adjusted_mode */ | |
365 | } | |
366 | ||
c19de8eb DL |
367 | static enum drm_mode_status |
368 | intel_dsi_mode_valid(struct drm_connector *connector, | |
369 | struct drm_display_mode *mode) | |
4e646495 JN |
370 | { |
371 | struct intel_connector *intel_connector = to_intel_connector(connector); | |
372 | struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode; | |
373 | struct intel_dsi *intel_dsi = intel_attached_dsi(connector); | |
374 | ||
375 | DRM_DEBUG_KMS("\n"); | |
376 | ||
377 | if (mode->flags & DRM_MODE_FLAG_DBLSCAN) { | |
378 | DRM_DEBUG_KMS("MODE_NO_DBLESCAN\n"); | |
379 | return MODE_NO_DBLESCAN; | |
380 | } | |
381 | ||
382 | if (fixed_mode) { | |
383 | if (mode->hdisplay > fixed_mode->hdisplay) | |
384 | return MODE_PANEL; | |
385 | if (mode->vdisplay > fixed_mode->vdisplay) | |
386 | return MODE_PANEL; | |
387 | } | |
388 | ||
389 | return intel_dsi->dev.dev_ops->mode_valid(&intel_dsi->dev, mode); | |
390 | } | |
391 | ||
392 | /* return txclkesc cycles in terms of divider and duration in us */ | |
393 | static u16 txclkesc(u32 divider, unsigned int us) | |
394 | { | |
395 | switch (divider) { | |
396 | case ESCAPE_CLOCK_DIVIDER_1: | |
397 | default: | |
398 | return 20 * us; | |
399 | case ESCAPE_CLOCK_DIVIDER_2: | |
400 | return 10 * us; | |
401 | case ESCAPE_CLOCK_DIVIDER_4: | |
402 | return 5 * us; | |
403 | } | |
404 | } | |
405 | ||
406 | /* return pixels in terms of txbyteclkhs */ | |
407 | static u16 txbyteclkhs(u16 pixels, int bpp, int lane_count) | |
408 | { | |
409 | return DIV_ROUND_UP(DIV_ROUND_UP(pixels * bpp, 8), lane_count); | |
410 | } | |
411 | ||
412 | static void set_dsi_timings(struct drm_encoder *encoder, | |
413 | const struct drm_display_mode *mode) | |
414 | { | |
415 | struct drm_device *dev = encoder->dev; | |
416 | struct drm_i915_private *dev_priv = dev->dev_private; | |
417 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); | |
418 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); | |
419 | int pipe = intel_crtc->pipe; | |
420 | unsigned int bpp = intel_crtc->config.pipe_bpp; | |
421 | unsigned int lane_count = intel_dsi->lane_count; | |
422 | ||
423 | u16 hactive, hfp, hsync, hbp, vfp, vsync, vbp; | |
424 | ||
425 | hactive = mode->hdisplay; | |
426 | hfp = mode->hsync_start - mode->hdisplay; | |
427 | hsync = mode->hsync_end - mode->hsync_start; | |
428 | hbp = mode->htotal - mode->hsync_end; | |
429 | ||
430 | vfp = mode->vsync_start - mode->vdisplay; | |
431 | vsync = mode->vsync_end - mode->vsync_start; | |
432 | vbp = mode->vtotal - mode->vsync_end; | |
433 | ||
434 | /* horizontal values are in terms of high speed byte clock */ | |
435 | hactive = txbyteclkhs(hactive, bpp, lane_count); | |
436 | hfp = txbyteclkhs(hfp, bpp, lane_count); | |
437 | hsync = txbyteclkhs(hsync, bpp, lane_count); | |
438 | hbp = txbyteclkhs(hbp, bpp, lane_count); | |
439 | ||
440 | I915_WRITE(MIPI_HACTIVE_AREA_COUNT(pipe), hactive); | |
441 | I915_WRITE(MIPI_HFP_COUNT(pipe), hfp); | |
442 | ||
443 | /* meaningful for video mode non-burst sync pulse mode only, can be zero | |
444 | * for non-burst sync events and burst modes */ | |
445 | I915_WRITE(MIPI_HSYNC_PADDING_COUNT(pipe), hsync); | |
446 | I915_WRITE(MIPI_HBP_COUNT(pipe), hbp); | |
447 | ||
448 | /* vertical values are in terms of lines */ | |
449 | I915_WRITE(MIPI_VFP_COUNT(pipe), vfp); | |
450 | I915_WRITE(MIPI_VSYNC_PADDING_COUNT(pipe), vsync); | |
451 | I915_WRITE(MIPI_VBP_COUNT(pipe), vbp); | |
452 | } | |
453 | ||
07e4fb9e | 454 | static void intel_dsi_prepare(struct intel_encoder *intel_encoder) |
4e646495 JN |
455 | { |
456 | struct drm_encoder *encoder = &intel_encoder->base; | |
457 | struct drm_device *dev = encoder->dev; | |
458 | struct drm_i915_private *dev_priv = dev->dev_private; | |
459 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); | |
460 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); | |
461 | struct drm_display_mode *adjusted_mode = | |
462 | &intel_crtc->config.adjusted_mode; | |
463 | int pipe = intel_crtc->pipe; | |
464 | unsigned int bpp = intel_crtc->config.pipe_bpp; | |
465 | u32 val, tmp; | |
466 | ||
6f2bcceb | 467 | DRM_DEBUG_KMS("pipe %c\n", pipe_name(pipe)); |
4e646495 JN |
468 | |
469 | /* escape clock divider, 20MHz, shared for A and C. device ready must be | |
470 | * off when doing this! txclkesc? */ | |
471 | tmp = I915_READ(MIPI_CTRL(0)); | |
472 | tmp &= ~ESCAPE_CLOCK_DIVIDER_MASK; | |
473 | I915_WRITE(MIPI_CTRL(0), tmp | ESCAPE_CLOCK_DIVIDER_1); | |
474 | ||
475 | /* read request priority is per pipe */ | |
476 | tmp = I915_READ(MIPI_CTRL(pipe)); | |
477 | tmp &= ~READ_REQUEST_PRIORITY_MASK; | |
478 | I915_WRITE(MIPI_CTRL(pipe), tmp | READ_REQUEST_PRIORITY_HIGH); | |
479 | ||
480 | /* XXX: why here, why like this? handling in irq handler?! */ | |
481 | I915_WRITE(MIPI_INTR_STAT(pipe), 0xffffffff); | |
482 | I915_WRITE(MIPI_INTR_EN(pipe), 0xffffffff); | |
483 | ||
f6da2842 | 484 | I915_WRITE(MIPI_DPHY_PARAM(pipe), intel_dsi->dphy_reg); |
4e646495 JN |
485 | |
486 | I915_WRITE(MIPI_DPI_RESOLUTION(pipe), | |
487 | adjusted_mode->vdisplay << VERTICAL_ADDRESS_SHIFT | | |
488 | adjusted_mode->hdisplay << HORIZONTAL_ADDRESS_SHIFT); | |
489 | ||
490 | set_dsi_timings(encoder, adjusted_mode); | |
491 | ||
492 | val = intel_dsi->lane_count << DATA_LANES_PRG_REG_SHIFT; | |
493 | if (is_cmd_mode(intel_dsi)) { | |
494 | val |= intel_dsi->channel << CMD_MODE_CHANNEL_NUMBER_SHIFT; | |
495 | val |= CMD_MODE_DATA_WIDTH_8_BIT; /* XXX */ | |
496 | } else { | |
497 | val |= intel_dsi->channel << VID_MODE_CHANNEL_NUMBER_SHIFT; | |
498 | ||
499 | /* XXX: cross-check bpp vs. pixel format? */ | |
500 | val |= intel_dsi->pixel_format; | |
501 | } | |
502 | I915_WRITE(MIPI_DSI_FUNC_PRG(pipe), val); | |
503 | ||
504 | /* timeouts for recovery. one frame IIUC. if counter expires, EOT and | |
505 | * stop state. */ | |
506 | ||
507 | /* | |
508 | * In burst mode, value greater than one DPI line Time in byte clock | |
509 | * (txbyteclkhs) To timeout this timer 1+ of the above said value is | |
510 | * recommended. | |
511 | * | |
512 | * In non-burst mode, Value greater than one DPI frame time in byte | |
513 | * clock(txbyteclkhs) To timeout this timer 1+ of the above said value | |
514 | * is recommended. | |
515 | * | |
516 | * In DBI only mode, value greater than one DBI frame time in byte | |
517 | * clock(txbyteclkhs) To timeout this timer 1+ of the above said value | |
518 | * is recommended. | |
519 | */ | |
520 | ||
521 | if (is_vid_mode(intel_dsi) && | |
522 | intel_dsi->video_mode_format == VIDEO_MODE_BURST) { | |
523 | I915_WRITE(MIPI_HS_TX_TIMEOUT(pipe), | |
524 | txbyteclkhs(adjusted_mode->htotal, bpp, | |
525 | intel_dsi->lane_count) + 1); | |
526 | } else { | |
527 | I915_WRITE(MIPI_HS_TX_TIMEOUT(pipe), | |
528 | txbyteclkhs(adjusted_mode->vtotal * | |
529 | adjusted_mode->htotal, | |
530 | bpp, intel_dsi->lane_count) + 1); | |
531 | } | |
f6da2842 SK |
532 | I915_WRITE(MIPI_LP_RX_TIMEOUT(pipe), intel_dsi->lp_rx_timeout); |
533 | I915_WRITE(MIPI_TURN_AROUND_TIMEOUT(pipe), intel_dsi->turn_arnd_val); | |
534 | I915_WRITE(MIPI_DEVICE_RESET_TIMER(pipe), intel_dsi->rst_timer_val); | |
4e646495 JN |
535 | |
536 | /* dphy stuff */ | |
537 | ||
538 | /* in terms of low power clock */ | |
f1c79f16 SK |
539 | I915_WRITE(MIPI_INIT_COUNT(pipe), txclkesc(intel_dsi->escape_clk_div, 100)); |
540 | ||
541 | val = 0; | |
542 | if (intel_dsi->eotp_pkt == 0) | |
543 | val |= EOT_DISABLE; | |
544 | ||
545 | if (intel_dsi->clock_stop) | |
546 | val |= CLOCKSTOP; | |
4e646495 JN |
547 | |
548 | /* recovery disables */ | |
f1c79f16 | 549 | I915_WRITE(MIPI_EOT_DISABLE(pipe), val); |
4e646495 | 550 | |
cf4dbd2e SK |
551 | /* in terms of low power clock */ |
552 | I915_WRITE(MIPI_INIT_COUNT(pipe), intel_dsi->init_count); | |
553 | ||
4e646495 JN |
554 | /* in terms of txbyteclkhs. actual high to low switch + |
555 | * MIPI_STOP_STATE_STALL * MIPI_LP_BYTECLK. | |
556 | * | |
557 | * XXX: write MIPI_STOP_STATE_STALL? | |
558 | */ | |
f6da2842 SK |
559 | I915_WRITE(MIPI_HIGH_LOW_SWITCH_COUNT(pipe), |
560 | intel_dsi->hs_to_lp_count); | |
4e646495 JN |
561 | |
562 | /* XXX: low power clock equivalence in terms of byte clock. the number | |
563 | * of byte clocks occupied in one low power clock. based on txbyteclkhs | |
564 | * and txclkesc. txclkesc time / txbyteclk time * (105 + | |
565 | * MIPI_STOP_STATE_STALL) / 105.??? | |
566 | */ | |
f6da2842 | 567 | I915_WRITE(MIPI_LP_BYTECLK(pipe), intel_dsi->lp_byte_clk); |
4e646495 JN |
568 | |
569 | /* the bw essential for transmitting 16 long packets containing 252 | |
570 | * bytes meant for dcs write memory command is programmed in this | |
571 | * register in terms of byte clocks. based on dsi transfer rate and the | |
572 | * number of lanes configured the time taken to transmit 16 long packets | |
573 | * in a dsi stream varies. */ | |
f6da2842 | 574 | I915_WRITE(MIPI_DBI_BW_CTRL(pipe), intel_dsi->bw_timer); |
4e646495 JN |
575 | |
576 | I915_WRITE(MIPI_CLK_LANE_SWITCH_TIME_CNT(pipe), | |
f6da2842 SK |
577 | intel_dsi->clk_lp_to_hs_count << LP_HS_SSW_CNT_SHIFT | |
578 | intel_dsi->clk_hs_to_lp_count << HS_LP_PWR_SW_CNT_SHIFT); | |
4e646495 JN |
579 | |
580 | if (is_vid_mode(intel_dsi)) | |
24d9c401 SK |
581 | /* Some panels might have resolution which is not a multiple of |
582 | * 64 like 1366 x 768. Enable RANDOM resolution support for such | |
583 | * panels by default */ | |
4e646495 | 584 | I915_WRITE(MIPI_VIDEO_MODE_FORMAT(pipe), |
f6da2842 | 585 | intel_dsi->video_frmt_cfg_bits | |
24d9c401 SK |
586 | intel_dsi->video_mode_format | |
587 | IP_TG_CONFIG | | |
588 | RANDOM_DPI_DISPLAY_RESOLUTION); | |
4e646495 JN |
589 | } |
590 | ||
07e4fb9e DV |
591 | static void intel_dsi_pre_pll_enable(struct intel_encoder *encoder) |
592 | { | |
593 | DRM_DEBUG_KMS("\n"); | |
594 | ||
595 | intel_dsi_prepare(encoder); | |
596 | ||
597 | vlv_enable_dsi_pll(encoder); | |
598 | } | |
599 | ||
4e646495 JN |
600 | static enum drm_connector_status |
601 | intel_dsi_detect(struct drm_connector *connector, bool force) | |
602 | { | |
603 | struct intel_dsi *intel_dsi = intel_attached_dsi(connector); | |
671dedd2 ID |
604 | struct intel_encoder *intel_encoder = &intel_dsi->base; |
605 | enum intel_display_power_domain power_domain; | |
606 | enum drm_connector_status connector_status; | |
607 | struct drm_i915_private *dev_priv = intel_encoder->base.dev->dev_private; | |
608 | ||
4e646495 | 609 | DRM_DEBUG_KMS("\n"); |
671dedd2 ID |
610 | power_domain = intel_display_port_power_domain(intel_encoder); |
611 | ||
612 | intel_display_power_get(dev_priv, power_domain); | |
613 | connector_status = intel_dsi->dev.dev_ops->detect(&intel_dsi->dev); | |
614 | intel_display_power_put(dev_priv, power_domain); | |
615 | ||
616 | return connector_status; | |
4e646495 JN |
617 | } |
618 | ||
619 | static int intel_dsi_get_modes(struct drm_connector *connector) | |
620 | { | |
621 | struct intel_connector *intel_connector = to_intel_connector(connector); | |
622 | struct drm_display_mode *mode; | |
623 | ||
624 | DRM_DEBUG_KMS("\n"); | |
625 | ||
626 | if (!intel_connector->panel.fixed_mode) { | |
627 | DRM_DEBUG_KMS("no fixed mode\n"); | |
628 | return 0; | |
629 | } | |
630 | ||
631 | mode = drm_mode_duplicate(connector->dev, | |
632 | intel_connector->panel.fixed_mode); | |
633 | if (!mode) { | |
634 | DRM_DEBUG_KMS("drm_mode_duplicate failed\n"); | |
635 | return 0; | |
636 | } | |
637 | ||
638 | drm_mode_probed_add(connector, mode); | |
639 | return 1; | |
640 | } | |
641 | ||
642 | static void intel_dsi_destroy(struct drm_connector *connector) | |
643 | { | |
644 | struct intel_connector *intel_connector = to_intel_connector(connector); | |
645 | ||
646 | DRM_DEBUG_KMS("\n"); | |
647 | intel_panel_fini(&intel_connector->panel); | |
4e646495 JN |
648 | drm_connector_cleanup(connector); |
649 | kfree(connector); | |
650 | } | |
651 | ||
652 | static const struct drm_encoder_funcs intel_dsi_funcs = { | |
653 | .destroy = intel_encoder_destroy, | |
654 | }; | |
655 | ||
656 | static const struct drm_connector_helper_funcs intel_dsi_connector_helper_funcs = { | |
657 | .get_modes = intel_dsi_get_modes, | |
658 | .mode_valid = intel_dsi_mode_valid, | |
659 | .best_encoder = intel_best_encoder, | |
660 | }; | |
661 | ||
662 | static const struct drm_connector_funcs intel_dsi_connector_funcs = { | |
663 | .dpms = intel_connector_dpms, | |
664 | .detect = intel_dsi_detect, | |
665 | .destroy = intel_dsi_destroy, | |
666 | .fill_modes = drm_helper_probe_single_connector_modes, | |
667 | }; | |
668 | ||
4328633d | 669 | void intel_dsi_init(struct drm_device *dev) |
4e646495 JN |
670 | { |
671 | struct intel_dsi *intel_dsi; | |
672 | struct intel_encoder *intel_encoder; | |
673 | struct drm_encoder *encoder; | |
674 | struct intel_connector *intel_connector; | |
675 | struct drm_connector *connector; | |
676 | struct drm_display_mode *fixed_mode = NULL; | |
b6fdd0f2 | 677 | struct drm_i915_private *dev_priv = dev->dev_private; |
4e646495 JN |
678 | const struct intel_dsi_device *dsi; |
679 | unsigned int i; | |
680 | ||
681 | DRM_DEBUG_KMS("\n"); | |
682 | ||
3e6bd011 SK |
683 | /* There is no detection method for MIPI so rely on VBT */ |
684 | if (!dev_priv->vbt.has_mipi) | |
4328633d | 685 | return; |
3e6bd011 | 686 | |
868d665b CJ |
687 | if (IS_VALLEYVIEW(dev)) { |
688 | dev_priv->mipi_mmio_base = VLV_MIPI_BASE; | |
689 | } else { | |
690 | DRM_ERROR("Unsupported Mipi device to reg base"); | |
691 | return; | |
692 | } | |
3e6bd011 | 693 | |
4e646495 JN |
694 | intel_dsi = kzalloc(sizeof(*intel_dsi), GFP_KERNEL); |
695 | if (!intel_dsi) | |
4328633d | 696 | return; |
4e646495 JN |
697 | |
698 | intel_connector = kzalloc(sizeof(*intel_connector), GFP_KERNEL); | |
699 | if (!intel_connector) { | |
700 | kfree(intel_dsi); | |
4328633d | 701 | return; |
4e646495 JN |
702 | } |
703 | ||
704 | intel_encoder = &intel_dsi->base; | |
705 | encoder = &intel_encoder->base; | |
706 | intel_dsi->attached_connector = intel_connector; | |
707 | ||
708 | connector = &intel_connector->base; | |
709 | ||
710 | drm_encoder_init(dev, encoder, &intel_dsi_funcs, DRM_MODE_ENCODER_DSI); | |
711 | ||
712 | /* XXX: very likely not all of these are needed */ | |
713 | intel_encoder->hot_plug = intel_dsi_hot_plug; | |
714 | intel_encoder->compute_config = intel_dsi_compute_config; | |
715 | intel_encoder->pre_pll_enable = intel_dsi_pre_pll_enable; | |
716 | intel_encoder->pre_enable = intel_dsi_pre_enable; | |
2634fd7f | 717 | intel_encoder->enable = intel_dsi_enable_nop; |
c315faf8 | 718 | intel_encoder->disable = intel_dsi_pre_disable; |
4e646495 JN |
719 | intel_encoder->post_disable = intel_dsi_post_disable; |
720 | intel_encoder->get_hw_state = intel_dsi_get_hw_state; | |
721 | intel_encoder->get_config = intel_dsi_get_config; | |
722 | ||
723 | intel_connector->get_hw_state = intel_connector_get_hw_state; | |
4932e2c3 | 724 | intel_connector->unregister = intel_connector_unregister; |
4e646495 JN |
725 | |
726 | for (i = 0; i < ARRAY_SIZE(intel_dsi_devices); i++) { | |
727 | dsi = &intel_dsi_devices[i]; | |
728 | intel_dsi->dev = *dsi; | |
729 | ||
730 | if (dsi->dev_ops->init(&intel_dsi->dev)) | |
731 | break; | |
732 | } | |
733 | ||
734 | if (i == ARRAY_SIZE(intel_dsi_devices)) { | |
735 | DRM_DEBUG_KMS("no device found\n"); | |
736 | goto err; | |
737 | } | |
738 | ||
739 | intel_encoder->type = INTEL_OUTPUT_DSI; | |
740 | intel_encoder->crtc_mask = (1 << 0); /* XXX */ | |
741 | ||
bc079e8b | 742 | intel_encoder->cloneable = 0; |
4e646495 JN |
743 | drm_connector_init(dev, connector, &intel_dsi_connector_funcs, |
744 | DRM_MODE_CONNECTOR_DSI); | |
745 | ||
746 | drm_connector_helper_add(connector, &intel_dsi_connector_helper_funcs); | |
747 | ||
748 | connector->display_info.subpixel_order = SubPixelHorizontalRGB; /*XXX*/ | |
749 | connector->interlace_allowed = false; | |
750 | connector->doublescan_allowed = false; | |
751 | ||
752 | intel_connector_attach_encoder(intel_connector, intel_encoder); | |
753 | ||
34ea3d38 | 754 | drm_connector_register(connector); |
4e646495 JN |
755 | |
756 | fixed_mode = dsi->dev_ops->get_modes(&intel_dsi->dev); | |
757 | if (!fixed_mode) { | |
758 | DRM_DEBUG_KMS("no fixed mode\n"); | |
759 | goto err; | |
760 | } | |
761 | ||
762 | fixed_mode->type |= DRM_MODE_TYPE_PREFERRED; | |
4b6ed685 | 763 | intel_panel_init(&intel_connector->panel, fixed_mode, NULL); |
4e646495 | 764 | |
4328633d | 765 | return; |
4e646495 JN |
766 | |
767 | err: | |
768 | drm_encoder_cleanup(&intel_encoder->base); | |
769 | kfree(intel_dsi); | |
770 | kfree(intel_connector); | |
4e646495 | 771 | } |