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4e646495 JN |
1 | /* |
2 | * Copyright © 2013 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
21 | * DEALINGS IN THE SOFTWARE. | |
22 | * | |
23 | * Author: Jani Nikula <jani.nikula@intel.com> | |
24 | */ | |
25 | ||
26 | #include <drm/drmP.h> | |
c6f95f27 | 27 | #include <drm/drm_atomic_helper.h> |
4e646495 JN |
28 | #include <drm/drm_crtc.h> |
29 | #include <drm/drm_edid.h> | |
30 | #include <drm/i915_drm.h> | |
593e0622 | 31 | #include <drm/drm_panel.h> |
7e9804fd | 32 | #include <drm/drm_mipi_dsi.h> |
4e646495 | 33 | #include <linux/slab.h> |
fc45e821 | 34 | #include <linux/gpio/consumer.h> |
4e646495 JN |
35 | #include "i915_drv.h" |
36 | #include "intel_drv.h" | |
37 | #include "intel_dsi.h" | |
4e646495 | 38 | |
593e0622 JN |
39 | static const struct { |
40 | u16 panel_id; | |
41 | struct drm_panel * (*init)(struct intel_dsi *intel_dsi, u16 panel_id); | |
42 | } intel_dsi_drivers[] = { | |
2ab8b458 SK |
43 | { |
44 | .panel_id = MIPI_DSI_GENERIC_PANEL_ID, | |
593e0622 | 45 | .init = vbt_panel_init, |
2ab8b458 | 46 | }, |
4e646495 JN |
47 | }; |
48 | ||
43367ec9 R |
49 | enum mipi_dsi_pixel_format pixel_format_from_register_bits(u32 fmt) |
50 | { | |
51 | /* It just so happens the VBT matches register contents. */ | |
52 | switch (fmt) { | |
53 | case VID_MODE_FORMAT_RGB888: | |
54 | return MIPI_DSI_FMT_RGB888; | |
55 | case VID_MODE_FORMAT_RGB666: | |
56 | return MIPI_DSI_FMT_RGB666; | |
57 | case VID_MODE_FORMAT_RGB666_PACKED: | |
58 | return MIPI_DSI_FMT_RGB666_PACKED; | |
59 | case VID_MODE_FORMAT_RGB565: | |
60 | return MIPI_DSI_FMT_RGB565; | |
61 | default: | |
62 | MISSING_CASE(fmt); | |
63 | return MIPI_DSI_FMT_RGB666; | |
64 | } | |
65 | } | |
66 | ||
7f6a6a4a | 67 | static void wait_for_dsi_fifo_empty(struct intel_dsi *intel_dsi, enum port port) |
3b1808bf JN |
68 | { |
69 | struct drm_encoder *encoder = &intel_dsi->base.base; | |
70 | struct drm_device *dev = encoder->dev; | |
71 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3b1808bf JN |
72 | u32 mask; |
73 | ||
74 | mask = LP_CTRL_FIFO_EMPTY | HS_CTRL_FIFO_EMPTY | | |
75 | LP_DATA_FIFO_EMPTY | HS_DATA_FIFO_EMPTY; | |
76 | ||
77 | if (wait_for((I915_READ(MIPI_GEN_FIFO_STAT(port)) & mask) == mask, 100)) | |
78 | DRM_ERROR("DPI FIFOs are not empty\n"); | |
79 | } | |
80 | ||
f0f59a00 VS |
81 | static void write_data(struct drm_i915_private *dev_priv, |
82 | i915_reg_t reg, | |
7e9804fd JN |
83 | const u8 *data, u32 len) |
84 | { | |
85 | u32 i, j; | |
86 | ||
87 | for (i = 0; i < len; i += 4) { | |
88 | u32 val = 0; | |
89 | ||
90 | for (j = 0; j < min_t(u32, len - i, 4); j++) | |
91 | val |= *data++ << 8 * j; | |
92 | ||
93 | I915_WRITE(reg, val); | |
94 | } | |
95 | } | |
96 | ||
f0f59a00 VS |
97 | static void read_data(struct drm_i915_private *dev_priv, |
98 | i915_reg_t reg, | |
7e9804fd JN |
99 | u8 *data, u32 len) |
100 | { | |
101 | u32 i, j; | |
102 | ||
103 | for (i = 0; i < len; i += 4) { | |
104 | u32 val = I915_READ(reg); | |
105 | ||
106 | for (j = 0; j < min_t(u32, len - i, 4); j++) | |
107 | *data++ = val >> 8 * j; | |
108 | } | |
109 | } | |
110 | ||
111 | static ssize_t intel_dsi_host_transfer(struct mipi_dsi_host *host, | |
112 | const struct mipi_dsi_msg *msg) | |
113 | { | |
114 | struct intel_dsi_host *intel_dsi_host = to_intel_dsi_host(host); | |
115 | struct drm_device *dev = intel_dsi_host->intel_dsi->base.base.dev; | |
116 | struct drm_i915_private *dev_priv = dev->dev_private; | |
117 | enum port port = intel_dsi_host->port; | |
118 | struct mipi_dsi_packet packet; | |
119 | ssize_t ret; | |
120 | const u8 *header, *data; | |
f0f59a00 VS |
121 | i915_reg_t data_reg, ctrl_reg; |
122 | u32 data_mask, ctrl_mask; | |
7e9804fd JN |
123 | |
124 | ret = mipi_dsi_create_packet(&packet, msg); | |
125 | if (ret < 0) | |
126 | return ret; | |
127 | ||
128 | header = packet.header; | |
129 | data = packet.payload; | |
130 | ||
131 | if (msg->flags & MIPI_DSI_MSG_USE_LPM) { | |
132 | data_reg = MIPI_LP_GEN_DATA(port); | |
133 | data_mask = LP_DATA_FIFO_FULL; | |
134 | ctrl_reg = MIPI_LP_GEN_CTRL(port); | |
135 | ctrl_mask = LP_CTRL_FIFO_FULL; | |
136 | } else { | |
137 | data_reg = MIPI_HS_GEN_DATA(port); | |
138 | data_mask = HS_DATA_FIFO_FULL; | |
139 | ctrl_reg = MIPI_HS_GEN_CTRL(port); | |
140 | ctrl_mask = HS_CTRL_FIFO_FULL; | |
141 | } | |
142 | ||
143 | /* note: this is never true for reads */ | |
144 | if (packet.payload_length) { | |
145 | ||
146 | if (wait_for((I915_READ(MIPI_GEN_FIFO_STAT(port)) & data_mask) == 0, 50)) | |
147 | DRM_ERROR("Timeout waiting for HS/LP DATA FIFO !full\n"); | |
148 | ||
149 | write_data(dev_priv, data_reg, packet.payload, | |
150 | packet.payload_length); | |
151 | } | |
152 | ||
153 | if (msg->rx_len) { | |
154 | I915_WRITE(MIPI_INTR_STAT(port), GEN_READ_DATA_AVAIL); | |
155 | } | |
156 | ||
157 | if (wait_for((I915_READ(MIPI_GEN_FIFO_STAT(port)) & ctrl_mask) == 0, 50)) { | |
158 | DRM_ERROR("Timeout waiting for HS/LP CTRL FIFO !full\n"); | |
159 | } | |
160 | ||
161 | I915_WRITE(ctrl_reg, header[2] << 16 | header[1] << 8 | header[0]); | |
162 | ||
163 | /* ->rx_len is set only for reads */ | |
164 | if (msg->rx_len) { | |
165 | data_mask = GEN_READ_DATA_AVAIL; | |
166 | if (wait_for((I915_READ(MIPI_INTR_STAT(port)) & data_mask) == data_mask, 50)) | |
167 | DRM_ERROR("Timeout waiting for read data.\n"); | |
168 | ||
169 | read_data(dev_priv, data_reg, msg->rx_buf, msg->rx_len); | |
170 | } | |
171 | ||
172 | /* XXX: fix for reads and writes */ | |
173 | return 4 + packet.payload_length; | |
174 | } | |
175 | ||
176 | static int intel_dsi_host_attach(struct mipi_dsi_host *host, | |
177 | struct mipi_dsi_device *dsi) | |
178 | { | |
179 | return 0; | |
180 | } | |
181 | ||
182 | static int intel_dsi_host_detach(struct mipi_dsi_host *host, | |
183 | struct mipi_dsi_device *dsi) | |
184 | { | |
185 | return 0; | |
186 | } | |
187 | ||
188 | static const struct mipi_dsi_host_ops intel_dsi_host_ops = { | |
189 | .attach = intel_dsi_host_attach, | |
190 | .detach = intel_dsi_host_detach, | |
191 | .transfer = intel_dsi_host_transfer, | |
192 | }; | |
193 | ||
194 | static struct intel_dsi_host *intel_dsi_host_init(struct intel_dsi *intel_dsi, | |
195 | enum port port) | |
196 | { | |
197 | struct intel_dsi_host *host; | |
198 | struct mipi_dsi_device *device; | |
199 | ||
200 | host = kzalloc(sizeof(*host), GFP_KERNEL); | |
201 | if (!host) | |
202 | return NULL; | |
203 | ||
204 | host->base.ops = &intel_dsi_host_ops; | |
205 | host->intel_dsi = intel_dsi; | |
206 | host->port = port; | |
207 | ||
208 | /* | |
209 | * We should call mipi_dsi_host_register(&host->base) here, but we don't | |
210 | * have a host->dev, and we don't have OF stuff either. So just use the | |
211 | * dsi framework as a library and hope for the best. Create the dsi | |
212 | * devices by ourselves here too. Need to be careful though, because we | |
213 | * don't initialize any of the driver model devices here. | |
214 | */ | |
215 | device = kzalloc(sizeof(*device), GFP_KERNEL); | |
216 | if (!device) { | |
217 | kfree(host); | |
218 | return NULL; | |
219 | } | |
220 | ||
221 | device->host = &host->base; | |
222 | host->device = device; | |
223 | ||
224 | return host; | |
225 | } | |
226 | ||
a2581a9e JN |
227 | /* |
228 | * send a video mode command | |
229 | * | |
230 | * XXX: commands with data in MIPI_DPI_DATA? | |
231 | */ | |
232 | static int dpi_send_cmd(struct intel_dsi *intel_dsi, u32 cmd, bool hs, | |
233 | enum port port) | |
234 | { | |
235 | struct drm_encoder *encoder = &intel_dsi->base.base; | |
236 | struct drm_device *dev = encoder->dev; | |
237 | struct drm_i915_private *dev_priv = dev->dev_private; | |
238 | u32 mask; | |
239 | ||
240 | /* XXX: pipe, hs */ | |
241 | if (hs) | |
242 | cmd &= ~DPI_LP_MODE; | |
243 | else | |
244 | cmd |= DPI_LP_MODE; | |
245 | ||
246 | /* clear bit */ | |
247 | I915_WRITE(MIPI_INTR_STAT(port), SPL_PKT_SENT_INTERRUPT); | |
248 | ||
249 | /* XXX: old code skips write if control unchanged */ | |
250 | if (cmd == I915_READ(MIPI_DPI_CONTROL(port))) | |
251 | DRM_ERROR("Same special packet %02x twice in a row.\n", cmd); | |
252 | ||
253 | I915_WRITE(MIPI_DPI_CONTROL(port), cmd); | |
254 | ||
255 | mask = SPL_PKT_SENT_INTERRUPT; | |
256 | if (wait_for((I915_READ(MIPI_INTR_STAT(port)) & mask) == mask, 100)) | |
257 | DRM_ERROR("Video mode command 0x%08x send failed.\n", cmd); | |
258 | ||
259 | return 0; | |
260 | } | |
261 | ||
e9fe51c6 | 262 | static void band_gap_reset(struct drm_i915_private *dev_priv) |
4ce8c9a7 | 263 | { |
a580516d | 264 | mutex_lock(&dev_priv->sb_lock); |
4ce8c9a7 | 265 | |
e9fe51c6 SK |
266 | vlv_flisdsi_write(dev_priv, 0x08, 0x0001); |
267 | vlv_flisdsi_write(dev_priv, 0x0F, 0x0005); | |
268 | vlv_flisdsi_write(dev_priv, 0x0F, 0x0025); | |
269 | udelay(150); | |
270 | vlv_flisdsi_write(dev_priv, 0x0F, 0x0000); | |
271 | vlv_flisdsi_write(dev_priv, 0x08, 0x0000); | |
4ce8c9a7 | 272 | |
a580516d | 273 | mutex_unlock(&dev_priv->sb_lock); |
4ce8c9a7 SK |
274 | } |
275 | ||
4e646495 JN |
276 | static inline bool is_vid_mode(struct intel_dsi *intel_dsi) |
277 | { | |
dfba2e2d | 278 | return intel_dsi->operation_mode == INTEL_DSI_VIDEO_MODE; |
4e646495 JN |
279 | } |
280 | ||
281 | static inline bool is_cmd_mode(struct intel_dsi *intel_dsi) | |
282 | { | |
dfba2e2d | 283 | return intel_dsi->operation_mode == INTEL_DSI_COMMAND_MODE; |
4e646495 JN |
284 | } |
285 | ||
4e646495 | 286 | static bool intel_dsi_compute_config(struct intel_encoder *encoder, |
a65347ba | 287 | struct intel_crtc_state *pipe_config) |
4e646495 | 288 | { |
4d1de975 | 289 | struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; |
4e646495 JN |
290 | struct intel_dsi *intel_dsi = container_of(encoder, struct intel_dsi, |
291 | base); | |
292 | struct intel_connector *intel_connector = intel_dsi->attached_connector; | |
293 | struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode; | |
a65347ba | 294 | struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; |
4e646495 JN |
295 | |
296 | DRM_DEBUG_KMS("\n"); | |
297 | ||
a65347ba JN |
298 | pipe_config->has_dsi_encoder = true; |
299 | ||
4e646495 JN |
300 | if (fixed_mode) |
301 | intel_fixed_panel_mode(fixed_mode, adjusted_mode); | |
302 | ||
f573de5a SK |
303 | /* DSI uses short packets for sync events, so clear mode flags for DSI */ |
304 | adjusted_mode->flags = 0; | |
305 | ||
4d1de975 JN |
306 | if (IS_BROXTON(dev_priv)) { |
307 | /* Dual link goes to DSI transcoder A. */ | |
308 | if (intel_dsi->ports == BIT(PORT_C)) | |
309 | pipe_config->cpu_transcoder = TRANSCODER_DSI_C; | |
310 | else | |
311 | pipe_config->cpu_transcoder = TRANSCODER_DSI_A; | |
312 | } | |
313 | ||
cd2d34d9 VS |
314 | /* |
315 | * FIXME move the DSI PLL calc from vlv_enable_dsi_pll() | |
316 | * to .compute_config(). | |
317 | */ | |
318 | pipe_config->clock_set = true; | |
319 | ||
4e646495 JN |
320 | return true; |
321 | } | |
322 | ||
37ab0810 | 323 | static void bxt_dsi_device_ready(struct intel_encoder *encoder) |
5505a244 | 324 | { |
37ab0810 | 325 | struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; |
5505a244 | 326 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); |
369602d3 | 327 | enum port port; |
37ab0810 | 328 | u32 val; |
5505a244 | 329 | |
37ab0810 | 330 | DRM_DEBUG_KMS("\n"); |
a9da9bce | 331 | |
37ab0810 | 332 | /* Exit Low power state in 4 steps*/ |
369602d3 | 333 | for_each_dsi_port(port, intel_dsi->ports) { |
5505a244 | 334 | |
37ab0810 SS |
335 | /* 1. Enable MIPI PHY transparent latch */ |
336 | val = I915_READ(BXT_MIPI_PORT_CTRL(port)); | |
337 | I915_WRITE(BXT_MIPI_PORT_CTRL(port), val | LP_OUTPUT_HOLD); | |
338 | usleep_range(2000, 2500); | |
339 | ||
340 | /* 2. Enter ULPS */ | |
341 | val = I915_READ(MIPI_DEVICE_READY(port)); | |
342 | val &= ~ULPS_STATE_MASK; | |
343 | val |= (ULPS_STATE_ENTER | DEVICE_READY); | |
344 | I915_WRITE(MIPI_DEVICE_READY(port), val); | |
345 | usleep_range(2, 3); | |
346 | ||
347 | /* 3. Exit ULPS */ | |
348 | val = I915_READ(MIPI_DEVICE_READY(port)); | |
349 | val &= ~ULPS_STATE_MASK; | |
350 | val |= (ULPS_STATE_EXIT | DEVICE_READY); | |
351 | I915_WRITE(MIPI_DEVICE_READY(port), val); | |
352 | usleep_range(1000, 1500); | |
5505a244 | 353 | |
37ab0810 SS |
354 | /* Clear ULPS and set device ready */ |
355 | val = I915_READ(MIPI_DEVICE_READY(port)); | |
356 | val &= ~ULPS_STATE_MASK; | |
357 | val |= DEVICE_READY; | |
358 | I915_WRITE(MIPI_DEVICE_READY(port), val); | |
369602d3 | 359 | } |
5505a244 GS |
360 | } |
361 | ||
37ab0810 | 362 | static void vlv_dsi_device_ready(struct intel_encoder *encoder) |
4e646495 | 363 | { |
1dbd7cb2 | 364 | struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; |
24ee0e64 GS |
365 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); |
366 | enum port port; | |
1dbd7cb2 SK |
367 | u32 val; |
368 | ||
4e646495 | 369 | DRM_DEBUG_KMS("\n"); |
4e646495 | 370 | |
a580516d | 371 | mutex_lock(&dev_priv->sb_lock); |
2095f9fc SK |
372 | /* program rcomp for compliance, reduce from 50 ohms to 45 ohms |
373 | * needed everytime after power gate */ | |
374 | vlv_flisdsi_write(dev_priv, 0x04, 0x0004); | |
a580516d | 375 | mutex_unlock(&dev_priv->sb_lock); |
2095f9fc SK |
376 | |
377 | /* bandgap reset is needed after everytime we do power gate */ | |
378 | band_gap_reset(dev_priv); | |
379 | ||
24ee0e64 | 380 | for_each_dsi_port(port, intel_dsi->ports) { |
aceb365c | 381 | |
24ee0e64 GS |
382 | I915_WRITE(MIPI_DEVICE_READY(port), ULPS_STATE_ENTER); |
383 | usleep_range(2500, 3000); | |
aceb365c | 384 | |
bf344e80 GS |
385 | /* Enable MIPI PHY transparent latch |
386 | * Common bit for both MIPI Port A & MIPI Port C | |
387 | * No similar bit in MIPI Port C reg | |
388 | */ | |
4ba7d93a | 389 | val = I915_READ(MIPI_PORT_CTRL(PORT_A)); |
bf344e80 | 390 | I915_WRITE(MIPI_PORT_CTRL(PORT_A), val | LP_OUTPUT_HOLD); |
24ee0e64 | 391 | usleep_range(1000, 1500); |
aceb365c | 392 | |
24ee0e64 GS |
393 | I915_WRITE(MIPI_DEVICE_READY(port), ULPS_STATE_EXIT); |
394 | usleep_range(2500, 3000); | |
395 | ||
396 | I915_WRITE(MIPI_DEVICE_READY(port), DEVICE_READY); | |
397 | usleep_range(2500, 3000); | |
398 | } | |
1dbd7cb2 | 399 | } |
1dbd7cb2 | 400 | |
37ab0810 SS |
401 | static void intel_dsi_device_ready(struct intel_encoder *encoder) |
402 | { | |
403 | struct drm_device *dev = encoder->base.dev; | |
404 | ||
666a4537 | 405 | if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) |
37ab0810 SS |
406 | vlv_dsi_device_ready(encoder); |
407 | else if (IS_BROXTON(dev)) | |
408 | bxt_dsi_device_ready(encoder); | |
409 | } | |
410 | ||
411 | static void intel_dsi_port_enable(struct intel_encoder *encoder) | |
412 | { | |
413 | struct drm_device *dev = encoder->base.dev; | |
414 | struct drm_i915_private *dev_priv = dev->dev_private; | |
415 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); | |
416 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); | |
417 | enum port port; | |
37ab0810 SS |
418 | |
419 | if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) { | |
f0f59a00 VS |
420 | u32 temp; |
421 | ||
37ab0810 SS |
422 | temp = I915_READ(VLV_CHICKEN_3); |
423 | temp &= ~PIXEL_OVERLAP_CNT_MASK | | |
424 | intel_dsi->pixel_overlap << | |
425 | PIXEL_OVERLAP_CNT_SHIFT; | |
426 | I915_WRITE(VLV_CHICKEN_3, temp); | |
427 | } | |
428 | ||
429 | for_each_dsi_port(port, intel_dsi->ports) { | |
f0f59a00 VS |
430 | i915_reg_t port_ctrl = IS_BROXTON(dev) ? |
431 | BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(port); | |
432 | u32 temp; | |
37ab0810 SS |
433 | |
434 | temp = I915_READ(port_ctrl); | |
435 | ||
436 | temp &= ~LANE_CONFIGURATION_MASK; | |
437 | temp &= ~DUAL_LINK_MODE_MASK; | |
438 | ||
701d25b4 | 439 | if (intel_dsi->ports == (BIT(PORT_A) | BIT(PORT_C))) { |
37ab0810 SS |
440 | temp |= (intel_dsi->dual_link - 1) |
441 | << DUAL_LINK_MODE_SHIFT; | |
442 | temp |= intel_crtc->pipe ? | |
443 | LANE_CONFIGURATION_DUAL_LINK_B : | |
444 | LANE_CONFIGURATION_DUAL_LINK_A; | |
445 | } | |
446 | /* assert ip_tg_enable signal */ | |
447 | I915_WRITE(port_ctrl, temp | DPI_ENABLE); | |
448 | POSTING_READ(port_ctrl); | |
449 | } | |
450 | } | |
451 | ||
452 | static void intel_dsi_port_disable(struct intel_encoder *encoder) | |
453 | { | |
454 | struct drm_device *dev = encoder->base.dev; | |
455 | struct drm_i915_private *dev_priv = dev->dev_private; | |
456 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); | |
457 | enum port port; | |
37ab0810 SS |
458 | |
459 | for_each_dsi_port(port, intel_dsi->ports) { | |
f0f59a00 VS |
460 | i915_reg_t port_ctrl = IS_BROXTON(dev) ? |
461 | BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(port); | |
462 | u32 temp; | |
463 | ||
37ab0810 | 464 | /* de-assert ip_tg_enable signal */ |
b389a45c SS |
465 | temp = I915_READ(port_ctrl); |
466 | I915_WRITE(port_ctrl, temp & ~DPI_ENABLE); | |
467 | POSTING_READ(port_ctrl); | |
37ab0810 SS |
468 | } |
469 | } | |
470 | ||
1dbd7cb2 SK |
471 | static void intel_dsi_enable(struct intel_encoder *encoder) |
472 | { | |
473 | struct drm_device *dev = encoder->base.dev; | |
474 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1dbd7cb2 | 475 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); |
4934b656 | 476 | enum port port; |
1dbd7cb2 SK |
477 | |
478 | DRM_DEBUG_KMS("\n"); | |
b9f5e07d | 479 | |
4934b656 JN |
480 | if (is_cmd_mode(intel_dsi)) { |
481 | for_each_dsi_port(port, intel_dsi->ports) | |
482 | I915_WRITE(MIPI_MAX_RETURN_PKT_SIZE(port), 8 * 4); | |
483 | } else { | |
4e646495 | 484 | msleep(20); /* XXX */ |
f03e4179 | 485 | for_each_dsi_port(port, intel_dsi->ports) |
a2581a9e | 486 | dpi_send_cmd(intel_dsi, TURN_ON, false, port); |
4e646495 JN |
487 | msleep(100); |
488 | ||
593e0622 | 489 | drm_panel_enable(intel_dsi->panel); |
2634fd7f | 490 | |
7f6a6a4a JN |
491 | for_each_dsi_port(port, intel_dsi->ports) |
492 | wait_for_dsi_fifo_empty(intel_dsi, port); | |
1381308b | 493 | |
5505a244 | 494 | intel_dsi_port_enable(encoder); |
4e646495 | 495 | } |
b029e66f SK |
496 | |
497 | intel_panel_enable_backlight(intel_dsi->attached_connector); | |
2634fd7f SK |
498 | } |
499 | ||
e3488e75 JN |
500 | static void intel_dsi_prepare(struct intel_encoder *intel_encoder); |
501 | ||
2634fd7f SK |
502 | static void intel_dsi_pre_enable(struct intel_encoder *encoder) |
503 | { | |
20e5bf66 SK |
504 | struct drm_device *dev = encoder->base.dev; |
505 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2634fd7f | 506 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); |
7f6a6a4a | 507 | enum port port; |
20e5bf66 | 508 | u32 tmp; |
2634fd7f SK |
509 | |
510 | DRM_DEBUG_KMS("\n"); | |
511 | ||
f00b5689 VS |
512 | /* |
513 | * The BIOS may leave the PLL in a wonky state where it doesn't | |
514 | * lock. It needs to be fully powered down to fix it. | |
515 | */ | |
516 | intel_disable_dsi_pll(encoder); | |
e3488e75 | 517 | intel_enable_dsi_pll(encoder); |
f00b5689 | 518 | |
58d4d32f | 519 | intel_dsi_prepare(encoder); |
e3488e75 | 520 | |
fc45e821 SK |
521 | /* Panel Enable over CRC PMIC */ |
522 | if (intel_dsi->gpio_panel) | |
523 | gpiod_set_value_cansleep(intel_dsi->gpio_panel, 1); | |
524 | ||
525 | msleep(intel_dsi->panel_on_delay); | |
526 | ||
666a4537 | 527 | if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
cd2d34d9 | 528 | /* Disable DPOunit clock gating, can stall pipe */ |
37ab0810 SS |
529 | tmp = I915_READ(DSPCLK_GATE_D); |
530 | tmp |= DPOUNIT_CLOCK_GATE_DISABLE; | |
531 | I915_WRITE(DSPCLK_GATE_D, tmp); | |
532 | } | |
2634fd7f SK |
533 | |
534 | /* put device in ready state */ | |
535 | intel_dsi_device_ready(encoder); | |
4e646495 | 536 | |
593e0622 | 537 | drm_panel_prepare(intel_dsi->panel); |
20e5bf66 | 538 | |
7f6a6a4a JN |
539 | for_each_dsi_port(port, intel_dsi->ports) |
540 | wait_for_dsi_fifo_empty(intel_dsi, port); | |
1381308b | 541 | |
2634fd7f SK |
542 | /* Enable port in pre-enable phase itself because as per hw team |
543 | * recommendation, port should be enabled befor plane & pipe */ | |
544 | intel_dsi_enable(encoder); | |
545 | } | |
546 | ||
547 | static void intel_dsi_enable_nop(struct intel_encoder *encoder) | |
548 | { | |
549 | DRM_DEBUG_KMS("\n"); | |
550 | ||
551 | /* for DSI port enable has to be done before pipe | |
552 | * and plane enable, so port enable is done in | |
553 | * pre_enable phase itself unlike other encoders | |
554 | */ | |
4e646495 JN |
555 | } |
556 | ||
c315faf8 ID |
557 | static void intel_dsi_pre_disable(struct intel_encoder *encoder) |
558 | { | |
559 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); | |
f03e4179 | 560 | enum port port; |
c315faf8 ID |
561 | |
562 | DRM_DEBUG_KMS("\n"); | |
563 | ||
b029e66f SK |
564 | intel_panel_disable_backlight(intel_dsi->attached_connector); |
565 | ||
c315faf8 ID |
566 | if (is_vid_mode(intel_dsi)) { |
567 | /* Send Shutdown command to the panel in LP mode */ | |
f03e4179 | 568 | for_each_dsi_port(port, intel_dsi->ports) |
a2581a9e | 569 | dpi_send_cmd(intel_dsi, SHUTDOWN, false, port); |
c315faf8 ID |
570 | msleep(10); |
571 | } | |
572 | } | |
573 | ||
4e646495 JN |
574 | static void intel_dsi_disable(struct intel_encoder *encoder) |
575 | { | |
1dbd7cb2 SK |
576 | struct drm_device *dev = encoder->base.dev; |
577 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4e646495 | 578 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); |
384f02a2 | 579 | enum port port; |
4e646495 JN |
580 | u32 temp; |
581 | ||
582 | DRM_DEBUG_KMS("\n"); | |
583 | ||
4e646495 | 584 | if (is_vid_mode(intel_dsi)) { |
7f6a6a4a JN |
585 | for_each_dsi_port(port, intel_dsi->ports) |
586 | wait_for_dsi_fifo_empty(intel_dsi, port); | |
1381308b | 587 | |
5505a244 | 588 | intel_dsi_port_disable(encoder); |
4e646495 JN |
589 | msleep(2); |
590 | } | |
591 | ||
384f02a2 GS |
592 | for_each_dsi_port(port, intel_dsi->ports) { |
593 | /* Panel commands can be sent when clock is in LP11 */ | |
594 | I915_WRITE(MIPI_DEVICE_READY(port), 0x0); | |
339023ec | 595 | |
b389a45c | 596 | intel_dsi_reset_clocks(encoder, port); |
384f02a2 | 597 | I915_WRITE(MIPI_EOT_DISABLE(port), CLOCKSTOP); |
339023ec | 598 | |
384f02a2 GS |
599 | temp = I915_READ(MIPI_DSI_FUNC_PRG(port)); |
600 | temp &= ~VID_MODE_FORMAT_MASK; | |
601 | I915_WRITE(MIPI_DSI_FUNC_PRG(port), temp); | |
339023ec | 602 | |
384f02a2 GS |
603 | I915_WRITE(MIPI_DEVICE_READY(port), 0x1); |
604 | } | |
1dbd7cb2 SK |
605 | /* if disable packets are sent before sending shutdown packet then in |
606 | * some next enable sequence send turn on packet error is observed */ | |
593e0622 | 607 | drm_panel_disable(intel_dsi->panel); |
1381308b | 608 | |
7f6a6a4a JN |
609 | for_each_dsi_port(port, intel_dsi->ports) |
610 | wait_for_dsi_fifo_empty(intel_dsi, port); | |
4e646495 JN |
611 | } |
612 | ||
1dbd7cb2 | 613 | static void intel_dsi_clear_device_ready(struct intel_encoder *encoder) |
4e646495 | 614 | { |
b389a45c | 615 | struct drm_device *dev = encoder->base.dev; |
1dbd7cb2 | 616 | struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; |
384f02a2 GS |
617 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); |
618 | enum port port; | |
1dbd7cb2 | 619 | |
4e646495 | 620 | DRM_DEBUG_KMS("\n"); |
384f02a2 | 621 | for_each_dsi_port(port, intel_dsi->ports) { |
f0f59a00 VS |
622 | /* Common bit for both MIPI Port A & MIPI Port C on VLV/CHV */ |
623 | i915_reg_t port_ctrl = IS_BROXTON(dev) ? | |
624 | BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(PORT_A); | |
625 | u32 val; | |
be4fc046 | 626 | |
384f02a2 GS |
627 | I915_WRITE(MIPI_DEVICE_READY(port), DEVICE_READY | |
628 | ULPS_STATE_ENTER); | |
629 | usleep_range(2000, 2500); | |
630 | ||
631 | I915_WRITE(MIPI_DEVICE_READY(port), DEVICE_READY | | |
632 | ULPS_STATE_EXIT); | |
633 | usleep_range(2000, 2500); | |
634 | ||
635 | I915_WRITE(MIPI_DEVICE_READY(port), DEVICE_READY | | |
636 | ULPS_STATE_ENTER); | |
637 | usleep_range(2000, 2500); | |
638 | ||
639 | /* Wait till Clock lanes are in LP-00 state for MIPI Port A | |
640 | * only. MIPI Port C has no similar bit for checking | |
641 | */ | |
b389a45c SS |
642 | if (wait_for(((I915_READ(port_ctrl) & AFE_LATCHOUT) |
643 | == 0x00000), 30)) | |
384f02a2 GS |
644 | DRM_ERROR("DSI LP not going Low\n"); |
645 | ||
b389a45c SS |
646 | /* Disable MIPI PHY transparent latch */ |
647 | val = I915_READ(port_ctrl); | |
648 | I915_WRITE(port_ctrl, val & ~LP_OUTPUT_HOLD); | |
384f02a2 GS |
649 | usleep_range(1000, 1500); |
650 | ||
651 | I915_WRITE(MIPI_DEVICE_READY(port), 0x00); | |
652 | usleep_range(2000, 2500); | |
653 | } | |
1dbd7cb2 | 654 | |
fe88fc68 | 655 | intel_disable_dsi_pll(encoder); |
4e646495 | 656 | } |
20e5bf66 | 657 | |
1dbd7cb2 SK |
658 | static void intel_dsi_post_disable(struct intel_encoder *encoder) |
659 | { | |
20e5bf66 | 660 | struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; |
1dbd7cb2 SK |
661 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); |
662 | ||
663 | DRM_DEBUG_KMS("\n"); | |
664 | ||
c315faf8 ID |
665 | intel_dsi_disable(encoder); |
666 | ||
1dbd7cb2 SK |
667 | intel_dsi_clear_device_ready(encoder); |
668 | ||
d6e3af54 US |
669 | if (!IS_BROXTON(dev_priv)) { |
670 | u32 val; | |
671 | ||
672 | val = I915_READ(DSPCLK_GATE_D); | |
673 | val &= ~DPOUNIT_CLOCK_GATE_DISABLE; | |
674 | I915_WRITE(DSPCLK_GATE_D, val); | |
675 | } | |
20e5bf66 | 676 | |
593e0622 | 677 | drm_panel_unprepare(intel_dsi->panel); |
df38e655 SK |
678 | |
679 | msleep(intel_dsi->panel_off_delay); | |
680 | msleep(intel_dsi->panel_pwr_cycle_delay); | |
fc45e821 SK |
681 | |
682 | /* Panel Disable over CRC PMIC */ | |
683 | if (intel_dsi->gpio_panel) | |
684 | gpiod_set_value_cansleep(intel_dsi->gpio_panel, 0); | |
1dbd7cb2 | 685 | } |
4e646495 JN |
686 | |
687 | static bool intel_dsi_get_hw_state(struct intel_encoder *encoder, | |
688 | enum pipe *pipe) | |
689 | { | |
690 | struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; | |
c0beefd2 GS |
691 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); |
692 | struct drm_device *dev = encoder->base.dev; | |
6d129bea | 693 | enum intel_display_power_domain power_domain; |
e7d7cad0 | 694 | enum port port; |
1dcec2f3 | 695 | bool active = false; |
4e646495 JN |
696 | |
697 | DRM_DEBUG_KMS("\n"); | |
698 | ||
6d129bea | 699 | power_domain = intel_display_port_power_domain(encoder); |
3f3f42b8 | 700 | if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) |
6d129bea ID |
701 | return false; |
702 | ||
db18b6a6 ID |
703 | /* |
704 | * On Broxton the PLL needs to be enabled with a valid divider | |
705 | * configuration, otherwise accessing DSI registers will hang the | |
706 | * machine. See BSpec North Display Engine registers/MIPI[BXT]. | |
707 | */ | |
708 | if (IS_BROXTON(dev_priv) && !intel_dsi_pll_is_enabled(dev_priv)) | |
709 | goto out_put_power; | |
710 | ||
4e646495 | 711 | /* XXX: this only works for one DSI output */ |
c0beefd2 | 712 | for_each_dsi_port(port, intel_dsi->ports) { |
f0f59a00 VS |
713 | i915_reg_t ctrl_reg = IS_BROXTON(dev) ? |
714 | BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(port); | |
1dcec2f3 | 715 | bool enabled = I915_READ(ctrl_reg) & DPI_ENABLE; |
c0beefd2 GS |
716 | |
717 | /* Due to some hardware limitations on BYT, MIPI Port C DPI | |
718 | * Enable bit does not get set. To check whether DSI Port C | |
719 | * was enabled in BIOS, check the Pipe B enable bit | |
720 | */ | |
666a4537 | 721 | if (IS_VALLEYVIEW(dev) && port == PORT_C) |
1dcec2f3 | 722 | enabled = I915_READ(PIPECONF(PIPE_B)) & PIPECONF_ENABLE; |
4e646495 | 723 | |
1dcec2f3 JN |
724 | /* Try command mode if video mode not enabled */ |
725 | if (!enabled) { | |
726 | u32 tmp = I915_READ(MIPI_DSI_FUNC_PRG(port)); | |
727 | enabled = tmp & CMD_MODE_DATA_WIDTH_MASK; | |
4e646495 | 728 | } |
1dcec2f3 JN |
729 | |
730 | if (!enabled) | |
731 | continue; | |
732 | ||
733 | if (!(I915_READ(MIPI_DEVICE_READY(port)) & DEVICE_READY)) | |
734 | continue; | |
735 | ||
6b93e9c8 JN |
736 | if (IS_BROXTON(dev_priv)) { |
737 | u32 tmp = I915_READ(MIPI_CTRL(port)); | |
738 | tmp &= BXT_PIPE_SELECT_MASK; | |
739 | tmp >>= BXT_PIPE_SELECT_SHIFT; | |
740 | ||
741 | if (WARN_ON(tmp > PIPE_C)) | |
742 | continue; | |
743 | ||
744 | *pipe = tmp; | |
745 | } else { | |
746 | *pipe = port == PORT_A ? PIPE_A : PIPE_B; | |
747 | } | |
748 | ||
1dcec2f3 JN |
749 | active = true; |
750 | break; | |
4e646495 | 751 | } |
1dcec2f3 | 752 | |
db18b6a6 | 753 | out_put_power: |
3f3f42b8 | 754 | intel_display_power_put(dev_priv, power_domain); |
4e646495 | 755 | |
1dcec2f3 | 756 | return active; |
4e646495 JN |
757 | } |
758 | ||
6f0e7535 R |
759 | static void bxt_dsi_get_pipe_config(struct intel_encoder *encoder, |
760 | struct intel_crtc_state *pipe_config) | |
761 | { | |
762 | struct drm_device *dev = encoder->base.dev; | |
763 | struct drm_i915_private *dev_priv = dev->dev_private; | |
764 | struct drm_display_mode *adjusted_mode = | |
765 | &pipe_config->base.adjusted_mode; | |
766 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); | |
767 | unsigned int bpp, fmt; | |
768 | enum port port; | |
769 | u16 vfp, vsync, vbp; | |
770 | ||
771 | /* | |
772 | * Atleast one port is active as encoder->get_config called only if | |
773 | * encoder->get_hw_state() returns true. | |
774 | */ | |
775 | for_each_dsi_port(port, intel_dsi->ports) { | |
776 | if (I915_READ(BXT_MIPI_PORT_CTRL(port)) & DPI_ENABLE) | |
777 | break; | |
778 | } | |
779 | ||
780 | fmt = I915_READ(MIPI_DSI_FUNC_PRG(port)) & VID_MODE_FORMAT_MASK; | |
781 | pipe_config->pipe_bpp = | |
782 | mipi_dsi_pixel_format_to_bpp( | |
783 | pixel_format_from_register_bits(fmt)); | |
784 | bpp = pipe_config->pipe_bpp; | |
785 | ||
786 | /* In terms of pixels */ | |
787 | adjusted_mode->crtc_hdisplay = | |
788 | I915_READ(BXT_MIPI_TRANS_HACTIVE(port)); | |
789 | adjusted_mode->crtc_vdisplay = | |
790 | I915_READ(BXT_MIPI_TRANS_VACTIVE(port)); | |
791 | adjusted_mode->crtc_vtotal = | |
792 | I915_READ(BXT_MIPI_TRANS_VTOTAL(port)); | |
793 | ||
794 | /* | |
795 | * TODO: Retrieve hfp, hsync and hbp. Adjust them for dual link and | |
796 | * calculate hsync_start, hsync_end, htotal and hblank_end | |
797 | */ | |
798 | ||
799 | /* vertical values are in terms of lines */ | |
800 | vfp = I915_READ(MIPI_VFP_COUNT(port)); | |
801 | vsync = I915_READ(MIPI_VSYNC_PADDING_COUNT(port)); | |
802 | vbp = I915_READ(MIPI_VBP_COUNT(port)); | |
803 | ||
804 | adjusted_mode->crtc_hblank_start = adjusted_mode->crtc_hdisplay; | |
805 | ||
806 | adjusted_mode->crtc_vsync_start = | |
807 | vfp + adjusted_mode->crtc_vdisplay; | |
808 | adjusted_mode->crtc_vsync_end = | |
809 | vsync + adjusted_mode->crtc_vsync_start; | |
810 | adjusted_mode->crtc_vblank_start = adjusted_mode->crtc_vdisplay; | |
811 | adjusted_mode->crtc_vblank_end = adjusted_mode->crtc_vtotal; | |
812 | } | |
813 | ||
814 | ||
4e646495 | 815 | static void intel_dsi_get_config(struct intel_encoder *encoder, |
5cec258b | 816 | struct intel_crtc_state *pipe_config) |
4e646495 | 817 | { |
6f0e7535 | 818 | struct drm_device *dev = encoder->base.dev; |
d7d85d85 | 819 | u32 pclk; |
4e646495 JN |
820 | DRM_DEBUG_KMS("\n"); |
821 | ||
a65347ba JN |
822 | pipe_config->has_dsi_encoder = true; |
823 | ||
6f0e7535 R |
824 | if (IS_BROXTON(dev)) |
825 | bxt_dsi_get_pipe_config(encoder, pipe_config); | |
826 | ||
d7d85d85 | 827 | pclk = intel_dsi_get_pclk(encoder, pipe_config->pipe_bpp); |
f573de5a SK |
828 | if (!pclk) |
829 | return; | |
830 | ||
2d112de7 | 831 | pipe_config->base.adjusted_mode.crtc_clock = pclk; |
f573de5a | 832 | pipe_config->port_clock = pclk; |
4e646495 JN |
833 | } |
834 | ||
c19de8eb DL |
835 | static enum drm_mode_status |
836 | intel_dsi_mode_valid(struct drm_connector *connector, | |
837 | struct drm_display_mode *mode) | |
4e646495 JN |
838 | { |
839 | struct intel_connector *intel_connector = to_intel_connector(connector); | |
840 | struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode; | |
759a1e98 | 841 | int max_dotclk = to_i915(connector->dev)->max_dotclk_freq; |
4e646495 JN |
842 | |
843 | DRM_DEBUG_KMS("\n"); | |
844 | ||
845 | if (mode->flags & DRM_MODE_FLAG_DBLSCAN) { | |
846 | DRM_DEBUG_KMS("MODE_NO_DBLESCAN\n"); | |
847 | return MODE_NO_DBLESCAN; | |
848 | } | |
849 | ||
850 | if (fixed_mode) { | |
851 | if (mode->hdisplay > fixed_mode->hdisplay) | |
852 | return MODE_PANEL; | |
853 | if (mode->vdisplay > fixed_mode->vdisplay) | |
854 | return MODE_PANEL; | |
759a1e98 MK |
855 | if (fixed_mode->clock > max_dotclk) |
856 | return MODE_CLOCK_HIGH; | |
4e646495 JN |
857 | } |
858 | ||
36d21f4c | 859 | return MODE_OK; |
4e646495 JN |
860 | } |
861 | ||
862 | /* return txclkesc cycles in terms of divider and duration in us */ | |
863 | static u16 txclkesc(u32 divider, unsigned int us) | |
864 | { | |
865 | switch (divider) { | |
866 | case ESCAPE_CLOCK_DIVIDER_1: | |
867 | default: | |
868 | return 20 * us; | |
869 | case ESCAPE_CLOCK_DIVIDER_2: | |
870 | return 10 * us; | |
871 | case ESCAPE_CLOCK_DIVIDER_4: | |
872 | return 5 * us; | |
873 | } | |
874 | } | |
875 | ||
876 | /* return pixels in terms of txbyteclkhs */ | |
7f0c8605 SK |
877 | static u16 txbyteclkhs(u16 pixels, int bpp, int lane_count, |
878 | u16 burst_mode_ratio) | |
4e646495 | 879 | { |
7f0c8605 | 880 | return DIV_ROUND_UP(DIV_ROUND_UP(pixels * bpp * burst_mode_ratio, |
7f3de833 | 881 | 8 * 100), lane_count); |
4e646495 JN |
882 | } |
883 | ||
884 | static void set_dsi_timings(struct drm_encoder *encoder, | |
5e7234c9 | 885 | const struct drm_display_mode *adjusted_mode) |
4e646495 JN |
886 | { |
887 | struct drm_device *dev = encoder->dev; | |
888 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4e646495 | 889 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); |
aa102d28 | 890 | enum port port; |
1e78aa01 | 891 | unsigned int bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format); |
4e646495 JN |
892 | unsigned int lane_count = intel_dsi->lane_count; |
893 | ||
894 | u16 hactive, hfp, hsync, hbp, vfp, vsync, vbp; | |
895 | ||
aad941d5 VS |
896 | hactive = adjusted_mode->crtc_hdisplay; |
897 | hfp = adjusted_mode->crtc_hsync_start - adjusted_mode->crtc_hdisplay; | |
898 | hsync = adjusted_mode->crtc_hsync_end - adjusted_mode->crtc_hsync_start; | |
899 | hbp = adjusted_mode->crtc_htotal - adjusted_mode->crtc_hsync_end; | |
4e646495 | 900 | |
aa102d28 GS |
901 | if (intel_dsi->dual_link) { |
902 | hactive /= 2; | |
903 | if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) | |
904 | hactive += intel_dsi->pixel_overlap; | |
905 | hfp /= 2; | |
906 | hsync /= 2; | |
907 | hbp /= 2; | |
908 | } | |
909 | ||
aad941d5 VS |
910 | vfp = adjusted_mode->crtc_vsync_start - adjusted_mode->crtc_vdisplay; |
911 | vsync = adjusted_mode->crtc_vsync_end - adjusted_mode->crtc_vsync_start; | |
912 | vbp = adjusted_mode->crtc_vtotal - adjusted_mode->crtc_vsync_end; | |
4e646495 JN |
913 | |
914 | /* horizontal values are in terms of high speed byte clock */ | |
7f0c8605 | 915 | hactive = txbyteclkhs(hactive, bpp, lane_count, |
7f3de833 | 916 | intel_dsi->burst_mode_ratio); |
7f0c8605 SK |
917 | hfp = txbyteclkhs(hfp, bpp, lane_count, intel_dsi->burst_mode_ratio); |
918 | hsync = txbyteclkhs(hsync, bpp, lane_count, | |
7f3de833 | 919 | intel_dsi->burst_mode_ratio); |
7f0c8605 | 920 | hbp = txbyteclkhs(hbp, bpp, lane_count, intel_dsi->burst_mode_ratio); |
4e646495 | 921 | |
aa102d28 | 922 | for_each_dsi_port(port, intel_dsi->ports) { |
d2e08c0f SS |
923 | if (IS_BROXTON(dev)) { |
924 | /* | |
925 | * Program hdisplay and vdisplay on MIPI transcoder. | |
926 | * This is different from calculated hactive and | |
927 | * vactive, as they are calculated per channel basis, | |
928 | * whereas these values should be based on resolution. | |
929 | */ | |
930 | I915_WRITE(BXT_MIPI_TRANS_HACTIVE(port), | |
aad941d5 | 931 | adjusted_mode->crtc_hdisplay); |
d2e08c0f | 932 | I915_WRITE(BXT_MIPI_TRANS_VACTIVE(port), |
aad941d5 | 933 | adjusted_mode->crtc_vdisplay); |
d2e08c0f | 934 | I915_WRITE(BXT_MIPI_TRANS_VTOTAL(port), |
aad941d5 | 935 | adjusted_mode->crtc_vtotal); |
d2e08c0f SS |
936 | } |
937 | ||
aa102d28 GS |
938 | I915_WRITE(MIPI_HACTIVE_AREA_COUNT(port), hactive); |
939 | I915_WRITE(MIPI_HFP_COUNT(port), hfp); | |
940 | ||
941 | /* meaningful for video mode non-burst sync pulse mode only, | |
942 | * can be zero for non-burst sync events and burst modes */ | |
943 | I915_WRITE(MIPI_HSYNC_PADDING_COUNT(port), hsync); | |
944 | I915_WRITE(MIPI_HBP_COUNT(port), hbp); | |
945 | ||
946 | /* vertical values are in terms of lines */ | |
947 | I915_WRITE(MIPI_VFP_COUNT(port), vfp); | |
948 | I915_WRITE(MIPI_VSYNC_PADDING_COUNT(port), vsync); | |
949 | I915_WRITE(MIPI_VBP_COUNT(port), vbp); | |
950 | } | |
4e646495 JN |
951 | } |
952 | ||
1e78aa01 JN |
953 | static u32 pixel_format_to_reg(enum mipi_dsi_pixel_format fmt) |
954 | { | |
955 | switch (fmt) { | |
956 | case MIPI_DSI_FMT_RGB888: | |
957 | return VID_MODE_FORMAT_RGB888; | |
958 | case MIPI_DSI_FMT_RGB666: | |
959 | return VID_MODE_FORMAT_RGB666; | |
960 | case MIPI_DSI_FMT_RGB666_PACKED: | |
961 | return VID_MODE_FORMAT_RGB666_PACKED; | |
962 | case MIPI_DSI_FMT_RGB565: | |
963 | return VID_MODE_FORMAT_RGB565; | |
964 | default: | |
965 | MISSING_CASE(fmt); | |
966 | return VID_MODE_FORMAT_RGB666; | |
967 | } | |
968 | } | |
969 | ||
07e4fb9e | 970 | static void intel_dsi_prepare(struct intel_encoder *intel_encoder) |
4e646495 JN |
971 | { |
972 | struct drm_encoder *encoder = &intel_encoder->base; | |
973 | struct drm_device *dev = encoder->dev; | |
974 | struct drm_i915_private *dev_priv = dev->dev_private; | |
975 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); | |
976 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); | |
7c5f93b0 | 977 | const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode; |
24ee0e64 | 978 | enum port port; |
1e78aa01 | 979 | unsigned int bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format); |
4e646495 | 980 | u32 val, tmp; |
24ee0e64 | 981 | u16 mode_hdisplay; |
4e646495 | 982 | |
e7d7cad0 | 983 | DRM_DEBUG_KMS("pipe %c\n", pipe_name(intel_crtc->pipe)); |
4e646495 | 984 | |
aad941d5 | 985 | mode_hdisplay = adjusted_mode->crtc_hdisplay; |
4e646495 | 986 | |
24ee0e64 GS |
987 | if (intel_dsi->dual_link) { |
988 | mode_hdisplay /= 2; | |
989 | if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) | |
990 | mode_hdisplay += intel_dsi->pixel_overlap; | |
991 | } | |
4e646495 | 992 | |
24ee0e64 | 993 | for_each_dsi_port(port, intel_dsi->ports) { |
666a4537 | 994 | if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
d2e08c0f SS |
995 | /* |
996 | * escape clock divider, 20MHz, shared for A and C. | |
997 | * device ready must be off when doing this! txclkesc? | |
998 | */ | |
999 | tmp = I915_READ(MIPI_CTRL(PORT_A)); | |
1000 | tmp &= ~ESCAPE_CLOCK_DIVIDER_MASK; | |
1001 | I915_WRITE(MIPI_CTRL(PORT_A), tmp | | |
1002 | ESCAPE_CLOCK_DIVIDER_1); | |
1003 | ||
1004 | /* read request priority is per pipe */ | |
1005 | tmp = I915_READ(MIPI_CTRL(port)); | |
1006 | tmp &= ~READ_REQUEST_PRIORITY_MASK; | |
1007 | I915_WRITE(MIPI_CTRL(port), tmp | | |
1008 | READ_REQUEST_PRIORITY_HIGH); | |
1009 | } else if (IS_BROXTON(dev)) { | |
56c48978 D |
1010 | enum pipe pipe = intel_crtc->pipe; |
1011 | ||
d2e08c0f SS |
1012 | tmp = I915_READ(MIPI_CTRL(port)); |
1013 | tmp &= ~BXT_PIPE_SELECT_MASK; | |
1014 | ||
56c48978 | 1015 | tmp |= BXT_PIPE_SELECT(pipe); |
d2e08c0f SS |
1016 | I915_WRITE(MIPI_CTRL(port), tmp); |
1017 | } | |
24ee0e64 GS |
1018 | |
1019 | /* XXX: why here, why like this? handling in irq handler?! */ | |
1020 | I915_WRITE(MIPI_INTR_STAT(port), 0xffffffff); | |
1021 | I915_WRITE(MIPI_INTR_EN(port), 0xffffffff); | |
1022 | ||
1023 | I915_WRITE(MIPI_DPHY_PARAM(port), intel_dsi->dphy_reg); | |
1024 | ||
1025 | I915_WRITE(MIPI_DPI_RESOLUTION(port), | |
aad941d5 | 1026 | adjusted_mode->crtc_vdisplay << VERTICAL_ADDRESS_SHIFT | |
24ee0e64 GS |
1027 | mode_hdisplay << HORIZONTAL_ADDRESS_SHIFT); |
1028 | } | |
4e646495 JN |
1029 | |
1030 | set_dsi_timings(encoder, adjusted_mode); | |
1031 | ||
1032 | val = intel_dsi->lane_count << DATA_LANES_PRG_REG_SHIFT; | |
1033 | if (is_cmd_mode(intel_dsi)) { | |
1034 | val |= intel_dsi->channel << CMD_MODE_CHANNEL_NUMBER_SHIFT; | |
1035 | val |= CMD_MODE_DATA_WIDTH_8_BIT; /* XXX */ | |
1036 | } else { | |
1037 | val |= intel_dsi->channel << VID_MODE_CHANNEL_NUMBER_SHIFT; | |
1e78aa01 | 1038 | val |= pixel_format_to_reg(intel_dsi->pixel_format); |
4e646495 | 1039 | } |
4e646495 | 1040 | |
24ee0e64 GS |
1041 | tmp = 0; |
1042 | if (intel_dsi->eotp_pkt == 0) | |
1043 | tmp |= EOT_DISABLE; | |
1044 | if (intel_dsi->clock_stop) | |
1045 | tmp |= CLOCKSTOP; | |
4e646495 | 1046 | |
24ee0e64 GS |
1047 | for_each_dsi_port(port, intel_dsi->ports) { |
1048 | I915_WRITE(MIPI_DSI_FUNC_PRG(port), val); | |
1049 | ||
1050 | /* timeouts for recovery. one frame IIUC. if counter expires, | |
1051 | * EOT and stop state. */ | |
1052 | ||
1053 | /* | |
1054 | * In burst mode, value greater than one DPI line Time in byte | |
1055 | * clock (txbyteclkhs) To timeout this timer 1+ of the above | |
1056 | * said value is recommended. | |
1057 | * | |
1058 | * In non-burst mode, Value greater than one DPI frame time in | |
1059 | * byte clock(txbyteclkhs) To timeout this timer 1+ of the above | |
1060 | * said value is recommended. | |
1061 | * | |
1062 | * In DBI only mode, value greater than one DBI frame time in | |
1063 | * byte clock(txbyteclkhs) To timeout this timer 1+ of the above | |
1064 | * said value is recommended. | |
1065 | */ | |
4e646495 | 1066 | |
24ee0e64 GS |
1067 | if (is_vid_mode(intel_dsi) && |
1068 | intel_dsi->video_mode_format == VIDEO_MODE_BURST) { | |
1069 | I915_WRITE(MIPI_HS_TX_TIMEOUT(port), | |
aad941d5 | 1070 | txbyteclkhs(adjusted_mode->crtc_htotal, bpp, |
124abe07 VS |
1071 | intel_dsi->lane_count, |
1072 | intel_dsi->burst_mode_ratio) + 1); | |
24ee0e64 GS |
1073 | } else { |
1074 | I915_WRITE(MIPI_HS_TX_TIMEOUT(port), | |
aad941d5 VS |
1075 | txbyteclkhs(adjusted_mode->crtc_vtotal * |
1076 | adjusted_mode->crtc_htotal, | |
124abe07 VS |
1077 | bpp, intel_dsi->lane_count, |
1078 | intel_dsi->burst_mode_ratio) + 1); | |
24ee0e64 GS |
1079 | } |
1080 | I915_WRITE(MIPI_LP_RX_TIMEOUT(port), intel_dsi->lp_rx_timeout); | |
1081 | I915_WRITE(MIPI_TURN_AROUND_TIMEOUT(port), | |
1082 | intel_dsi->turn_arnd_val); | |
1083 | I915_WRITE(MIPI_DEVICE_RESET_TIMER(port), | |
1084 | intel_dsi->rst_timer_val); | |
f1c79f16 | 1085 | |
24ee0e64 | 1086 | /* dphy stuff */ |
f1c79f16 | 1087 | |
24ee0e64 GS |
1088 | /* in terms of low power clock */ |
1089 | I915_WRITE(MIPI_INIT_COUNT(port), | |
1090 | txclkesc(intel_dsi->escape_clk_div, 100)); | |
4e646495 | 1091 | |
d2e08c0f SS |
1092 | if (IS_BROXTON(dev) && (!intel_dsi->dual_link)) { |
1093 | /* | |
1094 | * BXT spec says write MIPI_INIT_COUNT for | |
1095 | * both the ports, even if only one is | |
1096 | * getting used. So write the other port | |
1097 | * if not in dual link mode. | |
1098 | */ | |
1099 | I915_WRITE(MIPI_INIT_COUNT(port == | |
1100 | PORT_A ? PORT_C : PORT_A), | |
1101 | intel_dsi->init_count); | |
1102 | } | |
4e646495 | 1103 | |
24ee0e64 | 1104 | /* recovery disables */ |
87c54d0e | 1105 | I915_WRITE(MIPI_EOT_DISABLE(port), tmp); |
cf4dbd2e | 1106 | |
24ee0e64 GS |
1107 | /* in terms of low power clock */ |
1108 | I915_WRITE(MIPI_INIT_COUNT(port), intel_dsi->init_count); | |
4e646495 | 1109 | |
24ee0e64 GS |
1110 | /* in terms of txbyteclkhs. actual high to low switch + |
1111 | * MIPI_STOP_STATE_STALL * MIPI_LP_BYTECLK. | |
1112 | * | |
1113 | * XXX: write MIPI_STOP_STATE_STALL? | |
1114 | */ | |
1115 | I915_WRITE(MIPI_HIGH_LOW_SWITCH_COUNT(port), | |
1116 | intel_dsi->hs_to_lp_count); | |
1117 | ||
1118 | /* XXX: low power clock equivalence in terms of byte clock. | |
1119 | * the number of byte clocks occupied in one low power clock. | |
1120 | * based on txbyteclkhs and txclkesc. | |
1121 | * txclkesc time / txbyteclk time * (105 + MIPI_STOP_STATE_STALL | |
1122 | * ) / 105.??? | |
1123 | */ | |
1124 | I915_WRITE(MIPI_LP_BYTECLK(port), intel_dsi->lp_byte_clk); | |
1125 | ||
1126 | /* the bw essential for transmitting 16 long packets containing | |
1127 | * 252 bytes meant for dcs write memory command is programmed in | |
1128 | * this register in terms of byte clocks. based on dsi transfer | |
1129 | * rate and the number of lanes configured the time taken to | |
1130 | * transmit 16 long packets in a dsi stream varies. */ | |
1131 | I915_WRITE(MIPI_DBI_BW_CTRL(port), intel_dsi->bw_timer); | |
1132 | ||
1133 | I915_WRITE(MIPI_CLK_LANE_SWITCH_TIME_CNT(port), | |
1134 | intel_dsi->clk_lp_to_hs_count << LP_HS_SSW_CNT_SHIFT | | |
1135 | intel_dsi->clk_hs_to_lp_count << HS_LP_PWR_SW_CNT_SHIFT); | |
1136 | ||
1137 | if (is_vid_mode(intel_dsi)) | |
1138 | /* Some panels might have resolution which is not a | |
1139 | * multiple of 64 like 1366 x 768. Enable RANDOM | |
1140 | * resolution support for such panels by default */ | |
1141 | I915_WRITE(MIPI_VIDEO_MODE_FORMAT(port), | |
1142 | intel_dsi->video_frmt_cfg_bits | | |
1143 | intel_dsi->video_mode_format | | |
1144 | IP_TG_CONFIG | | |
1145 | RANDOM_DPI_DISPLAY_RESOLUTION); | |
1146 | } | |
4e646495 JN |
1147 | } |
1148 | ||
1149 | static enum drm_connector_status | |
1150 | intel_dsi_detect(struct drm_connector *connector, bool force) | |
1151 | { | |
36d21f4c | 1152 | return connector_status_connected; |
4e646495 JN |
1153 | } |
1154 | ||
1155 | static int intel_dsi_get_modes(struct drm_connector *connector) | |
1156 | { | |
1157 | struct intel_connector *intel_connector = to_intel_connector(connector); | |
1158 | struct drm_display_mode *mode; | |
1159 | ||
1160 | DRM_DEBUG_KMS("\n"); | |
1161 | ||
1162 | if (!intel_connector->panel.fixed_mode) { | |
1163 | DRM_DEBUG_KMS("no fixed mode\n"); | |
1164 | return 0; | |
1165 | } | |
1166 | ||
1167 | mode = drm_mode_duplicate(connector->dev, | |
1168 | intel_connector->panel.fixed_mode); | |
1169 | if (!mode) { | |
1170 | DRM_DEBUG_KMS("drm_mode_duplicate failed\n"); | |
1171 | return 0; | |
1172 | } | |
1173 | ||
1174 | drm_mode_probed_add(connector, mode); | |
1175 | return 1; | |
1176 | } | |
1177 | ||
593e0622 | 1178 | static void intel_dsi_connector_destroy(struct drm_connector *connector) |
4e646495 JN |
1179 | { |
1180 | struct intel_connector *intel_connector = to_intel_connector(connector); | |
1181 | ||
1182 | DRM_DEBUG_KMS("\n"); | |
1183 | intel_panel_fini(&intel_connector->panel); | |
4e646495 JN |
1184 | drm_connector_cleanup(connector); |
1185 | kfree(connector); | |
1186 | } | |
1187 | ||
593e0622 JN |
1188 | static void intel_dsi_encoder_destroy(struct drm_encoder *encoder) |
1189 | { | |
1190 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); | |
1191 | ||
1192 | if (intel_dsi->panel) { | |
1193 | drm_panel_detach(intel_dsi->panel); | |
1194 | /* XXX: Logically this call belongs in the panel driver. */ | |
1195 | drm_panel_remove(intel_dsi->panel); | |
1196 | } | |
fc45e821 SK |
1197 | |
1198 | /* dispose of the gpios */ | |
1199 | if (intel_dsi->gpio_panel) | |
1200 | gpiod_put(intel_dsi->gpio_panel); | |
1201 | ||
593e0622 JN |
1202 | intel_encoder_destroy(encoder); |
1203 | } | |
1204 | ||
4e646495 | 1205 | static const struct drm_encoder_funcs intel_dsi_funcs = { |
593e0622 | 1206 | .destroy = intel_dsi_encoder_destroy, |
4e646495 JN |
1207 | }; |
1208 | ||
1209 | static const struct drm_connector_helper_funcs intel_dsi_connector_helper_funcs = { | |
1210 | .get_modes = intel_dsi_get_modes, | |
1211 | .mode_valid = intel_dsi_mode_valid, | |
1212 | .best_encoder = intel_best_encoder, | |
1213 | }; | |
1214 | ||
1215 | static const struct drm_connector_funcs intel_dsi_connector_funcs = { | |
4d688a2a | 1216 | .dpms = drm_atomic_helper_connector_dpms, |
4e646495 | 1217 | .detect = intel_dsi_detect, |
593e0622 | 1218 | .destroy = intel_dsi_connector_destroy, |
4e646495 | 1219 | .fill_modes = drm_helper_probe_single_connector_modes, |
2545e4a6 | 1220 | .atomic_get_property = intel_connector_atomic_get_property, |
c6f95f27 | 1221 | .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, |
98969725 | 1222 | .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, |
4e646495 JN |
1223 | }; |
1224 | ||
4328633d | 1225 | void intel_dsi_init(struct drm_device *dev) |
4e646495 JN |
1226 | { |
1227 | struct intel_dsi *intel_dsi; | |
1228 | struct intel_encoder *intel_encoder; | |
1229 | struct drm_encoder *encoder; | |
1230 | struct intel_connector *intel_connector; | |
1231 | struct drm_connector *connector; | |
593e0622 | 1232 | struct drm_display_mode *scan, *fixed_mode = NULL; |
b6fdd0f2 | 1233 | struct drm_i915_private *dev_priv = dev->dev_private; |
7e9804fd | 1234 | enum port port; |
4e646495 JN |
1235 | unsigned int i; |
1236 | ||
1237 | DRM_DEBUG_KMS("\n"); | |
1238 | ||
3e6bd011 | 1239 | /* There is no detection method for MIPI so rely on VBT */ |
7137aec1 | 1240 | if (!intel_bios_is_dsi_present(dev_priv, &port)) |
4328633d | 1241 | return; |
3e6bd011 | 1242 | |
666a4537 | 1243 | if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
868d665b | 1244 | dev_priv->mipi_mmio_base = VLV_MIPI_BASE; |
c6c794a2 SS |
1245 | } else if (IS_BROXTON(dev)) { |
1246 | dev_priv->mipi_mmio_base = BXT_MIPI_BASE; | |
868d665b CJ |
1247 | } else { |
1248 | DRM_ERROR("Unsupported Mipi device to reg base"); | |
1249 | return; | |
1250 | } | |
3e6bd011 | 1251 | |
4e646495 JN |
1252 | intel_dsi = kzalloc(sizeof(*intel_dsi), GFP_KERNEL); |
1253 | if (!intel_dsi) | |
4328633d | 1254 | return; |
4e646495 | 1255 | |
08d9bc92 | 1256 | intel_connector = intel_connector_alloc(); |
4e646495 JN |
1257 | if (!intel_connector) { |
1258 | kfree(intel_dsi); | |
4328633d | 1259 | return; |
4e646495 JN |
1260 | } |
1261 | ||
1262 | intel_encoder = &intel_dsi->base; | |
1263 | encoder = &intel_encoder->base; | |
1264 | intel_dsi->attached_connector = intel_connector; | |
1265 | ||
1266 | connector = &intel_connector->base; | |
1267 | ||
13a3d91f VS |
1268 | drm_encoder_init(dev, encoder, &intel_dsi_funcs, DRM_MODE_ENCODER_DSI, |
1269 | NULL); | |
4e646495 | 1270 | |
4e646495 | 1271 | intel_encoder->compute_config = intel_dsi_compute_config; |
4e646495 | 1272 | intel_encoder->pre_enable = intel_dsi_pre_enable; |
2634fd7f | 1273 | intel_encoder->enable = intel_dsi_enable_nop; |
c315faf8 | 1274 | intel_encoder->disable = intel_dsi_pre_disable; |
4e646495 JN |
1275 | intel_encoder->post_disable = intel_dsi_post_disable; |
1276 | intel_encoder->get_hw_state = intel_dsi_get_hw_state; | |
1277 | intel_encoder->get_config = intel_dsi_get_config; | |
1278 | ||
1279 | intel_connector->get_hw_state = intel_connector_get_hw_state; | |
4932e2c3 | 1280 | intel_connector->unregister = intel_connector_unregister; |
4e646495 | 1281 | |
2e85ab4f JN |
1282 | /* |
1283 | * On BYT/CHV, pipe A maps to MIPI DSI port A, pipe B maps to MIPI DSI | |
1284 | * port C. BXT isn't limited like this. | |
1285 | */ | |
1286 | if (IS_BROXTON(dev_priv)) | |
1287 | intel_encoder->crtc_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C); | |
1288 | else if (port == PORT_A) | |
701d25b4 | 1289 | intel_encoder->crtc_mask = BIT(PIPE_A); |
7137aec1 | 1290 | else |
701d25b4 | 1291 | intel_encoder->crtc_mask = BIT(PIPE_B); |
e7d7cad0 | 1292 | |
82425785 | 1293 | if (dev_priv->vbt.dsi.config->dual_link) |
701d25b4 | 1294 | intel_dsi->ports = BIT(PORT_A) | BIT(PORT_C); |
7137aec1 | 1295 | else |
701d25b4 | 1296 | intel_dsi->ports = BIT(port); |
82425785 | 1297 | |
7e9804fd JN |
1298 | /* Create a DSI host (and a device) for each port. */ |
1299 | for_each_dsi_port(port, intel_dsi->ports) { | |
1300 | struct intel_dsi_host *host; | |
1301 | ||
1302 | host = intel_dsi_host_init(intel_dsi, port); | |
1303 | if (!host) | |
1304 | goto err; | |
1305 | ||
1306 | intel_dsi->dsi_hosts[port] = host; | |
1307 | } | |
1308 | ||
593e0622 JN |
1309 | for (i = 0; i < ARRAY_SIZE(intel_dsi_drivers); i++) { |
1310 | intel_dsi->panel = intel_dsi_drivers[i].init(intel_dsi, | |
1311 | intel_dsi_drivers[i].panel_id); | |
1312 | if (intel_dsi->panel) | |
4e646495 JN |
1313 | break; |
1314 | } | |
1315 | ||
593e0622 | 1316 | if (!intel_dsi->panel) { |
4e646495 JN |
1317 | DRM_DEBUG_KMS("no device found\n"); |
1318 | goto err; | |
1319 | } | |
1320 | ||
fc45e821 SK |
1321 | /* |
1322 | * In case of BYT with CRC PMIC, we need to use GPIO for | |
1323 | * Panel control. | |
1324 | */ | |
1325 | if (dev_priv->vbt.dsi.config->pwm_blc == PPS_BLC_PMIC) { | |
1326 | intel_dsi->gpio_panel = | |
1327 | gpiod_get(dev->dev, "panel", GPIOD_OUT_HIGH); | |
1328 | ||
1329 | if (IS_ERR(intel_dsi->gpio_panel)) { | |
1330 | DRM_ERROR("Failed to own gpio for panel control\n"); | |
1331 | intel_dsi->gpio_panel = NULL; | |
1332 | } | |
1333 | } | |
1334 | ||
4e646495 | 1335 | intel_encoder->type = INTEL_OUTPUT_DSI; |
bc079e8b | 1336 | intel_encoder->cloneable = 0; |
4e646495 JN |
1337 | drm_connector_init(dev, connector, &intel_dsi_connector_funcs, |
1338 | DRM_MODE_CONNECTOR_DSI); | |
1339 | ||
1340 | drm_connector_helper_add(connector, &intel_dsi_connector_helper_funcs); | |
1341 | ||
1342 | connector->display_info.subpixel_order = SubPixelHorizontalRGB; /*XXX*/ | |
1343 | connector->interlace_allowed = false; | |
1344 | connector->doublescan_allowed = false; | |
1345 | ||
1346 | intel_connector_attach_encoder(intel_connector, intel_encoder); | |
1347 | ||
34ea3d38 | 1348 | drm_connector_register(connector); |
4e646495 | 1349 | |
593e0622 JN |
1350 | drm_panel_attach(intel_dsi->panel, connector); |
1351 | ||
1352 | mutex_lock(&dev->mode_config.mutex); | |
1353 | drm_panel_get_modes(intel_dsi->panel); | |
1354 | list_for_each_entry(scan, &connector->probed_modes, head) { | |
1355 | if ((scan->type & DRM_MODE_TYPE_PREFERRED)) { | |
1356 | fixed_mode = drm_mode_duplicate(dev, scan); | |
1357 | break; | |
1358 | } | |
1359 | } | |
1360 | mutex_unlock(&dev->mode_config.mutex); | |
1361 | ||
4e646495 JN |
1362 | if (!fixed_mode) { |
1363 | DRM_DEBUG_KMS("no fixed mode\n"); | |
1364 | goto err; | |
1365 | } | |
1366 | ||
4b6ed685 | 1367 | intel_panel_init(&intel_connector->panel, fixed_mode, NULL); |
b029e66f | 1368 | intel_panel_setup_backlight(connector, INVALID_PIPE); |
4e646495 | 1369 | |
4328633d | 1370 | return; |
4e646495 JN |
1371 | |
1372 | err: | |
1373 | drm_encoder_cleanup(&intel_encoder->base); | |
1374 | kfree(intel_dsi); | |
1375 | kfree(intel_connector); | |
4e646495 | 1376 | } |