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4e646495 JN |
1 | /* |
2 | * Copyright © 2013 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
21 | * DEALINGS IN THE SOFTWARE. | |
22 | * | |
23 | * Author: Jani Nikula <jani.nikula@intel.com> | |
24 | */ | |
25 | ||
26 | #include <drm/drmP.h> | |
c6f95f27 | 27 | #include <drm/drm_atomic_helper.h> |
4e646495 JN |
28 | #include <drm/drm_crtc.h> |
29 | #include <drm/drm_edid.h> | |
30 | #include <drm/i915_drm.h> | |
7e9804fd | 31 | #include <drm/drm_mipi_dsi.h> |
4e646495 | 32 | #include <linux/slab.h> |
fc45e821 | 33 | #include <linux/gpio/consumer.h> |
4e646495 JN |
34 | #include "i915_drv.h" |
35 | #include "intel_drv.h" | |
36 | #include "intel_dsi.h" | |
4e646495 | 37 | |
042ab0c3 R |
38 | /* return pixels in terms of txbyteclkhs */ |
39 | static u16 txbyteclkhs(u16 pixels, int bpp, int lane_count, | |
40 | u16 burst_mode_ratio) | |
41 | { | |
42 | return DIV_ROUND_UP(DIV_ROUND_UP(pixels * bpp * burst_mode_ratio, | |
43 | 8 * 100), lane_count); | |
44 | } | |
45 | ||
cefc4e18 R |
46 | /* return pixels equvalent to txbyteclkhs */ |
47 | static u16 pixels_from_txbyteclkhs(u16 clk_hs, int bpp, int lane_count, | |
48 | u16 burst_mode_ratio) | |
49 | { | |
50 | return DIV_ROUND_UP((clk_hs * lane_count * 8 * 100), | |
51 | (bpp * burst_mode_ratio)); | |
52 | } | |
53 | ||
43367ec9 R |
54 | enum mipi_dsi_pixel_format pixel_format_from_register_bits(u32 fmt) |
55 | { | |
56 | /* It just so happens the VBT matches register contents. */ | |
57 | switch (fmt) { | |
58 | case VID_MODE_FORMAT_RGB888: | |
59 | return MIPI_DSI_FMT_RGB888; | |
60 | case VID_MODE_FORMAT_RGB666: | |
61 | return MIPI_DSI_FMT_RGB666; | |
62 | case VID_MODE_FORMAT_RGB666_PACKED: | |
63 | return MIPI_DSI_FMT_RGB666_PACKED; | |
64 | case VID_MODE_FORMAT_RGB565: | |
65 | return MIPI_DSI_FMT_RGB565; | |
66 | default: | |
67 | MISSING_CASE(fmt); | |
68 | return MIPI_DSI_FMT_RGB666; | |
69 | } | |
70 | } | |
71 | ||
3870b89a | 72 | void wait_for_dsi_fifo_empty(struct intel_dsi *intel_dsi, enum port port) |
3b1808bf JN |
73 | { |
74 | struct drm_encoder *encoder = &intel_dsi->base.base; | |
75 | struct drm_device *dev = encoder->dev; | |
fac5e23e | 76 | struct drm_i915_private *dev_priv = to_i915(dev); |
3b1808bf JN |
77 | u32 mask; |
78 | ||
79 | mask = LP_CTRL_FIFO_EMPTY | HS_CTRL_FIFO_EMPTY | | |
80 | LP_DATA_FIFO_EMPTY | HS_DATA_FIFO_EMPTY; | |
81 | ||
9b6a2d72 CW |
82 | if (intel_wait_for_register(dev_priv, |
83 | MIPI_GEN_FIFO_STAT(port), mask, mask, | |
84 | 100)) | |
3b1808bf JN |
85 | DRM_ERROR("DPI FIFOs are not empty\n"); |
86 | } | |
87 | ||
f0f59a00 VS |
88 | static void write_data(struct drm_i915_private *dev_priv, |
89 | i915_reg_t reg, | |
7e9804fd JN |
90 | const u8 *data, u32 len) |
91 | { | |
92 | u32 i, j; | |
93 | ||
94 | for (i = 0; i < len; i += 4) { | |
95 | u32 val = 0; | |
96 | ||
97 | for (j = 0; j < min_t(u32, len - i, 4); j++) | |
98 | val |= *data++ << 8 * j; | |
99 | ||
100 | I915_WRITE(reg, val); | |
101 | } | |
102 | } | |
103 | ||
f0f59a00 VS |
104 | static void read_data(struct drm_i915_private *dev_priv, |
105 | i915_reg_t reg, | |
7e9804fd JN |
106 | u8 *data, u32 len) |
107 | { | |
108 | u32 i, j; | |
109 | ||
110 | for (i = 0; i < len; i += 4) { | |
111 | u32 val = I915_READ(reg); | |
112 | ||
113 | for (j = 0; j < min_t(u32, len - i, 4); j++) | |
114 | *data++ = val >> 8 * j; | |
115 | } | |
116 | } | |
117 | ||
118 | static ssize_t intel_dsi_host_transfer(struct mipi_dsi_host *host, | |
119 | const struct mipi_dsi_msg *msg) | |
120 | { | |
121 | struct intel_dsi_host *intel_dsi_host = to_intel_dsi_host(host); | |
122 | struct drm_device *dev = intel_dsi_host->intel_dsi->base.base.dev; | |
fac5e23e | 123 | struct drm_i915_private *dev_priv = to_i915(dev); |
7e9804fd JN |
124 | enum port port = intel_dsi_host->port; |
125 | struct mipi_dsi_packet packet; | |
126 | ssize_t ret; | |
127 | const u8 *header, *data; | |
f0f59a00 VS |
128 | i915_reg_t data_reg, ctrl_reg; |
129 | u32 data_mask, ctrl_mask; | |
7e9804fd JN |
130 | |
131 | ret = mipi_dsi_create_packet(&packet, msg); | |
132 | if (ret < 0) | |
133 | return ret; | |
134 | ||
135 | header = packet.header; | |
136 | data = packet.payload; | |
137 | ||
138 | if (msg->flags & MIPI_DSI_MSG_USE_LPM) { | |
139 | data_reg = MIPI_LP_GEN_DATA(port); | |
140 | data_mask = LP_DATA_FIFO_FULL; | |
141 | ctrl_reg = MIPI_LP_GEN_CTRL(port); | |
142 | ctrl_mask = LP_CTRL_FIFO_FULL; | |
143 | } else { | |
144 | data_reg = MIPI_HS_GEN_DATA(port); | |
145 | data_mask = HS_DATA_FIFO_FULL; | |
146 | ctrl_reg = MIPI_HS_GEN_CTRL(port); | |
147 | ctrl_mask = HS_CTRL_FIFO_FULL; | |
148 | } | |
149 | ||
150 | /* note: this is never true for reads */ | |
151 | if (packet.payload_length) { | |
8c6cea0b CW |
152 | if (intel_wait_for_register(dev_priv, |
153 | MIPI_GEN_FIFO_STAT(port), | |
154 | data_mask, 0, | |
155 | 50)) | |
7e9804fd JN |
156 | DRM_ERROR("Timeout waiting for HS/LP DATA FIFO !full\n"); |
157 | ||
158 | write_data(dev_priv, data_reg, packet.payload, | |
159 | packet.payload_length); | |
160 | } | |
161 | ||
162 | if (msg->rx_len) { | |
163 | I915_WRITE(MIPI_INTR_STAT(port), GEN_READ_DATA_AVAIL); | |
164 | } | |
165 | ||
84c2aa90 CW |
166 | if (intel_wait_for_register(dev_priv, |
167 | MIPI_GEN_FIFO_STAT(port), | |
168 | ctrl_mask, 0, | |
169 | 50)) { | |
7e9804fd JN |
170 | DRM_ERROR("Timeout waiting for HS/LP CTRL FIFO !full\n"); |
171 | } | |
172 | ||
173 | I915_WRITE(ctrl_reg, header[2] << 16 | header[1] << 8 | header[0]); | |
174 | ||
175 | /* ->rx_len is set only for reads */ | |
176 | if (msg->rx_len) { | |
177 | data_mask = GEN_READ_DATA_AVAIL; | |
e7615b37 CW |
178 | if (intel_wait_for_register(dev_priv, |
179 | MIPI_INTR_STAT(port), | |
180 | data_mask, data_mask, | |
181 | 50)) | |
7e9804fd JN |
182 | DRM_ERROR("Timeout waiting for read data.\n"); |
183 | ||
184 | read_data(dev_priv, data_reg, msg->rx_buf, msg->rx_len); | |
185 | } | |
186 | ||
187 | /* XXX: fix for reads and writes */ | |
188 | return 4 + packet.payload_length; | |
189 | } | |
190 | ||
191 | static int intel_dsi_host_attach(struct mipi_dsi_host *host, | |
192 | struct mipi_dsi_device *dsi) | |
193 | { | |
194 | return 0; | |
195 | } | |
196 | ||
197 | static int intel_dsi_host_detach(struct mipi_dsi_host *host, | |
198 | struct mipi_dsi_device *dsi) | |
199 | { | |
200 | return 0; | |
201 | } | |
202 | ||
203 | static const struct mipi_dsi_host_ops intel_dsi_host_ops = { | |
204 | .attach = intel_dsi_host_attach, | |
205 | .detach = intel_dsi_host_detach, | |
206 | .transfer = intel_dsi_host_transfer, | |
207 | }; | |
208 | ||
209 | static struct intel_dsi_host *intel_dsi_host_init(struct intel_dsi *intel_dsi, | |
210 | enum port port) | |
211 | { | |
212 | struct intel_dsi_host *host; | |
213 | struct mipi_dsi_device *device; | |
214 | ||
215 | host = kzalloc(sizeof(*host), GFP_KERNEL); | |
216 | if (!host) | |
217 | return NULL; | |
218 | ||
219 | host->base.ops = &intel_dsi_host_ops; | |
220 | host->intel_dsi = intel_dsi; | |
221 | host->port = port; | |
222 | ||
223 | /* | |
224 | * We should call mipi_dsi_host_register(&host->base) here, but we don't | |
225 | * have a host->dev, and we don't have OF stuff either. So just use the | |
226 | * dsi framework as a library and hope for the best. Create the dsi | |
227 | * devices by ourselves here too. Need to be careful though, because we | |
228 | * don't initialize any of the driver model devices here. | |
229 | */ | |
230 | device = kzalloc(sizeof(*device), GFP_KERNEL); | |
231 | if (!device) { | |
232 | kfree(host); | |
233 | return NULL; | |
234 | } | |
235 | ||
236 | device->host = &host->base; | |
237 | host->device = device; | |
238 | ||
239 | return host; | |
240 | } | |
241 | ||
a2581a9e JN |
242 | /* |
243 | * send a video mode command | |
244 | * | |
245 | * XXX: commands with data in MIPI_DPI_DATA? | |
246 | */ | |
247 | static int dpi_send_cmd(struct intel_dsi *intel_dsi, u32 cmd, bool hs, | |
248 | enum port port) | |
249 | { | |
250 | struct drm_encoder *encoder = &intel_dsi->base.base; | |
251 | struct drm_device *dev = encoder->dev; | |
fac5e23e | 252 | struct drm_i915_private *dev_priv = to_i915(dev); |
a2581a9e JN |
253 | u32 mask; |
254 | ||
255 | /* XXX: pipe, hs */ | |
256 | if (hs) | |
257 | cmd &= ~DPI_LP_MODE; | |
258 | else | |
259 | cmd |= DPI_LP_MODE; | |
260 | ||
261 | /* clear bit */ | |
262 | I915_WRITE(MIPI_INTR_STAT(port), SPL_PKT_SENT_INTERRUPT); | |
263 | ||
264 | /* XXX: old code skips write if control unchanged */ | |
265 | if (cmd == I915_READ(MIPI_DPI_CONTROL(port))) | |
266 | DRM_ERROR("Same special packet %02x twice in a row.\n", cmd); | |
267 | ||
268 | I915_WRITE(MIPI_DPI_CONTROL(port), cmd); | |
269 | ||
270 | mask = SPL_PKT_SENT_INTERRUPT; | |
2af05078 CW |
271 | if (intel_wait_for_register(dev_priv, |
272 | MIPI_INTR_STAT(port), mask, mask, | |
273 | 100)) | |
a2581a9e JN |
274 | DRM_ERROR("Video mode command 0x%08x send failed.\n", cmd); |
275 | ||
276 | return 0; | |
277 | } | |
278 | ||
e9fe51c6 | 279 | static void band_gap_reset(struct drm_i915_private *dev_priv) |
4ce8c9a7 | 280 | { |
a580516d | 281 | mutex_lock(&dev_priv->sb_lock); |
4ce8c9a7 | 282 | |
e9fe51c6 SK |
283 | vlv_flisdsi_write(dev_priv, 0x08, 0x0001); |
284 | vlv_flisdsi_write(dev_priv, 0x0F, 0x0005); | |
285 | vlv_flisdsi_write(dev_priv, 0x0F, 0x0025); | |
286 | udelay(150); | |
287 | vlv_flisdsi_write(dev_priv, 0x0F, 0x0000); | |
288 | vlv_flisdsi_write(dev_priv, 0x08, 0x0000); | |
4ce8c9a7 | 289 | |
a580516d | 290 | mutex_unlock(&dev_priv->sb_lock); |
4ce8c9a7 SK |
291 | } |
292 | ||
4e646495 JN |
293 | static inline bool is_vid_mode(struct intel_dsi *intel_dsi) |
294 | { | |
dfba2e2d | 295 | return intel_dsi->operation_mode == INTEL_DSI_VIDEO_MODE; |
4e646495 JN |
296 | } |
297 | ||
298 | static inline bool is_cmd_mode(struct intel_dsi *intel_dsi) | |
299 | { | |
dfba2e2d | 300 | return intel_dsi->operation_mode == INTEL_DSI_COMMAND_MODE; |
4e646495 JN |
301 | } |
302 | ||
4e646495 | 303 | static bool intel_dsi_compute_config(struct intel_encoder *encoder, |
0a478c27 ML |
304 | struct intel_crtc_state *pipe_config, |
305 | struct drm_connector_state *conn_state) | |
4e646495 | 306 | { |
fac5e23e | 307 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
4e646495 JN |
308 | struct intel_dsi *intel_dsi = container_of(encoder, struct intel_dsi, |
309 | base); | |
310 | struct intel_connector *intel_connector = intel_dsi->attached_connector; | |
f4ee265f VS |
311 | struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc); |
312 | const struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode; | |
a65347ba | 313 | struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; |
47eacbab | 314 | int ret; |
4e646495 JN |
315 | |
316 | DRM_DEBUG_KMS("\n"); | |
317 | ||
f4ee265f | 318 | if (fixed_mode) { |
4e646495 JN |
319 | intel_fixed_panel_mode(fixed_mode, adjusted_mode); |
320 | ||
f4ee265f VS |
321 | if (HAS_GMCH_DISPLAY(dev_priv)) |
322 | intel_gmch_panel_fitting(crtc, pipe_config, | |
eead06df | 323 | conn_state->scaling_mode); |
f4ee265f VS |
324 | else |
325 | intel_pch_panel_fitting(crtc, pipe_config, | |
eead06df | 326 | conn_state->scaling_mode); |
f4ee265f VS |
327 | } |
328 | ||
f573de5a SK |
329 | /* DSI uses short packets for sync events, so clear mode flags for DSI */ |
330 | adjusted_mode->flags = 0; | |
331 | ||
cc3f90f0 | 332 | if (IS_GEN9_LP(dev_priv)) { |
4d1de975 JN |
333 | /* Dual link goes to DSI transcoder A. */ |
334 | if (intel_dsi->ports == BIT(PORT_C)) | |
335 | pipe_config->cpu_transcoder = TRANSCODER_DSI_C; | |
336 | else | |
337 | pipe_config->cpu_transcoder = TRANSCODER_DSI_A; | |
338 | } | |
339 | ||
47eacbab VS |
340 | ret = intel_compute_dsi_pll(encoder, pipe_config); |
341 | if (ret) | |
342 | return false; | |
343 | ||
cd2d34d9 VS |
344 | pipe_config->clock_set = true; |
345 | ||
4e646495 JN |
346 | return true; |
347 | } | |
348 | ||
8a1deb32 | 349 | static bool glk_dsi_enable_io(struct intel_encoder *encoder) |
46448483 D |
350 | { |
351 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); | |
352 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); | |
353 | enum port port; | |
74e4ce6a | 354 | u32 tmp; |
8a1deb32 | 355 | bool cold_boot = false; |
46448483 D |
356 | |
357 | /* Set the MIPI mode | |
358 | * If MIPI_Mode is off, then writing to LP_Wake bit is not reflecting. | |
359 | * Power ON MIPI IO first and then write into IO reset and LP wake bits | |
360 | */ | |
361 | for_each_dsi_port(port, intel_dsi->ports) { | |
362 | tmp = I915_READ(MIPI_CTRL(port)); | |
363 | I915_WRITE(MIPI_CTRL(port), tmp | GLK_MIPIIO_ENABLE); | |
364 | } | |
365 | ||
366 | /* Put the IO into reset */ | |
367 | tmp = I915_READ(MIPI_CTRL(PORT_A)); | |
368 | tmp &= ~GLK_MIPIIO_RESET_RELEASED; | |
369 | I915_WRITE(MIPI_CTRL(PORT_A), tmp); | |
370 | ||
371 | /* Program LP Wake */ | |
372 | for_each_dsi_port(port, intel_dsi->ports) { | |
373 | tmp = I915_READ(MIPI_CTRL(port)); | |
8a1deb32 MC |
374 | if (!(I915_READ(MIPI_DEVICE_READY(port)) & DEVICE_READY)) |
375 | tmp &= ~GLK_LP_WAKE; | |
376 | else | |
377 | tmp |= GLK_LP_WAKE; | |
46448483 D |
378 | I915_WRITE(MIPI_CTRL(port), tmp); |
379 | } | |
380 | ||
381 | /* Wait for Pwr ACK */ | |
382 | for_each_dsi_port(port, intel_dsi->ports) { | |
383 | if (intel_wait_for_register(dev_priv, | |
384 | MIPI_CTRL(port), GLK_MIPIIO_PORT_POWERED, | |
385 | GLK_MIPIIO_PORT_POWERED, 20)) | |
386 | DRM_ERROR("MIPIO port is powergated\n"); | |
387 | } | |
8a1deb32 MC |
388 | |
389 | /* Check for cold boot scenario */ | |
390 | for_each_dsi_port(port, intel_dsi->ports) { | |
391 | cold_boot |= !(I915_READ(MIPI_DEVICE_READY(port)) & | |
392 | DEVICE_READY); | |
393 | } | |
394 | ||
395 | return cold_boot; | |
74e4ce6a MC |
396 | } |
397 | ||
398 | static void glk_dsi_device_ready(struct intel_encoder *encoder) | |
399 | { | |
400 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); | |
401 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); | |
402 | enum port port; | |
403 | u32 val; | |
46448483 D |
404 | |
405 | /* Wait for MIPI PHY status bit to set */ | |
406 | for_each_dsi_port(port, intel_dsi->ports) { | |
407 | if (intel_wait_for_register(dev_priv, | |
408 | MIPI_CTRL(port), GLK_PHY_STATUS_PORT_READY, | |
409 | GLK_PHY_STATUS_PORT_READY, 20)) | |
410 | DRM_ERROR("PHY is not ON\n"); | |
411 | } | |
412 | ||
413 | /* Get IO out of reset */ | |
74e4ce6a MC |
414 | val = I915_READ(MIPI_CTRL(PORT_A)); |
415 | I915_WRITE(MIPI_CTRL(PORT_A), val | GLK_MIPIIO_RESET_RELEASED); | |
46448483 D |
416 | |
417 | /* Get IO out of Low power state*/ | |
418 | for_each_dsi_port(port, intel_dsi->ports) { | |
419 | if (!(I915_READ(MIPI_DEVICE_READY(port)) & DEVICE_READY)) { | |
420 | val = I915_READ(MIPI_DEVICE_READY(port)); | |
421 | val &= ~ULPS_STATE_MASK; | |
422 | val |= DEVICE_READY; | |
423 | I915_WRITE(MIPI_DEVICE_READY(port), val); | |
424 | usleep_range(10, 15); | |
8a1deb32 MC |
425 | } else { |
426 | /* Enter ULPS */ | |
427 | val = I915_READ(MIPI_DEVICE_READY(port)); | |
428 | val &= ~ULPS_STATE_MASK; | |
429 | val |= (ULPS_STATE_ENTER | DEVICE_READY); | |
430 | I915_WRITE(MIPI_DEVICE_READY(port), val); | |
46448483 | 431 | |
8a1deb32 MC |
432 | /* Wait for ULPS active */ |
433 | if (intel_wait_for_register(dev_priv, | |
3acbec03 | 434 | MIPI_CTRL(port), GLK_ULPS_NOT_ACTIVE, 0, 20)) |
8a1deb32 | 435 | DRM_ERROR("ULPS not active\n"); |
46448483 | 436 | |
8a1deb32 MC |
437 | /* Exit ULPS */ |
438 | val = I915_READ(MIPI_DEVICE_READY(port)); | |
439 | val &= ~ULPS_STATE_MASK; | |
440 | val |= (ULPS_STATE_EXIT | DEVICE_READY); | |
441 | I915_WRITE(MIPI_DEVICE_READY(port), val); | |
46448483 | 442 | |
8a1deb32 MC |
443 | /* Enter Normal Mode */ |
444 | val = I915_READ(MIPI_DEVICE_READY(port)); | |
445 | val &= ~ULPS_STATE_MASK; | |
446 | val |= (ULPS_STATE_NORMAL_OPERATION | DEVICE_READY); | |
447 | I915_WRITE(MIPI_DEVICE_READY(port), val); | |
46448483 | 448 | |
8a1deb32 MC |
449 | val = I915_READ(MIPI_CTRL(port)); |
450 | val &= ~GLK_LP_WAKE; | |
451 | I915_WRITE(MIPI_CTRL(port), val); | |
452 | } | |
46448483 D |
453 | } |
454 | ||
455 | /* Wait for Stop state */ | |
456 | for_each_dsi_port(port, intel_dsi->ports) { | |
457 | if (intel_wait_for_register(dev_priv, | |
458 | MIPI_CTRL(port), GLK_DATA_LANE_STOP_STATE, | |
459 | GLK_DATA_LANE_STOP_STATE, 20)) | |
460 | DRM_ERROR("Date lane not in STOP state\n"); | |
461 | } | |
462 | ||
463 | /* Wait for AFE LATCH */ | |
464 | for_each_dsi_port(port, intel_dsi->ports) { | |
465 | if (intel_wait_for_register(dev_priv, | |
466 | BXT_MIPI_PORT_CTRL(port), AFE_LATCHOUT, | |
467 | AFE_LATCHOUT, 20)) | |
468 | DRM_ERROR("D-PHY not entering LP-11 state\n"); | |
469 | } | |
470 | } | |
471 | ||
37ab0810 | 472 | static void bxt_dsi_device_ready(struct intel_encoder *encoder) |
5505a244 | 473 | { |
fac5e23e | 474 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
5505a244 | 475 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); |
369602d3 | 476 | enum port port; |
37ab0810 | 477 | u32 val; |
5505a244 | 478 | |
37ab0810 | 479 | DRM_DEBUG_KMS("\n"); |
a9da9bce | 480 | |
eba4daf0 | 481 | /* Enable MIPI PHY transparent latch */ |
369602d3 | 482 | for_each_dsi_port(port, intel_dsi->ports) { |
37ab0810 SS |
483 | val = I915_READ(BXT_MIPI_PORT_CTRL(port)); |
484 | I915_WRITE(BXT_MIPI_PORT_CTRL(port), val | LP_OUTPUT_HOLD); | |
485 | usleep_range(2000, 2500); | |
eba4daf0 | 486 | } |
37ab0810 | 487 | |
eba4daf0 US |
488 | /* Clear ULPS and set device ready */ |
489 | for_each_dsi_port(port, intel_dsi->ports) { | |
37ab0810 SS |
490 | val = I915_READ(MIPI_DEVICE_READY(port)); |
491 | val &= ~ULPS_STATE_MASK; | |
37ab0810 | 492 | I915_WRITE(MIPI_DEVICE_READY(port), val); |
eba4daf0 | 493 | usleep_range(2000, 2500); |
37ab0810 SS |
494 | val |= DEVICE_READY; |
495 | I915_WRITE(MIPI_DEVICE_READY(port), val); | |
369602d3 | 496 | } |
5505a244 GS |
497 | } |
498 | ||
37ab0810 | 499 | static void vlv_dsi_device_ready(struct intel_encoder *encoder) |
4e646495 | 500 | { |
fac5e23e | 501 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
24ee0e64 GS |
502 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); |
503 | enum port port; | |
1dbd7cb2 SK |
504 | u32 val; |
505 | ||
4e646495 | 506 | DRM_DEBUG_KMS("\n"); |
4e646495 | 507 | |
a580516d | 508 | mutex_lock(&dev_priv->sb_lock); |
2095f9fc SK |
509 | /* program rcomp for compliance, reduce from 50 ohms to 45 ohms |
510 | * needed everytime after power gate */ | |
511 | vlv_flisdsi_write(dev_priv, 0x04, 0x0004); | |
a580516d | 512 | mutex_unlock(&dev_priv->sb_lock); |
2095f9fc SK |
513 | |
514 | /* bandgap reset is needed after everytime we do power gate */ | |
515 | band_gap_reset(dev_priv); | |
516 | ||
24ee0e64 | 517 | for_each_dsi_port(port, intel_dsi->ports) { |
aceb365c | 518 | |
24ee0e64 GS |
519 | I915_WRITE(MIPI_DEVICE_READY(port), ULPS_STATE_ENTER); |
520 | usleep_range(2500, 3000); | |
aceb365c | 521 | |
bf344e80 GS |
522 | /* Enable MIPI PHY transparent latch |
523 | * Common bit for both MIPI Port A & MIPI Port C | |
524 | * No similar bit in MIPI Port C reg | |
525 | */ | |
4ba7d93a | 526 | val = I915_READ(MIPI_PORT_CTRL(PORT_A)); |
bf344e80 | 527 | I915_WRITE(MIPI_PORT_CTRL(PORT_A), val | LP_OUTPUT_HOLD); |
24ee0e64 | 528 | usleep_range(1000, 1500); |
aceb365c | 529 | |
24ee0e64 GS |
530 | I915_WRITE(MIPI_DEVICE_READY(port), ULPS_STATE_EXIT); |
531 | usleep_range(2500, 3000); | |
532 | ||
533 | I915_WRITE(MIPI_DEVICE_READY(port), DEVICE_READY); | |
534 | usleep_range(2500, 3000); | |
535 | } | |
1dbd7cb2 | 536 | } |
1dbd7cb2 | 537 | |
37ab0810 SS |
538 | static void intel_dsi_device_ready(struct intel_encoder *encoder) |
539 | { | |
e2d214ae | 540 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
37ab0810 | 541 | |
e2d214ae | 542 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) |
37ab0810 | 543 | vlv_dsi_device_ready(encoder); |
46448483 | 544 | else if (IS_BROXTON(dev_priv)) |
37ab0810 | 545 | bxt_dsi_device_ready(encoder); |
46448483 D |
546 | else if (IS_GEMINILAKE(dev_priv)) |
547 | glk_dsi_device_ready(encoder); | |
37ab0810 SS |
548 | } |
549 | ||
46448483 D |
550 | static void glk_dsi_enter_low_power_mode(struct intel_encoder *encoder) |
551 | { | |
552 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); | |
553 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); | |
554 | enum port port; | |
555 | u32 val; | |
556 | ||
557 | /* Enter ULPS */ | |
558 | for_each_dsi_port(port, intel_dsi->ports) { | |
559 | val = I915_READ(MIPI_DEVICE_READY(port)); | |
560 | val &= ~ULPS_STATE_MASK; | |
561 | val |= (ULPS_STATE_ENTER | DEVICE_READY); | |
562 | I915_WRITE(MIPI_DEVICE_READY(port), val); | |
563 | } | |
564 | ||
565 | /* Wait for MIPI PHY status bit to unset */ | |
566 | for_each_dsi_port(port, intel_dsi->ports) { | |
567 | if (intel_wait_for_register(dev_priv, | |
568 | MIPI_CTRL(port), | |
569 | GLK_PHY_STATUS_PORT_READY, 0, 20)) | |
570 | DRM_ERROR("PHY is not turning OFF\n"); | |
571 | } | |
572 | ||
573 | /* Wait for Pwr ACK bit to unset */ | |
574 | for_each_dsi_port(port, intel_dsi->ports) { | |
575 | if (intel_wait_for_register(dev_priv, | |
576 | MIPI_CTRL(port), | |
577 | GLK_MIPIIO_PORT_POWERED, 0, 20)) | |
578 | DRM_ERROR("MIPI IO Port is not powergated\n"); | |
579 | } | |
580 | } | |
581 | ||
582 | static void glk_dsi_disable_mipi_io(struct intel_encoder *encoder) | |
583 | { | |
584 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); | |
585 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); | |
586 | enum port port; | |
587 | u32 tmp; | |
588 | ||
589 | /* Put the IO into reset */ | |
590 | tmp = I915_READ(MIPI_CTRL(PORT_A)); | |
591 | tmp &= ~GLK_MIPIIO_RESET_RELEASED; | |
592 | I915_WRITE(MIPI_CTRL(PORT_A), tmp); | |
593 | ||
594 | /* Wait for MIPI PHY status bit to unset */ | |
595 | for_each_dsi_port(port, intel_dsi->ports) { | |
596 | if (intel_wait_for_register(dev_priv, | |
597 | MIPI_CTRL(port), | |
598 | GLK_PHY_STATUS_PORT_READY, 0, 20)) | |
599 | DRM_ERROR("PHY is not turning OFF\n"); | |
600 | } | |
601 | ||
602 | /* Clear MIPI mode */ | |
603 | for_each_dsi_port(port, intel_dsi->ports) { | |
604 | tmp = I915_READ(MIPI_CTRL(port)); | |
605 | tmp &= ~GLK_MIPIIO_ENABLE; | |
606 | I915_WRITE(MIPI_CTRL(port), tmp); | |
607 | } | |
608 | } | |
609 | ||
610 | static void glk_dsi_clear_device_ready(struct intel_encoder *encoder) | |
611 | { | |
612 | glk_dsi_enter_low_power_mode(encoder); | |
613 | glk_dsi_disable_mipi_io(encoder); | |
614 | } | |
615 | ||
616 | static void vlv_dsi_clear_device_ready(struct intel_encoder *encoder) | |
14be7a5c HG |
617 | { |
618 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); | |
619 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); | |
620 | enum port port; | |
621 | ||
622 | DRM_DEBUG_KMS("\n"); | |
623 | for_each_dsi_port(port, intel_dsi->ports) { | |
624 | /* Common bit for both MIPI Port A & MIPI Port C on VLV/CHV */ | |
625 | i915_reg_t port_ctrl = IS_GEN9_LP(dev_priv) ? | |
626 | BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(PORT_A); | |
627 | u32 val; | |
628 | ||
629 | I915_WRITE(MIPI_DEVICE_READY(port), DEVICE_READY | | |
630 | ULPS_STATE_ENTER); | |
631 | usleep_range(2000, 2500); | |
632 | ||
633 | I915_WRITE(MIPI_DEVICE_READY(port), DEVICE_READY | | |
634 | ULPS_STATE_EXIT); | |
635 | usleep_range(2000, 2500); | |
636 | ||
637 | I915_WRITE(MIPI_DEVICE_READY(port), DEVICE_READY | | |
638 | ULPS_STATE_ENTER); | |
639 | usleep_range(2000, 2500); | |
640 | ||
1e08a260 HG |
641 | /* |
642 | * On VLV/CHV, wait till Clock lanes are in LP-00 state for MIPI | |
643 | * Port A only. MIPI Port C has no similar bit for checking. | |
14be7a5c | 644 | */ |
1e08a260 HG |
645 | if ((IS_GEN9_LP(dev_priv) || port == PORT_A) && |
646 | intel_wait_for_register(dev_priv, | |
14be7a5c HG |
647 | port_ctrl, AFE_LATCHOUT, 0, |
648 | 30)) | |
649 | DRM_ERROR("DSI LP not going Low\n"); | |
650 | ||
651 | /* Disable MIPI PHY transparent latch */ | |
652 | val = I915_READ(port_ctrl); | |
653 | I915_WRITE(port_ctrl, val & ~LP_OUTPUT_HOLD); | |
654 | usleep_range(1000, 1500); | |
655 | ||
656 | I915_WRITE(MIPI_DEVICE_READY(port), 0x00); | |
657 | usleep_range(2000, 2500); | |
658 | } | |
659 | } | |
660 | ||
37ab0810 SS |
661 | static void intel_dsi_port_enable(struct intel_encoder *encoder) |
662 | { | |
663 | struct drm_device *dev = encoder->base.dev; | |
fac5e23e | 664 | struct drm_i915_private *dev_priv = to_i915(dev); |
37ab0810 SS |
665 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); |
666 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); | |
667 | enum port port; | |
37ab0810 SS |
668 | |
669 | if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) { | |
f0f59a00 | 670 | u32 temp; |
6043801f D |
671 | if (IS_GEN9_LP(dev_priv)) { |
672 | for_each_dsi_port(port, intel_dsi->ports) { | |
673 | temp = I915_READ(MIPI_CTRL(port)); | |
674 | temp &= ~BXT_PIXEL_OVERLAP_CNT_MASK | | |
675 | intel_dsi->pixel_overlap << | |
676 | BXT_PIXEL_OVERLAP_CNT_SHIFT; | |
677 | I915_WRITE(MIPI_CTRL(port), temp); | |
678 | } | |
679 | } else { | |
680 | temp = I915_READ(VLV_CHICKEN_3); | |
681 | temp &= ~PIXEL_OVERLAP_CNT_MASK | | |
37ab0810 SS |
682 | intel_dsi->pixel_overlap << |
683 | PIXEL_OVERLAP_CNT_SHIFT; | |
6043801f D |
684 | I915_WRITE(VLV_CHICKEN_3, temp); |
685 | } | |
37ab0810 SS |
686 | } |
687 | ||
688 | for_each_dsi_port(port, intel_dsi->ports) { | |
cc3f90f0 | 689 | i915_reg_t port_ctrl = IS_GEN9_LP(dev_priv) ? |
f0f59a00 VS |
690 | BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(port); |
691 | u32 temp; | |
37ab0810 SS |
692 | |
693 | temp = I915_READ(port_ctrl); | |
694 | ||
695 | temp &= ~LANE_CONFIGURATION_MASK; | |
696 | temp &= ~DUAL_LINK_MODE_MASK; | |
697 | ||
701d25b4 | 698 | if (intel_dsi->ports == (BIT(PORT_A) | BIT(PORT_C))) { |
37ab0810 SS |
699 | temp |= (intel_dsi->dual_link - 1) |
700 | << DUAL_LINK_MODE_SHIFT; | |
812b1d2f BP |
701 | if (IS_BROXTON(dev_priv)) |
702 | temp |= LANE_CONFIGURATION_DUAL_LINK_A; | |
703 | else | |
704 | temp |= intel_crtc->pipe ? | |
37ab0810 SS |
705 | LANE_CONFIGURATION_DUAL_LINK_B : |
706 | LANE_CONFIGURATION_DUAL_LINK_A; | |
707 | } | |
708 | /* assert ip_tg_enable signal */ | |
709 | I915_WRITE(port_ctrl, temp | DPI_ENABLE); | |
710 | POSTING_READ(port_ctrl); | |
711 | } | |
712 | } | |
713 | ||
714 | static void intel_dsi_port_disable(struct intel_encoder *encoder) | |
715 | { | |
716 | struct drm_device *dev = encoder->base.dev; | |
fac5e23e | 717 | struct drm_i915_private *dev_priv = to_i915(dev); |
37ab0810 SS |
718 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); |
719 | enum port port; | |
37ab0810 SS |
720 | |
721 | for_each_dsi_port(port, intel_dsi->ports) { | |
cc3f90f0 | 722 | i915_reg_t port_ctrl = IS_GEN9_LP(dev_priv) ? |
f0f59a00 VS |
723 | BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(port); |
724 | u32 temp; | |
725 | ||
37ab0810 | 726 | /* de-assert ip_tg_enable signal */ |
b389a45c SS |
727 | temp = I915_READ(port_ctrl); |
728 | I915_WRITE(port_ctrl, temp & ~DPI_ENABLE); | |
729 | POSTING_READ(port_ctrl); | |
37ab0810 SS |
730 | } |
731 | } | |
732 | ||
5eff0edf | 733 | static void intel_dsi_prepare(struct intel_encoder *intel_encoder, |
5f88a9c6 | 734 | const struct intel_crtc_state *pipe_config); |
c7991eca | 735 | static void intel_dsi_unprepare(struct intel_encoder *encoder); |
e3488e75 | 736 | |
25b4620e HG |
737 | static void intel_dsi_msleep(struct intel_dsi *intel_dsi, int msec) |
738 | { | |
739 | struct drm_i915_private *dev_priv = to_i915(intel_dsi->base.base.dev); | |
740 | ||
741 | /* For v3 VBTs in vid-mode the delays are part of the VBT sequences */ | |
742 | if (is_vid_mode(intel_dsi) && dev_priv->vbt.dsi.seq_version >= 3) | |
743 | return; | |
744 | ||
745 | msleep(msec); | |
746 | } | |
747 | ||
249f6962 HG |
748 | /* |
749 | * Panel enable/disable sequences from the VBT spec. | |
750 | * | |
751 | * Note the spec has AssertReset / DeassertReset swapped from their | |
752 | * usual naming. We use the normal names to avoid confusion (so below | |
753 | * they are swapped compared to the spec). | |
754 | * | |
755 | * Steps starting with MIPI refer to VBT sequences, note that for v2 | |
756 | * VBTs several steps which have a VBT in v2 are expected to be handled | |
757 | * directly by the driver, by directly driving gpios for example. | |
758 | * | |
759 | * v2 video mode seq v3 video mode seq command mode seq | |
760 | * - power on - MIPIPanelPowerOn - power on | |
761 | * - wait t1+t2 - wait t1+t2 | |
762 | * - MIPIDeassertResetPin - MIPIDeassertResetPin - MIPIDeassertResetPin | |
763 | * - io lines to lp-11 - io lines to lp-11 - io lines to lp-11 | |
764 | * - MIPISendInitialDcsCmds - MIPISendInitialDcsCmds - MIPISendInitialDcsCmds | |
765 | * - MIPITearOn | |
766 | * - MIPIDisplayOn | |
767 | * - turn on DPI - turn on DPI - set pipe to dsr mode | |
768 | * - MIPIDisplayOn - MIPIDisplayOn | |
769 | * - wait t5 - wait t5 | |
770 | * - backlight on - MIPIBacklightOn - backlight on | |
771 | * ... ... ... issue mem cmds ... | |
772 | * - backlight off - MIPIBacklightOff - backlight off | |
773 | * - wait t6 - wait t6 | |
774 | * - MIPIDisplayOff | |
775 | * - turn off DPI - turn off DPI - disable pipe dsr mode | |
776 | * - MIPITearOff | |
777 | * - MIPIDisplayOff - MIPIDisplayOff | |
778 | * - io lines to lp-00 - io lines to lp-00 - io lines to lp-00 | |
779 | * - MIPIAssertResetPin - MIPIAssertResetPin - MIPIAssertResetPin | |
780 | * - wait t3 - wait t3 | |
781 | * - power off - MIPIPanelPowerOff - power off | |
782 | * - wait t4 - wait t4 | |
783 | */ | |
784 | ||
fd6bbda9 | 785 | static void intel_dsi_pre_enable(struct intel_encoder *encoder, |
5f88a9c6 VS |
786 | const struct intel_crtc_state *pipe_config, |
787 | const struct drm_connector_state *conn_state) | |
2634fd7f | 788 | { |
5eff0edf | 789 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
2634fd7f | 790 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); |
5a2e65e7 | 791 | enum port port; |
1881a423 | 792 | u32 val; |
8a1deb32 | 793 | bool glk_cold_boot = false; |
2634fd7f SK |
794 | |
795 | DRM_DEBUG_KMS("\n"); | |
796 | ||
f00b5689 VS |
797 | /* |
798 | * The BIOS may leave the PLL in a wonky state where it doesn't | |
799 | * lock. It needs to be fully powered down to fix it. | |
800 | */ | |
801 | intel_disable_dsi_pll(encoder); | |
5eff0edf | 802 | intel_enable_dsi_pll(encoder, pipe_config); |
f00b5689 | 803 | |
1881a423 US |
804 | if (IS_BROXTON(dev_priv)) { |
805 | /* Add MIPI IO reset programming for modeset */ | |
806 | val = I915_READ(BXT_P_CR_GT_DISP_PWRON); | |
807 | I915_WRITE(BXT_P_CR_GT_DISP_PWRON, | |
808 | val | MIPIO_RST_CTRL); | |
809 | ||
810 | /* Power up DSI regulator */ | |
811 | I915_WRITE(BXT_P_DSI_REGULATOR_CFG, STAP_SELECT); | |
812 | I915_WRITE(BXT_P_DSI_REGULATOR_TX_CTRL, 0); | |
813 | } | |
814 | ||
d1877c0f VS |
815 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { |
816 | u32 val; | |
817 | ||
cd2d34d9 | 818 | /* Disable DPOunit clock gating, can stall pipe */ |
d1877c0f VS |
819 | val = I915_READ(DSPCLK_GATE_D); |
820 | val |= DPOUNIT_CLOCK_GATE_DISABLE; | |
821 | I915_WRITE(DSPCLK_GATE_D, val); | |
37ab0810 | 822 | } |
2634fd7f | 823 | |
8a1deb32 MC |
824 | if (!IS_GEMINILAKE(dev_priv)) |
825 | intel_dsi_prepare(encoder, pipe_config); | |
deae2006 HG |
826 | |
827 | /* Power on, try both CRC pmic gpio and VBT */ | |
828 | if (intel_dsi->gpio_panel) | |
829 | gpiod_set_value_cansleep(intel_dsi->gpio_panel, 1); | |
b0dd6887 | 830 | intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_POWER_ON); |
25b4620e | 831 | intel_dsi_msleep(intel_dsi, intel_dsi->panel_on_delay); |
deae2006 | 832 | |
3e40fa8a | 833 | /* Deassert reset */ |
b0dd6887 | 834 | intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DEASSERT_RESET); |
3e40fa8a | 835 | |
8a1deb32 MC |
836 | if (IS_GEMINILAKE(dev_priv)) { |
837 | glk_cold_boot = glk_dsi_enable_io(encoder); | |
838 | ||
839 | /* Prepare port in cold boot(s3/s4) scenario */ | |
840 | if (glk_cold_boot) | |
841 | intel_dsi_prepare(encoder, pipe_config); | |
842 | } | |
74e4ce6a | 843 | |
3e40fa8a | 844 | /* Put device in ready state (LP-11) */ |
2634fd7f | 845 | intel_dsi_device_ready(encoder); |
4e646495 | 846 | |
8a1deb32 MC |
847 | /* Prepare port in normal boot scenario */ |
848 | if (IS_GEMINILAKE(dev_priv) && !glk_cold_boot) | |
849 | intel_dsi_prepare(encoder, pipe_config); | |
850 | ||
3e40fa8a | 851 | /* Send initialization commands in LP mode */ |
b0dd6887 | 852 | intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_INIT_OTP); |
20e5bf66 | 853 | |
2634fd7f SK |
854 | /* Enable port in pre-enable phase itself because as per hw team |
855 | * recommendation, port should be enabled befor plane & pipe */ | |
5a2e65e7 HG |
856 | if (is_cmd_mode(intel_dsi)) { |
857 | for_each_dsi_port(port, intel_dsi->ports) | |
858 | I915_WRITE(MIPI_MAX_RETURN_PKT_SIZE(port), 8 * 4); | |
b0dd6887 JN |
859 | intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_TEAR_ON); |
860 | intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DISPLAY_ON); | |
5a2e65e7 HG |
861 | } else { |
862 | msleep(20); /* XXX */ | |
863 | for_each_dsi_port(port, intel_dsi->ports) | |
864 | dpi_send_cmd(intel_dsi, TURN_ON, false, port); | |
25b4620e | 865 | intel_dsi_msleep(intel_dsi, 100); |
5a2e65e7 | 866 | |
b0dd6887 | 867 | intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DISPLAY_ON); |
5a2e65e7 HG |
868 | |
869 | intel_dsi_port_enable(encoder); | |
870 | } | |
871 | ||
b037d58f | 872 | intel_panel_enable_backlight(pipe_config, conn_state); |
b0dd6887 | 873 | intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_BACKLIGHT_ON); |
2634fd7f SK |
874 | } |
875 | ||
fefc51e8 JN |
876 | /* |
877 | * DSI port enable has to be done before pipe and plane enable, so we do it in | |
878 | * the pre_enable hook. | |
879 | */ | |
fd6bbda9 | 880 | static void intel_dsi_enable_nop(struct intel_encoder *encoder, |
5f88a9c6 VS |
881 | const struct intel_crtc_state *pipe_config, |
882 | const struct drm_connector_state *conn_state) | |
2634fd7f SK |
883 | { |
884 | DRM_DEBUG_KMS("\n"); | |
4e646495 JN |
885 | } |
886 | ||
fefc51e8 JN |
887 | /* |
888 | * DSI port disable has to be done after pipe and plane disable, so we do it in | |
889 | * the post_disable hook. | |
890 | */ | |
891 | static void intel_dsi_disable(struct intel_encoder *encoder, | |
5f88a9c6 VS |
892 | const struct intel_crtc_state *old_crtc_state, |
893 | const struct drm_connector_state *old_conn_state) | |
c315faf8 ID |
894 | { |
895 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); | |
f03e4179 | 896 | enum port port; |
c315faf8 ID |
897 | |
898 | DRM_DEBUG_KMS("\n"); | |
899 | ||
b0dd6887 | 900 | intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_BACKLIGHT_OFF); |
b037d58f | 901 | intel_panel_disable_backlight(old_conn_state); |
b029e66f | 902 | |
39831451 HG |
903 | /* |
904 | * According to the spec we should send SHUTDOWN before | |
905 | * MIPI_SEQ_DISPLAY_OFF only for v3+ VBTs, but field testing | |
906 | * has shown that the v3 sequence works for v2 VBTs too | |
907 | */ | |
c315faf8 ID |
908 | if (is_vid_mode(intel_dsi)) { |
909 | /* Send Shutdown command to the panel in LP mode */ | |
f03e4179 | 910 | for_each_dsi_port(port, intel_dsi->ports) |
a2581a9e | 911 | dpi_send_cmd(intel_dsi, SHUTDOWN, false, port); |
c315faf8 ID |
912 | msleep(10); |
913 | } | |
914 | } | |
915 | ||
46448483 D |
916 | static void intel_dsi_clear_device_ready(struct intel_encoder *encoder) |
917 | { | |
918 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); | |
919 | ||
920 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv) || | |
921 | IS_BROXTON(dev_priv)) | |
922 | vlv_dsi_clear_device_ready(encoder); | |
923 | else if (IS_GEMINILAKE(dev_priv)) | |
924 | glk_dsi_clear_device_ready(encoder); | |
925 | } | |
926 | ||
fd6bbda9 | 927 | static void intel_dsi_post_disable(struct intel_encoder *encoder, |
5f88a9c6 VS |
928 | const struct intel_crtc_state *pipe_config, |
929 | const struct drm_connector_state *conn_state) | |
1dbd7cb2 | 930 | { |
fac5e23e | 931 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
1dbd7cb2 | 932 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); |
5a2e65e7 | 933 | enum port port; |
1881a423 | 934 | u32 val; |
1dbd7cb2 SK |
935 | |
936 | DRM_DEBUG_KMS("\n"); | |
937 | ||
5a2e65e7 HG |
938 | if (is_vid_mode(intel_dsi)) { |
939 | for_each_dsi_port(port, intel_dsi->ports) | |
940 | wait_for_dsi_fifo_empty(intel_dsi, port); | |
941 | ||
942 | intel_dsi_port_disable(encoder); | |
943 | usleep_range(2000, 5000); | |
944 | } | |
945 | ||
c7991eca | 946 | intel_dsi_unprepare(encoder); |
5a2e65e7 HG |
947 | |
948 | /* | |
949 | * if disable packets are sent before sending shutdown packet then in | |
950 | * some next enable sequence send turn on packet error is observed | |
951 | */ | |
7108b436 | 952 | if (is_cmd_mode(intel_dsi)) |
b0dd6887 JN |
953 | intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_TEAR_OFF); |
954 | intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DISPLAY_OFF); | |
c315faf8 | 955 | |
3e40fa8a | 956 | /* Transition to LP-00 */ |
1dbd7cb2 SK |
957 | intel_dsi_clear_device_ready(encoder); |
958 | ||
1881a423 US |
959 | if (IS_BROXTON(dev_priv)) { |
960 | /* Power down DSI regulator to save power */ | |
961 | I915_WRITE(BXT_P_DSI_REGULATOR_CFG, STAP_SELECT); | |
962 | I915_WRITE(BXT_P_DSI_REGULATOR_TX_CTRL, HS_IO_CTRL_SELECT); | |
963 | ||
964 | /* Add MIPI IO reset programming for modeset */ | |
965 | val = I915_READ(BXT_P_CR_GT_DISP_PWRON); | |
966 | I915_WRITE(BXT_P_CR_GT_DISP_PWRON, | |
967 | val & ~MIPIO_RST_CTRL); | |
968 | } | |
969 | ||
e840fd31 HG |
970 | intel_disable_dsi_pll(encoder); |
971 | ||
d1877c0f | 972 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { |
d6e3af54 US |
973 | u32 val; |
974 | ||
975 | val = I915_READ(DSPCLK_GATE_D); | |
976 | val &= ~DPOUNIT_CLOCK_GATE_DISABLE; | |
977 | I915_WRITE(DSPCLK_GATE_D, val); | |
978 | } | |
20e5bf66 | 979 | |
3e40fa8a | 980 | /* Assert reset */ |
b0dd6887 | 981 | intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_ASSERT_RESET); |
df38e655 | 982 | |
c7dc5275 | 983 | /* Power off, try both CRC pmic gpio and VBT */ |
25b4620e | 984 | intel_dsi_msleep(intel_dsi, intel_dsi->panel_off_delay); |
b0dd6887 | 985 | intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_POWER_OFF); |
fc45e821 SK |
986 | if (intel_dsi->gpio_panel) |
987 | gpiod_set_value_cansleep(intel_dsi->gpio_panel, 0); | |
1d5c65ed VS |
988 | |
989 | /* | |
990 | * FIXME As we do with eDP, just make a note of the time here | |
991 | * and perform the wait before the next panel power on. | |
992 | */ | |
25b4620e | 993 | intel_dsi_msleep(intel_dsi, intel_dsi->panel_pwr_cycle_delay); |
1dbd7cb2 | 994 | } |
4e646495 JN |
995 | |
996 | static bool intel_dsi_get_hw_state(struct intel_encoder *encoder, | |
997 | enum pipe *pipe) | |
998 | { | |
fac5e23e | 999 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
c0beefd2 | 1000 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); |
e7d7cad0 | 1001 | enum port port; |
1dcec2f3 | 1002 | bool active = false; |
4e646495 JN |
1003 | |
1004 | DRM_DEBUG_KMS("\n"); | |
1005 | ||
79f255a0 ACO |
1006 | if (!intel_display_power_get_if_enabled(dev_priv, |
1007 | encoder->power_domain)) | |
6d129bea ID |
1008 | return false; |
1009 | ||
db18b6a6 ID |
1010 | /* |
1011 | * On Broxton the PLL needs to be enabled with a valid divider | |
1012 | * configuration, otherwise accessing DSI registers will hang the | |
1013 | * machine. See BSpec North Display Engine registers/MIPI[BXT]. | |
1014 | */ | |
cc3f90f0 | 1015 | if (IS_GEN9_LP(dev_priv) && !intel_dsi_pll_is_enabled(dev_priv)) |
db18b6a6 ID |
1016 | goto out_put_power; |
1017 | ||
4e646495 | 1018 | /* XXX: this only works for one DSI output */ |
c0beefd2 | 1019 | for_each_dsi_port(port, intel_dsi->ports) { |
cc3f90f0 | 1020 | i915_reg_t ctrl_reg = IS_GEN9_LP(dev_priv) ? |
f0f59a00 | 1021 | BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(port); |
1dcec2f3 | 1022 | bool enabled = I915_READ(ctrl_reg) & DPI_ENABLE; |
c0beefd2 | 1023 | |
e6f57789 JN |
1024 | /* |
1025 | * Due to some hardware limitations on VLV/CHV, the DPI enable | |
1026 | * bit in port C control register does not get set. As a | |
1027 | * workaround, check pipe B conf instead. | |
c0beefd2 | 1028 | */ |
920a14b2 TU |
1029 | if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && |
1030 | port == PORT_C) | |
1dcec2f3 | 1031 | enabled = I915_READ(PIPECONF(PIPE_B)) & PIPECONF_ENABLE; |
4e646495 | 1032 | |
1dcec2f3 JN |
1033 | /* Try command mode if video mode not enabled */ |
1034 | if (!enabled) { | |
1035 | u32 tmp = I915_READ(MIPI_DSI_FUNC_PRG(port)); | |
1036 | enabled = tmp & CMD_MODE_DATA_WIDTH_MASK; | |
4e646495 | 1037 | } |
1dcec2f3 JN |
1038 | |
1039 | if (!enabled) | |
1040 | continue; | |
1041 | ||
1042 | if (!(I915_READ(MIPI_DEVICE_READY(port)) & DEVICE_READY)) | |
1043 | continue; | |
1044 | ||
cc3f90f0 | 1045 | if (IS_GEN9_LP(dev_priv)) { |
6b93e9c8 JN |
1046 | u32 tmp = I915_READ(MIPI_CTRL(port)); |
1047 | tmp &= BXT_PIPE_SELECT_MASK; | |
1048 | tmp >>= BXT_PIPE_SELECT_SHIFT; | |
1049 | ||
1050 | if (WARN_ON(tmp > PIPE_C)) | |
1051 | continue; | |
1052 | ||
1053 | *pipe = tmp; | |
1054 | } else { | |
1055 | *pipe = port == PORT_A ? PIPE_A : PIPE_B; | |
1056 | } | |
1057 | ||
1dcec2f3 JN |
1058 | active = true; |
1059 | break; | |
4e646495 | 1060 | } |
1dcec2f3 | 1061 | |
db18b6a6 | 1062 | out_put_power: |
79f255a0 | 1063 | intel_display_power_put(dev_priv, encoder->power_domain); |
4e646495 | 1064 | |
1dcec2f3 | 1065 | return active; |
4e646495 JN |
1066 | } |
1067 | ||
6f0e7535 | 1068 | static void bxt_dsi_get_pipe_config(struct intel_encoder *encoder, |
5f88a9c6 | 1069 | struct intel_crtc_state *pipe_config) |
6f0e7535 R |
1070 | { |
1071 | struct drm_device *dev = encoder->base.dev; | |
fac5e23e | 1072 | struct drm_i915_private *dev_priv = to_i915(dev); |
6f0e7535 R |
1073 | struct drm_display_mode *adjusted_mode = |
1074 | &pipe_config->base.adjusted_mode; | |
042ab0c3 R |
1075 | struct drm_display_mode *adjusted_mode_sw; |
1076 | struct intel_crtc *intel_crtc; | |
6f0e7535 | 1077 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); |
cefc4e18 | 1078 | unsigned int lane_count = intel_dsi->lane_count; |
6f0e7535 R |
1079 | unsigned int bpp, fmt; |
1080 | enum port port; | |
cefc4e18 | 1081 | u16 hactive, hfp, hsync, hbp, vfp, vsync, vbp; |
042ab0c3 R |
1082 | u16 hfp_sw, hsync_sw, hbp_sw; |
1083 | u16 crtc_htotal_sw, crtc_hsync_start_sw, crtc_hsync_end_sw, | |
1084 | crtc_hblank_start_sw, crtc_hblank_end_sw; | |
1085 | ||
5eff0edf | 1086 | /* FIXME: hw readout should not depend on SW state */ |
042ab0c3 R |
1087 | intel_crtc = to_intel_crtc(encoder->base.crtc); |
1088 | adjusted_mode_sw = &intel_crtc->config->base.adjusted_mode; | |
6f0e7535 R |
1089 | |
1090 | /* | |
1091 | * Atleast one port is active as encoder->get_config called only if | |
1092 | * encoder->get_hw_state() returns true. | |
1093 | */ | |
1094 | for_each_dsi_port(port, intel_dsi->ports) { | |
1095 | if (I915_READ(BXT_MIPI_PORT_CTRL(port)) & DPI_ENABLE) | |
1096 | break; | |
1097 | } | |
1098 | ||
1099 | fmt = I915_READ(MIPI_DSI_FUNC_PRG(port)) & VID_MODE_FORMAT_MASK; | |
1100 | pipe_config->pipe_bpp = | |
1101 | mipi_dsi_pixel_format_to_bpp( | |
1102 | pixel_format_from_register_bits(fmt)); | |
1103 | bpp = pipe_config->pipe_bpp; | |
1104 | ||
1105 | /* In terms of pixels */ | |
1106 | adjusted_mode->crtc_hdisplay = | |
1107 | I915_READ(BXT_MIPI_TRANS_HACTIVE(port)); | |
1108 | adjusted_mode->crtc_vdisplay = | |
1109 | I915_READ(BXT_MIPI_TRANS_VACTIVE(port)); | |
1110 | adjusted_mode->crtc_vtotal = | |
1111 | I915_READ(BXT_MIPI_TRANS_VTOTAL(port)); | |
1112 | ||
cefc4e18 R |
1113 | hactive = adjusted_mode->crtc_hdisplay; |
1114 | hfp = I915_READ(MIPI_HFP_COUNT(port)); | |
1115 | ||
6f0e7535 | 1116 | /* |
cefc4e18 R |
1117 | * Meaningful for video mode non-burst sync pulse mode only, |
1118 | * can be zero for non-burst sync events and burst modes | |
6f0e7535 | 1119 | */ |
cefc4e18 R |
1120 | hsync = I915_READ(MIPI_HSYNC_PADDING_COUNT(port)); |
1121 | hbp = I915_READ(MIPI_HBP_COUNT(port)); | |
1122 | ||
1123 | /* harizontal values are in terms of high speed byte clock */ | |
1124 | hfp = pixels_from_txbyteclkhs(hfp, bpp, lane_count, | |
1125 | intel_dsi->burst_mode_ratio); | |
1126 | hsync = pixels_from_txbyteclkhs(hsync, bpp, lane_count, | |
1127 | intel_dsi->burst_mode_ratio); | |
1128 | hbp = pixels_from_txbyteclkhs(hbp, bpp, lane_count, | |
1129 | intel_dsi->burst_mode_ratio); | |
1130 | ||
1131 | if (intel_dsi->dual_link) { | |
1132 | hfp *= 2; | |
1133 | hsync *= 2; | |
1134 | hbp *= 2; | |
1135 | } | |
6f0e7535 R |
1136 | |
1137 | /* vertical values are in terms of lines */ | |
1138 | vfp = I915_READ(MIPI_VFP_COUNT(port)); | |
1139 | vsync = I915_READ(MIPI_VSYNC_PADDING_COUNT(port)); | |
1140 | vbp = I915_READ(MIPI_VBP_COUNT(port)); | |
1141 | ||
cefc4e18 R |
1142 | adjusted_mode->crtc_htotal = hactive + hfp + hsync + hbp; |
1143 | adjusted_mode->crtc_hsync_start = hfp + adjusted_mode->crtc_hdisplay; | |
1144 | adjusted_mode->crtc_hsync_end = hsync + adjusted_mode->crtc_hsync_start; | |
6f0e7535 | 1145 | adjusted_mode->crtc_hblank_start = adjusted_mode->crtc_hdisplay; |
cefc4e18 | 1146 | adjusted_mode->crtc_hblank_end = adjusted_mode->crtc_htotal; |
6f0e7535 | 1147 | |
cefc4e18 R |
1148 | adjusted_mode->crtc_vsync_start = vfp + adjusted_mode->crtc_vdisplay; |
1149 | adjusted_mode->crtc_vsync_end = vsync + adjusted_mode->crtc_vsync_start; | |
6f0e7535 R |
1150 | adjusted_mode->crtc_vblank_start = adjusted_mode->crtc_vdisplay; |
1151 | adjusted_mode->crtc_vblank_end = adjusted_mode->crtc_vtotal; | |
6f0e7535 | 1152 | |
042ab0c3 R |
1153 | /* |
1154 | * In BXT DSI there is no regs programmed with few horizontal timings | |
1155 | * in Pixels but txbyteclkhs.. So retrieval process adds some | |
1156 | * ROUND_UP ERRORS in the process of PIXELS<==>txbyteclkhs. | |
1157 | * Actually here for the given adjusted_mode, we are calculating the | |
1158 | * value programmed to the port and then back to the horizontal timing | |
1159 | * param in pixels. This is the expected value, including roundup errors | |
1160 | * And if that is same as retrieved value from port, then | |
1161 | * (HW state) adjusted_mode's horizontal timings are corrected to | |
1162 | * match with SW state to nullify the errors. | |
1163 | */ | |
1164 | /* Calculating the value programmed to the Port register */ | |
1165 | hfp_sw = adjusted_mode_sw->crtc_hsync_start - | |
1166 | adjusted_mode_sw->crtc_hdisplay; | |
1167 | hsync_sw = adjusted_mode_sw->crtc_hsync_end - | |
1168 | adjusted_mode_sw->crtc_hsync_start; | |
1169 | hbp_sw = adjusted_mode_sw->crtc_htotal - | |
1170 | adjusted_mode_sw->crtc_hsync_end; | |
1171 | ||
1172 | if (intel_dsi->dual_link) { | |
1173 | hfp_sw /= 2; | |
1174 | hsync_sw /= 2; | |
1175 | hbp_sw /= 2; | |
1176 | } | |
1177 | ||
1178 | hfp_sw = txbyteclkhs(hfp_sw, bpp, lane_count, | |
1179 | intel_dsi->burst_mode_ratio); | |
1180 | hsync_sw = txbyteclkhs(hsync_sw, bpp, lane_count, | |
1181 | intel_dsi->burst_mode_ratio); | |
1182 | hbp_sw = txbyteclkhs(hbp_sw, bpp, lane_count, | |
1183 | intel_dsi->burst_mode_ratio); | |
1184 | ||
1185 | /* Reverse calculating the adjusted mode parameters from port reg vals*/ | |
1186 | hfp_sw = pixels_from_txbyteclkhs(hfp_sw, bpp, lane_count, | |
1187 | intel_dsi->burst_mode_ratio); | |
1188 | hsync_sw = pixels_from_txbyteclkhs(hsync_sw, bpp, lane_count, | |
1189 | intel_dsi->burst_mode_ratio); | |
1190 | hbp_sw = pixels_from_txbyteclkhs(hbp_sw, bpp, lane_count, | |
1191 | intel_dsi->burst_mode_ratio); | |
1192 | ||
1193 | if (intel_dsi->dual_link) { | |
1194 | hfp_sw *= 2; | |
1195 | hsync_sw *= 2; | |
1196 | hbp_sw *= 2; | |
1197 | } | |
1198 | ||
1199 | crtc_htotal_sw = adjusted_mode_sw->crtc_hdisplay + hfp_sw + | |
1200 | hsync_sw + hbp_sw; | |
1201 | crtc_hsync_start_sw = hfp_sw + adjusted_mode_sw->crtc_hdisplay; | |
1202 | crtc_hsync_end_sw = hsync_sw + crtc_hsync_start_sw; | |
1203 | crtc_hblank_start_sw = adjusted_mode_sw->crtc_hdisplay; | |
1204 | crtc_hblank_end_sw = crtc_htotal_sw; | |
1205 | ||
1206 | if (adjusted_mode->crtc_htotal == crtc_htotal_sw) | |
1207 | adjusted_mode->crtc_htotal = adjusted_mode_sw->crtc_htotal; | |
1208 | ||
1209 | if (adjusted_mode->crtc_hsync_start == crtc_hsync_start_sw) | |
1210 | adjusted_mode->crtc_hsync_start = | |
1211 | adjusted_mode_sw->crtc_hsync_start; | |
1212 | ||
1213 | if (adjusted_mode->crtc_hsync_end == crtc_hsync_end_sw) | |
1214 | adjusted_mode->crtc_hsync_end = | |
1215 | adjusted_mode_sw->crtc_hsync_end; | |
1216 | ||
1217 | if (adjusted_mode->crtc_hblank_start == crtc_hblank_start_sw) | |
1218 | adjusted_mode->crtc_hblank_start = | |
1219 | adjusted_mode_sw->crtc_hblank_start; | |
1220 | ||
1221 | if (adjusted_mode->crtc_hblank_end == crtc_hblank_end_sw) | |
1222 | adjusted_mode->crtc_hblank_end = | |
1223 | adjusted_mode_sw->crtc_hblank_end; | |
1224 | } | |
6f0e7535 | 1225 | |
4e646495 | 1226 | static void intel_dsi_get_config(struct intel_encoder *encoder, |
5cec258b | 1227 | struct intel_crtc_state *pipe_config) |
4e646495 | 1228 | { |
e2d214ae | 1229 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
d7d85d85 | 1230 | u32 pclk; |
4e646495 JN |
1231 | DRM_DEBUG_KMS("\n"); |
1232 | ||
cc3f90f0 | 1233 | if (IS_GEN9_LP(dev_priv)) |
6f0e7535 R |
1234 | bxt_dsi_get_pipe_config(encoder, pipe_config); |
1235 | ||
47eacbab VS |
1236 | pclk = intel_dsi_get_pclk(encoder, pipe_config->pipe_bpp, |
1237 | pipe_config); | |
f573de5a SK |
1238 | if (!pclk) |
1239 | return; | |
1240 | ||
2d112de7 | 1241 | pipe_config->base.adjusted_mode.crtc_clock = pclk; |
f573de5a | 1242 | pipe_config->port_clock = pclk; |
4e646495 JN |
1243 | } |
1244 | ||
c19de8eb DL |
1245 | static enum drm_mode_status |
1246 | intel_dsi_mode_valid(struct drm_connector *connector, | |
1247 | struct drm_display_mode *mode) | |
4e646495 JN |
1248 | { |
1249 | struct intel_connector *intel_connector = to_intel_connector(connector); | |
f4ee265f | 1250 | const struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode; |
759a1e98 | 1251 | int max_dotclk = to_i915(connector->dev)->max_dotclk_freq; |
4e646495 JN |
1252 | |
1253 | DRM_DEBUG_KMS("\n"); | |
1254 | ||
1255 | if (mode->flags & DRM_MODE_FLAG_DBLSCAN) { | |
1256 | DRM_DEBUG_KMS("MODE_NO_DBLESCAN\n"); | |
1257 | return MODE_NO_DBLESCAN; | |
1258 | } | |
1259 | ||
1260 | if (fixed_mode) { | |
1261 | if (mode->hdisplay > fixed_mode->hdisplay) | |
1262 | return MODE_PANEL; | |
1263 | if (mode->vdisplay > fixed_mode->vdisplay) | |
1264 | return MODE_PANEL; | |
759a1e98 MK |
1265 | if (fixed_mode->clock > max_dotclk) |
1266 | return MODE_CLOCK_HIGH; | |
4e646495 JN |
1267 | } |
1268 | ||
36d21f4c | 1269 | return MODE_OK; |
4e646495 JN |
1270 | } |
1271 | ||
1272 | /* return txclkesc cycles in terms of divider and duration in us */ | |
1273 | static u16 txclkesc(u32 divider, unsigned int us) | |
1274 | { | |
1275 | switch (divider) { | |
1276 | case ESCAPE_CLOCK_DIVIDER_1: | |
1277 | default: | |
1278 | return 20 * us; | |
1279 | case ESCAPE_CLOCK_DIVIDER_2: | |
1280 | return 10 * us; | |
1281 | case ESCAPE_CLOCK_DIVIDER_4: | |
1282 | return 5 * us; | |
1283 | } | |
1284 | } | |
1285 | ||
4e646495 | 1286 | static void set_dsi_timings(struct drm_encoder *encoder, |
5e7234c9 | 1287 | const struct drm_display_mode *adjusted_mode) |
4e646495 JN |
1288 | { |
1289 | struct drm_device *dev = encoder->dev; | |
fac5e23e | 1290 | struct drm_i915_private *dev_priv = to_i915(dev); |
4e646495 | 1291 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); |
aa102d28 | 1292 | enum port port; |
1e78aa01 | 1293 | unsigned int bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format); |
4e646495 JN |
1294 | unsigned int lane_count = intel_dsi->lane_count; |
1295 | ||
1296 | u16 hactive, hfp, hsync, hbp, vfp, vsync, vbp; | |
1297 | ||
aad941d5 VS |
1298 | hactive = adjusted_mode->crtc_hdisplay; |
1299 | hfp = adjusted_mode->crtc_hsync_start - adjusted_mode->crtc_hdisplay; | |
1300 | hsync = adjusted_mode->crtc_hsync_end - adjusted_mode->crtc_hsync_start; | |
1301 | hbp = adjusted_mode->crtc_htotal - adjusted_mode->crtc_hsync_end; | |
4e646495 | 1302 | |
aa102d28 GS |
1303 | if (intel_dsi->dual_link) { |
1304 | hactive /= 2; | |
1305 | if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) | |
1306 | hactive += intel_dsi->pixel_overlap; | |
1307 | hfp /= 2; | |
1308 | hsync /= 2; | |
1309 | hbp /= 2; | |
1310 | } | |
1311 | ||
aad941d5 VS |
1312 | vfp = adjusted_mode->crtc_vsync_start - adjusted_mode->crtc_vdisplay; |
1313 | vsync = adjusted_mode->crtc_vsync_end - adjusted_mode->crtc_vsync_start; | |
1314 | vbp = adjusted_mode->crtc_vtotal - adjusted_mode->crtc_vsync_end; | |
4e646495 JN |
1315 | |
1316 | /* horizontal values are in terms of high speed byte clock */ | |
7f0c8605 | 1317 | hactive = txbyteclkhs(hactive, bpp, lane_count, |
7f3de833 | 1318 | intel_dsi->burst_mode_ratio); |
7f0c8605 SK |
1319 | hfp = txbyteclkhs(hfp, bpp, lane_count, intel_dsi->burst_mode_ratio); |
1320 | hsync = txbyteclkhs(hsync, bpp, lane_count, | |
7f3de833 | 1321 | intel_dsi->burst_mode_ratio); |
7f0c8605 | 1322 | hbp = txbyteclkhs(hbp, bpp, lane_count, intel_dsi->burst_mode_ratio); |
4e646495 | 1323 | |
aa102d28 | 1324 | for_each_dsi_port(port, intel_dsi->ports) { |
cc3f90f0 | 1325 | if (IS_GEN9_LP(dev_priv)) { |
d2e08c0f SS |
1326 | /* |
1327 | * Program hdisplay and vdisplay on MIPI transcoder. | |
1328 | * This is different from calculated hactive and | |
1329 | * vactive, as they are calculated per channel basis, | |
1330 | * whereas these values should be based on resolution. | |
1331 | */ | |
1332 | I915_WRITE(BXT_MIPI_TRANS_HACTIVE(port), | |
aad941d5 | 1333 | adjusted_mode->crtc_hdisplay); |
d2e08c0f | 1334 | I915_WRITE(BXT_MIPI_TRANS_VACTIVE(port), |
aad941d5 | 1335 | adjusted_mode->crtc_vdisplay); |
d2e08c0f | 1336 | I915_WRITE(BXT_MIPI_TRANS_VTOTAL(port), |
aad941d5 | 1337 | adjusted_mode->crtc_vtotal); |
d2e08c0f SS |
1338 | } |
1339 | ||
aa102d28 GS |
1340 | I915_WRITE(MIPI_HACTIVE_AREA_COUNT(port), hactive); |
1341 | I915_WRITE(MIPI_HFP_COUNT(port), hfp); | |
1342 | ||
1343 | /* meaningful for video mode non-burst sync pulse mode only, | |
1344 | * can be zero for non-burst sync events and burst modes */ | |
1345 | I915_WRITE(MIPI_HSYNC_PADDING_COUNT(port), hsync); | |
1346 | I915_WRITE(MIPI_HBP_COUNT(port), hbp); | |
1347 | ||
1348 | /* vertical values are in terms of lines */ | |
1349 | I915_WRITE(MIPI_VFP_COUNT(port), vfp); | |
1350 | I915_WRITE(MIPI_VSYNC_PADDING_COUNT(port), vsync); | |
1351 | I915_WRITE(MIPI_VBP_COUNT(port), vbp); | |
1352 | } | |
4e646495 JN |
1353 | } |
1354 | ||
1e78aa01 JN |
1355 | static u32 pixel_format_to_reg(enum mipi_dsi_pixel_format fmt) |
1356 | { | |
1357 | switch (fmt) { | |
1358 | case MIPI_DSI_FMT_RGB888: | |
1359 | return VID_MODE_FORMAT_RGB888; | |
1360 | case MIPI_DSI_FMT_RGB666: | |
1361 | return VID_MODE_FORMAT_RGB666; | |
1362 | case MIPI_DSI_FMT_RGB666_PACKED: | |
1363 | return VID_MODE_FORMAT_RGB666_PACKED; | |
1364 | case MIPI_DSI_FMT_RGB565: | |
1365 | return VID_MODE_FORMAT_RGB565; | |
1366 | default: | |
1367 | MISSING_CASE(fmt); | |
1368 | return VID_MODE_FORMAT_RGB666; | |
1369 | } | |
1370 | } | |
1371 | ||
5eff0edf | 1372 | static void intel_dsi_prepare(struct intel_encoder *intel_encoder, |
5f88a9c6 | 1373 | const struct intel_crtc_state *pipe_config) |
4e646495 JN |
1374 | { |
1375 | struct drm_encoder *encoder = &intel_encoder->base; | |
1376 | struct drm_device *dev = encoder->dev; | |
fac5e23e | 1377 | struct drm_i915_private *dev_priv = to_i915(dev); |
5eff0edf | 1378 | struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc); |
4e646495 | 1379 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); |
5eff0edf | 1380 | const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; |
24ee0e64 | 1381 | enum port port; |
1e78aa01 | 1382 | unsigned int bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format); |
4e646495 | 1383 | u32 val, tmp; |
24ee0e64 | 1384 | u16 mode_hdisplay; |
4e646495 | 1385 | |
e7d7cad0 | 1386 | DRM_DEBUG_KMS("pipe %c\n", pipe_name(intel_crtc->pipe)); |
4e646495 | 1387 | |
aad941d5 | 1388 | mode_hdisplay = adjusted_mode->crtc_hdisplay; |
4e646495 | 1389 | |
24ee0e64 GS |
1390 | if (intel_dsi->dual_link) { |
1391 | mode_hdisplay /= 2; | |
1392 | if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) | |
1393 | mode_hdisplay += intel_dsi->pixel_overlap; | |
1394 | } | |
4e646495 | 1395 | |
24ee0e64 | 1396 | for_each_dsi_port(port, intel_dsi->ports) { |
920a14b2 | 1397 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { |
d2e08c0f SS |
1398 | /* |
1399 | * escape clock divider, 20MHz, shared for A and C. | |
1400 | * device ready must be off when doing this! txclkesc? | |
1401 | */ | |
1402 | tmp = I915_READ(MIPI_CTRL(PORT_A)); | |
1403 | tmp &= ~ESCAPE_CLOCK_DIVIDER_MASK; | |
1404 | I915_WRITE(MIPI_CTRL(PORT_A), tmp | | |
1405 | ESCAPE_CLOCK_DIVIDER_1); | |
1406 | ||
1407 | /* read request priority is per pipe */ | |
1408 | tmp = I915_READ(MIPI_CTRL(port)); | |
1409 | tmp &= ~READ_REQUEST_PRIORITY_MASK; | |
1410 | I915_WRITE(MIPI_CTRL(port), tmp | | |
1411 | READ_REQUEST_PRIORITY_HIGH); | |
cc3f90f0 | 1412 | } else if (IS_GEN9_LP(dev_priv)) { |
56c48978 D |
1413 | enum pipe pipe = intel_crtc->pipe; |
1414 | ||
d2e08c0f SS |
1415 | tmp = I915_READ(MIPI_CTRL(port)); |
1416 | tmp &= ~BXT_PIPE_SELECT_MASK; | |
1417 | ||
56c48978 | 1418 | tmp |= BXT_PIPE_SELECT(pipe); |
d2e08c0f SS |
1419 | I915_WRITE(MIPI_CTRL(port), tmp); |
1420 | } | |
24ee0e64 GS |
1421 | |
1422 | /* XXX: why here, why like this? handling in irq handler?! */ | |
1423 | I915_WRITE(MIPI_INTR_STAT(port), 0xffffffff); | |
1424 | I915_WRITE(MIPI_INTR_EN(port), 0xffffffff); | |
1425 | ||
1426 | I915_WRITE(MIPI_DPHY_PARAM(port), intel_dsi->dphy_reg); | |
1427 | ||
1428 | I915_WRITE(MIPI_DPI_RESOLUTION(port), | |
aad941d5 | 1429 | adjusted_mode->crtc_vdisplay << VERTICAL_ADDRESS_SHIFT | |
24ee0e64 GS |
1430 | mode_hdisplay << HORIZONTAL_ADDRESS_SHIFT); |
1431 | } | |
4e646495 JN |
1432 | |
1433 | set_dsi_timings(encoder, adjusted_mode); | |
1434 | ||
1435 | val = intel_dsi->lane_count << DATA_LANES_PRG_REG_SHIFT; | |
1436 | if (is_cmd_mode(intel_dsi)) { | |
1437 | val |= intel_dsi->channel << CMD_MODE_CHANNEL_NUMBER_SHIFT; | |
1438 | val |= CMD_MODE_DATA_WIDTH_8_BIT; /* XXX */ | |
1439 | } else { | |
1440 | val |= intel_dsi->channel << VID_MODE_CHANNEL_NUMBER_SHIFT; | |
1e78aa01 | 1441 | val |= pixel_format_to_reg(intel_dsi->pixel_format); |
4e646495 | 1442 | } |
4e646495 | 1443 | |
24ee0e64 GS |
1444 | tmp = 0; |
1445 | if (intel_dsi->eotp_pkt == 0) | |
1446 | tmp |= EOT_DISABLE; | |
1447 | if (intel_dsi->clock_stop) | |
1448 | tmp |= CLOCKSTOP; | |
4e646495 | 1449 | |
cc3f90f0 | 1450 | if (IS_GEN9_LP(dev_priv)) { |
f90e8c36 JN |
1451 | tmp |= BXT_DPHY_DEFEATURE_EN; |
1452 | if (!is_cmd_mode(intel_dsi)) | |
1453 | tmp |= BXT_DEFEATURE_DPI_FIFO_CTR; | |
1454 | } | |
1455 | ||
24ee0e64 GS |
1456 | for_each_dsi_port(port, intel_dsi->ports) { |
1457 | I915_WRITE(MIPI_DSI_FUNC_PRG(port), val); | |
1458 | ||
1459 | /* timeouts for recovery. one frame IIUC. if counter expires, | |
1460 | * EOT and stop state. */ | |
1461 | ||
1462 | /* | |
1463 | * In burst mode, value greater than one DPI line Time in byte | |
1464 | * clock (txbyteclkhs) To timeout this timer 1+ of the above | |
1465 | * said value is recommended. | |
1466 | * | |
1467 | * In non-burst mode, Value greater than one DPI frame time in | |
1468 | * byte clock(txbyteclkhs) To timeout this timer 1+ of the above | |
1469 | * said value is recommended. | |
1470 | * | |
1471 | * In DBI only mode, value greater than one DBI frame time in | |
1472 | * byte clock(txbyteclkhs) To timeout this timer 1+ of the above | |
1473 | * said value is recommended. | |
1474 | */ | |
4e646495 | 1475 | |
24ee0e64 GS |
1476 | if (is_vid_mode(intel_dsi) && |
1477 | intel_dsi->video_mode_format == VIDEO_MODE_BURST) { | |
1478 | I915_WRITE(MIPI_HS_TX_TIMEOUT(port), | |
aad941d5 | 1479 | txbyteclkhs(adjusted_mode->crtc_htotal, bpp, |
124abe07 VS |
1480 | intel_dsi->lane_count, |
1481 | intel_dsi->burst_mode_ratio) + 1); | |
24ee0e64 GS |
1482 | } else { |
1483 | I915_WRITE(MIPI_HS_TX_TIMEOUT(port), | |
aad941d5 VS |
1484 | txbyteclkhs(adjusted_mode->crtc_vtotal * |
1485 | adjusted_mode->crtc_htotal, | |
124abe07 VS |
1486 | bpp, intel_dsi->lane_count, |
1487 | intel_dsi->burst_mode_ratio) + 1); | |
24ee0e64 GS |
1488 | } |
1489 | I915_WRITE(MIPI_LP_RX_TIMEOUT(port), intel_dsi->lp_rx_timeout); | |
1490 | I915_WRITE(MIPI_TURN_AROUND_TIMEOUT(port), | |
1491 | intel_dsi->turn_arnd_val); | |
1492 | I915_WRITE(MIPI_DEVICE_RESET_TIMER(port), | |
1493 | intel_dsi->rst_timer_val); | |
f1c79f16 | 1494 | |
24ee0e64 | 1495 | /* dphy stuff */ |
f1c79f16 | 1496 | |
24ee0e64 GS |
1497 | /* in terms of low power clock */ |
1498 | I915_WRITE(MIPI_INIT_COUNT(port), | |
1499 | txclkesc(intel_dsi->escape_clk_div, 100)); | |
4e646495 | 1500 | |
cc3f90f0 | 1501 | if (IS_GEN9_LP(dev_priv) && (!intel_dsi->dual_link)) { |
d2e08c0f SS |
1502 | /* |
1503 | * BXT spec says write MIPI_INIT_COUNT for | |
1504 | * both the ports, even if only one is | |
1505 | * getting used. So write the other port | |
1506 | * if not in dual link mode. | |
1507 | */ | |
1508 | I915_WRITE(MIPI_INIT_COUNT(port == | |
1509 | PORT_A ? PORT_C : PORT_A), | |
1510 | intel_dsi->init_count); | |
1511 | } | |
4e646495 | 1512 | |
24ee0e64 | 1513 | /* recovery disables */ |
87c54d0e | 1514 | I915_WRITE(MIPI_EOT_DISABLE(port), tmp); |
cf4dbd2e | 1515 | |
24ee0e64 GS |
1516 | /* in terms of low power clock */ |
1517 | I915_WRITE(MIPI_INIT_COUNT(port), intel_dsi->init_count); | |
4e646495 | 1518 | |
24ee0e64 GS |
1519 | /* in terms of txbyteclkhs. actual high to low switch + |
1520 | * MIPI_STOP_STATE_STALL * MIPI_LP_BYTECLK. | |
1521 | * | |
1522 | * XXX: write MIPI_STOP_STATE_STALL? | |
1523 | */ | |
1524 | I915_WRITE(MIPI_HIGH_LOW_SWITCH_COUNT(port), | |
1525 | intel_dsi->hs_to_lp_count); | |
1526 | ||
1527 | /* XXX: low power clock equivalence in terms of byte clock. | |
1528 | * the number of byte clocks occupied in one low power clock. | |
1529 | * based on txbyteclkhs and txclkesc. | |
1530 | * txclkesc time / txbyteclk time * (105 + MIPI_STOP_STATE_STALL | |
1531 | * ) / 105.??? | |
1532 | */ | |
1533 | I915_WRITE(MIPI_LP_BYTECLK(port), intel_dsi->lp_byte_clk); | |
1534 | ||
b426f985 D |
1535 | if (IS_GEMINILAKE(dev_priv)) { |
1536 | I915_WRITE(MIPI_TLPX_TIME_COUNT(port), | |
1537 | intel_dsi->lp_byte_clk); | |
1538 | /* Shadow of DPHY reg */ | |
1539 | I915_WRITE(MIPI_CLK_LANE_TIMING(port), | |
1540 | intel_dsi->dphy_reg); | |
1541 | } | |
1542 | ||
24ee0e64 GS |
1543 | /* the bw essential for transmitting 16 long packets containing |
1544 | * 252 bytes meant for dcs write memory command is programmed in | |
1545 | * this register in terms of byte clocks. based on dsi transfer | |
1546 | * rate and the number of lanes configured the time taken to | |
1547 | * transmit 16 long packets in a dsi stream varies. */ | |
1548 | I915_WRITE(MIPI_DBI_BW_CTRL(port), intel_dsi->bw_timer); | |
1549 | ||
1550 | I915_WRITE(MIPI_CLK_LANE_SWITCH_TIME_CNT(port), | |
1551 | intel_dsi->clk_lp_to_hs_count << LP_HS_SSW_CNT_SHIFT | | |
1552 | intel_dsi->clk_hs_to_lp_count << HS_LP_PWR_SW_CNT_SHIFT); | |
1553 | ||
1554 | if (is_vid_mode(intel_dsi)) | |
1555 | /* Some panels might have resolution which is not a | |
1556 | * multiple of 64 like 1366 x 768. Enable RANDOM | |
1557 | * resolution support for such panels by default */ | |
1558 | I915_WRITE(MIPI_VIDEO_MODE_FORMAT(port), | |
1559 | intel_dsi->video_frmt_cfg_bits | | |
1560 | intel_dsi->video_mode_format | | |
1561 | IP_TG_CONFIG | | |
1562 | RANDOM_DPI_DISPLAY_RESOLUTION); | |
1563 | } | |
4e646495 JN |
1564 | } |
1565 | ||
c7991eca HG |
1566 | static void intel_dsi_unprepare(struct intel_encoder *encoder) |
1567 | { | |
1568 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); | |
1569 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); | |
1570 | enum port port; | |
1571 | u32 val; | |
1572 | ||
46448483 D |
1573 | if (!IS_GEMINILAKE(dev_priv)) { |
1574 | for_each_dsi_port(port, intel_dsi->ports) { | |
1575 | /* Panel commands can be sent when clock is in LP11 */ | |
1576 | I915_WRITE(MIPI_DEVICE_READY(port), 0x0); | |
c7991eca | 1577 | |
46448483 D |
1578 | intel_dsi_reset_clocks(encoder, port); |
1579 | I915_WRITE(MIPI_EOT_DISABLE(port), CLOCKSTOP); | |
c7991eca | 1580 | |
46448483 D |
1581 | val = I915_READ(MIPI_DSI_FUNC_PRG(port)); |
1582 | val &= ~VID_MODE_FORMAT_MASK; | |
1583 | I915_WRITE(MIPI_DSI_FUNC_PRG(port), val); | |
c7991eca | 1584 | |
46448483 D |
1585 | I915_WRITE(MIPI_DEVICE_READY(port), 0x1); |
1586 | } | |
c7991eca HG |
1587 | } |
1588 | } | |
1589 | ||
4e646495 JN |
1590 | static int intel_dsi_get_modes(struct drm_connector *connector) |
1591 | { | |
1592 | struct intel_connector *intel_connector = to_intel_connector(connector); | |
1593 | struct drm_display_mode *mode; | |
1594 | ||
1595 | DRM_DEBUG_KMS("\n"); | |
1596 | ||
1597 | if (!intel_connector->panel.fixed_mode) { | |
1598 | DRM_DEBUG_KMS("no fixed mode\n"); | |
1599 | return 0; | |
1600 | } | |
1601 | ||
1602 | mode = drm_mode_duplicate(connector->dev, | |
1603 | intel_connector->panel.fixed_mode); | |
1604 | if (!mode) { | |
1605 | DRM_DEBUG_KMS("drm_mode_duplicate failed\n"); | |
1606 | return 0; | |
1607 | } | |
1608 | ||
1609 | drm_mode_probed_add(connector, mode); | |
1610 | return 1; | |
1611 | } | |
1612 | ||
593e0622 | 1613 | static void intel_dsi_connector_destroy(struct drm_connector *connector) |
4e646495 JN |
1614 | { |
1615 | struct intel_connector *intel_connector = to_intel_connector(connector); | |
1616 | ||
1617 | DRM_DEBUG_KMS("\n"); | |
1618 | intel_panel_fini(&intel_connector->panel); | |
4e646495 JN |
1619 | drm_connector_cleanup(connector); |
1620 | kfree(connector); | |
1621 | } | |
1622 | ||
593e0622 JN |
1623 | static void intel_dsi_encoder_destroy(struct drm_encoder *encoder) |
1624 | { | |
1625 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); | |
1626 | ||
fc45e821 SK |
1627 | /* dispose of the gpios */ |
1628 | if (intel_dsi->gpio_panel) | |
1629 | gpiod_put(intel_dsi->gpio_panel); | |
1630 | ||
593e0622 JN |
1631 | intel_encoder_destroy(encoder); |
1632 | } | |
1633 | ||
4e646495 | 1634 | static const struct drm_encoder_funcs intel_dsi_funcs = { |
593e0622 | 1635 | .destroy = intel_dsi_encoder_destroy, |
4e646495 JN |
1636 | }; |
1637 | ||
1638 | static const struct drm_connector_helper_funcs intel_dsi_connector_helper_funcs = { | |
1639 | .get_modes = intel_dsi_get_modes, | |
1640 | .mode_valid = intel_dsi_mode_valid, | |
ba14a1ad | 1641 | .atomic_check = intel_digital_connector_atomic_check, |
4e646495 JN |
1642 | }; |
1643 | ||
1644 | static const struct drm_connector_funcs intel_dsi_connector_funcs = { | |
1ebaa0b9 | 1645 | .late_register = intel_connector_register, |
c191eca1 | 1646 | .early_unregister = intel_connector_unregister, |
593e0622 | 1647 | .destroy = intel_dsi_connector_destroy, |
4e646495 | 1648 | .fill_modes = drm_helper_probe_single_connector_modes, |
ba14a1ad ML |
1649 | .atomic_get_property = intel_digital_connector_atomic_get_property, |
1650 | .atomic_set_property = intel_digital_connector_atomic_set_property, | |
c6f95f27 | 1651 | .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, |
ba14a1ad | 1652 | .atomic_duplicate_state = intel_digital_connector_duplicate_state, |
4e646495 JN |
1653 | }; |
1654 | ||
f4ee265f VS |
1655 | static void intel_dsi_add_properties(struct intel_connector *connector) |
1656 | { | |
8b45330a | 1657 | struct drm_i915_private *dev_priv = to_i915(connector->base.dev); |
f4ee265f VS |
1658 | |
1659 | if (connector->panel.fixed_mode) { | |
8b45330a ML |
1660 | u32 allowed_scalers; |
1661 | ||
1662 | allowed_scalers = BIT(DRM_MODE_SCALE_ASPECT) | BIT(DRM_MODE_SCALE_FULLSCREEN); | |
1663 | if (!HAS_GMCH_DISPLAY(dev_priv)) | |
1664 | allowed_scalers |= BIT(DRM_MODE_SCALE_CENTER); | |
1665 | ||
1666 | drm_connector_attach_scaling_mode_property(&connector->base, | |
1667 | allowed_scalers); | |
1668 | ||
eead06df | 1669 | connector->base.state->scaling_mode = DRM_MODE_SCALE_ASPECT; |
f4ee265f VS |
1670 | } |
1671 | } | |
1672 | ||
c39055b0 | 1673 | void intel_dsi_init(struct drm_i915_private *dev_priv) |
4e646495 | 1674 | { |
c39055b0 | 1675 | struct drm_device *dev = &dev_priv->drm; |
4e646495 JN |
1676 | struct intel_dsi *intel_dsi; |
1677 | struct intel_encoder *intel_encoder; | |
1678 | struct drm_encoder *encoder; | |
1679 | struct intel_connector *intel_connector; | |
1680 | struct drm_connector *connector; | |
593e0622 | 1681 | struct drm_display_mode *scan, *fixed_mode = NULL; |
7e9804fd | 1682 | enum port port; |
4e646495 JN |
1683 | |
1684 | DRM_DEBUG_KMS("\n"); | |
1685 | ||
3e6bd011 | 1686 | /* There is no detection method for MIPI so rely on VBT */ |
7137aec1 | 1687 | if (!intel_bios_is_dsi_present(dev_priv, &port)) |
4328633d | 1688 | return; |
3e6bd011 | 1689 | |
920a14b2 | 1690 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { |
868d665b | 1691 | dev_priv->mipi_mmio_base = VLV_MIPI_BASE; |
cc3f90f0 | 1692 | } else if (IS_GEN9_LP(dev_priv)) { |
c6c794a2 | 1693 | dev_priv->mipi_mmio_base = BXT_MIPI_BASE; |
868d665b CJ |
1694 | } else { |
1695 | DRM_ERROR("Unsupported Mipi device to reg base"); | |
1696 | return; | |
1697 | } | |
3e6bd011 | 1698 | |
4e646495 JN |
1699 | intel_dsi = kzalloc(sizeof(*intel_dsi), GFP_KERNEL); |
1700 | if (!intel_dsi) | |
4328633d | 1701 | return; |
4e646495 | 1702 | |
08d9bc92 | 1703 | intel_connector = intel_connector_alloc(); |
4e646495 JN |
1704 | if (!intel_connector) { |
1705 | kfree(intel_dsi); | |
4328633d | 1706 | return; |
4e646495 JN |
1707 | } |
1708 | ||
1709 | intel_encoder = &intel_dsi->base; | |
1710 | encoder = &intel_encoder->base; | |
1711 | intel_dsi->attached_connector = intel_connector; | |
1712 | ||
1713 | connector = &intel_connector->base; | |
1714 | ||
13a3d91f | 1715 | drm_encoder_init(dev, encoder, &intel_dsi_funcs, DRM_MODE_ENCODER_DSI, |
580d8ed5 | 1716 | "DSI %c", port_name(port)); |
4e646495 | 1717 | |
4e646495 | 1718 | intel_encoder->compute_config = intel_dsi_compute_config; |
4e646495 | 1719 | intel_encoder->pre_enable = intel_dsi_pre_enable; |
2634fd7f | 1720 | intel_encoder->enable = intel_dsi_enable_nop; |
fefc51e8 | 1721 | intel_encoder->disable = intel_dsi_disable; |
4e646495 JN |
1722 | intel_encoder->post_disable = intel_dsi_post_disable; |
1723 | intel_encoder->get_hw_state = intel_dsi_get_hw_state; | |
1724 | intel_encoder->get_config = intel_dsi_get_config; | |
1725 | ||
1726 | intel_connector->get_hw_state = intel_connector_get_hw_state; | |
1727 | ||
03cdc1d4 | 1728 | intel_encoder->port = port; |
79f255a0 | 1729 | |
2e85ab4f JN |
1730 | /* |
1731 | * On BYT/CHV, pipe A maps to MIPI DSI port A, pipe B maps to MIPI DSI | |
1732 | * port C. BXT isn't limited like this. | |
1733 | */ | |
cc3f90f0 | 1734 | if (IS_GEN9_LP(dev_priv)) |
2e85ab4f JN |
1735 | intel_encoder->crtc_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C); |
1736 | else if (port == PORT_A) | |
701d25b4 | 1737 | intel_encoder->crtc_mask = BIT(PIPE_A); |
7137aec1 | 1738 | else |
701d25b4 | 1739 | intel_encoder->crtc_mask = BIT(PIPE_B); |
e7d7cad0 | 1740 | |
90198355 | 1741 | if (dev_priv->vbt.dsi.config->dual_link) { |
701d25b4 | 1742 | intel_dsi->ports = BIT(PORT_A) | BIT(PORT_C); |
90198355 JN |
1743 | |
1744 | switch (dev_priv->vbt.dsi.config->dl_dcs_backlight_ports) { | |
1745 | case DL_DCS_PORT_A: | |
1746 | intel_dsi->dcs_backlight_ports = BIT(PORT_A); | |
1747 | break; | |
1748 | case DL_DCS_PORT_C: | |
1749 | intel_dsi->dcs_backlight_ports = BIT(PORT_C); | |
1750 | break; | |
1751 | default: | |
1752 | case DL_DCS_PORT_A_AND_C: | |
1753 | intel_dsi->dcs_backlight_ports = BIT(PORT_A) | BIT(PORT_C); | |
1754 | break; | |
1755 | } | |
1ecc1c6c D |
1756 | |
1757 | switch (dev_priv->vbt.dsi.config->dl_dcs_cabc_ports) { | |
1758 | case DL_DCS_PORT_A: | |
1759 | intel_dsi->dcs_cabc_ports = BIT(PORT_A); | |
1760 | break; | |
1761 | case DL_DCS_PORT_C: | |
1762 | intel_dsi->dcs_cabc_ports = BIT(PORT_C); | |
1763 | break; | |
1764 | default: | |
1765 | case DL_DCS_PORT_A_AND_C: | |
1766 | intel_dsi->dcs_cabc_ports = BIT(PORT_A) | BIT(PORT_C); | |
1767 | break; | |
1768 | } | |
90198355 | 1769 | } else { |
701d25b4 | 1770 | intel_dsi->ports = BIT(port); |
90198355 | 1771 | intel_dsi->dcs_backlight_ports = BIT(port); |
1ecc1c6c | 1772 | intel_dsi->dcs_cabc_ports = BIT(port); |
90198355 | 1773 | } |
82425785 | 1774 | |
1ecc1c6c D |
1775 | if (!dev_priv->vbt.dsi.config->cabc_supported) |
1776 | intel_dsi->dcs_cabc_ports = 0; | |
1777 | ||
7e9804fd JN |
1778 | /* Create a DSI host (and a device) for each port. */ |
1779 | for_each_dsi_port(port, intel_dsi->ports) { | |
1780 | struct intel_dsi_host *host; | |
1781 | ||
1782 | host = intel_dsi_host_init(intel_dsi, port); | |
1783 | if (!host) | |
1784 | goto err; | |
1785 | ||
1786 | intel_dsi->dsi_hosts[port] = host; | |
1787 | } | |
1788 | ||
3f751d65 | 1789 | if (!intel_dsi_vbt_init(intel_dsi, MIPI_DSI_GENERIC_PANEL_ID)) { |
4e646495 JN |
1790 | DRM_DEBUG_KMS("no device found\n"); |
1791 | goto err; | |
1792 | } | |
1793 | ||
fc45e821 SK |
1794 | /* |
1795 | * In case of BYT with CRC PMIC, we need to use GPIO for | |
1796 | * Panel control. | |
1797 | */ | |
645a2f6e US |
1798 | if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && |
1799 | (dev_priv->vbt.dsi.config->pwm_blc == PPS_BLC_PMIC)) { | |
fc45e821 SK |
1800 | intel_dsi->gpio_panel = |
1801 | gpiod_get(dev->dev, "panel", GPIOD_OUT_HIGH); | |
1802 | ||
1803 | if (IS_ERR(intel_dsi->gpio_panel)) { | |
1804 | DRM_ERROR("Failed to own gpio for panel control\n"); | |
1805 | intel_dsi->gpio_panel = NULL; | |
1806 | } | |
1807 | } | |
1808 | ||
4e646495 | 1809 | intel_encoder->type = INTEL_OUTPUT_DSI; |
79f255a0 | 1810 | intel_encoder->power_domain = POWER_DOMAIN_PORT_DSI; |
bc079e8b | 1811 | intel_encoder->cloneable = 0; |
4e646495 JN |
1812 | drm_connector_init(dev, connector, &intel_dsi_connector_funcs, |
1813 | DRM_MODE_CONNECTOR_DSI); | |
1814 | ||
1815 | drm_connector_helper_add(connector, &intel_dsi_connector_helper_funcs); | |
1816 | ||
1817 | connector->display_info.subpixel_order = SubPixelHorizontalRGB; /*XXX*/ | |
1818 | connector->interlace_allowed = false; | |
1819 | connector->doublescan_allowed = false; | |
1820 | ||
1821 | intel_connector_attach_encoder(intel_connector, intel_encoder); | |
1822 | ||
593e0622 | 1823 | mutex_lock(&dev->mode_config.mutex); |
3f751d65 | 1824 | intel_dsi_vbt_get_modes(intel_dsi); |
593e0622 JN |
1825 | list_for_each_entry(scan, &connector->probed_modes, head) { |
1826 | if ((scan->type & DRM_MODE_TYPE_PREFERRED)) { | |
1827 | fixed_mode = drm_mode_duplicate(dev, scan); | |
1828 | break; | |
1829 | } | |
1830 | } | |
1831 | mutex_unlock(&dev->mode_config.mutex); | |
1832 | ||
4e646495 JN |
1833 | if (!fixed_mode) { |
1834 | DRM_DEBUG_KMS("no fixed mode\n"); | |
1835 | goto err; | |
1836 | } | |
1837 | ||
df457245 VS |
1838 | connector->display_info.width_mm = fixed_mode->width_mm; |
1839 | connector->display_info.height_mm = fixed_mode->height_mm; | |
1840 | ||
dc911f5b | 1841 | intel_panel_init(&intel_connector->panel, fixed_mode, NULL, NULL); |
fda9ee98 | 1842 | intel_panel_setup_backlight(connector, INVALID_PIPE); |
f4ee265f VS |
1843 | |
1844 | intel_dsi_add_properties(intel_connector); | |
1845 | ||
4328633d | 1846 | return; |
4e646495 JN |
1847 | |
1848 | err: | |
1849 | drm_encoder_cleanup(&intel_encoder->base); | |
1850 | kfree(intel_dsi); | |
1851 | kfree(intel_connector); | |
4e646495 | 1852 | } |