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79e53945 JB |
1 | /* |
2 | * Copyright 2006 Dave Airlie <airlied@linux.ie> | |
3 | * Copyright © 2006-2007 Intel Corporation | |
4 | * | |
5 | * Permission is hereby granted, free of charge, to any person obtaining a | |
6 | * copy of this software and associated documentation files (the "Software"), | |
7 | * to deal in the Software without restriction, including without limitation | |
8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
9 | * and/or sell copies of the Software, and to permit persons to whom the | |
10 | * Software is furnished to do so, subject to the following conditions: | |
11 | * | |
12 | * The above copyright notice and this permission notice (including the next | |
13 | * paragraph) shall be included in all copies or substantial portions of the | |
14 | * Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
21 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
22 | * DEALINGS IN THE SOFTWARE. | |
23 | * | |
24 | * Authors: | |
25 | * Eric Anholt <eric@anholt.net> | |
26 | */ | |
27 | #include <linux/i2c.h> | |
5a0e3ad6 | 28 | #include <linux/slab.h> |
760285e7 | 29 | #include <drm/drmP.h> |
c6f95f27 | 30 | #include <drm/drm_atomic_helper.h> |
760285e7 | 31 | #include <drm/drm_crtc.h> |
79e53945 | 32 | #include "intel_drv.h" |
760285e7 | 33 | #include <drm/i915_drm.h> |
79e53945 JB |
34 | #include "i915_drv.h" |
35 | #include "dvo.h" | |
36 | ||
37 | #define SIL164_ADDR 0x38 | |
38 | #define CH7xxx_ADDR 0x76 | |
39 | #define TFP410_ADDR 0x38 | |
7434a255 | 40 | #define NS2501_ADDR 0x38 |
79e53945 | 41 | |
ea5b213a | 42 | static const struct intel_dvo_device intel_dvo_devices[] = { |
79e53945 JB |
43 | { |
44 | .type = INTEL_DVO_CHIP_TMDS, | |
45 | .name = "sil164", | |
46 | .dvo_reg = DVOC, | |
47 | .slave_addr = SIL164_ADDR, | |
48 | .dev_ops = &sil164_ops, | |
49 | }, | |
50 | { | |
51 | .type = INTEL_DVO_CHIP_TMDS, | |
52 | .name = "ch7xxx", | |
53 | .dvo_reg = DVOC, | |
54 | .slave_addr = CH7xxx_ADDR, | |
55 | .dev_ops = &ch7xxx_ops, | |
56 | }, | |
98304ad1 | 57 | { |
58 | .type = INTEL_DVO_CHIP_TMDS, | |
59 | .name = "ch7xxx", | |
60 | .dvo_reg = DVOC, | |
61 | .slave_addr = 0x75, /* For some ch7010 */ | |
62 | .dev_ops = &ch7xxx_ops, | |
63 | }, | |
79e53945 JB |
64 | { |
65 | .type = INTEL_DVO_CHIP_LVDS, | |
66 | .name = "ivch", | |
67 | .dvo_reg = DVOA, | |
68 | .slave_addr = 0x02, /* Might also be 0x44, 0x84, 0xc4 */ | |
69 | .dev_ops = &ivch_ops, | |
70 | }, | |
71 | { | |
72 | .type = INTEL_DVO_CHIP_TMDS, | |
73 | .name = "tfp410", | |
74 | .dvo_reg = DVOC, | |
75 | .slave_addr = TFP410_ADDR, | |
76 | .dev_ops = &tfp410_ops, | |
77 | }, | |
78 | { | |
79 | .type = INTEL_DVO_CHIP_LVDS, | |
80 | .name = "ch7017", | |
81 | .dvo_reg = DVOC, | |
82 | .slave_addr = 0x75, | |
a6b17b43 | 83 | .gpio = GMBUS_PORT_DPB, |
79e53945 | 84 | .dev_ops = &ch7017_ops, |
7434a255 TR |
85 | }, |
86 | { | |
87 | .type = INTEL_DVO_CHIP_TMDS, | |
88 | .name = "ns2501", | |
316e0157 | 89 | .dvo_reg = DVOB, |
7434a255 TR |
90 | .slave_addr = NS2501_ADDR, |
91 | .dev_ops = &ns2501_ops, | |
92 | } | |
79e53945 JB |
93 | }; |
94 | ||
ea5b213a CW |
95 | struct intel_dvo { |
96 | struct intel_encoder base; | |
97 | ||
98 | struct intel_dvo_device dev; | |
99 | ||
100 | struct drm_display_mode *panel_fixed_mode; | |
101 | bool panel_wants_dither; | |
102 | }; | |
103 | ||
69438e64 | 104 | static struct intel_dvo *enc_to_dvo(struct intel_encoder *encoder) |
ea5b213a | 105 | { |
69438e64 | 106 | return container_of(encoder, struct intel_dvo, base); |
ea5b213a CW |
107 | } |
108 | ||
df0e9248 CW |
109 | static struct intel_dvo *intel_attached_dvo(struct drm_connector *connector) |
110 | { | |
79fde301 | 111 | return enc_to_dvo(intel_attached_encoder(connector)); |
df0e9248 CW |
112 | } |
113 | ||
732ce74f | 114 | static bool intel_dvo_connector_get_hw_state(struct intel_connector *connector) |
79e53945 | 115 | { |
f417c11b VS |
116 | struct drm_device *dev = connector->base.dev; |
117 | struct drm_i915_private *dev_priv = dev->dev_private; | |
732ce74f | 118 | struct intel_dvo *intel_dvo = intel_attached_dvo(&connector->base); |
f417c11b VS |
119 | u32 tmp; |
120 | ||
121 | tmp = I915_READ(intel_dvo->dev.dvo_reg); | |
122 | ||
123 | if (!(tmp & DVO_ENABLE)) | |
124 | return false; | |
732ce74f DV |
125 | |
126 | return intel_dvo->dev.dev_ops->get_hw_state(&intel_dvo->dev); | |
127 | } | |
128 | ||
129 | static bool intel_dvo_get_hw_state(struct intel_encoder *encoder, | |
130 | enum pipe *pipe) | |
131 | { | |
132 | struct drm_device *dev = encoder->base.dev; | |
133 | struct drm_i915_private *dev_priv = dev->dev_private; | |
69438e64 | 134 | struct intel_dvo *intel_dvo = enc_to_dvo(encoder); |
732ce74f DV |
135 | u32 tmp; |
136 | ||
137 | tmp = I915_READ(intel_dvo->dev.dvo_reg); | |
138 | ||
139 | if (!(tmp & DVO_ENABLE)) | |
140 | return false; | |
141 | ||
142 | *pipe = PORT_TO_PIPE(tmp); | |
143 | ||
144 | return true; | |
145 | } | |
146 | ||
045ac3b5 | 147 | static void intel_dvo_get_config(struct intel_encoder *encoder, |
5cec258b | 148 | struct intel_crtc_state *pipe_config) |
045ac3b5 JB |
149 | { |
150 | struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; | |
69438e64 | 151 | struct intel_dvo *intel_dvo = enc_to_dvo(encoder); |
045ac3b5 JB |
152 | u32 tmp, flags = 0; |
153 | ||
154 | tmp = I915_READ(intel_dvo->dev.dvo_reg); | |
155 | if (tmp & DVO_HSYNC_ACTIVE_HIGH) | |
156 | flags |= DRM_MODE_FLAG_PHSYNC; | |
157 | else | |
158 | flags |= DRM_MODE_FLAG_NHSYNC; | |
159 | if (tmp & DVO_VSYNC_ACTIVE_HIGH) | |
160 | flags |= DRM_MODE_FLAG_PVSYNC; | |
161 | else | |
162 | flags |= DRM_MODE_FLAG_NVSYNC; | |
163 | ||
2d112de7 | 164 | pipe_config->base.adjusted_mode.flags |= flags; |
18442d08 | 165 | |
2d112de7 | 166 | pipe_config->base.adjusted_mode.crtc_clock = pipe_config->port_clock; |
045ac3b5 JB |
167 | } |
168 | ||
19c63fa8 DV |
169 | static void intel_disable_dvo(struct intel_encoder *encoder) |
170 | { | |
171 | struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; | |
69438e64 | 172 | struct intel_dvo *intel_dvo = enc_to_dvo(encoder); |
19c63fa8 DV |
173 | u32 dvo_reg = intel_dvo->dev.dvo_reg; |
174 | u32 temp = I915_READ(dvo_reg); | |
175 | ||
176 | intel_dvo->dev.dev_ops->dpms(&intel_dvo->dev, false); | |
177 | I915_WRITE(dvo_reg, temp & ~DVO_ENABLE); | |
178 | I915_READ(dvo_reg); | |
179 | } | |
180 | ||
181 | static void intel_enable_dvo(struct intel_encoder *encoder) | |
182 | { | |
183 | struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; | |
69438e64 | 184 | struct intel_dvo *intel_dvo = enc_to_dvo(encoder); |
48f34e10 | 185 | struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); |
ea5b213a | 186 | u32 dvo_reg = intel_dvo->dev.dvo_reg; |
79e53945 JB |
187 | u32 temp = I915_READ(dvo_reg); |
188 | ||
48f34e10 | 189 | intel_dvo->dev.dev_ops->mode_set(&intel_dvo->dev, |
6e3c9717 ACO |
190 | &crtc->config->base.mode, |
191 | &crtc->config->base.adjusted_mode); | |
48f34e10 | 192 | |
c9c054c2 VS |
193 | I915_WRITE(dvo_reg, temp | DVO_ENABLE); |
194 | I915_READ(dvo_reg); | |
195 | ||
19c63fa8 DV |
196 | intel_dvo->dev.dev_ops->dpms(&intel_dvo->dev, true); |
197 | } | |
198 | ||
6b1c087b | 199 | /* Special dpms function to support cloning between dvo/sdvo/crt. */ |
b2cabb0e | 200 | static void intel_dvo_dpms(struct drm_connector *connector, int mode) |
79e53945 | 201 | { |
b2cabb0e DV |
202 | struct intel_dvo *intel_dvo = intel_attached_dvo(connector); |
203 | struct drm_crtc *crtc; | |
5cec258b | 204 | struct intel_crtc_state *config; |
b2cabb0e DV |
205 | |
206 | /* dvo supports only 2 dpms states. */ | |
207 | if (mode != DRM_MODE_DPMS_ON) | |
208 | mode = DRM_MODE_DPMS_OFF; | |
209 | ||
210 | if (mode == connector->dpms) | |
211 | return; | |
212 | ||
213 | connector->dpms = mode; | |
214 | ||
215 | /* Only need to change hw state when actually enabled */ | |
216 | crtc = intel_dvo->base.base.crtc; | |
217 | if (!crtc) { | |
218 | intel_dvo->base.connectors_active = false; | |
219 | return; | |
220 | } | |
79e53945 | 221 | |
6b1c087b JN |
222 | /* We call connector dpms manually below in case pipe dpms doesn't |
223 | * change due to cloning. */ | |
79e53945 | 224 | if (mode == DRM_MODE_DPMS_ON) { |
6e3c9717 | 225 | config = to_intel_crtc(crtc)->config; |
48f34e10 | 226 | |
b2cabb0e DV |
227 | intel_dvo->base.connectors_active = true; |
228 | ||
229 | intel_crtc_update_dpms(crtc); | |
230 | ||
fac3274c | 231 | intel_dvo->dev.dev_ops->dpms(&intel_dvo->dev, true); |
79e53945 | 232 | } else { |
fac3274c | 233 | intel_dvo->dev.dev_ops->dpms(&intel_dvo->dev, false); |
b2cabb0e DV |
234 | |
235 | intel_dvo->base.connectors_active = false; | |
236 | ||
237 | intel_crtc_update_dpms(crtc); | |
79e53945 | 238 | } |
0a91ca29 | 239 | |
b980514c | 240 | intel_modeset_check_state(connector->dev); |
79e53945 JB |
241 | } |
242 | ||
c19de8eb DL |
243 | static enum drm_mode_status |
244 | intel_dvo_mode_valid(struct drm_connector *connector, | |
245 | struct drm_display_mode *mode) | |
79e53945 | 246 | { |
df0e9248 | 247 | struct intel_dvo *intel_dvo = intel_attached_dvo(connector); |
79e53945 JB |
248 | |
249 | if (mode->flags & DRM_MODE_FLAG_DBLSCAN) | |
250 | return MODE_NO_DBLESCAN; | |
251 | ||
252 | /* XXX: Validate clock range */ | |
253 | ||
ea5b213a CW |
254 | if (intel_dvo->panel_fixed_mode) { |
255 | if (mode->hdisplay > intel_dvo->panel_fixed_mode->hdisplay) | |
79e53945 | 256 | return MODE_PANEL; |
ea5b213a | 257 | if (mode->vdisplay > intel_dvo->panel_fixed_mode->vdisplay) |
79e53945 JB |
258 | return MODE_PANEL; |
259 | } | |
260 | ||
ea5b213a | 261 | return intel_dvo->dev.dev_ops->mode_valid(&intel_dvo->dev, mode); |
79e53945 JB |
262 | } |
263 | ||
a3470375 | 264 | static bool intel_dvo_compute_config(struct intel_encoder *encoder, |
5cec258b | 265 | struct intel_crtc_state *pipe_config) |
79e53945 | 266 | { |
a3470375 | 267 | struct intel_dvo *intel_dvo = enc_to_dvo(encoder); |
2d112de7 | 268 | struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; |
79e53945 JB |
269 | |
270 | /* If we have timings from the BIOS for the panel, put them in | |
271 | * to the adjusted mode. The CRTC will be set up for this mode, | |
272 | * with the panel scaling set up to source from the H/VDisplay | |
273 | * of the original mode. | |
274 | */ | |
ea5b213a CW |
275 | if (intel_dvo->panel_fixed_mode != NULL) { |
276 | #define C(x) adjusted_mode->x = intel_dvo->panel_fixed_mode->x | |
79e53945 JB |
277 | C(hdisplay); |
278 | C(hsync_start); | |
279 | C(hsync_end); | |
280 | C(htotal); | |
281 | C(vdisplay); | |
282 | C(vsync_start); | |
283 | C(vsync_end); | |
284 | C(vtotal); | |
285 | C(clock); | |
79e53945 | 286 | #undef C |
0d971748 DV |
287 | |
288 | drm_mode_set_crtcinfo(adjusted_mode, 0); | |
79e53945 JB |
289 | } |
290 | ||
79e53945 JB |
291 | return true; |
292 | } | |
293 | ||
912b0e2d | 294 | static void intel_dvo_pre_enable(struct intel_encoder *encoder) |
79e53945 | 295 | { |
79fde301 | 296 | struct drm_device *dev = encoder->base.dev; |
79e53945 | 297 | struct drm_i915_private *dev_priv = dev->dev_private; |
79fde301 | 298 | struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); |
6e3c9717 | 299 | struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode; |
79fde301 DV |
300 | struct intel_dvo *intel_dvo = enc_to_dvo(encoder); |
301 | int pipe = crtc->pipe; | |
79e53945 | 302 | u32 dvo_val; |
ea5b213a | 303 | u32 dvo_reg = intel_dvo->dev.dvo_reg, dvo_srcdim_reg; |
79e53945 JB |
304 | |
305 | switch (dvo_reg) { | |
306 | case DVOA: | |
307 | default: | |
308 | dvo_srcdim_reg = DVOA_SRCDIM; | |
309 | break; | |
310 | case DVOB: | |
311 | dvo_srcdim_reg = DVOB_SRCDIM; | |
312 | break; | |
313 | case DVOC: | |
314 | dvo_srcdim_reg = DVOC_SRCDIM; | |
315 | break; | |
316 | } | |
317 | ||
79e53945 JB |
318 | /* Save the data order, since I don't know what it should be set to. */ |
319 | dvo_val = I915_READ(dvo_reg) & | |
320 | (DVO_PRESERVE_MASK | DVO_DATA_ORDER_GBRG); | |
321 | dvo_val |= DVO_DATA_ORDER_FP | DVO_BORDER_ENABLE | | |
322 | DVO_BLANK_ACTIVE_HIGH; | |
323 | ||
324 | if (pipe == 1) | |
325 | dvo_val |= DVO_PIPE_B_SELECT; | |
326 | dvo_val |= DVO_PIPE_STALL; | |
327 | if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) | |
328 | dvo_val |= DVO_HSYNC_ACTIVE_HIGH; | |
329 | if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) | |
330 | dvo_val |= DVO_VSYNC_ACTIVE_HIGH; | |
331 | ||
79e53945 JB |
332 | /*I915_WRITE(DVOB_SRCDIM, |
333 | (adjusted_mode->hdisplay << DVO_SRCDIM_HORIZONTAL_SHIFT) | | |
334 | (adjusted_mode->VDisplay << DVO_SRCDIM_VERTICAL_SHIFT));*/ | |
335 | I915_WRITE(dvo_srcdim_reg, | |
336 | (adjusted_mode->hdisplay << DVO_SRCDIM_HORIZONTAL_SHIFT) | | |
337 | (adjusted_mode->vdisplay << DVO_SRCDIM_VERTICAL_SHIFT)); | |
338 | /*I915_WRITE(DVOB, dvo_val);*/ | |
339 | I915_WRITE(dvo_reg, dvo_val); | |
340 | } | |
341 | ||
342 | /** | |
343 | * Detect the output connection on our DVO device. | |
344 | * | |
345 | * Unimplemented. | |
346 | */ | |
7b334fcb | 347 | static enum drm_connector_status |
930a9e28 | 348 | intel_dvo_detect(struct drm_connector *connector, bool force) |
79e53945 | 349 | { |
df0e9248 | 350 | struct intel_dvo *intel_dvo = intel_attached_dvo(connector); |
164c8598 | 351 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", |
c23cc417 | 352 | connector->base.id, connector->name); |
ea5b213a | 353 | return intel_dvo->dev.dev_ops->detect(&intel_dvo->dev); |
79e53945 JB |
354 | } |
355 | ||
356 | static int intel_dvo_get_modes(struct drm_connector *connector) | |
357 | { | |
df0e9248 | 358 | struct intel_dvo *intel_dvo = intel_attached_dvo(connector); |
f899fc64 | 359 | struct drm_i915_private *dev_priv = connector->dev->dev_private; |
79e53945 JB |
360 | |
361 | /* We should probably have an i2c driver get_modes function for those | |
362 | * devices which will have a fixed set of modes determined by the chip | |
363 | * (TV-out, for example), but for now with just TMDS and LVDS, | |
364 | * that's not the case. | |
365 | */ | |
f899fc64 | 366 | intel_ddc_get_modes(connector, |
3bd7d909 | 367 | intel_gmbus_get_adapter(dev_priv, GMBUS_PORT_DPC)); |
79e53945 JB |
368 | if (!list_empty(&connector->probed_modes)) |
369 | return 1; | |
370 | ||
ea5b213a | 371 | if (intel_dvo->panel_fixed_mode != NULL) { |
79e53945 | 372 | struct drm_display_mode *mode; |
ea5b213a | 373 | mode = drm_mode_duplicate(connector->dev, intel_dvo->panel_fixed_mode); |
79e53945 JB |
374 | if (mode) { |
375 | drm_mode_probed_add(connector, mode); | |
376 | return 1; | |
377 | } | |
378 | } | |
ea5b213a | 379 | |
79e53945 JB |
380 | return 0; |
381 | } | |
382 | ||
ea5b213a | 383 | static void intel_dvo_destroy(struct drm_connector *connector) |
79e53945 | 384 | { |
79e53945 | 385 | drm_connector_cleanup(connector); |
599be16c | 386 | kfree(connector); |
79e53945 | 387 | } |
79e53945 | 388 | |
79e53945 | 389 | static const struct drm_connector_funcs intel_dvo_connector_funcs = { |
b2cabb0e | 390 | .dpms = intel_dvo_dpms, |
79e53945 JB |
391 | .detect = intel_dvo_detect, |
392 | .destroy = intel_dvo_destroy, | |
393 | .fill_modes = drm_helper_probe_single_connector_modes, | |
c6f95f27 | 394 | .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, |
79e53945 JB |
395 | }; |
396 | ||
397 | static const struct drm_connector_helper_funcs intel_dvo_connector_helper_funcs = { | |
398 | .mode_valid = intel_dvo_mode_valid, | |
399 | .get_modes = intel_dvo_get_modes, | |
df0e9248 | 400 | .best_encoder = intel_best_encoder, |
79e53945 JB |
401 | }; |
402 | ||
b358d0a6 | 403 | static void intel_dvo_enc_destroy(struct drm_encoder *encoder) |
79e53945 | 404 | { |
69438e64 | 405 | struct intel_dvo *intel_dvo = enc_to_dvo(to_intel_encoder(encoder)); |
ea5b213a CW |
406 | |
407 | if (intel_dvo->dev.dev_ops->destroy) | |
408 | intel_dvo->dev.dev_ops->destroy(&intel_dvo->dev); | |
409 | ||
410 | kfree(intel_dvo->panel_fixed_mode); | |
411 | ||
412 | intel_encoder_destroy(encoder); | |
79e53945 JB |
413 | } |
414 | ||
415 | static const struct drm_encoder_funcs intel_dvo_enc_funcs = { | |
416 | .destroy = intel_dvo_enc_destroy, | |
417 | }; | |
418 | ||
79e53945 JB |
419 | /** |
420 | * Attempts to get a fixed panel timing for LVDS (currently only the i830). | |
421 | * | |
422 | * Other chips with DVO LVDS will need to extend this to deal with the LVDS | |
423 | * chip being on DVOB/C and having multiple pipes. | |
424 | */ | |
425 | static struct drm_display_mode * | |
ea5b213a | 426 | intel_dvo_get_current_mode(struct drm_connector *connector) |
79e53945 JB |
427 | { |
428 | struct drm_device *dev = connector->dev; | |
429 | struct drm_i915_private *dev_priv = dev->dev_private; | |
df0e9248 | 430 | struct intel_dvo *intel_dvo = intel_attached_dvo(connector); |
ea5b213a | 431 | uint32_t dvo_val = I915_READ(intel_dvo->dev.dvo_reg); |
79e53945 JB |
432 | struct drm_display_mode *mode = NULL; |
433 | ||
434 | /* If the DVO port is active, that'll be the LVDS, so we can pull out | |
435 | * its timings to get how the BIOS set up the panel. | |
436 | */ | |
437 | if (dvo_val & DVO_ENABLE) { | |
438 | struct drm_crtc *crtc; | |
439 | int pipe = (dvo_val & DVO_PIPE_B_SELECT) ? 1 : 0; | |
440 | ||
f875c15a | 441 | crtc = intel_get_crtc_for_pipe(dev, pipe); |
79e53945 JB |
442 | if (crtc) { |
443 | mode = intel_crtc_mode_get(dev, crtc); | |
79e53945 JB |
444 | if (mode) { |
445 | mode->type |= DRM_MODE_TYPE_PREFERRED; | |
446 | if (dvo_val & DVO_HSYNC_ACTIVE_HIGH) | |
447 | mode->flags |= DRM_MODE_FLAG_PHSYNC; | |
448 | if (dvo_val & DVO_VSYNC_ACTIVE_HIGH) | |
449 | mode->flags |= DRM_MODE_FLAG_PVSYNC; | |
450 | } | |
451 | } | |
452 | } | |
ea5b213a | 453 | |
79e53945 JB |
454 | return mode; |
455 | } | |
456 | ||
457 | void intel_dvo_init(struct drm_device *dev) | |
458 | { | |
f899fc64 | 459 | struct drm_i915_private *dev_priv = dev->dev_private; |
21d40d37 | 460 | struct intel_encoder *intel_encoder; |
ea5b213a | 461 | struct intel_dvo *intel_dvo; |
599be16c | 462 | struct intel_connector *intel_connector; |
79e53945 | 463 | int i; |
79e53945 | 464 | int encoder_type = DRM_MODE_ENCODER_NONE; |
ea5b213a | 465 | |
b14c5679 | 466 | intel_dvo = kzalloc(sizeof(*intel_dvo), GFP_KERNEL); |
ea5b213a | 467 | if (!intel_dvo) |
79e53945 JB |
468 | return; |
469 | ||
b14c5679 | 470 | intel_connector = kzalloc(sizeof(*intel_connector), GFP_KERNEL); |
599be16c | 471 | if (!intel_connector) { |
ea5b213a | 472 | kfree(intel_dvo); |
599be16c ZW |
473 | return; |
474 | } | |
475 | ||
ea5b213a | 476 | intel_encoder = &intel_dvo->base; |
373a3cf7 CW |
477 | drm_encoder_init(dev, &intel_encoder->base, |
478 | &intel_dvo_enc_funcs, encoder_type); | |
ea5b213a | 479 | |
19c63fa8 DV |
480 | intel_encoder->disable = intel_disable_dvo; |
481 | intel_encoder->enable = intel_enable_dvo; | |
732ce74f | 482 | intel_encoder->get_hw_state = intel_dvo_get_hw_state; |
045ac3b5 | 483 | intel_encoder->get_config = intel_dvo_get_config; |
a3470375 | 484 | intel_encoder->compute_config = intel_dvo_compute_config; |
912b0e2d | 485 | intel_encoder->pre_enable = intel_dvo_pre_enable; |
732ce74f | 486 | intel_connector->get_hw_state = intel_dvo_connector_get_hw_state; |
4932e2c3 | 487 | intel_connector->unregister = intel_connector_unregister; |
19c63fa8 | 488 | |
79e53945 JB |
489 | /* Now, try to find a controller */ |
490 | for (i = 0; i < ARRAY_SIZE(intel_dvo_devices); i++) { | |
599be16c | 491 | struct drm_connector *connector = &intel_connector->base; |
ea5b213a | 492 | const struct intel_dvo_device *dvo = &intel_dvo_devices[i]; |
f899fc64 | 493 | struct i2c_adapter *i2c; |
79e53945 | 494 | int gpio; |
e4bfff54 | 495 | bool dvoinit; |
79e53945 | 496 | |
79e53945 JB |
497 | /* Allow the I2C driver info to specify the GPIO to be used in |
498 | * special cases, but otherwise default to what's defined | |
499 | * in the spec. | |
500 | */ | |
3bd7d909 | 501 | if (intel_gmbus_is_port_valid(dvo->gpio)) |
79e53945 JB |
502 | gpio = dvo->gpio; |
503 | else if (dvo->type == INTEL_DVO_CHIP_LVDS) | |
f573c660 | 504 | gpio = GMBUS_PORT_SSC; |
79e53945 | 505 | else |
a6b17b43 | 506 | gpio = GMBUS_PORT_DPB; |
79e53945 JB |
507 | |
508 | /* Set up the I2C bus necessary for the chip we're probing. | |
509 | * It appears that everything is on GPIOE except for panels | |
510 | * on i830 laptops, which are on GPIOB (DVOA). | |
511 | */ | |
3bd7d909 | 512 | i2c = intel_gmbus_get_adapter(dev_priv, gpio); |
79e53945 | 513 | |
ea5b213a | 514 | intel_dvo->dev = *dvo; |
e4bfff54 DMEA |
515 | |
516 | /* GMBUS NAK handling seems to be unstable, hence let the | |
517 | * transmitter detection run in bit banging mode for now. | |
518 | */ | |
519 | intel_gmbus_force_bit(i2c, true); | |
520 | ||
521 | dvoinit = dvo->dev_ops->init(&intel_dvo->dev, i2c); | |
522 | ||
523 | intel_gmbus_force_bit(i2c, false); | |
524 | ||
525 | if (!dvoinit) | |
79e53945 JB |
526 | continue; |
527 | ||
21d40d37 EA |
528 | intel_encoder->type = INTEL_OUTPUT_DVO; |
529 | intel_encoder->crtc_mask = (1 << 0) | (1 << 1); | |
79e53945 JB |
530 | switch (dvo->type) { |
531 | case INTEL_DVO_CHIP_TMDS: | |
bc079e8b VS |
532 | intel_encoder->cloneable = (1 << INTEL_OUTPUT_ANALOG) | |
533 | (1 << INTEL_OUTPUT_DVO); | |
79e53945 JB |
534 | drm_connector_init(dev, connector, |
535 | &intel_dvo_connector_funcs, | |
536 | DRM_MODE_CONNECTOR_DVII); | |
537 | encoder_type = DRM_MODE_ENCODER_TMDS; | |
538 | break; | |
539 | case INTEL_DVO_CHIP_LVDS: | |
bc079e8b | 540 | intel_encoder->cloneable = 0; |
79e53945 JB |
541 | drm_connector_init(dev, connector, |
542 | &intel_dvo_connector_funcs, | |
543 | DRM_MODE_CONNECTOR_LVDS); | |
544 | encoder_type = DRM_MODE_ENCODER_LVDS; | |
545 | break; | |
546 | } | |
547 | ||
548 | drm_connector_helper_add(connector, | |
549 | &intel_dvo_connector_helper_funcs); | |
550 | connector->display_info.subpixel_order = SubPixelHorizontalRGB; | |
551 | connector->interlace_allowed = false; | |
552 | connector->doublescan_allowed = false; | |
553 | ||
df0e9248 | 554 | intel_connector_attach_encoder(intel_connector, intel_encoder); |
79e53945 JB |
555 | if (dvo->type == INTEL_DVO_CHIP_LVDS) { |
556 | /* For our LVDS chipsets, we should hopefully be able | |
557 | * to dig the fixed panel mode out of the BIOS data. | |
558 | * However, it's in a different format from the BIOS | |
559 | * data on chipsets with integrated LVDS (stored in AIM | |
560 | * headers, likely), so for now, just get the current | |
561 | * mode being output through DVO. | |
562 | */ | |
ea5b213a | 563 | intel_dvo->panel_fixed_mode = |
79e53945 | 564 | intel_dvo_get_current_mode(connector); |
ea5b213a | 565 | intel_dvo->panel_wants_dither = true; |
79e53945 JB |
566 | } |
567 | ||
34ea3d38 | 568 | drm_connector_register(connector); |
79e53945 JB |
569 | return; |
570 | } | |
571 | ||
373a3cf7 | 572 | drm_encoder_cleanup(&intel_encoder->base); |
ea5b213a | 573 | kfree(intel_dvo); |
599be16c | 574 | kfree(intel_connector); |
79e53945 | 575 | } |