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79e53945 JB |
1 | /* |
2 | * Copyright 2006 Dave Airlie <airlied@linux.ie> | |
3 | * Copyright © 2006-2007 Intel Corporation | |
4 | * | |
5 | * Permission is hereby granted, free of charge, to any person obtaining a | |
6 | * copy of this software and associated documentation files (the "Software"), | |
7 | * to deal in the Software without restriction, including without limitation | |
8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
9 | * and/or sell copies of the Software, and to permit persons to whom the | |
10 | * Software is furnished to do so, subject to the following conditions: | |
11 | * | |
12 | * The above copyright notice and this permission notice (including the next | |
13 | * paragraph) shall be included in all copies or substantial portions of the | |
14 | * Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
21 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
22 | * DEALINGS IN THE SOFTWARE. | |
23 | * | |
24 | * Authors: | |
25 | * Eric Anholt <eric@anholt.net> | |
26 | */ | |
27 | #include <linux/i2c.h> | |
5a0e3ad6 | 28 | #include <linux/slab.h> |
760285e7 | 29 | #include <drm/drmP.h> |
c6f95f27 | 30 | #include <drm/drm_atomic_helper.h> |
760285e7 | 31 | #include <drm/drm_crtc.h> |
79e53945 | 32 | #include "intel_drv.h" |
760285e7 | 33 | #include <drm/i915_drm.h> |
79e53945 JB |
34 | #include "i915_drv.h" |
35 | #include "dvo.h" | |
36 | ||
37 | #define SIL164_ADDR 0x38 | |
38 | #define CH7xxx_ADDR 0x76 | |
39 | #define TFP410_ADDR 0x38 | |
7434a255 | 40 | #define NS2501_ADDR 0x38 |
79e53945 | 41 | |
ea5b213a | 42 | static const struct intel_dvo_device intel_dvo_devices[] = { |
79e53945 JB |
43 | { |
44 | .type = INTEL_DVO_CHIP_TMDS, | |
45 | .name = "sil164", | |
46 | .dvo_reg = DVOC, | |
78e0d2e3 | 47 | .dvo_srcdim_reg = DVOC_SRCDIM, |
79e53945 JB |
48 | .slave_addr = SIL164_ADDR, |
49 | .dev_ops = &sil164_ops, | |
50 | }, | |
51 | { | |
52 | .type = INTEL_DVO_CHIP_TMDS, | |
53 | .name = "ch7xxx", | |
54 | .dvo_reg = DVOC, | |
78e0d2e3 | 55 | .dvo_srcdim_reg = DVOC_SRCDIM, |
79e53945 JB |
56 | .slave_addr = CH7xxx_ADDR, |
57 | .dev_ops = &ch7xxx_ops, | |
58 | }, | |
98304ad1 | 59 | { |
60 | .type = INTEL_DVO_CHIP_TMDS, | |
61 | .name = "ch7xxx", | |
62 | .dvo_reg = DVOC, | |
78e0d2e3 | 63 | .dvo_srcdim_reg = DVOC_SRCDIM, |
98304ad1 | 64 | .slave_addr = 0x75, /* For some ch7010 */ |
65 | .dev_ops = &ch7xxx_ops, | |
66 | }, | |
79e53945 JB |
67 | { |
68 | .type = INTEL_DVO_CHIP_LVDS, | |
69 | .name = "ivch", | |
70 | .dvo_reg = DVOA, | |
78e0d2e3 | 71 | .dvo_srcdim_reg = DVOA_SRCDIM, |
79e53945 JB |
72 | .slave_addr = 0x02, /* Might also be 0x44, 0x84, 0xc4 */ |
73 | .dev_ops = &ivch_ops, | |
74 | }, | |
75 | { | |
76 | .type = INTEL_DVO_CHIP_TMDS, | |
77 | .name = "tfp410", | |
78 | .dvo_reg = DVOC, | |
78e0d2e3 | 79 | .dvo_srcdim_reg = DVOC_SRCDIM, |
79e53945 JB |
80 | .slave_addr = TFP410_ADDR, |
81 | .dev_ops = &tfp410_ops, | |
82 | }, | |
83 | { | |
84 | .type = INTEL_DVO_CHIP_LVDS, | |
85 | .name = "ch7017", | |
86 | .dvo_reg = DVOC, | |
78e0d2e3 | 87 | .dvo_srcdim_reg = DVOC_SRCDIM, |
79e53945 | 88 | .slave_addr = 0x75, |
988c7015 | 89 | .gpio = GMBUS_PIN_DPB, |
79e53945 | 90 | .dev_ops = &ch7017_ops, |
7434a255 TR |
91 | }, |
92 | { | |
93 | .type = INTEL_DVO_CHIP_TMDS, | |
94 | .name = "ns2501", | |
316e0157 | 95 | .dvo_reg = DVOB, |
78e0d2e3 | 96 | .dvo_srcdim_reg = DVOB_SRCDIM, |
7434a255 TR |
97 | .slave_addr = NS2501_ADDR, |
98 | .dev_ops = &ns2501_ops, | |
99 | } | |
79e53945 JB |
100 | }; |
101 | ||
ea5b213a CW |
102 | struct intel_dvo { |
103 | struct intel_encoder base; | |
104 | ||
105 | struct intel_dvo_device dev; | |
106 | ||
28694070 VS |
107 | struct intel_connector *attached_connector; |
108 | ||
ea5b213a CW |
109 | bool panel_wants_dither; |
110 | }; | |
111 | ||
69438e64 | 112 | static struct intel_dvo *enc_to_dvo(struct intel_encoder *encoder) |
ea5b213a | 113 | { |
69438e64 | 114 | return container_of(encoder, struct intel_dvo, base); |
ea5b213a CW |
115 | } |
116 | ||
df0e9248 CW |
117 | static struct intel_dvo *intel_attached_dvo(struct drm_connector *connector) |
118 | { | |
79fde301 | 119 | return enc_to_dvo(intel_attached_encoder(connector)); |
df0e9248 CW |
120 | } |
121 | ||
732ce74f | 122 | static bool intel_dvo_connector_get_hw_state(struct intel_connector *connector) |
79e53945 | 123 | { |
f417c11b | 124 | struct drm_device *dev = connector->base.dev; |
fac5e23e | 125 | struct drm_i915_private *dev_priv = to_i915(dev); |
732ce74f | 126 | struct intel_dvo *intel_dvo = intel_attached_dvo(&connector->base); |
f417c11b VS |
127 | u32 tmp; |
128 | ||
129 | tmp = I915_READ(intel_dvo->dev.dvo_reg); | |
130 | ||
131 | if (!(tmp & DVO_ENABLE)) | |
132 | return false; | |
732ce74f DV |
133 | |
134 | return intel_dvo->dev.dev_ops->get_hw_state(&intel_dvo->dev); | |
135 | } | |
136 | ||
137 | static bool intel_dvo_get_hw_state(struct intel_encoder *encoder, | |
138 | enum pipe *pipe) | |
139 | { | |
140 | struct drm_device *dev = encoder->base.dev; | |
fac5e23e | 141 | struct drm_i915_private *dev_priv = to_i915(dev); |
69438e64 | 142 | struct intel_dvo *intel_dvo = enc_to_dvo(encoder); |
732ce74f DV |
143 | u32 tmp; |
144 | ||
145 | tmp = I915_READ(intel_dvo->dev.dvo_reg); | |
146 | ||
147 | if (!(tmp & DVO_ENABLE)) | |
148 | return false; | |
149 | ||
150 | *pipe = PORT_TO_PIPE(tmp); | |
151 | ||
152 | return true; | |
153 | } | |
154 | ||
045ac3b5 | 155 | static void intel_dvo_get_config(struct intel_encoder *encoder, |
5cec258b | 156 | struct intel_crtc_state *pipe_config) |
045ac3b5 | 157 | { |
fac5e23e | 158 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
69438e64 | 159 | struct intel_dvo *intel_dvo = enc_to_dvo(encoder); |
045ac3b5 JB |
160 | u32 tmp, flags = 0; |
161 | ||
162 | tmp = I915_READ(intel_dvo->dev.dvo_reg); | |
163 | if (tmp & DVO_HSYNC_ACTIVE_HIGH) | |
164 | flags |= DRM_MODE_FLAG_PHSYNC; | |
165 | else | |
166 | flags |= DRM_MODE_FLAG_NHSYNC; | |
167 | if (tmp & DVO_VSYNC_ACTIVE_HIGH) | |
168 | flags |= DRM_MODE_FLAG_PVSYNC; | |
169 | else | |
170 | flags |= DRM_MODE_FLAG_NVSYNC; | |
171 | ||
2d112de7 | 172 | pipe_config->base.adjusted_mode.flags |= flags; |
18442d08 | 173 | |
2d112de7 | 174 | pipe_config->base.adjusted_mode.crtc_clock = pipe_config->port_clock; |
045ac3b5 JB |
175 | } |
176 | ||
fd6bbda9 ML |
177 | static void intel_disable_dvo(struct intel_encoder *encoder, |
178 | struct intel_crtc_state *old_crtc_state, | |
179 | struct drm_connector_state *old_conn_state) | |
19c63fa8 | 180 | { |
fac5e23e | 181 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
69438e64 | 182 | struct intel_dvo *intel_dvo = enc_to_dvo(encoder); |
f0f59a00 | 183 | i915_reg_t dvo_reg = intel_dvo->dev.dvo_reg; |
19c63fa8 DV |
184 | u32 temp = I915_READ(dvo_reg); |
185 | ||
186 | intel_dvo->dev.dev_ops->dpms(&intel_dvo->dev, false); | |
187 | I915_WRITE(dvo_reg, temp & ~DVO_ENABLE); | |
188 | I915_READ(dvo_reg); | |
189 | } | |
190 | ||
fd6bbda9 ML |
191 | static void intel_enable_dvo(struct intel_encoder *encoder, |
192 | struct intel_crtc_state *pipe_config, | |
193 | struct drm_connector_state *conn_state) | |
19c63fa8 | 194 | { |
fac5e23e | 195 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
69438e64 | 196 | struct intel_dvo *intel_dvo = enc_to_dvo(encoder); |
48f34e10 | 197 | struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); |
f0f59a00 | 198 | i915_reg_t dvo_reg = intel_dvo->dev.dvo_reg; |
79e53945 JB |
199 | u32 temp = I915_READ(dvo_reg); |
200 | ||
48f34e10 | 201 | intel_dvo->dev.dev_ops->mode_set(&intel_dvo->dev, |
6e3c9717 ACO |
202 | &crtc->config->base.mode, |
203 | &crtc->config->base.adjusted_mode); | |
48f34e10 | 204 | |
c9c054c2 VS |
205 | I915_WRITE(dvo_reg, temp | DVO_ENABLE); |
206 | I915_READ(dvo_reg); | |
207 | ||
19c63fa8 DV |
208 | intel_dvo->dev.dev_ops->dpms(&intel_dvo->dev, true); |
209 | } | |
210 | ||
c19de8eb DL |
211 | static enum drm_mode_status |
212 | intel_dvo_mode_valid(struct drm_connector *connector, | |
213 | struct drm_display_mode *mode) | |
79e53945 | 214 | { |
df0e9248 | 215 | struct intel_dvo *intel_dvo = intel_attached_dvo(connector); |
28694070 VS |
216 | const struct drm_display_mode *fixed_mode = |
217 | to_intel_connector(connector)->panel.fixed_mode; | |
26a91555 MK |
218 | int max_dotclk = to_i915(connector->dev)->max_dotclk_freq; |
219 | int target_clock = mode->clock; | |
79e53945 JB |
220 | |
221 | if (mode->flags & DRM_MODE_FLAG_DBLSCAN) | |
222 | return MODE_NO_DBLESCAN; | |
223 | ||
224 | /* XXX: Validate clock range */ | |
225 | ||
28694070 VS |
226 | if (fixed_mode) { |
227 | if (mode->hdisplay > fixed_mode->hdisplay) | |
79e53945 | 228 | return MODE_PANEL; |
28694070 | 229 | if (mode->vdisplay > fixed_mode->vdisplay) |
79e53945 | 230 | return MODE_PANEL; |
26a91555 | 231 | |
28694070 | 232 | target_clock = fixed_mode->clock; |
79e53945 JB |
233 | } |
234 | ||
26a91555 MK |
235 | if (target_clock > max_dotclk) |
236 | return MODE_CLOCK_HIGH; | |
237 | ||
ea5b213a | 238 | return intel_dvo->dev.dev_ops->mode_valid(&intel_dvo->dev, mode); |
79e53945 JB |
239 | } |
240 | ||
a3470375 | 241 | static bool intel_dvo_compute_config(struct intel_encoder *encoder, |
5cec258b | 242 | struct intel_crtc_state *pipe_config) |
79e53945 | 243 | { |
a3470375 | 244 | struct intel_dvo *intel_dvo = enc_to_dvo(encoder); |
28694070 VS |
245 | const struct drm_display_mode *fixed_mode = |
246 | intel_dvo->attached_connector->panel.fixed_mode; | |
2d112de7 | 247 | struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; |
79e53945 JB |
248 | |
249 | /* If we have timings from the BIOS for the panel, put them in | |
250 | * to the adjusted mode. The CRTC will be set up for this mode, | |
251 | * with the panel scaling set up to source from the H/VDisplay | |
252 | * of the original mode. | |
253 | */ | |
28694070 VS |
254 | if (fixed_mode) |
255 | intel_fixed_panel_mode(fixed_mode, adjusted_mode); | |
79e53945 | 256 | |
79e53945 JB |
257 | return true; |
258 | } | |
259 | ||
fd6bbda9 ML |
260 | static void intel_dvo_pre_enable(struct intel_encoder *encoder, |
261 | struct intel_crtc_state *pipe_config, | |
262 | struct drm_connector_state *conn_state) | |
79e53945 | 263 | { |
79fde301 | 264 | struct drm_device *dev = encoder->base.dev; |
fac5e23e | 265 | struct drm_i915_private *dev_priv = to_i915(dev); |
79fde301 | 266 | struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); |
7c5f93b0 | 267 | const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode; |
79fde301 DV |
268 | struct intel_dvo *intel_dvo = enc_to_dvo(encoder); |
269 | int pipe = crtc->pipe; | |
79e53945 | 270 | u32 dvo_val; |
f0f59a00 VS |
271 | i915_reg_t dvo_reg = intel_dvo->dev.dvo_reg; |
272 | i915_reg_t dvo_srcdim_reg = intel_dvo->dev.dvo_srcdim_reg; | |
79e53945 | 273 | |
79e53945 JB |
274 | /* Save the data order, since I don't know what it should be set to. */ |
275 | dvo_val = I915_READ(dvo_reg) & | |
276 | (DVO_PRESERVE_MASK | DVO_DATA_ORDER_GBRG); | |
277 | dvo_val |= DVO_DATA_ORDER_FP | DVO_BORDER_ENABLE | | |
278 | DVO_BLANK_ACTIVE_HIGH; | |
279 | ||
280 | if (pipe == 1) | |
281 | dvo_val |= DVO_PIPE_B_SELECT; | |
282 | dvo_val |= DVO_PIPE_STALL; | |
283 | if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) | |
284 | dvo_val |= DVO_HSYNC_ACTIVE_HIGH; | |
285 | if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) | |
286 | dvo_val |= DVO_VSYNC_ACTIVE_HIGH; | |
287 | ||
79e53945 | 288 | /*I915_WRITE(DVOB_SRCDIM, |
aad941d5 VS |
289 | (adjusted_mode->crtc_hdisplay << DVO_SRCDIM_HORIZONTAL_SHIFT) | |
290 | (adjusted_mode->crtc_vdisplay << DVO_SRCDIM_VERTICAL_SHIFT));*/ | |
79e53945 | 291 | I915_WRITE(dvo_srcdim_reg, |
aad941d5 VS |
292 | (adjusted_mode->crtc_hdisplay << DVO_SRCDIM_HORIZONTAL_SHIFT) | |
293 | (adjusted_mode->crtc_vdisplay << DVO_SRCDIM_VERTICAL_SHIFT)); | |
79e53945 JB |
294 | /*I915_WRITE(DVOB, dvo_val);*/ |
295 | I915_WRITE(dvo_reg, dvo_val); | |
296 | } | |
297 | ||
298 | /** | |
299 | * Detect the output connection on our DVO device. | |
300 | * | |
301 | * Unimplemented. | |
302 | */ | |
7b334fcb | 303 | static enum drm_connector_status |
930a9e28 | 304 | intel_dvo_detect(struct drm_connector *connector, bool force) |
79e53945 | 305 | { |
df0e9248 | 306 | struct intel_dvo *intel_dvo = intel_attached_dvo(connector); |
164c8598 | 307 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", |
c23cc417 | 308 | connector->base.id, connector->name); |
ea5b213a | 309 | return intel_dvo->dev.dev_ops->detect(&intel_dvo->dev); |
79e53945 JB |
310 | } |
311 | ||
312 | static int intel_dvo_get_modes(struct drm_connector *connector) | |
313 | { | |
fac5e23e | 314 | struct drm_i915_private *dev_priv = to_i915(connector->dev); |
28694070 VS |
315 | const struct drm_display_mode *fixed_mode = |
316 | to_intel_connector(connector)->panel.fixed_mode; | |
79e53945 JB |
317 | |
318 | /* We should probably have an i2c driver get_modes function for those | |
319 | * devices which will have a fixed set of modes determined by the chip | |
320 | * (TV-out, for example), but for now with just TMDS and LVDS, | |
321 | * that's not the case. | |
322 | */ | |
f899fc64 | 323 | intel_ddc_get_modes(connector, |
988c7015 | 324 | intel_gmbus_get_adapter(dev_priv, GMBUS_PIN_DPC)); |
79e53945 JB |
325 | if (!list_empty(&connector->probed_modes)) |
326 | return 1; | |
327 | ||
28694070 | 328 | if (fixed_mode) { |
79e53945 | 329 | struct drm_display_mode *mode; |
28694070 | 330 | mode = drm_mode_duplicate(connector->dev, fixed_mode); |
79e53945 JB |
331 | if (mode) { |
332 | drm_mode_probed_add(connector, mode); | |
333 | return 1; | |
334 | } | |
335 | } | |
ea5b213a | 336 | |
79e53945 JB |
337 | return 0; |
338 | } | |
339 | ||
ea5b213a | 340 | static void intel_dvo_destroy(struct drm_connector *connector) |
79e53945 | 341 | { |
79e53945 | 342 | drm_connector_cleanup(connector); |
28694070 | 343 | intel_panel_fini(&to_intel_connector(connector)->panel); |
599be16c | 344 | kfree(connector); |
79e53945 | 345 | } |
79e53945 | 346 | |
79e53945 | 347 | static const struct drm_connector_funcs intel_dvo_connector_funcs = { |
4d688a2a | 348 | .dpms = drm_atomic_helper_connector_dpms, |
79e53945 | 349 | .detect = intel_dvo_detect, |
1ebaa0b9 | 350 | .late_register = intel_connector_register, |
c191eca1 | 351 | .early_unregister = intel_connector_unregister, |
79e53945 JB |
352 | .destroy = intel_dvo_destroy, |
353 | .fill_modes = drm_helper_probe_single_connector_modes, | |
2545e4a6 | 354 | .atomic_get_property = intel_connector_atomic_get_property, |
c6f95f27 | 355 | .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, |
98969725 | 356 | .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, |
79e53945 JB |
357 | }; |
358 | ||
359 | static const struct drm_connector_helper_funcs intel_dvo_connector_helper_funcs = { | |
360 | .mode_valid = intel_dvo_mode_valid, | |
361 | .get_modes = intel_dvo_get_modes, | |
79e53945 JB |
362 | }; |
363 | ||
b358d0a6 | 364 | static void intel_dvo_enc_destroy(struct drm_encoder *encoder) |
79e53945 | 365 | { |
69438e64 | 366 | struct intel_dvo *intel_dvo = enc_to_dvo(to_intel_encoder(encoder)); |
ea5b213a CW |
367 | |
368 | if (intel_dvo->dev.dev_ops->destroy) | |
369 | intel_dvo->dev.dev_ops->destroy(&intel_dvo->dev); | |
370 | ||
ea5b213a | 371 | intel_encoder_destroy(encoder); |
79e53945 JB |
372 | } |
373 | ||
374 | static const struct drm_encoder_funcs intel_dvo_enc_funcs = { | |
375 | .destroy = intel_dvo_enc_destroy, | |
376 | }; | |
377 | ||
79e53945 JB |
378 | /** |
379 | * Attempts to get a fixed panel timing for LVDS (currently only the i830). | |
380 | * | |
381 | * Other chips with DVO LVDS will need to extend this to deal with the LVDS | |
382 | * chip being on DVOB/C and having multiple pipes. | |
383 | */ | |
384 | static struct drm_display_mode * | |
ea5b213a | 385 | intel_dvo_get_current_mode(struct drm_connector *connector) |
79e53945 JB |
386 | { |
387 | struct drm_device *dev = connector->dev; | |
fac5e23e | 388 | struct drm_i915_private *dev_priv = to_i915(dev); |
df0e9248 | 389 | struct intel_dvo *intel_dvo = intel_attached_dvo(connector); |
ea5b213a | 390 | uint32_t dvo_val = I915_READ(intel_dvo->dev.dvo_reg); |
79e53945 JB |
391 | struct drm_display_mode *mode = NULL; |
392 | ||
393 | /* If the DVO port is active, that'll be the LVDS, so we can pull out | |
394 | * its timings to get how the BIOS set up the panel. | |
395 | */ | |
396 | if (dvo_val & DVO_ENABLE) { | |
397 | struct drm_crtc *crtc; | |
398 | int pipe = (dvo_val & DVO_PIPE_B_SELECT) ? 1 : 0; | |
399 | ||
f875c15a | 400 | crtc = intel_get_crtc_for_pipe(dev, pipe); |
79e53945 JB |
401 | if (crtc) { |
402 | mode = intel_crtc_mode_get(dev, crtc); | |
79e53945 JB |
403 | if (mode) { |
404 | mode->type |= DRM_MODE_TYPE_PREFERRED; | |
405 | if (dvo_val & DVO_HSYNC_ACTIVE_HIGH) | |
406 | mode->flags |= DRM_MODE_FLAG_PHSYNC; | |
407 | if (dvo_val & DVO_VSYNC_ACTIVE_HIGH) | |
408 | mode->flags |= DRM_MODE_FLAG_PVSYNC; | |
409 | } | |
410 | } | |
411 | } | |
ea5b213a | 412 | |
79e53945 JB |
413 | return mode; |
414 | } | |
415 | ||
580d8ed5 VS |
416 | static char intel_dvo_port_name(i915_reg_t dvo_reg) |
417 | { | |
418 | if (i915_mmio_reg_equal(dvo_reg, DVOA)) | |
419 | return 'A'; | |
420 | else if (i915_mmio_reg_equal(dvo_reg, DVOB)) | |
421 | return 'B'; | |
422 | else if (i915_mmio_reg_equal(dvo_reg, DVOC)) | |
423 | return 'C'; | |
424 | else | |
425 | return '?'; | |
426 | } | |
427 | ||
79e53945 JB |
428 | void intel_dvo_init(struct drm_device *dev) |
429 | { | |
fac5e23e | 430 | struct drm_i915_private *dev_priv = to_i915(dev); |
21d40d37 | 431 | struct intel_encoder *intel_encoder; |
ea5b213a | 432 | struct intel_dvo *intel_dvo; |
599be16c | 433 | struct intel_connector *intel_connector; |
79e53945 | 434 | int i; |
79e53945 | 435 | int encoder_type = DRM_MODE_ENCODER_NONE; |
ea5b213a | 436 | |
b14c5679 | 437 | intel_dvo = kzalloc(sizeof(*intel_dvo), GFP_KERNEL); |
ea5b213a | 438 | if (!intel_dvo) |
79e53945 JB |
439 | return; |
440 | ||
9bdbd0b9 | 441 | intel_connector = intel_connector_alloc(); |
599be16c | 442 | if (!intel_connector) { |
ea5b213a | 443 | kfree(intel_dvo); |
599be16c ZW |
444 | return; |
445 | } | |
446 | ||
28694070 VS |
447 | intel_dvo->attached_connector = intel_connector; |
448 | ||
ea5b213a CW |
449 | intel_encoder = &intel_dvo->base; |
450 | ||
19c63fa8 DV |
451 | intel_encoder->disable = intel_disable_dvo; |
452 | intel_encoder->enable = intel_enable_dvo; | |
732ce74f | 453 | intel_encoder->get_hw_state = intel_dvo_get_hw_state; |
045ac3b5 | 454 | intel_encoder->get_config = intel_dvo_get_config; |
a3470375 | 455 | intel_encoder->compute_config = intel_dvo_compute_config; |
912b0e2d | 456 | intel_encoder->pre_enable = intel_dvo_pre_enable; |
732ce74f | 457 | intel_connector->get_hw_state = intel_dvo_connector_get_hw_state; |
19c63fa8 | 458 | |
79e53945 JB |
459 | /* Now, try to find a controller */ |
460 | for (i = 0; i < ARRAY_SIZE(intel_dvo_devices); i++) { | |
599be16c | 461 | struct drm_connector *connector = &intel_connector->base; |
ea5b213a | 462 | const struct intel_dvo_device *dvo = &intel_dvo_devices[i]; |
f899fc64 | 463 | struct i2c_adapter *i2c; |
79e53945 | 464 | int gpio; |
e4bfff54 | 465 | bool dvoinit; |
46509475 | 466 | enum pipe pipe; |
699ab787 | 467 | uint32_t dpll[I915_MAX_PIPES]; |
79e53945 | 468 | |
79e53945 JB |
469 | /* Allow the I2C driver info to specify the GPIO to be used in |
470 | * special cases, but otherwise default to what's defined | |
471 | * in the spec. | |
472 | */ | |
88ac7939 | 473 | if (intel_gmbus_is_valid_pin(dev_priv, dvo->gpio)) |
79e53945 JB |
474 | gpio = dvo->gpio; |
475 | else if (dvo->type == INTEL_DVO_CHIP_LVDS) | |
988c7015 | 476 | gpio = GMBUS_PIN_SSC; |
79e53945 | 477 | else |
988c7015 | 478 | gpio = GMBUS_PIN_DPB; |
79e53945 JB |
479 | |
480 | /* Set up the I2C bus necessary for the chip we're probing. | |
481 | * It appears that everything is on GPIOE except for panels | |
482 | * on i830 laptops, which are on GPIOB (DVOA). | |
483 | */ | |
3bd7d909 | 484 | i2c = intel_gmbus_get_adapter(dev_priv, gpio); |
79e53945 | 485 | |
ea5b213a | 486 | intel_dvo->dev = *dvo; |
e4bfff54 DMEA |
487 | |
488 | /* GMBUS NAK handling seems to be unstable, hence let the | |
489 | * transmitter detection run in bit banging mode for now. | |
490 | */ | |
491 | intel_gmbus_force_bit(i2c, true); | |
492 | ||
46509475 VS |
493 | /* ns2501 requires the DVO 2x clock before it will |
494 | * respond to i2c accesses, so make sure we have | |
495 | * have the clock enabled before we attempt to | |
496 | * initialize the device. | |
497 | */ | |
498 | for_each_pipe(dev_priv, pipe) { | |
499 | dpll[pipe] = I915_READ(DPLL(pipe)); | |
500 | I915_WRITE(DPLL(pipe), dpll[pipe] | DPLL_DVO_2X_MODE); | |
501 | } | |
502 | ||
e4bfff54 DMEA |
503 | dvoinit = dvo->dev_ops->init(&intel_dvo->dev, i2c); |
504 | ||
46509475 VS |
505 | /* restore the DVO 2x clock state to original */ |
506 | for_each_pipe(dev_priv, pipe) { | |
507 | I915_WRITE(DPLL(pipe), dpll[pipe]); | |
508 | } | |
509 | ||
e4bfff54 DMEA |
510 | intel_gmbus_force_bit(i2c, false); |
511 | ||
512 | if (!dvoinit) | |
79e53945 JB |
513 | continue; |
514 | ||
580d8ed5 VS |
515 | drm_encoder_init(dev, &intel_encoder->base, |
516 | &intel_dvo_enc_funcs, encoder_type, | |
517 | "DVO %c", intel_dvo_port_name(dvo->dvo_reg)); | |
518 | ||
21d40d37 EA |
519 | intel_encoder->type = INTEL_OUTPUT_DVO; |
520 | intel_encoder->crtc_mask = (1 << 0) | (1 << 1); | |
79e53945 JB |
521 | switch (dvo->type) { |
522 | case INTEL_DVO_CHIP_TMDS: | |
bc079e8b VS |
523 | intel_encoder->cloneable = (1 << INTEL_OUTPUT_ANALOG) | |
524 | (1 << INTEL_OUTPUT_DVO); | |
79e53945 JB |
525 | drm_connector_init(dev, connector, |
526 | &intel_dvo_connector_funcs, | |
527 | DRM_MODE_CONNECTOR_DVII); | |
528 | encoder_type = DRM_MODE_ENCODER_TMDS; | |
529 | break; | |
530 | case INTEL_DVO_CHIP_LVDS: | |
bc079e8b | 531 | intel_encoder->cloneable = 0; |
79e53945 JB |
532 | drm_connector_init(dev, connector, |
533 | &intel_dvo_connector_funcs, | |
534 | DRM_MODE_CONNECTOR_LVDS); | |
535 | encoder_type = DRM_MODE_ENCODER_LVDS; | |
536 | break; | |
537 | } | |
538 | ||
539 | drm_connector_helper_add(connector, | |
540 | &intel_dvo_connector_helper_funcs); | |
541 | connector->display_info.subpixel_order = SubPixelHorizontalRGB; | |
542 | connector->interlace_allowed = false; | |
543 | connector->doublescan_allowed = false; | |
544 | ||
df0e9248 | 545 | intel_connector_attach_encoder(intel_connector, intel_encoder); |
79e53945 JB |
546 | if (dvo->type == INTEL_DVO_CHIP_LVDS) { |
547 | /* For our LVDS chipsets, we should hopefully be able | |
548 | * to dig the fixed panel mode out of the BIOS data. | |
549 | * However, it's in a different format from the BIOS | |
550 | * data on chipsets with integrated LVDS (stored in AIM | |
551 | * headers, likely), so for now, just get the current | |
552 | * mode being output through DVO. | |
553 | */ | |
28694070 VS |
554 | intel_panel_init(&intel_connector->panel, |
555 | intel_dvo_get_current_mode(connector), | |
556 | NULL); | |
ea5b213a | 557 | intel_dvo->panel_wants_dither = true; |
79e53945 JB |
558 | } |
559 | ||
79e53945 JB |
560 | return; |
561 | } | |
562 | ||
373a3cf7 | 563 | drm_encoder_cleanup(&intel_encoder->base); |
ea5b213a | 564 | kfree(intel_dvo); |
599be16c | 565 | kfree(intel_connector); |
79e53945 | 566 | } |