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88d2ba2e TU |
1 | /* |
2 | * Copyright © 2016 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | */ | |
24 | ||
25 | #include "i915_drv.h" | |
26 | #include "intel_ringbuffer.h" | |
27 | #include "intel_lrc.h" | |
28 | ||
63ffbcda JL |
29 | /* Haswell does have the CXT_SIZE register however it does not appear to be |
30 | * valid. Now, docs explain in dwords what is in the context object. The full | |
31 | * size is 70720 bytes, however, the power context and execlist context will | |
32 | * never be saved (power context is stored elsewhere, and execlists don't work | |
33 | * on HSW) - so the final size, including the extra state required for the | |
34 | * Resource Streamer, is 66944 bytes, which rounds to 17 pages. | |
35 | */ | |
36 | #define HSW_CXT_TOTAL_SIZE (17 * PAGE_SIZE) | |
37 | /* Same as Haswell, but 72064 bytes now. */ | |
38 | #define GEN8_CXT_TOTAL_SIZE (18 * PAGE_SIZE) | |
39 | ||
40 | #define GEN8_LR_CONTEXT_RENDER_SIZE (20 * PAGE_SIZE) | |
41 | #define GEN9_LR_CONTEXT_RENDER_SIZE (22 * PAGE_SIZE) | |
42 | ||
43 | #define GEN8_LR_CONTEXT_OTHER_SIZE ( 2 * PAGE_SIZE) | |
44 | ||
b8400f01 | 45 | struct engine_class_info { |
88d2ba2e | 46 | const char *name; |
b8400f01 OM |
47 | int (*init_legacy)(struct intel_engine_cs *engine); |
48 | int (*init_execlists)(struct intel_engine_cs *engine); | |
49 | }; | |
50 | ||
51 | static const struct engine_class_info intel_engine_classes[] = { | |
52 | [RENDER_CLASS] = { | |
53 | .name = "rcs", | |
54 | .init_execlists = logical_render_ring_init, | |
55 | .init_legacy = intel_init_render_ring_buffer, | |
56 | }, | |
57 | [COPY_ENGINE_CLASS] = { | |
58 | .name = "bcs", | |
59 | .init_execlists = logical_xcs_ring_init, | |
60 | .init_legacy = intel_init_blt_ring_buffer, | |
61 | }, | |
62 | [VIDEO_DECODE_CLASS] = { | |
63 | .name = "vcs", | |
64 | .init_execlists = logical_xcs_ring_init, | |
65 | .init_legacy = intel_init_bsd_ring_buffer, | |
66 | }, | |
67 | [VIDEO_ENHANCEMENT_CLASS] = { | |
68 | .name = "vecs", | |
69 | .init_execlists = logical_xcs_ring_init, | |
70 | .init_legacy = intel_init_vebox_ring_buffer, | |
71 | }, | |
72 | }; | |
73 | ||
74 | struct engine_info { | |
237ae7c7 | 75 | unsigned int hw_id; |
1d39f281 | 76 | unsigned int uabi_id; |
0908180b DCS |
77 | u8 class; |
78 | u8 instance; | |
88d2ba2e TU |
79 | u32 mmio_base; |
80 | unsigned irq_shift; | |
b8400f01 OM |
81 | }; |
82 | ||
83 | static const struct engine_info intel_engines[] = { | |
88d2ba2e | 84 | [RCS] = { |
5ec2cf7e | 85 | .hw_id = RCS_HW, |
1d39f281 | 86 | .uabi_id = I915_EXEC_RENDER, |
0908180b DCS |
87 | .class = RENDER_CLASS, |
88 | .instance = 0, | |
88d2ba2e TU |
89 | .mmio_base = RENDER_RING_BASE, |
90 | .irq_shift = GEN8_RCS_IRQ_SHIFT, | |
88d2ba2e TU |
91 | }, |
92 | [BCS] = { | |
5ec2cf7e | 93 | .hw_id = BCS_HW, |
1d39f281 | 94 | .uabi_id = I915_EXEC_BLT, |
0908180b DCS |
95 | .class = COPY_ENGINE_CLASS, |
96 | .instance = 0, | |
88d2ba2e TU |
97 | .mmio_base = BLT_RING_BASE, |
98 | .irq_shift = GEN8_BCS_IRQ_SHIFT, | |
88d2ba2e TU |
99 | }, |
100 | [VCS] = { | |
5ec2cf7e | 101 | .hw_id = VCS_HW, |
1d39f281 | 102 | .uabi_id = I915_EXEC_BSD, |
0908180b DCS |
103 | .class = VIDEO_DECODE_CLASS, |
104 | .instance = 0, | |
88d2ba2e TU |
105 | .mmio_base = GEN6_BSD_RING_BASE, |
106 | .irq_shift = GEN8_VCS1_IRQ_SHIFT, | |
88d2ba2e TU |
107 | }, |
108 | [VCS2] = { | |
5ec2cf7e | 109 | .hw_id = VCS2_HW, |
1d39f281 | 110 | .uabi_id = I915_EXEC_BSD, |
0908180b DCS |
111 | .class = VIDEO_DECODE_CLASS, |
112 | .instance = 1, | |
88d2ba2e TU |
113 | .mmio_base = GEN8_BSD2_RING_BASE, |
114 | .irq_shift = GEN8_VCS2_IRQ_SHIFT, | |
88d2ba2e TU |
115 | }, |
116 | [VECS] = { | |
5ec2cf7e | 117 | .hw_id = VECS_HW, |
1d39f281 | 118 | .uabi_id = I915_EXEC_VEBOX, |
0908180b DCS |
119 | .class = VIDEO_ENHANCEMENT_CLASS, |
120 | .instance = 0, | |
88d2ba2e TU |
121 | .mmio_base = VEBOX_RING_BASE, |
122 | .irq_shift = GEN8_VECS_IRQ_SHIFT, | |
88d2ba2e TU |
123 | }, |
124 | }; | |
125 | ||
63ffbcda JL |
126 | /** |
127 | * ___intel_engine_context_size() - return the size of the context for an engine | |
128 | * @dev_priv: i915 device private | |
129 | * @class: engine class | |
130 | * | |
131 | * Each engine class may require a different amount of space for a context | |
132 | * image. | |
133 | * | |
134 | * Return: size (in bytes) of an engine class specific context image | |
135 | * | |
136 | * Note: this size includes the HWSP, which is part of the context image | |
137 | * in LRC mode, but does not include the "shared data page" used with | |
138 | * GuC submission. The caller should account for this if using the GuC. | |
139 | */ | |
140 | static u32 | |
141 | __intel_engine_context_size(struct drm_i915_private *dev_priv, u8 class) | |
142 | { | |
143 | u32 cxt_size; | |
144 | ||
145 | BUILD_BUG_ON(I915_GTT_PAGE_SIZE != PAGE_SIZE); | |
146 | ||
147 | switch (class) { | |
148 | case RENDER_CLASS: | |
149 | switch (INTEL_GEN(dev_priv)) { | |
150 | default: | |
151 | MISSING_CASE(INTEL_GEN(dev_priv)); | |
f65f8417 | 152 | case 10: |
63ffbcda JL |
153 | case 9: |
154 | return GEN9_LR_CONTEXT_RENDER_SIZE; | |
155 | case 8: | |
156 | return i915.enable_execlists ? | |
157 | GEN8_LR_CONTEXT_RENDER_SIZE : | |
158 | GEN8_CXT_TOTAL_SIZE; | |
159 | case 7: | |
160 | if (IS_HASWELL(dev_priv)) | |
161 | return HSW_CXT_TOTAL_SIZE; | |
162 | ||
163 | cxt_size = I915_READ(GEN7_CXT_SIZE); | |
164 | return round_up(GEN7_CXT_TOTAL_SIZE(cxt_size) * 64, | |
165 | PAGE_SIZE); | |
166 | case 6: | |
167 | cxt_size = I915_READ(CXT_SIZE); | |
168 | return round_up(GEN6_CXT_TOTAL_SIZE(cxt_size) * 64, | |
169 | PAGE_SIZE); | |
170 | case 5: | |
171 | case 4: | |
172 | case 3: | |
173 | case 2: | |
174 | /* For the special day when i810 gets merged. */ | |
175 | case 1: | |
176 | return 0; | |
177 | } | |
178 | break; | |
179 | default: | |
180 | MISSING_CASE(class); | |
181 | case VIDEO_DECODE_CLASS: | |
182 | case VIDEO_ENHANCEMENT_CLASS: | |
183 | case COPY_ENGINE_CLASS: | |
184 | if (INTEL_GEN(dev_priv) < 8) | |
185 | return 0; | |
186 | return GEN8_LR_CONTEXT_OTHER_SIZE; | |
187 | } | |
188 | } | |
189 | ||
3b3f1650 | 190 | static int |
88d2ba2e TU |
191 | intel_engine_setup(struct drm_i915_private *dev_priv, |
192 | enum intel_engine_id id) | |
193 | { | |
194 | const struct engine_info *info = &intel_engines[id]; | |
b8400f01 | 195 | const struct engine_class_info *class_info; |
3b3f1650 AG |
196 | struct intel_engine_cs *engine; |
197 | ||
b8400f01 OM |
198 | GEM_BUG_ON(info->class >= ARRAY_SIZE(intel_engine_classes)); |
199 | class_info = &intel_engine_classes[info->class]; | |
200 | ||
3b3f1650 AG |
201 | GEM_BUG_ON(dev_priv->engine[id]); |
202 | engine = kzalloc(sizeof(*engine), GFP_KERNEL); | |
203 | if (!engine) | |
204 | return -ENOMEM; | |
88d2ba2e TU |
205 | |
206 | engine->id = id; | |
207 | engine->i915 = dev_priv; | |
6e516148 | 208 | WARN_ON(snprintf(engine->name, sizeof(engine->name), "%s%u", |
b8400f01 OM |
209 | class_info->name, info->instance) >= |
210 | sizeof(engine->name)); | |
1d39f281 | 211 | engine->uabi_id = info->uabi_id; |
5ec2cf7e | 212 | engine->hw_id = engine->guc_id = info->hw_id; |
88d2ba2e TU |
213 | engine->mmio_base = info->mmio_base; |
214 | engine->irq_shift = info->irq_shift; | |
0908180b DCS |
215 | engine->class = info->class; |
216 | engine->instance = info->instance; | |
88d2ba2e | 217 | |
63ffbcda JL |
218 | engine->context_size = __intel_engine_context_size(dev_priv, |
219 | engine->class); | |
220 | if (WARN_ON(engine->context_size > BIT(20))) | |
221 | engine->context_size = 0; | |
222 | ||
0de9136d CW |
223 | /* Nothing to do here, execute in order of dependencies */ |
224 | engine->schedule = NULL; | |
225 | ||
3fc03069 CD |
226 | ATOMIC_INIT_NOTIFIER_HEAD(&engine->context_status_notifier); |
227 | ||
3b3f1650 AG |
228 | dev_priv->engine[id] = engine; |
229 | return 0; | |
88d2ba2e TU |
230 | } |
231 | ||
232 | /** | |
63ffbcda | 233 | * intel_engines_init_mmio() - allocate and prepare the Engine Command Streamers |
bf9e8429 | 234 | * @dev_priv: i915 device private |
88d2ba2e TU |
235 | * |
236 | * Return: non-zero if the initialization failed. | |
237 | */ | |
63ffbcda | 238 | int intel_engines_init_mmio(struct drm_i915_private *dev_priv) |
88d2ba2e | 239 | { |
c1bb1145 | 240 | struct intel_device_info *device_info = mkwrite_device_info(dev_priv); |
5f9be054 | 241 | const unsigned int ring_mask = INTEL_INFO(dev_priv)->ring_mask; |
3b3f1650 AG |
242 | struct intel_engine_cs *engine; |
243 | enum intel_engine_id id; | |
5f9be054 | 244 | unsigned int mask = 0; |
88d2ba2e | 245 | unsigned int i; |
bb8f0f5a | 246 | int err; |
88d2ba2e | 247 | |
70006ad6 TU |
248 | WARN_ON(ring_mask == 0); |
249 | WARN_ON(ring_mask & | |
88d2ba2e TU |
250 | GENMASK(sizeof(mask) * BITS_PER_BYTE - 1, I915_NUM_ENGINES)); |
251 | ||
252 | for (i = 0; i < ARRAY_SIZE(intel_engines); i++) { | |
253 | if (!HAS_ENGINE(dev_priv, i)) | |
254 | continue; | |
255 | ||
bb8f0f5a CW |
256 | err = intel_engine_setup(dev_priv, i); |
257 | if (err) | |
258 | goto cleanup; | |
259 | ||
260 | mask |= ENGINE_MASK(i); | |
261 | } | |
262 | ||
263 | /* | |
264 | * Catch failures to update intel_engines table when the new engines | |
265 | * are added to the driver by a warning and disabling the forgotten | |
266 | * engines. | |
267 | */ | |
268 | if (WARN_ON(mask != ring_mask)) | |
269 | device_info->ring_mask = mask; | |
270 | ||
5f9be054 CW |
271 | /* We always presume we have at least RCS available for later probing */ |
272 | if (WARN_ON(!HAS_ENGINE(dev_priv, RCS))) { | |
273 | err = -ENODEV; | |
274 | goto cleanup; | |
275 | } | |
276 | ||
bb8f0f5a CW |
277 | device_info->num_rings = hweight32(mask); |
278 | ||
279 | return 0; | |
280 | ||
281 | cleanup: | |
282 | for_each_engine(engine, dev_priv, id) | |
283 | kfree(engine); | |
284 | return err; | |
285 | } | |
286 | ||
287 | /** | |
63ffbcda | 288 | * intel_engines_init() - init the Engine Command Streamers |
bb8f0f5a CW |
289 | * @dev_priv: i915 device private |
290 | * | |
291 | * Return: non-zero if the initialization failed. | |
292 | */ | |
293 | int intel_engines_init(struct drm_i915_private *dev_priv) | |
294 | { | |
bb8f0f5a CW |
295 | struct intel_engine_cs *engine; |
296 | enum intel_engine_id id, err_id; | |
33def1ff | 297 | int err; |
bb8f0f5a CW |
298 | |
299 | for_each_engine(engine, dev_priv, id) { | |
b8400f01 OM |
300 | const struct engine_class_info *class_info = |
301 | &intel_engine_classes[engine->class]; | |
bb8f0f5a CW |
302 | int (*init)(struct intel_engine_cs *engine); |
303 | ||
88d2ba2e | 304 | if (i915.enable_execlists) |
b8400f01 | 305 | init = class_info->init_execlists; |
88d2ba2e | 306 | else |
b8400f01 | 307 | init = class_info->init_legacy; |
33def1ff TU |
308 | |
309 | err = -EINVAL; | |
310 | err_id = id; | |
311 | ||
312 | if (GEM_WARN_ON(!init)) | |
313 | goto cleanup; | |
88d2ba2e | 314 | |
bb8f0f5a | 315 | err = init(engine); |
33def1ff | 316 | if (err) |
88d2ba2e TU |
317 | goto cleanup; |
318 | ||
ff44ad51 | 319 | GEM_BUG_ON(!engine->submit_request); |
88d2ba2e TU |
320 | } |
321 | ||
88d2ba2e TU |
322 | return 0; |
323 | ||
324 | cleanup: | |
3b3f1650 | 325 | for_each_engine(engine, dev_priv, id) { |
33def1ff | 326 | if (id >= err_id) { |
bb8f0f5a | 327 | kfree(engine); |
33def1ff TU |
328 | dev_priv->engine[id] = NULL; |
329 | } else { | |
8ee7c6e2 | 330 | dev_priv->gt.cleanup_engine(engine); |
33def1ff | 331 | } |
88d2ba2e | 332 | } |
bb8f0f5a | 333 | return err; |
88d2ba2e TU |
334 | } |
335 | ||
73cb9701 | 336 | void intel_engine_init_global_seqno(struct intel_engine_cs *engine, u32 seqno) |
57f275a2 CW |
337 | { |
338 | struct drm_i915_private *dev_priv = engine->i915; | |
339 | ||
340 | /* Our semaphore implementation is strictly monotonic (i.e. we proceed | |
341 | * so long as the semaphore value in the register/page is greater | |
342 | * than the sync value), so whenever we reset the seqno, | |
343 | * so long as we reset the tracking semaphore value to 0, it will | |
344 | * always be before the next request's seqno. If we don't reset | |
345 | * the semaphore value, then when the seqno moves backwards all | |
346 | * future waits will complete instantly (causing rendering corruption). | |
347 | */ | |
348 | if (IS_GEN6(dev_priv) || IS_GEN7(dev_priv)) { | |
349 | I915_WRITE(RING_SYNC_0(engine->mmio_base), 0); | |
350 | I915_WRITE(RING_SYNC_1(engine->mmio_base), 0); | |
351 | if (HAS_VEBOX(dev_priv)) | |
352 | I915_WRITE(RING_SYNC_2(engine->mmio_base), 0); | |
353 | } | |
51d545d0 CW |
354 | if (dev_priv->semaphore) { |
355 | struct page *page = i915_vma_first_page(dev_priv->semaphore); | |
356 | void *semaphores; | |
357 | ||
358 | /* Semaphores are in noncoherent memory, flush to be safe */ | |
24caf655 | 359 | semaphores = kmap_atomic(page); |
57f275a2 CW |
360 | memset(semaphores + GEN8_SEMAPHORE_OFFSET(engine->id, 0), |
361 | 0, I915_NUM_ENGINES * gen8_semaphore_seqno_size); | |
51d545d0 CW |
362 | drm_clflush_virt_range(semaphores + GEN8_SEMAPHORE_OFFSET(engine->id, 0), |
363 | I915_NUM_ENGINES * gen8_semaphore_seqno_size); | |
24caf655 | 364 | kunmap_atomic(semaphores); |
57f275a2 | 365 | } |
57f275a2 CW |
366 | |
367 | intel_write_status_page(engine, I915_GEM_HWS_INDEX, seqno); | |
14a6bbf9 | 368 | clear_bit(ENGINE_IRQ_BREADCRUMB, &engine->irq_posted); |
73cb9701 | 369 | |
57f275a2 CW |
370 | /* After manually advancing the seqno, fake the interrupt in case |
371 | * there are any waiters for that seqno. | |
372 | */ | |
373 | intel_engine_wakeup(engine); | |
2ca9faa5 CW |
374 | |
375 | GEM_BUG_ON(intel_engine_get_seqno(engine) != seqno); | |
57f275a2 CW |
376 | } |
377 | ||
73cb9701 | 378 | static void intel_engine_init_timeline(struct intel_engine_cs *engine) |
dcff85c8 | 379 | { |
73cb9701 | 380 | engine->timeline = &engine->i915->gt.global_timeline.engine[engine->id]; |
dcff85c8 CW |
381 | } |
382 | ||
019bf277 TU |
383 | /** |
384 | * intel_engines_setup_common - setup engine state not requiring hw access | |
385 | * @engine: Engine to setup. | |
386 | * | |
387 | * Initializes @engine@ structure members shared between legacy and execlists | |
388 | * submission modes which do not require hardware access. | |
389 | * | |
390 | * Typically done early in the submission mode specific engine setup stage. | |
391 | */ | |
392 | void intel_engine_setup_common(struct intel_engine_cs *engine) | |
393 | { | |
20311bd3 CW |
394 | engine->execlist_queue = RB_ROOT; |
395 | engine->execlist_first = NULL; | |
019bf277 | 396 | |
73cb9701 | 397 | intel_engine_init_timeline(engine); |
019bf277 | 398 | intel_engine_init_hangcheck(engine); |
115003e9 | 399 | i915_gem_batch_pool_init(engine, &engine->batch_pool); |
7756e454 CW |
400 | |
401 | intel_engine_init_cmd_parser(engine); | |
019bf277 TU |
402 | } |
403 | ||
adc320c4 CW |
404 | int intel_engine_create_scratch(struct intel_engine_cs *engine, int size) |
405 | { | |
406 | struct drm_i915_gem_object *obj; | |
407 | struct i915_vma *vma; | |
408 | int ret; | |
409 | ||
410 | WARN_ON(engine->scratch); | |
411 | ||
187685cb | 412 | obj = i915_gem_object_create_stolen(engine->i915, size); |
adc320c4 | 413 | if (!obj) |
920cf419 | 414 | obj = i915_gem_object_create_internal(engine->i915, size); |
adc320c4 CW |
415 | if (IS_ERR(obj)) { |
416 | DRM_ERROR("Failed to allocate scratch page\n"); | |
417 | return PTR_ERR(obj); | |
418 | } | |
419 | ||
a01cb37a | 420 | vma = i915_vma_instance(obj, &engine->i915->ggtt.base, NULL); |
adc320c4 CW |
421 | if (IS_ERR(vma)) { |
422 | ret = PTR_ERR(vma); | |
423 | goto err_unref; | |
424 | } | |
425 | ||
426 | ret = i915_vma_pin(vma, 0, 4096, PIN_GLOBAL | PIN_HIGH); | |
427 | if (ret) | |
428 | goto err_unref; | |
429 | ||
430 | engine->scratch = vma; | |
bde13ebd CW |
431 | DRM_DEBUG_DRIVER("%s pipe control offset: 0x%08x\n", |
432 | engine->name, i915_ggtt_offset(vma)); | |
adc320c4 CW |
433 | return 0; |
434 | ||
435 | err_unref: | |
436 | i915_gem_object_put(obj); | |
437 | return ret; | |
438 | } | |
439 | ||
440 | static void intel_engine_cleanup_scratch(struct intel_engine_cs *engine) | |
441 | { | |
19880c4a | 442 | i915_vma_unpin_and_release(&engine->scratch); |
adc320c4 CW |
443 | } |
444 | ||
486e93f7 DCS |
445 | static void cleanup_phys_status_page(struct intel_engine_cs *engine) |
446 | { | |
447 | struct drm_i915_private *dev_priv = engine->i915; | |
448 | ||
449 | if (!dev_priv->status_page_dmah) | |
450 | return; | |
451 | ||
452 | drm_pci_free(&dev_priv->drm, dev_priv->status_page_dmah); | |
453 | engine->status_page.page_addr = NULL; | |
454 | } | |
455 | ||
456 | static void cleanup_status_page(struct intel_engine_cs *engine) | |
457 | { | |
458 | struct i915_vma *vma; | |
459 | struct drm_i915_gem_object *obj; | |
460 | ||
461 | vma = fetch_and_zero(&engine->status_page.vma); | |
462 | if (!vma) | |
463 | return; | |
464 | ||
465 | obj = vma->obj; | |
466 | ||
467 | i915_vma_unpin(vma); | |
468 | i915_vma_close(vma); | |
469 | ||
470 | i915_gem_object_unpin_map(obj); | |
471 | __i915_gem_object_release_unless_active(obj); | |
472 | } | |
473 | ||
474 | static int init_status_page(struct intel_engine_cs *engine) | |
475 | { | |
476 | struct drm_i915_gem_object *obj; | |
477 | struct i915_vma *vma; | |
478 | unsigned int flags; | |
479 | void *vaddr; | |
480 | int ret; | |
481 | ||
482 | obj = i915_gem_object_create_internal(engine->i915, PAGE_SIZE); | |
483 | if (IS_ERR(obj)) { | |
484 | DRM_ERROR("Failed to allocate status page\n"); | |
485 | return PTR_ERR(obj); | |
486 | } | |
487 | ||
488 | ret = i915_gem_object_set_cache_level(obj, I915_CACHE_LLC); | |
489 | if (ret) | |
490 | goto err; | |
491 | ||
492 | vma = i915_vma_instance(obj, &engine->i915->ggtt.base, NULL); | |
493 | if (IS_ERR(vma)) { | |
494 | ret = PTR_ERR(vma); | |
495 | goto err; | |
496 | } | |
497 | ||
498 | flags = PIN_GLOBAL; | |
499 | if (!HAS_LLC(engine->i915)) | |
500 | /* On g33, we cannot place HWS above 256MiB, so | |
501 | * restrict its pinning to the low mappable arena. | |
502 | * Though this restriction is not documented for | |
503 | * gen4, gen5, or byt, they also behave similarly | |
504 | * and hang if the HWS is placed at the top of the | |
505 | * GTT. To generalise, it appears that all !llc | |
506 | * platforms have issues with us placing the HWS | |
507 | * above the mappable region (even though we never | |
508 | * actually map it). | |
509 | */ | |
510 | flags |= PIN_MAPPABLE; | |
511 | ret = i915_vma_pin(vma, 0, 4096, flags); | |
512 | if (ret) | |
513 | goto err; | |
514 | ||
515 | vaddr = i915_gem_object_pin_map(obj, I915_MAP_WB); | |
516 | if (IS_ERR(vaddr)) { | |
517 | ret = PTR_ERR(vaddr); | |
518 | goto err_unpin; | |
519 | } | |
520 | ||
521 | engine->status_page.vma = vma; | |
522 | engine->status_page.ggtt_offset = i915_ggtt_offset(vma); | |
523 | engine->status_page.page_addr = memset(vaddr, 0, PAGE_SIZE); | |
524 | ||
525 | DRM_DEBUG_DRIVER("%s hws offset: 0x%08x\n", | |
526 | engine->name, i915_ggtt_offset(vma)); | |
527 | return 0; | |
528 | ||
529 | err_unpin: | |
530 | i915_vma_unpin(vma); | |
531 | err: | |
532 | i915_gem_object_put(obj); | |
533 | return ret; | |
534 | } | |
535 | ||
536 | static int init_phys_status_page(struct intel_engine_cs *engine) | |
537 | { | |
538 | struct drm_i915_private *dev_priv = engine->i915; | |
539 | ||
540 | GEM_BUG_ON(engine->id != RCS); | |
541 | ||
542 | dev_priv->status_page_dmah = | |
543 | drm_pci_alloc(&dev_priv->drm, PAGE_SIZE, PAGE_SIZE); | |
544 | if (!dev_priv->status_page_dmah) | |
545 | return -ENOMEM; | |
546 | ||
547 | engine->status_page.page_addr = dev_priv->status_page_dmah->vaddr; | |
548 | memset(engine->status_page.page_addr, 0, PAGE_SIZE); | |
549 | ||
550 | return 0; | |
551 | } | |
552 | ||
019bf277 TU |
553 | /** |
554 | * intel_engines_init_common - initialize cengine state which might require hw access | |
555 | * @engine: Engine to initialize. | |
556 | * | |
557 | * Initializes @engine@ structure members shared between legacy and execlists | |
558 | * submission modes which do require hardware access. | |
559 | * | |
560 | * Typcally done at later stages of submission mode specific engine setup. | |
561 | * | |
562 | * Returns zero on success or an error code on failure. | |
563 | */ | |
564 | int intel_engine_init_common(struct intel_engine_cs *engine) | |
565 | { | |
266a240b | 566 | struct intel_ring *ring; |
019bf277 TU |
567 | int ret; |
568 | ||
ff44ad51 CW |
569 | engine->set_default_submission(engine); |
570 | ||
e8a9c58f CW |
571 | /* We may need to do things with the shrinker which |
572 | * require us to immediately switch back to the default | |
573 | * context. This can cause a problem as pinning the | |
574 | * default context also requires GTT space which may not | |
575 | * be available. To avoid this we always pin the default | |
576 | * context. | |
577 | */ | |
266a240b CW |
578 | ring = engine->context_pin(engine, engine->i915->kernel_context); |
579 | if (IS_ERR(ring)) | |
580 | return PTR_ERR(ring); | |
019bf277 | 581 | |
e8a9c58f CW |
582 | ret = intel_engine_init_breadcrumbs(engine); |
583 | if (ret) | |
584 | goto err_unpin; | |
585 | ||
4e50f082 CW |
586 | ret = i915_gem_render_state_init(engine); |
587 | if (ret) | |
486e93f7 DCS |
588 | goto err_breadcrumbs; |
589 | ||
590 | if (HWS_NEEDS_PHYSICAL(engine->i915)) | |
591 | ret = init_phys_status_page(engine); | |
592 | else | |
593 | ret = init_status_page(engine); | |
594 | if (ret) | |
595 | goto err_rs_fini; | |
4e50f082 | 596 | |
7756e454 | 597 | return 0; |
e8a9c58f | 598 | |
486e93f7 DCS |
599 | err_rs_fini: |
600 | i915_gem_render_state_fini(engine); | |
601 | err_breadcrumbs: | |
602 | intel_engine_fini_breadcrumbs(engine); | |
e8a9c58f CW |
603 | err_unpin: |
604 | engine->context_unpin(engine, engine->i915->kernel_context); | |
605 | return ret; | |
019bf277 | 606 | } |
96a945aa CW |
607 | |
608 | /** | |
609 | * intel_engines_cleanup_common - cleans up the engine state created by | |
610 | * the common initiailizers. | |
611 | * @engine: Engine to cleanup. | |
612 | * | |
613 | * This cleans up everything created by the common helpers. | |
614 | */ | |
615 | void intel_engine_cleanup_common(struct intel_engine_cs *engine) | |
616 | { | |
adc320c4 CW |
617 | intel_engine_cleanup_scratch(engine); |
618 | ||
486e93f7 DCS |
619 | if (HWS_NEEDS_PHYSICAL(engine->i915)) |
620 | cleanup_phys_status_page(engine); | |
621 | else | |
622 | cleanup_status_page(engine); | |
623 | ||
4e50f082 | 624 | i915_gem_render_state_fini(engine); |
96a945aa | 625 | intel_engine_fini_breadcrumbs(engine); |
7756e454 | 626 | intel_engine_cleanup_cmd_parser(engine); |
96a945aa | 627 | i915_gem_batch_pool_fini(&engine->batch_pool); |
e8a9c58f CW |
628 | |
629 | engine->context_unpin(engine, engine->i915->kernel_context); | |
96a945aa | 630 | } |
1b36595f CW |
631 | |
632 | u64 intel_engine_get_active_head(struct intel_engine_cs *engine) | |
633 | { | |
634 | struct drm_i915_private *dev_priv = engine->i915; | |
635 | u64 acthd; | |
636 | ||
637 | if (INTEL_GEN(dev_priv) >= 8) | |
638 | acthd = I915_READ64_2x32(RING_ACTHD(engine->mmio_base), | |
639 | RING_ACTHD_UDW(engine->mmio_base)); | |
640 | else if (INTEL_GEN(dev_priv) >= 4) | |
641 | acthd = I915_READ(RING_ACTHD(engine->mmio_base)); | |
642 | else | |
643 | acthd = I915_READ(ACTHD); | |
644 | ||
645 | return acthd; | |
646 | } | |
647 | ||
648 | u64 intel_engine_get_last_batch_head(struct intel_engine_cs *engine) | |
649 | { | |
650 | struct drm_i915_private *dev_priv = engine->i915; | |
651 | u64 bbaddr; | |
652 | ||
653 | if (INTEL_GEN(dev_priv) >= 8) | |
654 | bbaddr = I915_READ64_2x32(RING_BBADDR(engine->mmio_base), | |
655 | RING_BBADDR_UDW(engine->mmio_base)); | |
656 | else | |
657 | bbaddr = I915_READ(RING_BBADDR(engine->mmio_base)); | |
658 | ||
659 | return bbaddr; | |
660 | } | |
0e704476 CW |
661 | |
662 | const char *i915_cache_level_str(struct drm_i915_private *i915, int type) | |
663 | { | |
664 | switch (type) { | |
665 | case I915_CACHE_NONE: return " uncached"; | |
666 | case I915_CACHE_LLC: return HAS_LLC(i915) ? " LLC" : " snooped"; | |
667 | case I915_CACHE_L3_LLC: return " L3+LLC"; | |
668 | case I915_CACHE_WT: return " WT"; | |
669 | default: return ""; | |
670 | } | |
671 | } | |
672 | ||
673 | static inline uint32_t | |
674 | read_subslice_reg(struct drm_i915_private *dev_priv, int slice, | |
675 | int subslice, i915_reg_t reg) | |
676 | { | |
677 | uint32_t mcr; | |
678 | uint32_t ret; | |
679 | enum forcewake_domains fw_domains; | |
680 | ||
681 | fw_domains = intel_uncore_forcewake_for_reg(dev_priv, reg, | |
682 | FW_REG_READ); | |
683 | fw_domains |= intel_uncore_forcewake_for_reg(dev_priv, | |
684 | GEN8_MCR_SELECTOR, | |
685 | FW_REG_READ | FW_REG_WRITE); | |
686 | ||
687 | spin_lock_irq(&dev_priv->uncore.lock); | |
688 | intel_uncore_forcewake_get__locked(dev_priv, fw_domains); | |
689 | ||
690 | mcr = I915_READ_FW(GEN8_MCR_SELECTOR); | |
691 | /* | |
692 | * The HW expects the slice and sublice selectors to be reset to 0 | |
693 | * after reading out the registers. | |
694 | */ | |
695 | WARN_ON_ONCE(mcr & (GEN8_MCR_SLICE_MASK | GEN8_MCR_SUBSLICE_MASK)); | |
696 | mcr &= ~(GEN8_MCR_SLICE_MASK | GEN8_MCR_SUBSLICE_MASK); | |
697 | mcr |= GEN8_MCR_SLICE(slice) | GEN8_MCR_SUBSLICE(subslice); | |
698 | I915_WRITE_FW(GEN8_MCR_SELECTOR, mcr); | |
699 | ||
700 | ret = I915_READ_FW(reg); | |
701 | ||
702 | mcr &= ~(GEN8_MCR_SLICE_MASK | GEN8_MCR_SUBSLICE_MASK); | |
703 | I915_WRITE_FW(GEN8_MCR_SELECTOR, mcr); | |
704 | ||
705 | intel_uncore_forcewake_put__locked(dev_priv, fw_domains); | |
706 | spin_unlock_irq(&dev_priv->uncore.lock); | |
707 | ||
708 | return ret; | |
709 | } | |
710 | ||
711 | /* NB: please notice the memset */ | |
712 | void intel_engine_get_instdone(struct intel_engine_cs *engine, | |
713 | struct intel_instdone *instdone) | |
714 | { | |
715 | struct drm_i915_private *dev_priv = engine->i915; | |
716 | u32 mmio_base = engine->mmio_base; | |
717 | int slice; | |
718 | int subslice; | |
719 | ||
720 | memset(instdone, 0, sizeof(*instdone)); | |
721 | ||
722 | switch (INTEL_GEN(dev_priv)) { | |
723 | default: | |
724 | instdone->instdone = I915_READ(RING_INSTDONE(mmio_base)); | |
725 | ||
726 | if (engine->id != RCS) | |
727 | break; | |
728 | ||
729 | instdone->slice_common = I915_READ(GEN7_SC_INSTDONE); | |
730 | for_each_instdone_slice_subslice(dev_priv, slice, subslice) { | |
731 | instdone->sampler[slice][subslice] = | |
732 | read_subslice_reg(dev_priv, slice, subslice, | |
733 | GEN7_SAMPLER_INSTDONE); | |
734 | instdone->row[slice][subslice] = | |
735 | read_subslice_reg(dev_priv, slice, subslice, | |
736 | GEN7_ROW_INSTDONE); | |
737 | } | |
738 | break; | |
739 | case 7: | |
740 | instdone->instdone = I915_READ(RING_INSTDONE(mmio_base)); | |
741 | ||
742 | if (engine->id != RCS) | |
743 | break; | |
744 | ||
745 | instdone->slice_common = I915_READ(GEN7_SC_INSTDONE); | |
746 | instdone->sampler[0][0] = I915_READ(GEN7_SAMPLER_INSTDONE); | |
747 | instdone->row[0][0] = I915_READ(GEN7_ROW_INSTDONE); | |
748 | ||
749 | break; | |
750 | case 6: | |
751 | case 5: | |
752 | case 4: | |
753 | instdone->instdone = I915_READ(RING_INSTDONE(mmio_base)); | |
754 | ||
755 | if (engine->id == RCS) | |
756 | /* HACK: Using the wrong struct member */ | |
757 | instdone->slice_common = I915_READ(GEN4_INSTDONE1); | |
758 | break; | |
759 | case 3: | |
760 | case 2: | |
761 | instdone->instdone = I915_READ(GEN2_INSTDONE); | |
762 | break; | |
763 | } | |
764 | } | |
f97fbf96 | 765 | |
133b4bd7 TU |
766 | static int wa_add(struct drm_i915_private *dev_priv, |
767 | i915_reg_t addr, | |
768 | const u32 mask, const u32 val) | |
769 | { | |
770 | const u32 idx = dev_priv->workarounds.count; | |
771 | ||
772 | if (WARN_ON(idx >= I915_MAX_WA_REGS)) | |
773 | return -ENOSPC; | |
774 | ||
775 | dev_priv->workarounds.reg[idx].addr = addr; | |
776 | dev_priv->workarounds.reg[idx].value = val; | |
777 | dev_priv->workarounds.reg[idx].mask = mask; | |
778 | ||
779 | dev_priv->workarounds.count++; | |
780 | ||
781 | return 0; | |
782 | } | |
783 | ||
784 | #define WA_REG(addr, mask, val) do { \ | |
785 | const int r = wa_add(dev_priv, (addr), (mask), (val)); \ | |
786 | if (r) \ | |
787 | return r; \ | |
788 | } while (0) | |
789 | ||
790 | #define WA_SET_BIT_MASKED(addr, mask) \ | |
791 | WA_REG(addr, (mask), _MASKED_BIT_ENABLE(mask)) | |
792 | ||
793 | #define WA_CLR_BIT_MASKED(addr, mask) \ | |
794 | WA_REG(addr, (mask), _MASKED_BIT_DISABLE(mask)) | |
795 | ||
796 | #define WA_SET_FIELD_MASKED(addr, mask, value) \ | |
797 | WA_REG(addr, mask, _MASKED_FIELD(mask, value)) | |
798 | ||
799 | #define WA_SET_BIT(addr, mask) WA_REG(addr, mask, I915_READ(addr) | (mask)) | |
800 | #define WA_CLR_BIT(addr, mask) WA_REG(addr, mask, I915_READ(addr) & ~(mask)) | |
801 | ||
802 | #define WA_WRITE(addr, val) WA_REG(addr, 0xffffffff, val) | |
803 | ||
804 | static int wa_ring_whitelist_reg(struct intel_engine_cs *engine, | |
805 | i915_reg_t reg) | |
806 | { | |
807 | struct drm_i915_private *dev_priv = engine->i915; | |
808 | struct i915_workarounds *wa = &dev_priv->workarounds; | |
809 | const uint32_t index = wa->hw_whitelist_count[engine->id]; | |
810 | ||
811 | if (WARN_ON(index >= RING_MAX_NONPRIV_SLOTS)) | |
812 | return -EINVAL; | |
813 | ||
814 | WA_WRITE(RING_FORCE_TO_NONPRIV(engine->mmio_base, index), | |
815 | i915_mmio_reg_offset(reg)); | |
816 | wa->hw_whitelist_count[engine->id]++; | |
817 | ||
818 | return 0; | |
819 | } | |
820 | ||
821 | static int gen8_init_workarounds(struct intel_engine_cs *engine) | |
822 | { | |
823 | struct drm_i915_private *dev_priv = engine->i915; | |
824 | ||
825 | WA_SET_BIT_MASKED(INSTPM, INSTPM_FORCE_ORDERING); | |
826 | ||
827 | /* WaDisableAsyncFlipPerfMode:bdw,chv */ | |
828 | WA_SET_BIT_MASKED(MI_MODE, ASYNC_FLIP_PERF_DISABLE); | |
829 | ||
830 | /* WaDisablePartialInstShootdown:bdw,chv */ | |
831 | WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, | |
832 | PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE); | |
833 | ||
834 | /* Use Force Non-Coherent whenever executing a 3D context. This is a | |
835 | * workaround for for a possible hang in the unlikely event a TLB | |
836 | * invalidation occurs during a PSD flush. | |
837 | */ | |
838 | /* WaForceEnableNonCoherent:bdw,chv */ | |
839 | /* WaHdcDisableFetchWhenMasked:bdw,chv */ | |
840 | WA_SET_BIT_MASKED(HDC_CHICKEN0, | |
841 | HDC_DONOT_FETCH_MEM_WHEN_MASKED | | |
842 | HDC_FORCE_NON_COHERENT); | |
843 | ||
844 | /* From the Haswell PRM, Command Reference: Registers, CACHE_MODE_0: | |
845 | * "The Hierarchical Z RAW Stall Optimization allows non-overlapping | |
846 | * polygons in the same 8x4 pixel/sample area to be processed without | |
847 | * stalling waiting for the earlier ones to write to Hierarchical Z | |
848 | * buffer." | |
849 | * | |
850 | * This optimization is off by default for BDW and CHV; turn it on. | |
851 | */ | |
852 | WA_CLR_BIT_MASKED(CACHE_MODE_0_GEN7, HIZ_RAW_STALL_OPT_DISABLE); | |
853 | ||
854 | /* Wa4x4STCOptimizationDisable:bdw,chv */ | |
855 | WA_SET_BIT_MASKED(CACHE_MODE_1, GEN8_4x4_STC_OPTIMIZATION_DISABLE); | |
856 | ||
857 | /* | |
858 | * BSpec recommends 8x4 when MSAA is used, | |
859 | * however in practice 16x4 seems fastest. | |
860 | * | |
861 | * Note that PS/WM thread counts depend on the WIZ hashing | |
862 | * disable bit, which we don't touch here, but it's good | |
863 | * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM). | |
864 | */ | |
865 | WA_SET_FIELD_MASKED(GEN7_GT_MODE, | |
866 | GEN6_WIZ_HASHING_MASK, | |
867 | GEN6_WIZ_HASHING_16x4); | |
868 | ||
869 | return 0; | |
870 | } | |
871 | ||
872 | static int bdw_init_workarounds(struct intel_engine_cs *engine) | |
873 | { | |
874 | struct drm_i915_private *dev_priv = engine->i915; | |
875 | int ret; | |
876 | ||
877 | ret = gen8_init_workarounds(engine); | |
878 | if (ret) | |
879 | return ret; | |
880 | ||
881 | /* WaDisableThreadStallDopClockGating:bdw (pre-production) */ | |
882 | WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, STALL_DOP_GATING_DISABLE); | |
883 | ||
884 | /* WaDisableDopClockGating:bdw | |
885 | * | |
886 | * Also see the related UCGTCL1 write in broadwell_init_clock_gating() | |
887 | * to disable EUTC clock gating. | |
888 | */ | |
889 | WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2, | |
890 | DOP_CLOCK_GATING_DISABLE); | |
891 | ||
892 | WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3, | |
893 | GEN8_SAMPLER_POWER_BYPASS_DIS); | |
894 | ||
895 | WA_SET_BIT_MASKED(HDC_CHICKEN0, | |
896 | /* WaForceContextSaveRestoreNonCoherent:bdw */ | |
897 | HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT | | |
898 | /* WaDisableFenceDestinationToSLM:bdw (pre-prod) */ | |
899 | (IS_BDW_GT3(dev_priv) ? HDC_FENCE_DEST_SLM_DISABLE : 0)); | |
900 | ||
901 | return 0; | |
902 | } | |
903 | ||
904 | static int chv_init_workarounds(struct intel_engine_cs *engine) | |
905 | { | |
906 | struct drm_i915_private *dev_priv = engine->i915; | |
907 | int ret; | |
908 | ||
909 | ret = gen8_init_workarounds(engine); | |
910 | if (ret) | |
911 | return ret; | |
912 | ||
913 | /* WaDisableThreadStallDopClockGating:chv */ | |
914 | WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, STALL_DOP_GATING_DISABLE); | |
915 | ||
916 | /* Improve HiZ throughput on CHV. */ | |
917 | WA_SET_BIT_MASKED(HIZ_CHICKEN, CHV_HZ_8X8_MODE_IN_1X); | |
918 | ||
919 | return 0; | |
920 | } | |
921 | ||
922 | static int gen9_init_workarounds(struct intel_engine_cs *engine) | |
923 | { | |
924 | struct drm_i915_private *dev_priv = engine->i915; | |
925 | int ret; | |
926 | ||
46c26662 | 927 | /* WaConextSwitchWithConcurrentTLBInvalidate:skl,bxt,kbl,glk,cfl */ |
133b4bd7 TU |
928 | I915_WRITE(GEN9_CSFE_CHICKEN1_RCS, _MASKED_BIT_ENABLE(GEN9_PREEMPT_GPGPU_SYNC_SWITCH_DISABLE)); |
929 | ||
46c26662 | 930 | /* WaEnableLbsSlaRetryTimerDecrement:skl,bxt,kbl,glk,cfl */ |
133b4bd7 TU |
931 | I915_WRITE(BDW_SCRATCH1, I915_READ(BDW_SCRATCH1) | |
932 | GEN9_LBS_SLA_RETRY_TIMER_DECREMENT_ENABLE); | |
933 | ||
98eed3d1 RV |
934 | /* WaDisableKillLogic:bxt,skl,kbl */ |
935 | if (!IS_COFFEELAKE(dev_priv)) | |
936 | I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | | |
937 | ECOCHK_DIS_TLB); | |
133b4bd7 | 938 | |
46c26662 RV |
939 | /* WaClearFlowControlGpgpuContextSave:skl,bxt,kbl,glk,cfl */ |
940 | /* WaDisablePartialInstShootdown:skl,bxt,kbl,glk,cfl */ | |
133b4bd7 TU |
941 | WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, |
942 | FLOW_CONTROL_ENABLE | | |
943 | PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE); | |
944 | ||
945 | /* Syncing dependencies between camera and graphics:skl,bxt,kbl */ | |
46c26662 RV |
946 | if (!IS_COFFEELAKE(dev_priv)) |
947 | WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3, | |
948 | GEN9_DISABLE_OCL_OOB_SUPPRESS_LOGIC); | |
133b4bd7 TU |
949 | |
950 | /* WaDisableDgMirrorFixInHalfSliceChicken5:bxt */ | |
951 | if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) | |
952 | WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5, | |
953 | GEN9_DG_MIRROR_FIX_ENABLE); | |
954 | ||
955 | /* WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken:bxt */ | |
956 | if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) { | |
957 | WA_SET_BIT_MASKED(GEN7_COMMON_SLICE_CHICKEN1, | |
958 | GEN9_RHWO_OPTIMIZATION_DISABLE); | |
959 | /* | |
960 | * WA also requires GEN9_SLICE_COMMON_ECO_CHICKEN0[14:14] to be set | |
961 | * but we do that in per ctx batchbuffer as there is an issue | |
962 | * with this register not getting restored on ctx restore | |
963 | */ | |
964 | } | |
965 | ||
46c26662 RV |
966 | /* WaEnableYV12BugFixInHalfSliceChicken7:skl,bxt,kbl,glk,cfl */ |
967 | /* WaEnableSamplerGPGPUPreemptionSupport:skl,bxt,kbl,cfl */ | |
133b4bd7 | 968 | WA_SET_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN7, |
0b71cea2 | 969 | GEN9_ENABLE_YV12_BUGFIX | |
133b4bd7 TU |
970 | GEN9_ENABLE_GPGPU_PREEMPTION); |
971 | ||
46c26662 RV |
972 | /* Wa4x4STCOptimizationDisable:skl,bxt,kbl,glk,cfl */ |
973 | /* WaDisablePartialResolveInVc:skl,bxt,kbl,cfl */ | |
133b4bd7 TU |
974 | WA_SET_BIT_MASKED(CACHE_MODE_1, (GEN8_4x4_STC_OPTIMIZATION_DISABLE | |
975 | GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE)); | |
976 | ||
46c26662 | 977 | /* WaCcsTlbPrefetchDisable:skl,bxt,kbl,glk,cfl */ |
133b4bd7 TU |
978 | WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5, |
979 | GEN9_CCS_TLB_PREFETCH_ENABLE); | |
980 | ||
981 | /* WaDisableMaskBasedCammingInRCC:bxt */ | |
982 | if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) | |
983 | WA_SET_BIT_MASKED(SLICE_ECO_CHICKEN0, | |
984 | PIXEL_MASK_CAMMING_DISABLE); | |
985 | ||
46c26662 | 986 | /* WaForceContextSaveRestoreNonCoherent:skl,bxt,kbl,cfl */ |
133b4bd7 TU |
987 | WA_SET_BIT_MASKED(HDC_CHICKEN0, |
988 | HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT | | |
989 | HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE); | |
990 | ||
991 | /* WaForceEnableNonCoherent and WaDisableHDCInvalidation are | |
992 | * both tied to WaForceContextSaveRestoreNonCoherent | |
993 | * in some hsds for skl. We keep the tie for all gen9. The | |
994 | * documentation is a bit hazy and so we want to get common behaviour, | |
995 | * even though there is no clear evidence we would need both on kbl/bxt. | |
996 | * This area has been source of system hangs so we play it safe | |
997 | * and mimic the skl regardless of what bspec says. | |
998 | * | |
999 | * Use Force Non-Coherent whenever executing a 3D context. This | |
1000 | * is a workaround for a possible hang in the unlikely event | |
1001 | * a TLB invalidation occurs during a PSD flush. | |
1002 | */ | |
1003 | ||
46c26662 | 1004 | /* WaForceEnableNonCoherent:skl,bxt,kbl,cfl */ |
133b4bd7 TU |
1005 | WA_SET_BIT_MASKED(HDC_CHICKEN0, |
1006 | HDC_FORCE_NON_COHERENT); | |
1007 | ||
98eed3d1 RV |
1008 | /* WaDisableHDCInvalidation:skl,bxt,kbl,cfl */ |
1009 | I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | | |
1010 | BDW_DISABLE_HDC_INVALIDATION); | |
133b4bd7 | 1011 | |
46c26662 | 1012 | /* WaDisableSamplerPowerBypassForSOPingPong:skl,bxt,kbl,cfl */ |
133b4bd7 TU |
1013 | if (IS_SKYLAKE(dev_priv) || |
1014 | IS_KABYLAKE(dev_priv) || | |
46c26662 | 1015 | IS_COFFEELAKE(dev_priv) || |
133b4bd7 TU |
1016 | IS_BXT_REVID(dev_priv, 0, BXT_REVID_B0)) |
1017 | WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3, | |
1018 | GEN8_SAMPLER_POWER_BYPASS_DIS); | |
1019 | ||
46c26662 | 1020 | /* WaDisableSTUnitPowerOptimization:skl,bxt,kbl,glk,cfl */ |
133b4bd7 TU |
1021 | WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN2, GEN8_ST_PO_DISABLE); |
1022 | ||
46c26662 | 1023 | /* WaOCLCoherentLineFlush:skl,bxt,kbl,cfl */ |
133b4bd7 TU |
1024 | I915_WRITE(GEN8_L3SQCREG4, (I915_READ(GEN8_L3SQCREG4) | |
1025 | GEN8_LQSC_FLUSH_COHERENT_LINES)); | |
1026 | ||
46c26662 | 1027 | /* WaVFEStateAfterPipeControlwithMediaStateClear:skl,bxt,glk,cfl */ |
133b4bd7 TU |
1028 | ret = wa_ring_whitelist_reg(engine, GEN9_CTX_PREEMPT_REG); |
1029 | if (ret) | |
1030 | return ret; | |
1031 | ||
46c26662 | 1032 | /* WaEnablePreemptionGranularityControlByUMD:skl,bxt,kbl,cfl */ |
133b4bd7 TU |
1033 | ret= wa_ring_whitelist_reg(engine, GEN8_CS_CHICKEN1); |
1034 | if (ret) | |
1035 | return ret; | |
1036 | ||
46c26662 | 1037 | /* WaAllowUMDToModifyHDCChicken1:skl,bxt,kbl,glk,cfl */ |
133b4bd7 TU |
1038 | ret = wa_ring_whitelist_reg(engine, GEN8_HDC_CHICKEN1); |
1039 | if (ret) | |
1040 | return ret; | |
1041 | ||
1042 | return 0; | |
1043 | } | |
1044 | ||
1045 | static int skl_tune_iz_hashing(struct intel_engine_cs *engine) | |
1046 | { | |
1047 | struct drm_i915_private *dev_priv = engine->i915; | |
1048 | u8 vals[3] = { 0, 0, 0 }; | |
1049 | unsigned int i; | |
1050 | ||
1051 | for (i = 0; i < 3; i++) { | |
1052 | u8 ss; | |
1053 | ||
1054 | /* | |
1055 | * Only consider slices where one, and only one, subslice has 7 | |
1056 | * EUs | |
1057 | */ | |
1058 | if (!is_power_of_2(INTEL_INFO(dev_priv)->sseu.subslice_7eu[i])) | |
1059 | continue; | |
1060 | ||
1061 | /* | |
1062 | * subslice_7eu[i] != 0 (because of the check above) and | |
1063 | * ss_max == 4 (maximum number of subslices possible per slice) | |
1064 | * | |
1065 | * -> 0 <= ss <= 3; | |
1066 | */ | |
1067 | ss = ffs(INTEL_INFO(dev_priv)->sseu.subslice_7eu[i]) - 1; | |
1068 | vals[i] = 3 - ss; | |
1069 | } | |
1070 | ||
1071 | if (vals[0] == 0 && vals[1] == 0 && vals[2] == 0) | |
1072 | return 0; | |
1073 | ||
1074 | /* Tune IZ hashing. See intel_device_info_runtime_init() */ | |
1075 | WA_SET_FIELD_MASKED(GEN7_GT_MODE, | |
1076 | GEN9_IZ_HASHING_MASK(2) | | |
1077 | GEN9_IZ_HASHING_MASK(1) | | |
1078 | GEN9_IZ_HASHING_MASK(0), | |
1079 | GEN9_IZ_HASHING(2, vals[2]) | | |
1080 | GEN9_IZ_HASHING(1, vals[1]) | | |
1081 | GEN9_IZ_HASHING(0, vals[0])); | |
1082 | ||
1083 | return 0; | |
1084 | } | |
1085 | ||
1086 | static int skl_init_workarounds(struct intel_engine_cs *engine) | |
1087 | { | |
1088 | struct drm_i915_private *dev_priv = engine->i915; | |
1089 | int ret; | |
1090 | ||
1091 | ret = gen9_init_workarounds(engine); | |
1092 | if (ret) | |
1093 | return ret; | |
1094 | ||
1095 | /* | |
1096 | * Actual WA is to disable percontext preemption granularity control | |
1097 | * until D0 which is the default case so this is equivalent to | |
1098 | * !WaDisablePerCtxtPreemptionGranularityControl:skl | |
1099 | */ | |
1100 | I915_WRITE(GEN7_FF_SLICE_CS_CHICKEN1, | |
1101 | _MASKED_BIT_ENABLE(GEN9_FFSC_PERCTX_PREEMPT_CTRL)); | |
1102 | ||
1103 | /* WaEnableGapsTsvCreditFix:skl */ | |
1104 | I915_WRITE(GEN8_GARBCNTL, (I915_READ(GEN8_GARBCNTL) | | |
1105 | GEN9_GAPS_TSV_CREDIT_DISABLE)); | |
1106 | ||
1107 | /* WaDisableGafsUnitClkGating:skl */ | |
4827c547 OM |
1108 | I915_WRITE(GEN7_UCGCTL4, (I915_READ(GEN7_UCGCTL4) | |
1109 | GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE)); | |
133b4bd7 TU |
1110 | |
1111 | /* WaInPlaceDecompressionHang:skl */ | |
1112 | if (IS_SKL_REVID(dev_priv, SKL_REVID_H0, REVID_FOREVER)) | |
efc886cb OM |
1113 | I915_WRITE(GEN9_GAMT_ECO_REG_RW_IA, |
1114 | (I915_READ(GEN9_GAMT_ECO_REG_RW_IA) | | |
1115 | GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS)); | |
133b4bd7 TU |
1116 | |
1117 | /* WaDisableLSQCROPERFforOCL:skl */ | |
1118 | ret = wa_ring_whitelist_reg(engine, GEN8_L3SQCREG4); | |
1119 | if (ret) | |
1120 | return ret; | |
1121 | ||
1122 | return skl_tune_iz_hashing(engine); | |
1123 | } | |
1124 | ||
1125 | static int bxt_init_workarounds(struct intel_engine_cs *engine) | |
1126 | { | |
1127 | struct drm_i915_private *dev_priv = engine->i915; | |
1128 | int ret; | |
1129 | ||
1130 | ret = gen9_init_workarounds(engine); | |
1131 | if (ret) | |
1132 | return ret; | |
1133 | ||
1134 | /* WaStoreMultiplePTEenable:bxt */ | |
1135 | /* This is a requirement according to Hardware specification */ | |
1136 | if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) | |
1137 | I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_TLBPF); | |
1138 | ||
1139 | /* WaSetClckGatingDisableMedia:bxt */ | |
1140 | if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) { | |
1141 | I915_WRITE(GEN7_MISCCPCTL, (I915_READ(GEN7_MISCCPCTL) & | |
1142 | ~GEN8_DOP_CLOCK_GATE_MEDIA_ENABLE)); | |
1143 | } | |
1144 | ||
1145 | /* WaDisableThreadStallDopClockGating:bxt */ | |
1146 | WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, | |
1147 | STALL_DOP_GATING_DISABLE); | |
1148 | ||
1149 | /* WaDisablePooledEuLoadBalancingFix:bxt */ | |
1150 | if (IS_BXT_REVID(dev_priv, BXT_REVID_B0, REVID_FOREVER)) { | |
212154ba OM |
1151 | I915_WRITE(FF_SLICE_CS_CHICKEN2, |
1152 | _MASKED_BIT_ENABLE(GEN9_POOLED_EU_LOAD_BALANCING_FIX_DISABLE)); | |
133b4bd7 TU |
1153 | } |
1154 | ||
1155 | /* WaDisableSbeCacheDispatchPortSharing:bxt */ | |
1156 | if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_B0)) { | |
1157 | WA_SET_BIT_MASKED( | |
1158 | GEN7_HALF_SLICE_CHICKEN1, | |
1159 | GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE); | |
1160 | } | |
1161 | ||
1162 | /* WaDisableObjectLevelPreemptionForTrifanOrPolygon:bxt */ | |
1163 | /* WaDisableObjectLevelPreemptionForInstancedDraw:bxt */ | |
1164 | /* WaDisableObjectLevelPreemtionForInstanceId:bxt */ | |
1165 | /* WaDisableLSQCROPERFforOCL:bxt */ | |
1166 | if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) { | |
1167 | ret = wa_ring_whitelist_reg(engine, GEN9_CS_DEBUG_MODE1); | |
1168 | if (ret) | |
1169 | return ret; | |
1170 | ||
1171 | ret = wa_ring_whitelist_reg(engine, GEN8_L3SQCREG4); | |
1172 | if (ret) | |
1173 | return ret; | |
1174 | } | |
1175 | ||
1176 | /* WaProgramL3SqcReg1DefaultForPerf:bxt */ | |
1177 | if (IS_BXT_REVID(dev_priv, BXT_REVID_B0, REVID_FOREVER)) | |
1178 | I915_WRITE(GEN8_L3SQCREG1, L3_GENERAL_PRIO_CREDITS(62) | | |
1179 | L3_HIGH_PRIO_CREDITS(2)); | |
1180 | ||
1181 | /* WaToEnableHwFixForPushConstHWBug:bxt */ | |
1182 | if (IS_BXT_REVID(dev_priv, BXT_REVID_C0, REVID_FOREVER)) | |
1183 | WA_SET_BIT_MASKED(COMMON_SLICE_CHICKEN2, | |
1184 | GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION); | |
1185 | ||
1186 | /* WaInPlaceDecompressionHang:bxt */ | |
1187 | if (IS_BXT_REVID(dev_priv, BXT_REVID_C0, REVID_FOREVER)) | |
efc886cb OM |
1188 | I915_WRITE(GEN9_GAMT_ECO_REG_RW_IA, |
1189 | (I915_READ(GEN9_GAMT_ECO_REG_RW_IA) | | |
1190 | GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS)); | |
133b4bd7 TU |
1191 | |
1192 | return 0; | |
1193 | } | |
1194 | ||
90007bca RV |
1195 | static int cnl_init_workarounds(struct intel_engine_cs *engine) |
1196 | { | |
1197 | struct drm_i915_private *dev_priv = engine->i915; | |
1198 | int ret; | |
1199 | ||
6cf20a01 | 1200 | /* WaDisableI2mCycleOnWRPort:cnl (pre-prod) */ |
86ebb015 | 1201 | if (IS_CNL_REVID(dev_priv, CNL_REVID_B0, CNL_REVID_B0)) |
6cf20a01 OM |
1202 | I915_WRITE(GAMT_CHKN_BIT_REG, |
1203 | (I915_READ(GAMT_CHKN_BIT_REG) | | |
1204 | GAMT_CHKN_DISABLE_I2M_CYCLE_ON_WR_PORT)); | |
86ebb015 | 1205 | |
acfb5554 RV |
1206 | /* WaForceContextSaveRestoreNonCoherent:cnl */ |
1207 | WA_SET_BIT_MASKED(CNL_HDC_CHICKEN0, | |
1208 | HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT); | |
1209 | ||
aa9f4c4f RV |
1210 | /* WaThrottleEUPerfToAvoidTDBackPressure:cnl(pre-prod) */ |
1211 | if (IS_CNL_REVID(dev_priv, CNL_REVID_B0, CNL_REVID_B0)) | |
1212 | WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, THROTTLE_12_5); | |
1213 | ||
e6d1a4f6 RV |
1214 | /* WaDisableReplayBufferBankArbitrationOptimization:cnl */ |
1215 | WA_SET_BIT_MASKED(COMMON_SLICE_CHICKEN2, | |
1216 | GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION); | |
1217 | ||
d1d24754 RV |
1218 | /* WaDisableEnhancedSBEVertexCaching:cnl (pre-prod) */ |
1219 | if (IS_CNL_REVID(dev_priv, 0, CNL_REVID_B0)) | |
1220 | WA_SET_BIT_MASKED(COMMON_SLICE_CHICKEN2, | |
1221 | GEN8_CSC2_SBE_VUE_CACHE_CONSERVATIVE); | |
1222 | ||
90007bca | 1223 | /* WaInPlaceDecompressionHang:cnl */ |
efc886cb OM |
1224 | I915_WRITE(GEN9_GAMT_ECO_REG_RW_IA, |
1225 | (I915_READ(GEN9_GAMT_ECO_REG_RW_IA) | | |
1226 | GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS)); | |
90007bca | 1227 | |
2cbecff4 | 1228 | /* WaPushConstantDereferenceHoldDisable:cnl */ |
b27f5901 | 1229 | WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2, PUSH_CONSTANT_DEREF_DISABLE); |
2cbecff4 | 1230 | |
392572fe RV |
1231 | /* FtrEnableFastAnisoL1BankingFix: cnl */ |
1232 | WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3, CNL_FAST_ANISO_L1_BANKING_FIX); | |
1233 | ||
90007bca RV |
1234 | /* WaEnablePreemptionGranularityControlByUMD:cnl */ |
1235 | ret= wa_ring_whitelist_reg(engine, GEN8_CS_CHICKEN1); | |
1236 | if (ret) | |
1237 | return ret; | |
1238 | ||
1239 | return 0; | |
1240 | } | |
1241 | ||
133b4bd7 TU |
1242 | static int kbl_init_workarounds(struct intel_engine_cs *engine) |
1243 | { | |
1244 | struct drm_i915_private *dev_priv = engine->i915; | |
1245 | int ret; | |
1246 | ||
1247 | ret = gen9_init_workarounds(engine); | |
1248 | if (ret) | |
1249 | return ret; | |
1250 | ||
1251 | /* WaEnableGapsTsvCreditFix:kbl */ | |
1252 | I915_WRITE(GEN8_GARBCNTL, (I915_READ(GEN8_GARBCNTL) | | |
1253 | GEN9_GAPS_TSV_CREDIT_DISABLE)); | |
1254 | ||
1255 | /* WaDisableDynamicCreditSharing:kbl */ | |
1256 | if (IS_KBL_REVID(dev_priv, 0, KBL_REVID_B0)) | |
c6ea497c OM |
1257 | I915_WRITE(GAMT_CHKN_BIT_REG, |
1258 | (I915_READ(GAMT_CHKN_BIT_REG) | | |
1259 | GAMT_CHKN_DISABLE_DYNAMIC_CREDIT_SHARING)); | |
133b4bd7 TU |
1260 | |
1261 | /* WaDisableFenceDestinationToSLM:kbl (pre-prod) */ | |
1262 | if (IS_KBL_REVID(dev_priv, KBL_REVID_A0, KBL_REVID_A0)) | |
1263 | WA_SET_BIT_MASKED(HDC_CHICKEN0, | |
1264 | HDC_FENCE_DEST_SLM_DISABLE); | |
1265 | ||
1266 | /* WaToEnableHwFixForPushConstHWBug:kbl */ | |
1267 | if (IS_KBL_REVID(dev_priv, KBL_REVID_C0, REVID_FOREVER)) | |
1268 | WA_SET_BIT_MASKED(COMMON_SLICE_CHICKEN2, | |
1269 | GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION); | |
1270 | ||
1271 | /* WaDisableGafsUnitClkGating:kbl */ | |
4827c547 OM |
1272 | I915_WRITE(GEN7_UCGCTL4, (I915_READ(GEN7_UCGCTL4) | |
1273 | GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE)); | |
133b4bd7 TU |
1274 | |
1275 | /* WaDisableSbeCacheDispatchPortSharing:kbl */ | |
1276 | WA_SET_BIT_MASKED( | |
1277 | GEN7_HALF_SLICE_CHICKEN1, | |
1278 | GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE); | |
1279 | ||
1280 | /* WaInPlaceDecompressionHang:kbl */ | |
efc886cb OM |
1281 | I915_WRITE(GEN9_GAMT_ECO_REG_RW_IA, |
1282 | (I915_READ(GEN9_GAMT_ECO_REG_RW_IA) | | |
1283 | GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS)); | |
133b4bd7 TU |
1284 | |
1285 | /* WaDisableLSQCROPERFforOCL:kbl */ | |
1286 | ret = wa_ring_whitelist_reg(engine, GEN8_L3SQCREG4); | |
1287 | if (ret) | |
1288 | return ret; | |
1289 | ||
1290 | return 0; | |
1291 | } | |
1292 | ||
1293 | static int glk_init_workarounds(struct intel_engine_cs *engine) | |
1294 | { | |
1295 | struct drm_i915_private *dev_priv = engine->i915; | |
1296 | int ret; | |
1297 | ||
1298 | ret = gen9_init_workarounds(engine); | |
1299 | if (ret) | |
1300 | return ret; | |
1301 | ||
1302 | /* WaToEnableHwFixForPushConstHWBug:glk */ | |
1303 | WA_SET_BIT_MASKED(COMMON_SLICE_CHICKEN2, | |
1304 | GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION); | |
1305 | ||
1306 | return 0; | |
1307 | } | |
1308 | ||
46c26662 RV |
1309 | static int cfl_init_workarounds(struct intel_engine_cs *engine) |
1310 | { | |
1311 | struct drm_i915_private *dev_priv = engine->i915; | |
1312 | int ret; | |
1313 | ||
1314 | ret = gen9_init_workarounds(engine); | |
1315 | if (ret) | |
1316 | return ret; | |
1317 | ||
1318 | /* WaEnableGapsTsvCreditFix:cfl */ | |
1319 | I915_WRITE(GEN8_GARBCNTL, (I915_READ(GEN8_GARBCNTL) | | |
1320 | GEN9_GAPS_TSV_CREDIT_DISABLE)); | |
1321 | ||
1322 | /* WaToEnableHwFixForPushConstHWBug:cfl */ | |
1323 | WA_SET_BIT_MASKED(COMMON_SLICE_CHICKEN2, | |
1324 | GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION); | |
1325 | ||
1326 | /* WaDisableGafsUnitClkGating:cfl */ | |
4827c547 OM |
1327 | I915_WRITE(GEN7_UCGCTL4, (I915_READ(GEN7_UCGCTL4) | |
1328 | GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE)); | |
46c26662 RV |
1329 | |
1330 | /* WaDisableSbeCacheDispatchPortSharing:cfl */ | |
1331 | WA_SET_BIT_MASKED( | |
1332 | GEN7_HALF_SLICE_CHICKEN1, | |
1333 | GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE); | |
1334 | ||
1335 | /* WaInPlaceDecompressionHang:cfl */ | |
efc886cb OM |
1336 | I915_WRITE(GEN9_GAMT_ECO_REG_RW_IA, |
1337 | (I915_READ(GEN9_GAMT_ECO_REG_RW_IA) | | |
1338 | GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS)); | |
46c26662 RV |
1339 | |
1340 | return 0; | |
1341 | } | |
1342 | ||
133b4bd7 TU |
1343 | int init_workarounds_ring(struct intel_engine_cs *engine) |
1344 | { | |
1345 | struct drm_i915_private *dev_priv = engine->i915; | |
02e012f1 | 1346 | int err; |
133b4bd7 TU |
1347 | |
1348 | WARN_ON(engine->id != RCS); | |
1349 | ||
1350 | dev_priv->workarounds.count = 0; | |
02e012f1 | 1351 | dev_priv->workarounds.hw_whitelist_count[engine->id] = 0; |
133b4bd7 TU |
1352 | |
1353 | if (IS_BROADWELL(dev_priv)) | |
02e012f1 CW |
1354 | err = bdw_init_workarounds(engine); |
1355 | else if (IS_CHERRYVIEW(dev_priv)) | |
1356 | err = chv_init_workarounds(engine); | |
1357 | else if (IS_SKYLAKE(dev_priv)) | |
1358 | err = skl_init_workarounds(engine); | |
1359 | else if (IS_BROXTON(dev_priv)) | |
1360 | err = bxt_init_workarounds(engine); | |
1361 | else if (IS_KABYLAKE(dev_priv)) | |
1362 | err = kbl_init_workarounds(engine); | |
1363 | else if (IS_GEMINILAKE(dev_priv)) | |
1364 | err = glk_init_workarounds(engine); | |
46c26662 RV |
1365 | else if (IS_COFFEELAKE(dev_priv)) |
1366 | err = cfl_init_workarounds(engine); | |
90007bca RV |
1367 | else if (IS_CANNONLAKE(dev_priv)) |
1368 | err = cnl_init_workarounds(engine); | |
02e012f1 CW |
1369 | else |
1370 | err = 0; | |
1371 | if (err) | |
1372 | return err; | |
133b4bd7 | 1373 | |
02e012f1 CW |
1374 | DRM_DEBUG_DRIVER("%s: Number of context specific w/a: %d\n", |
1375 | engine->name, dev_priv->workarounds.count); | |
133b4bd7 TU |
1376 | return 0; |
1377 | } | |
1378 | ||
1379 | int intel_ring_workarounds_emit(struct drm_i915_gem_request *req) | |
1380 | { | |
1381 | struct i915_workarounds *w = &req->i915->workarounds; | |
1382 | u32 *cs; | |
1383 | int ret, i; | |
1384 | ||
1385 | if (w->count == 0) | |
1386 | return 0; | |
1387 | ||
1388 | ret = req->engine->emit_flush(req, EMIT_BARRIER); | |
1389 | if (ret) | |
1390 | return ret; | |
1391 | ||
1392 | cs = intel_ring_begin(req, (w->count * 2 + 2)); | |
1393 | if (IS_ERR(cs)) | |
1394 | return PTR_ERR(cs); | |
1395 | ||
1396 | *cs++ = MI_LOAD_REGISTER_IMM(w->count); | |
1397 | for (i = 0; i < w->count; i++) { | |
1398 | *cs++ = i915_mmio_reg_offset(w->reg[i].addr); | |
1399 | *cs++ = w->reg[i].value; | |
1400 | } | |
1401 | *cs++ = MI_NOOP; | |
1402 | ||
1403 | intel_ring_advance(req, cs); | |
1404 | ||
1405 | ret = req->engine->emit_flush(req, EMIT_BARRIER); | |
1406 | if (ret) | |
1407 | return ret; | |
1408 | ||
133b4bd7 TU |
1409 | return 0; |
1410 | } | |
1411 | ||
a091d4ee CW |
1412 | static bool ring_is_idle(struct intel_engine_cs *engine) |
1413 | { | |
1414 | struct drm_i915_private *dev_priv = engine->i915; | |
1415 | bool idle = true; | |
1416 | ||
1417 | intel_runtime_pm_get(dev_priv); | |
1418 | ||
aed2fc10 CW |
1419 | /* First check that no commands are left in the ring */ |
1420 | if ((I915_READ_HEAD(engine) & HEAD_ADDR) != | |
1421 | (I915_READ_TAIL(engine) & TAIL_ADDR)) | |
1422 | idle = false; | |
1423 | ||
a091d4ee CW |
1424 | /* No bit for gen2, so assume the CS parser is idle */ |
1425 | if (INTEL_GEN(dev_priv) > 2 && !(I915_READ_MODE(engine) & MODE_IDLE)) | |
1426 | idle = false; | |
1427 | ||
1428 | intel_runtime_pm_put(dev_priv); | |
1429 | ||
1430 | return idle; | |
1431 | } | |
1432 | ||
5400367a CW |
1433 | /** |
1434 | * intel_engine_is_idle() - Report if the engine has finished process all work | |
1435 | * @engine: the intel_engine_cs | |
1436 | * | |
1437 | * Return true if there are no requests pending, nothing left to be submitted | |
1438 | * to hardware, and that the engine is idle. | |
1439 | */ | |
1440 | bool intel_engine_is_idle(struct intel_engine_cs *engine) | |
1441 | { | |
1442 | struct drm_i915_private *dev_priv = engine->i915; | |
1443 | ||
a8e9a419 CW |
1444 | /* More white lies, if wedged, hw state is inconsistent */ |
1445 | if (i915_terminally_wedged(&dev_priv->gpu_error)) | |
1446 | return true; | |
1447 | ||
5400367a CW |
1448 | /* Any inflight/incomplete requests? */ |
1449 | if (!i915_seqno_passed(intel_engine_get_seqno(engine), | |
1450 | intel_engine_last_submit(engine))) | |
1451 | return false; | |
1452 | ||
8968a364 CW |
1453 | if (I915_SELFTEST_ONLY(engine->breadcrumbs.mock)) |
1454 | return true; | |
1455 | ||
5400367a CW |
1456 | /* Interrupt/tasklet pending? */ |
1457 | if (test_bit(ENGINE_IRQ_EXECLIST, &engine->irq_posted)) | |
1458 | return false; | |
1459 | ||
1460 | /* Both ports drained, no more ELSP submission? */ | |
77f0d0e9 | 1461 | if (port_request(&engine->execlist_port[0])) |
5400367a CW |
1462 | return false; |
1463 | ||
d6edb6e3 CW |
1464 | /* ELSP is empty, but there are ready requests? */ |
1465 | if (READ_ONCE(engine->execlist_first)) | |
1466 | return false; | |
1467 | ||
5400367a | 1468 | /* Ring stopped? */ |
a091d4ee | 1469 | if (!ring_is_idle(engine)) |
5400367a CW |
1470 | return false; |
1471 | ||
1472 | return true; | |
1473 | } | |
1474 | ||
05425249 CW |
1475 | bool intel_engines_are_idle(struct drm_i915_private *dev_priv) |
1476 | { | |
1477 | struct intel_engine_cs *engine; | |
1478 | enum intel_engine_id id; | |
1479 | ||
8490ae20 CW |
1480 | if (READ_ONCE(dev_priv->gt.active_requests)) |
1481 | return false; | |
1482 | ||
1483 | /* If the driver is wedged, HW state may be very inconsistent and | |
1484 | * report that it is still busy, even though we have stopped using it. | |
1485 | */ | |
1486 | if (i915_terminally_wedged(&dev_priv->gpu_error)) | |
1487 | return true; | |
1488 | ||
05425249 CW |
1489 | for_each_engine(engine, dev_priv, id) { |
1490 | if (!intel_engine_is_idle(engine)) | |
1491 | return false; | |
1492 | } | |
1493 | ||
1494 | return true; | |
1495 | } | |
1496 | ||
ff44ad51 CW |
1497 | void intel_engines_reset_default_submission(struct drm_i915_private *i915) |
1498 | { | |
1499 | struct intel_engine_cs *engine; | |
1500 | enum intel_engine_id id; | |
1501 | ||
1502 | for_each_engine(engine, i915, id) | |
1503 | engine->set_default_submission(engine); | |
1504 | } | |
1505 | ||
6c067579 CW |
1506 | void intel_engines_mark_idle(struct drm_i915_private *i915) |
1507 | { | |
1508 | struct intel_engine_cs *engine; | |
1509 | enum intel_engine_id id; | |
1510 | ||
1511 | for_each_engine(engine, i915, id) { | |
1512 | intel_engine_disarm_breadcrumbs(engine); | |
1513 | i915_gem_batch_pool_fini(&engine->batch_pool); | |
9cd90018 | 1514 | tasklet_kill(&engine->irq_tasklet); |
6c067579 CW |
1515 | engine->no_priolist = false; |
1516 | } | |
1517 | } | |
1518 | ||
90cad095 CW |
1519 | bool intel_engine_can_store_dword(struct intel_engine_cs *engine) |
1520 | { | |
1521 | switch (INTEL_GEN(engine->i915)) { | |
1522 | case 2: | |
1523 | return false; /* uses physical not virtual addresses */ | |
1524 | case 3: | |
1525 | /* maybe only uses physical not virtual addresses */ | |
1526 | return !(IS_I915G(engine->i915) || IS_I915GM(engine->i915)); | |
1527 | case 6: | |
1528 | return engine->class != VIDEO_DECODE_CLASS; /* b0rked */ | |
1529 | default: | |
1530 | return true; | |
1531 | } | |
1532 | } | |
1533 | ||
f97fbf96 CW |
1534 | #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST) |
1535 | #include "selftests/mock_engine.c" | |
1536 | #endif |