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88d2ba2e TU |
1 | /* |
2 | * Copyright © 2016 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | */ | |
24 | ||
25 | #include "i915_drv.h" | |
26 | #include "intel_ringbuffer.h" | |
27 | #include "intel_lrc.h" | |
28 | ||
29 | static const struct engine_info { | |
30 | const char *name; | |
237ae7c7 MW |
31 | unsigned int exec_id; |
32 | unsigned int hw_id; | |
88d2ba2e TU |
33 | u32 mmio_base; |
34 | unsigned irq_shift; | |
35 | int (*init_legacy)(struct intel_engine_cs *engine); | |
36 | int (*init_execlists)(struct intel_engine_cs *engine); | |
37 | } intel_engines[] = { | |
38 | [RCS] = { | |
39 | .name = "render ring", | |
40 | .exec_id = I915_EXEC_RENDER, | |
5ec2cf7e | 41 | .hw_id = RCS_HW, |
88d2ba2e TU |
42 | .mmio_base = RENDER_RING_BASE, |
43 | .irq_shift = GEN8_RCS_IRQ_SHIFT, | |
44 | .init_execlists = logical_render_ring_init, | |
45 | .init_legacy = intel_init_render_ring_buffer, | |
46 | }, | |
47 | [BCS] = { | |
48 | .name = "blitter ring", | |
49 | .exec_id = I915_EXEC_BLT, | |
5ec2cf7e | 50 | .hw_id = BCS_HW, |
88d2ba2e TU |
51 | .mmio_base = BLT_RING_BASE, |
52 | .irq_shift = GEN8_BCS_IRQ_SHIFT, | |
53 | .init_execlists = logical_xcs_ring_init, | |
54 | .init_legacy = intel_init_blt_ring_buffer, | |
55 | }, | |
56 | [VCS] = { | |
57 | .name = "bsd ring", | |
58 | .exec_id = I915_EXEC_BSD, | |
5ec2cf7e | 59 | .hw_id = VCS_HW, |
88d2ba2e TU |
60 | .mmio_base = GEN6_BSD_RING_BASE, |
61 | .irq_shift = GEN8_VCS1_IRQ_SHIFT, | |
62 | .init_execlists = logical_xcs_ring_init, | |
63 | .init_legacy = intel_init_bsd_ring_buffer, | |
64 | }, | |
65 | [VCS2] = { | |
66 | .name = "bsd2 ring", | |
67 | .exec_id = I915_EXEC_BSD, | |
5ec2cf7e | 68 | .hw_id = VCS2_HW, |
88d2ba2e TU |
69 | .mmio_base = GEN8_BSD2_RING_BASE, |
70 | .irq_shift = GEN8_VCS2_IRQ_SHIFT, | |
71 | .init_execlists = logical_xcs_ring_init, | |
72 | .init_legacy = intel_init_bsd2_ring_buffer, | |
73 | }, | |
74 | [VECS] = { | |
75 | .name = "video enhancement ring", | |
76 | .exec_id = I915_EXEC_VEBOX, | |
5ec2cf7e | 77 | .hw_id = VECS_HW, |
88d2ba2e TU |
78 | .mmio_base = VEBOX_RING_BASE, |
79 | .irq_shift = GEN8_VECS_IRQ_SHIFT, | |
80 | .init_execlists = logical_xcs_ring_init, | |
81 | .init_legacy = intel_init_vebox_ring_buffer, | |
82 | }, | |
83 | }; | |
84 | ||
3b3f1650 | 85 | static int |
88d2ba2e TU |
86 | intel_engine_setup(struct drm_i915_private *dev_priv, |
87 | enum intel_engine_id id) | |
88 | { | |
89 | const struct engine_info *info = &intel_engines[id]; | |
3b3f1650 AG |
90 | struct intel_engine_cs *engine; |
91 | ||
92 | GEM_BUG_ON(dev_priv->engine[id]); | |
93 | engine = kzalloc(sizeof(*engine), GFP_KERNEL); | |
94 | if (!engine) | |
95 | return -ENOMEM; | |
88d2ba2e TU |
96 | |
97 | engine->id = id; | |
98 | engine->i915 = dev_priv; | |
99 | engine->name = info->name; | |
100 | engine->exec_id = info->exec_id; | |
5ec2cf7e | 101 | engine->hw_id = engine->guc_id = info->hw_id; |
88d2ba2e TU |
102 | engine->mmio_base = info->mmio_base; |
103 | engine->irq_shift = info->irq_shift; | |
104 | ||
0de9136d CW |
105 | /* Nothing to do here, execute in order of dependencies */ |
106 | engine->schedule = NULL; | |
107 | ||
3b3f1650 AG |
108 | dev_priv->engine[id] = engine; |
109 | return 0; | |
88d2ba2e TU |
110 | } |
111 | ||
112 | /** | |
bb8f0f5a | 113 | * intel_engines_init_early() - allocate the Engine Command Streamers |
bf9e8429 | 114 | * @dev_priv: i915 device private |
88d2ba2e TU |
115 | * |
116 | * Return: non-zero if the initialization failed. | |
117 | */ | |
bb8f0f5a | 118 | int intel_engines_init_early(struct drm_i915_private *dev_priv) |
88d2ba2e | 119 | { |
c1bb1145 | 120 | struct intel_device_info *device_info = mkwrite_device_info(dev_priv); |
70006ad6 | 121 | unsigned int ring_mask = INTEL_INFO(dev_priv)->ring_mask; |
88d2ba2e | 122 | unsigned int mask = 0; |
3b3f1650 AG |
123 | struct intel_engine_cs *engine; |
124 | enum intel_engine_id id; | |
88d2ba2e | 125 | unsigned int i; |
bb8f0f5a | 126 | int err; |
88d2ba2e | 127 | |
70006ad6 TU |
128 | WARN_ON(ring_mask == 0); |
129 | WARN_ON(ring_mask & | |
88d2ba2e TU |
130 | GENMASK(sizeof(mask) * BITS_PER_BYTE - 1, I915_NUM_ENGINES)); |
131 | ||
132 | for (i = 0; i < ARRAY_SIZE(intel_engines); i++) { | |
133 | if (!HAS_ENGINE(dev_priv, i)) | |
134 | continue; | |
135 | ||
bb8f0f5a CW |
136 | err = intel_engine_setup(dev_priv, i); |
137 | if (err) | |
138 | goto cleanup; | |
139 | ||
140 | mask |= ENGINE_MASK(i); | |
141 | } | |
142 | ||
143 | /* | |
144 | * Catch failures to update intel_engines table when the new engines | |
145 | * are added to the driver by a warning and disabling the forgotten | |
146 | * engines. | |
147 | */ | |
148 | if (WARN_ON(mask != ring_mask)) | |
149 | device_info->ring_mask = mask; | |
150 | ||
151 | device_info->num_rings = hweight32(mask); | |
152 | ||
153 | return 0; | |
154 | ||
155 | cleanup: | |
156 | for_each_engine(engine, dev_priv, id) | |
157 | kfree(engine); | |
158 | return err; | |
159 | } | |
160 | ||
161 | /** | |
162 | * intel_engines_init() - allocate, populate and init the Engine Command Streamers | |
163 | * @dev_priv: i915 device private | |
164 | * | |
165 | * Return: non-zero if the initialization failed. | |
166 | */ | |
167 | int intel_engines_init(struct drm_i915_private *dev_priv) | |
168 | { | |
169 | struct intel_device_info *device_info = mkwrite_device_info(dev_priv); | |
170 | struct intel_engine_cs *engine; | |
171 | enum intel_engine_id id, err_id; | |
172 | unsigned int mask = 0; | |
173 | int err = 0; | |
174 | ||
175 | for_each_engine(engine, dev_priv, id) { | |
176 | int (*init)(struct intel_engine_cs *engine); | |
177 | ||
88d2ba2e | 178 | if (i915.enable_execlists) |
bb8f0f5a | 179 | init = intel_engines[id].init_execlists; |
88d2ba2e | 180 | else |
bb8f0f5a CW |
181 | init = intel_engines[id].init_legacy; |
182 | if (!init) { | |
183 | kfree(engine); | |
184 | dev_priv->engine[id] = NULL; | |
88d2ba2e | 185 | continue; |
bb8f0f5a | 186 | } |
88d2ba2e | 187 | |
bb8f0f5a CW |
188 | err = init(engine); |
189 | if (err) { | |
190 | err_id = id; | |
88d2ba2e | 191 | goto cleanup; |
bb8f0f5a | 192 | } |
88d2ba2e | 193 | |
bb8f0f5a | 194 | mask |= ENGINE_MASK(id); |
88d2ba2e TU |
195 | } |
196 | ||
197 | /* | |
198 | * Catch failures to update intel_engines table when the new engines | |
199 | * are added to the driver by a warning and disabling the forgotten | |
200 | * engines. | |
201 | */ | |
bb8f0f5a | 202 | if (WARN_ON(mask != INTEL_INFO(dev_priv)->ring_mask)) |
c1bb1145 TU |
203 | device_info->ring_mask = mask; |
204 | ||
205 | device_info->num_rings = hweight32(mask); | |
88d2ba2e TU |
206 | |
207 | return 0; | |
208 | ||
209 | cleanup: | |
3b3f1650 | 210 | for_each_engine(engine, dev_priv, id) { |
bb8f0f5a CW |
211 | if (id >= err_id) |
212 | kfree(engine); | |
88d2ba2e | 213 | else |
8ee7c6e2 | 214 | dev_priv->gt.cleanup_engine(engine); |
88d2ba2e | 215 | } |
bb8f0f5a | 216 | return err; |
88d2ba2e TU |
217 | } |
218 | ||
73cb9701 | 219 | void intel_engine_init_global_seqno(struct intel_engine_cs *engine, u32 seqno) |
57f275a2 CW |
220 | { |
221 | struct drm_i915_private *dev_priv = engine->i915; | |
222 | ||
223 | /* Our semaphore implementation is strictly monotonic (i.e. we proceed | |
224 | * so long as the semaphore value in the register/page is greater | |
225 | * than the sync value), so whenever we reset the seqno, | |
226 | * so long as we reset the tracking semaphore value to 0, it will | |
227 | * always be before the next request's seqno. If we don't reset | |
228 | * the semaphore value, then when the seqno moves backwards all | |
229 | * future waits will complete instantly (causing rendering corruption). | |
230 | */ | |
231 | if (IS_GEN6(dev_priv) || IS_GEN7(dev_priv)) { | |
232 | I915_WRITE(RING_SYNC_0(engine->mmio_base), 0); | |
233 | I915_WRITE(RING_SYNC_1(engine->mmio_base), 0); | |
234 | if (HAS_VEBOX(dev_priv)) | |
235 | I915_WRITE(RING_SYNC_2(engine->mmio_base), 0); | |
236 | } | |
51d545d0 CW |
237 | if (dev_priv->semaphore) { |
238 | struct page *page = i915_vma_first_page(dev_priv->semaphore); | |
239 | void *semaphores; | |
240 | ||
241 | /* Semaphores are in noncoherent memory, flush to be safe */ | |
242 | semaphores = kmap(page); | |
57f275a2 CW |
243 | memset(semaphores + GEN8_SEMAPHORE_OFFSET(engine->id, 0), |
244 | 0, I915_NUM_ENGINES * gen8_semaphore_seqno_size); | |
51d545d0 CW |
245 | drm_clflush_virt_range(semaphores + GEN8_SEMAPHORE_OFFSET(engine->id, 0), |
246 | I915_NUM_ENGINES * gen8_semaphore_seqno_size); | |
57f275a2 CW |
247 | kunmap(page); |
248 | } | |
57f275a2 CW |
249 | |
250 | intel_write_status_page(engine, I915_GEM_HWS_INDEX, seqno); | |
251 | if (engine->irq_seqno_barrier) | |
252 | engine->irq_seqno_barrier(engine); | |
73cb9701 CW |
253 | |
254 | GEM_BUG_ON(i915_gem_active_isset(&engine->timeline->last_request)); | |
57f275a2 CW |
255 | engine->hangcheck.seqno = seqno; |
256 | ||
257 | /* After manually advancing the seqno, fake the interrupt in case | |
258 | * there are any waiters for that seqno. | |
259 | */ | |
260 | intel_engine_wakeup(engine); | |
261 | } | |
262 | ||
73cb9701 | 263 | static void intel_engine_init_timeline(struct intel_engine_cs *engine) |
dcff85c8 | 264 | { |
73cb9701 | 265 | engine->timeline = &engine->i915->gt.global_timeline.engine[engine->id]; |
dcff85c8 CW |
266 | } |
267 | ||
019bf277 TU |
268 | /** |
269 | * intel_engines_setup_common - setup engine state not requiring hw access | |
270 | * @engine: Engine to setup. | |
271 | * | |
272 | * Initializes @engine@ structure members shared between legacy and execlists | |
273 | * submission modes which do not require hardware access. | |
274 | * | |
275 | * Typically done early in the submission mode specific engine setup stage. | |
276 | */ | |
277 | void intel_engine_setup_common(struct intel_engine_cs *engine) | |
278 | { | |
20311bd3 CW |
279 | engine->execlist_queue = RB_ROOT; |
280 | engine->execlist_first = NULL; | |
019bf277 | 281 | |
73cb9701 | 282 | intel_engine_init_timeline(engine); |
019bf277 | 283 | intel_engine_init_hangcheck(engine); |
115003e9 | 284 | i915_gem_batch_pool_init(engine, &engine->batch_pool); |
7756e454 CW |
285 | |
286 | intel_engine_init_cmd_parser(engine); | |
019bf277 TU |
287 | } |
288 | ||
adc320c4 CW |
289 | int intel_engine_create_scratch(struct intel_engine_cs *engine, int size) |
290 | { | |
291 | struct drm_i915_gem_object *obj; | |
292 | struct i915_vma *vma; | |
293 | int ret; | |
294 | ||
295 | WARN_ON(engine->scratch); | |
296 | ||
187685cb | 297 | obj = i915_gem_object_create_stolen(engine->i915, size); |
adc320c4 | 298 | if (!obj) |
920cf419 | 299 | obj = i915_gem_object_create_internal(engine->i915, size); |
adc320c4 CW |
300 | if (IS_ERR(obj)) { |
301 | DRM_ERROR("Failed to allocate scratch page\n"); | |
302 | return PTR_ERR(obj); | |
303 | } | |
304 | ||
a01cb37a | 305 | vma = i915_vma_instance(obj, &engine->i915->ggtt.base, NULL); |
adc320c4 CW |
306 | if (IS_ERR(vma)) { |
307 | ret = PTR_ERR(vma); | |
308 | goto err_unref; | |
309 | } | |
310 | ||
311 | ret = i915_vma_pin(vma, 0, 4096, PIN_GLOBAL | PIN_HIGH); | |
312 | if (ret) | |
313 | goto err_unref; | |
314 | ||
315 | engine->scratch = vma; | |
bde13ebd CW |
316 | DRM_DEBUG_DRIVER("%s pipe control offset: 0x%08x\n", |
317 | engine->name, i915_ggtt_offset(vma)); | |
adc320c4 CW |
318 | return 0; |
319 | ||
320 | err_unref: | |
321 | i915_gem_object_put(obj); | |
322 | return ret; | |
323 | } | |
324 | ||
325 | static void intel_engine_cleanup_scratch(struct intel_engine_cs *engine) | |
326 | { | |
19880c4a | 327 | i915_vma_unpin_and_release(&engine->scratch); |
adc320c4 CW |
328 | } |
329 | ||
019bf277 TU |
330 | /** |
331 | * intel_engines_init_common - initialize cengine state which might require hw access | |
332 | * @engine: Engine to initialize. | |
333 | * | |
334 | * Initializes @engine@ structure members shared between legacy and execlists | |
335 | * submission modes which do require hardware access. | |
336 | * | |
337 | * Typcally done at later stages of submission mode specific engine setup. | |
338 | * | |
339 | * Returns zero on success or an error code on failure. | |
340 | */ | |
341 | int intel_engine_init_common(struct intel_engine_cs *engine) | |
342 | { | |
343 | int ret; | |
344 | ||
e8a9c58f CW |
345 | /* We may need to do things with the shrinker which |
346 | * require us to immediately switch back to the default | |
347 | * context. This can cause a problem as pinning the | |
348 | * default context also requires GTT space which may not | |
349 | * be available. To avoid this we always pin the default | |
350 | * context. | |
351 | */ | |
352 | ret = engine->context_pin(engine, engine->i915->kernel_context); | |
019bf277 TU |
353 | if (ret) |
354 | return ret; | |
355 | ||
e8a9c58f CW |
356 | ret = intel_engine_init_breadcrumbs(engine); |
357 | if (ret) | |
358 | goto err_unpin; | |
359 | ||
4e50f082 CW |
360 | ret = i915_gem_render_state_init(engine); |
361 | if (ret) | |
e8a9c58f | 362 | goto err_unpin; |
4e50f082 | 363 | |
7756e454 | 364 | return 0; |
e8a9c58f CW |
365 | |
366 | err_unpin: | |
367 | engine->context_unpin(engine, engine->i915->kernel_context); | |
368 | return ret; | |
019bf277 | 369 | } |
96a945aa CW |
370 | |
371 | /** | |
372 | * intel_engines_cleanup_common - cleans up the engine state created by | |
373 | * the common initiailizers. | |
374 | * @engine: Engine to cleanup. | |
375 | * | |
376 | * This cleans up everything created by the common helpers. | |
377 | */ | |
378 | void intel_engine_cleanup_common(struct intel_engine_cs *engine) | |
379 | { | |
adc320c4 CW |
380 | intel_engine_cleanup_scratch(engine); |
381 | ||
4e50f082 | 382 | i915_gem_render_state_fini(engine); |
96a945aa | 383 | intel_engine_fini_breadcrumbs(engine); |
7756e454 | 384 | intel_engine_cleanup_cmd_parser(engine); |
96a945aa | 385 | i915_gem_batch_pool_fini(&engine->batch_pool); |
e8a9c58f CW |
386 | |
387 | engine->context_unpin(engine, engine->i915->kernel_context); | |
96a945aa | 388 | } |
1b36595f CW |
389 | |
390 | u64 intel_engine_get_active_head(struct intel_engine_cs *engine) | |
391 | { | |
392 | struct drm_i915_private *dev_priv = engine->i915; | |
393 | u64 acthd; | |
394 | ||
395 | if (INTEL_GEN(dev_priv) >= 8) | |
396 | acthd = I915_READ64_2x32(RING_ACTHD(engine->mmio_base), | |
397 | RING_ACTHD_UDW(engine->mmio_base)); | |
398 | else if (INTEL_GEN(dev_priv) >= 4) | |
399 | acthd = I915_READ(RING_ACTHD(engine->mmio_base)); | |
400 | else | |
401 | acthd = I915_READ(ACTHD); | |
402 | ||
403 | return acthd; | |
404 | } | |
405 | ||
406 | u64 intel_engine_get_last_batch_head(struct intel_engine_cs *engine) | |
407 | { | |
408 | struct drm_i915_private *dev_priv = engine->i915; | |
409 | u64 bbaddr; | |
410 | ||
411 | if (INTEL_GEN(dev_priv) >= 8) | |
412 | bbaddr = I915_READ64_2x32(RING_BBADDR(engine->mmio_base), | |
413 | RING_BBADDR_UDW(engine->mmio_base)); | |
414 | else | |
415 | bbaddr = I915_READ(RING_BBADDR(engine->mmio_base)); | |
416 | ||
417 | return bbaddr; | |
418 | } | |
0e704476 CW |
419 | |
420 | const char *i915_cache_level_str(struct drm_i915_private *i915, int type) | |
421 | { | |
422 | switch (type) { | |
423 | case I915_CACHE_NONE: return " uncached"; | |
424 | case I915_CACHE_LLC: return HAS_LLC(i915) ? " LLC" : " snooped"; | |
425 | case I915_CACHE_L3_LLC: return " L3+LLC"; | |
426 | case I915_CACHE_WT: return " WT"; | |
427 | default: return ""; | |
428 | } | |
429 | } | |
430 | ||
431 | static inline uint32_t | |
432 | read_subslice_reg(struct drm_i915_private *dev_priv, int slice, | |
433 | int subslice, i915_reg_t reg) | |
434 | { | |
435 | uint32_t mcr; | |
436 | uint32_t ret; | |
437 | enum forcewake_domains fw_domains; | |
438 | ||
439 | fw_domains = intel_uncore_forcewake_for_reg(dev_priv, reg, | |
440 | FW_REG_READ); | |
441 | fw_domains |= intel_uncore_forcewake_for_reg(dev_priv, | |
442 | GEN8_MCR_SELECTOR, | |
443 | FW_REG_READ | FW_REG_WRITE); | |
444 | ||
445 | spin_lock_irq(&dev_priv->uncore.lock); | |
446 | intel_uncore_forcewake_get__locked(dev_priv, fw_domains); | |
447 | ||
448 | mcr = I915_READ_FW(GEN8_MCR_SELECTOR); | |
449 | /* | |
450 | * The HW expects the slice and sublice selectors to be reset to 0 | |
451 | * after reading out the registers. | |
452 | */ | |
453 | WARN_ON_ONCE(mcr & (GEN8_MCR_SLICE_MASK | GEN8_MCR_SUBSLICE_MASK)); | |
454 | mcr &= ~(GEN8_MCR_SLICE_MASK | GEN8_MCR_SUBSLICE_MASK); | |
455 | mcr |= GEN8_MCR_SLICE(slice) | GEN8_MCR_SUBSLICE(subslice); | |
456 | I915_WRITE_FW(GEN8_MCR_SELECTOR, mcr); | |
457 | ||
458 | ret = I915_READ_FW(reg); | |
459 | ||
460 | mcr &= ~(GEN8_MCR_SLICE_MASK | GEN8_MCR_SUBSLICE_MASK); | |
461 | I915_WRITE_FW(GEN8_MCR_SELECTOR, mcr); | |
462 | ||
463 | intel_uncore_forcewake_put__locked(dev_priv, fw_domains); | |
464 | spin_unlock_irq(&dev_priv->uncore.lock); | |
465 | ||
466 | return ret; | |
467 | } | |
468 | ||
469 | /* NB: please notice the memset */ | |
470 | void intel_engine_get_instdone(struct intel_engine_cs *engine, | |
471 | struct intel_instdone *instdone) | |
472 | { | |
473 | struct drm_i915_private *dev_priv = engine->i915; | |
474 | u32 mmio_base = engine->mmio_base; | |
475 | int slice; | |
476 | int subslice; | |
477 | ||
478 | memset(instdone, 0, sizeof(*instdone)); | |
479 | ||
480 | switch (INTEL_GEN(dev_priv)) { | |
481 | default: | |
482 | instdone->instdone = I915_READ(RING_INSTDONE(mmio_base)); | |
483 | ||
484 | if (engine->id != RCS) | |
485 | break; | |
486 | ||
487 | instdone->slice_common = I915_READ(GEN7_SC_INSTDONE); | |
488 | for_each_instdone_slice_subslice(dev_priv, slice, subslice) { | |
489 | instdone->sampler[slice][subslice] = | |
490 | read_subslice_reg(dev_priv, slice, subslice, | |
491 | GEN7_SAMPLER_INSTDONE); | |
492 | instdone->row[slice][subslice] = | |
493 | read_subslice_reg(dev_priv, slice, subslice, | |
494 | GEN7_ROW_INSTDONE); | |
495 | } | |
496 | break; | |
497 | case 7: | |
498 | instdone->instdone = I915_READ(RING_INSTDONE(mmio_base)); | |
499 | ||
500 | if (engine->id != RCS) | |
501 | break; | |
502 | ||
503 | instdone->slice_common = I915_READ(GEN7_SC_INSTDONE); | |
504 | instdone->sampler[0][0] = I915_READ(GEN7_SAMPLER_INSTDONE); | |
505 | instdone->row[0][0] = I915_READ(GEN7_ROW_INSTDONE); | |
506 | ||
507 | break; | |
508 | case 6: | |
509 | case 5: | |
510 | case 4: | |
511 | instdone->instdone = I915_READ(RING_INSTDONE(mmio_base)); | |
512 | ||
513 | if (engine->id == RCS) | |
514 | /* HACK: Using the wrong struct member */ | |
515 | instdone->slice_common = I915_READ(GEN4_INSTDONE1); | |
516 | break; | |
517 | case 3: | |
518 | case 2: | |
519 | instdone->instdone = I915_READ(GEN2_INSTDONE); | |
520 | break; | |
521 | } | |
522 | } | |
f97fbf96 | 523 | |
133b4bd7 TU |
524 | static int wa_add(struct drm_i915_private *dev_priv, |
525 | i915_reg_t addr, | |
526 | const u32 mask, const u32 val) | |
527 | { | |
528 | const u32 idx = dev_priv->workarounds.count; | |
529 | ||
530 | if (WARN_ON(idx >= I915_MAX_WA_REGS)) | |
531 | return -ENOSPC; | |
532 | ||
533 | dev_priv->workarounds.reg[idx].addr = addr; | |
534 | dev_priv->workarounds.reg[idx].value = val; | |
535 | dev_priv->workarounds.reg[idx].mask = mask; | |
536 | ||
537 | dev_priv->workarounds.count++; | |
538 | ||
539 | return 0; | |
540 | } | |
541 | ||
542 | #define WA_REG(addr, mask, val) do { \ | |
543 | const int r = wa_add(dev_priv, (addr), (mask), (val)); \ | |
544 | if (r) \ | |
545 | return r; \ | |
546 | } while (0) | |
547 | ||
548 | #define WA_SET_BIT_MASKED(addr, mask) \ | |
549 | WA_REG(addr, (mask), _MASKED_BIT_ENABLE(mask)) | |
550 | ||
551 | #define WA_CLR_BIT_MASKED(addr, mask) \ | |
552 | WA_REG(addr, (mask), _MASKED_BIT_DISABLE(mask)) | |
553 | ||
554 | #define WA_SET_FIELD_MASKED(addr, mask, value) \ | |
555 | WA_REG(addr, mask, _MASKED_FIELD(mask, value)) | |
556 | ||
557 | #define WA_SET_BIT(addr, mask) WA_REG(addr, mask, I915_READ(addr) | (mask)) | |
558 | #define WA_CLR_BIT(addr, mask) WA_REG(addr, mask, I915_READ(addr) & ~(mask)) | |
559 | ||
560 | #define WA_WRITE(addr, val) WA_REG(addr, 0xffffffff, val) | |
561 | ||
562 | static int wa_ring_whitelist_reg(struct intel_engine_cs *engine, | |
563 | i915_reg_t reg) | |
564 | { | |
565 | struct drm_i915_private *dev_priv = engine->i915; | |
566 | struct i915_workarounds *wa = &dev_priv->workarounds; | |
567 | const uint32_t index = wa->hw_whitelist_count[engine->id]; | |
568 | ||
569 | if (WARN_ON(index >= RING_MAX_NONPRIV_SLOTS)) | |
570 | return -EINVAL; | |
571 | ||
572 | WA_WRITE(RING_FORCE_TO_NONPRIV(engine->mmio_base, index), | |
573 | i915_mmio_reg_offset(reg)); | |
574 | wa->hw_whitelist_count[engine->id]++; | |
575 | ||
576 | return 0; | |
577 | } | |
578 | ||
579 | static int gen8_init_workarounds(struct intel_engine_cs *engine) | |
580 | { | |
581 | struct drm_i915_private *dev_priv = engine->i915; | |
582 | ||
583 | WA_SET_BIT_MASKED(INSTPM, INSTPM_FORCE_ORDERING); | |
584 | ||
585 | /* WaDisableAsyncFlipPerfMode:bdw,chv */ | |
586 | WA_SET_BIT_MASKED(MI_MODE, ASYNC_FLIP_PERF_DISABLE); | |
587 | ||
588 | /* WaDisablePartialInstShootdown:bdw,chv */ | |
589 | WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, | |
590 | PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE); | |
591 | ||
592 | /* Use Force Non-Coherent whenever executing a 3D context. This is a | |
593 | * workaround for for a possible hang in the unlikely event a TLB | |
594 | * invalidation occurs during a PSD flush. | |
595 | */ | |
596 | /* WaForceEnableNonCoherent:bdw,chv */ | |
597 | /* WaHdcDisableFetchWhenMasked:bdw,chv */ | |
598 | WA_SET_BIT_MASKED(HDC_CHICKEN0, | |
599 | HDC_DONOT_FETCH_MEM_WHEN_MASKED | | |
600 | HDC_FORCE_NON_COHERENT); | |
601 | ||
602 | /* From the Haswell PRM, Command Reference: Registers, CACHE_MODE_0: | |
603 | * "The Hierarchical Z RAW Stall Optimization allows non-overlapping | |
604 | * polygons in the same 8x4 pixel/sample area to be processed without | |
605 | * stalling waiting for the earlier ones to write to Hierarchical Z | |
606 | * buffer." | |
607 | * | |
608 | * This optimization is off by default for BDW and CHV; turn it on. | |
609 | */ | |
610 | WA_CLR_BIT_MASKED(CACHE_MODE_0_GEN7, HIZ_RAW_STALL_OPT_DISABLE); | |
611 | ||
612 | /* Wa4x4STCOptimizationDisable:bdw,chv */ | |
613 | WA_SET_BIT_MASKED(CACHE_MODE_1, GEN8_4x4_STC_OPTIMIZATION_DISABLE); | |
614 | ||
615 | /* | |
616 | * BSpec recommends 8x4 when MSAA is used, | |
617 | * however in practice 16x4 seems fastest. | |
618 | * | |
619 | * Note that PS/WM thread counts depend on the WIZ hashing | |
620 | * disable bit, which we don't touch here, but it's good | |
621 | * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM). | |
622 | */ | |
623 | WA_SET_FIELD_MASKED(GEN7_GT_MODE, | |
624 | GEN6_WIZ_HASHING_MASK, | |
625 | GEN6_WIZ_HASHING_16x4); | |
626 | ||
627 | return 0; | |
628 | } | |
629 | ||
630 | static int bdw_init_workarounds(struct intel_engine_cs *engine) | |
631 | { | |
632 | struct drm_i915_private *dev_priv = engine->i915; | |
633 | int ret; | |
634 | ||
635 | ret = gen8_init_workarounds(engine); | |
636 | if (ret) | |
637 | return ret; | |
638 | ||
639 | /* WaDisableThreadStallDopClockGating:bdw (pre-production) */ | |
640 | WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, STALL_DOP_GATING_DISABLE); | |
641 | ||
642 | /* WaDisableDopClockGating:bdw | |
643 | * | |
644 | * Also see the related UCGTCL1 write in broadwell_init_clock_gating() | |
645 | * to disable EUTC clock gating. | |
646 | */ | |
647 | WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2, | |
648 | DOP_CLOCK_GATING_DISABLE); | |
649 | ||
650 | WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3, | |
651 | GEN8_SAMPLER_POWER_BYPASS_DIS); | |
652 | ||
653 | WA_SET_BIT_MASKED(HDC_CHICKEN0, | |
654 | /* WaForceContextSaveRestoreNonCoherent:bdw */ | |
655 | HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT | | |
656 | /* WaDisableFenceDestinationToSLM:bdw (pre-prod) */ | |
657 | (IS_BDW_GT3(dev_priv) ? HDC_FENCE_DEST_SLM_DISABLE : 0)); | |
658 | ||
659 | return 0; | |
660 | } | |
661 | ||
662 | static int chv_init_workarounds(struct intel_engine_cs *engine) | |
663 | { | |
664 | struct drm_i915_private *dev_priv = engine->i915; | |
665 | int ret; | |
666 | ||
667 | ret = gen8_init_workarounds(engine); | |
668 | if (ret) | |
669 | return ret; | |
670 | ||
671 | /* WaDisableThreadStallDopClockGating:chv */ | |
672 | WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, STALL_DOP_GATING_DISABLE); | |
673 | ||
674 | /* Improve HiZ throughput on CHV. */ | |
675 | WA_SET_BIT_MASKED(HIZ_CHICKEN, CHV_HZ_8X8_MODE_IN_1X); | |
676 | ||
677 | return 0; | |
678 | } | |
679 | ||
680 | static int gen9_init_workarounds(struct intel_engine_cs *engine) | |
681 | { | |
682 | struct drm_i915_private *dev_priv = engine->i915; | |
683 | int ret; | |
684 | ||
685 | /* WaConextSwitchWithConcurrentTLBInvalidate:skl,bxt,kbl,glk */ | |
686 | I915_WRITE(GEN9_CSFE_CHICKEN1_RCS, _MASKED_BIT_ENABLE(GEN9_PREEMPT_GPGPU_SYNC_SWITCH_DISABLE)); | |
687 | ||
688 | /* WaEnableLbsSlaRetryTimerDecrement:skl,bxt,kbl,glk */ | |
689 | I915_WRITE(BDW_SCRATCH1, I915_READ(BDW_SCRATCH1) | | |
690 | GEN9_LBS_SLA_RETRY_TIMER_DECREMENT_ENABLE); | |
691 | ||
692 | /* WaDisableKillLogic:bxt,skl,kbl */ | |
693 | I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | | |
694 | ECOCHK_DIS_TLB); | |
695 | ||
696 | /* WaClearFlowControlGpgpuContextSave:skl,bxt,kbl,glk */ | |
697 | /* WaDisablePartialInstShootdown:skl,bxt,kbl,glk */ | |
698 | WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, | |
699 | FLOW_CONTROL_ENABLE | | |
700 | PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE); | |
701 | ||
702 | /* Syncing dependencies between camera and graphics:skl,bxt,kbl */ | |
703 | WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3, | |
704 | GEN9_DISABLE_OCL_OOB_SUPPRESS_LOGIC); | |
705 | ||
706 | /* WaDisableDgMirrorFixInHalfSliceChicken5:bxt */ | |
707 | if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) | |
708 | WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5, | |
709 | GEN9_DG_MIRROR_FIX_ENABLE); | |
710 | ||
711 | /* WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken:bxt */ | |
712 | if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) { | |
713 | WA_SET_BIT_MASKED(GEN7_COMMON_SLICE_CHICKEN1, | |
714 | GEN9_RHWO_OPTIMIZATION_DISABLE); | |
715 | /* | |
716 | * WA also requires GEN9_SLICE_COMMON_ECO_CHICKEN0[14:14] to be set | |
717 | * but we do that in per ctx batchbuffer as there is an issue | |
718 | * with this register not getting restored on ctx restore | |
719 | */ | |
720 | } | |
721 | ||
722 | /* WaEnableSamplerGPGPUPreemptionSupport:skl,bxt,kbl */ | |
723 | WA_SET_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN7, | |
724 | GEN9_ENABLE_GPGPU_PREEMPTION); | |
725 | ||
726 | /* Wa4x4STCOptimizationDisable:skl,bxt,kbl,glk */ | |
727 | /* WaDisablePartialResolveInVc:skl,bxt,kbl */ | |
728 | WA_SET_BIT_MASKED(CACHE_MODE_1, (GEN8_4x4_STC_OPTIMIZATION_DISABLE | | |
729 | GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE)); | |
730 | ||
731 | /* WaCcsTlbPrefetchDisable:skl,bxt,kbl,glk */ | |
732 | WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5, | |
733 | GEN9_CCS_TLB_PREFETCH_ENABLE); | |
734 | ||
735 | /* WaDisableMaskBasedCammingInRCC:bxt */ | |
736 | if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) | |
737 | WA_SET_BIT_MASKED(SLICE_ECO_CHICKEN0, | |
738 | PIXEL_MASK_CAMMING_DISABLE); | |
739 | ||
740 | /* WaForceContextSaveRestoreNonCoherent:skl,bxt,kbl */ | |
741 | WA_SET_BIT_MASKED(HDC_CHICKEN0, | |
742 | HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT | | |
743 | HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE); | |
744 | ||
745 | /* WaForceEnableNonCoherent and WaDisableHDCInvalidation are | |
746 | * both tied to WaForceContextSaveRestoreNonCoherent | |
747 | * in some hsds for skl. We keep the tie for all gen9. The | |
748 | * documentation is a bit hazy and so we want to get common behaviour, | |
749 | * even though there is no clear evidence we would need both on kbl/bxt. | |
750 | * This area has been source of system hangs so we play it safe | |
751 | * and mimic the skl regardless of what bspec says. | |
752 | * | |
753 | * Use Force Non-Coherent whenever executing a 3D context. This | |
754 | * is a workaround for a possible hang in the unlikely event | |
755 | * a TLB invalidation occurs during a PSD flush. | |
756 | */ | |
757 | ||
758 | /* WaForceEnableNonCoherent:skl,bxt,kbl */ | |
759 | WA_SET_BIT_MASKED(HDC_CHICKEN0, | |
760 | HDC_FORCE_NON_COHERENT); | |
761 | ||
762 | /* WaDisableHDCInvalidation:skl,bxt,kbl */ | |
763 | I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | | |
764 | BDW_DISABLE_HDC_INVALIDATION); | |
765 | ||
766 | /* WaDisableSamplerPowerBypassForSOPingPong:skl,bxt,kbl */ | |
767 | if (IS_SKYLAKE(dev_priv) || | |
768 | IS_KABYLAKE(dev_priv) || | |
769 | IS_BXT_REVID(dev_priv, 0, BXT_REVID_B0)) | |
770 | WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3, | |
771 | GEN8_SAMPLER_POWER_BYPASS_DIS); | |
772 | ||
773 | /* WaDisableSTUnitPowerOptimization:skl,bxt,kbl,glk */ | |
774 | WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN2, GEN8_ST_PO_DISABLE); | |
775 | ||
776 | /* WaOCLCoherentLineFlush:skl,bxt,kbl */ | |
777 | I915_WRITE(GEN8_L3SQCREG4, (I915_READ(GEN8_L3SQCREG4) | | |
778 | GEN8_LQSC_FLUSH_COHERENT_LINES)); | |
779 | ||
780 | /* WaVFEStateAfterPipeControlwithMediaStateClear:skl,bxt,glk */ | |
781 | ret = wa_ring_whitelist_reg(engine, GEN9_CTX_PREEMPT_REG); | |
782 | if (ret) | |
783 | return ret; | |
784 | ||
785 | /* WaEnablePreemptionGranularityControlByUMD:skl,bxt,kbl */ | |
786 | ret= wa_ring_whitelist_reg(engine, GEN8_CS_CHICKEN1); | |
787 | if (ret) | |
788 | return ret; | |
789 | ||
790 | /* WaAllowUMDToModifyHDCChicken1:skl,bxt,kbl,glk */ | |
791 | ret = wa_ring_whitelist_reg(engine, GEN8_HDC_CHICKEN1); | |
792 | if (ret) | |
793 | return ret; | |
794 | ||
795 | return 0; | |
796 | } | |
797 | ||
798 | static int skl_tune_iz_hashing(struct intel_engine_cs *engine) | |
799 | { | |
800 | struct drm_i915_private *dev_priv = engine->i915; | |
801 | u8 vals[3] = { 0, 0, 0 }; | |
802 | unsigned int i; | |
803 | ||
804 | for (i = 0; i < 3; i++) { | |
805 | u8 ss; | |
806 | ||
807 | /* | |
808 | * Only consider slices where one, and only one, subslice has 7 | |
809 | * EUs | |
810 | */ | |
811 | if (!is_power_of_2(INTEL_INFO(dev_priv)->sseu.subslice_7eu[i])) | |
812 | continue; | |
813 | ||
814 | /* | |
815 | * subslice_7eu[i] != 0 (because of the check above) and | |
816 | * ss_max == 4 (maximum number of subslices possible per slice) | |
817 | * | |
818 | * -> 0 <= ss <= 3; | |
819 | */ | |
820 | ss = ffs(INTEL_INFO(dev_priv)->sseu.subslice_7eu[i]) - 1; | |
821 | vals[i] = 3 - ss; | |
822 | } | |
823 | ||
824 | if (vals[0] == 0 && vals[1] == 0 && vals[2] == 0) | |
825 | return 0; | |
826 | ||
827 | /* Tune IZ hashing. See intel_device_info_runtime_init() */ | |
828 | WA_SET_FIELD_MASKED(GEN7_GT_MODE, | |
829 | GEN9_IZ_HASHING_MASK(2) | | |
830 | GEN9_IZ_HASHING_MASK(1) | | |
831 | GEN9_IZ_HASHING_MASK(0), | |
832 | GEN9_IZ_HASHING(2, vals[2]) | | |
833 | GEN9_IZ_HASHING(1, vals[1]) | | |
834 | GEN9_IZ_HASHING(0, vals[0])); | |
835 | ||
836 | return 0; | |
837 | } | |
838 | ||
839 | static int skl_init_workarounds(struct intel_engine_cs *engine) | |
840 | { | |
841 | struct drm_i915_private *dev_priv = engine->i915; | |
842 | int ret; | |
843 | ||
844 | ret = gen9_init_workarounds(engine); | |
845 | if (ret) | |
846 | return ret; | |
847 | ||
848 | /* | |
849 | * Actual WA is to disable percontext preemption granularity control | |
850 | * until D0 which is the default case so this is equivalent to | |
851 | * !WaDisablePerCtxtPreemptionGranularityControl:skl | |
852 | */ | |
853 | I915_WRITE(GEN7_FF_SLICE_CS_CHICKEN1, | |
854 | _MASKED_BIT_ENABLE(GEN9_FFSC_PERCTX_PREEMPT_CTRL)); | |
855 | ||
856 | /* WaEnableGapsTsvCreditFix:skl */ | |
857 | I915_WRITE(GEN8_GARBCNTL, (I915_READ(GEN8_GARBCNTL) | | |
858 | GEN9_GAPS_TSV_CREDIT_DISABLE)); | |
859 | ||
860 | /* WaDisableGafsUnitClkGating:skl */ | |
861 | WA_SET_BIT(GEN7_UCGCTL4, GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE); | |
862 | ||
863 | /* WaInPlaceDecompressionHang:skl */ | |
864 | if (IS_SKL_REVID(dev_priv, SKL_REVID_H0, REVID_FOREVER)) | |
865 | WA_SET_BIT(GEN9_GAMT_ECO_REG_RW_IA, | |
866 | GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS); | |
867 | ||
868 | /* WaDisableLSQCROPERFforOCL:skl */ | |
869 | ret = wa_ring_whitelist_reg(engine, GEN8_L3SQCREG4); | |
870 | if (ret) | |
871 | return ret; | |
872 | ||
873 | return skl_tune_iz_hashing(engine); | |
874 | } | |
875 | ||
876 | static int bxt_init_workarounds(struct intel_engine_cs *engine) | |
877 | { | |
878 | struct drm_i915_private *dev_priv = engine->i915; | |
879 | int ret; | |
880 | ||
881 | ret = gen9_init_workarounds(engine); | |
882 | if (ret) | |
883 | return ret; | |
884 | ||
885 | /* WaStoreMultiplePTEenable:bxt */ | |
886 | /* This is a requirement according to Hardware specification */ | |
887 | if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) | |
888 | I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_TLBPF); | |
889 | ||
890 | /* WaSetClckGatingDisableMedia:bxt */ | |
891 | if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) { | |
892 | I915_WRITE(GEN7_MISCCPCTL, (I915_READ(GEN7_MISCCPCTL) & | |
893 | ~GEN8_DOP_CLOCK_GATE_MEDIA_ENABLE)); | |
894 | } | |
895 | ||
896 | /* WaDisableThreadStallDopClockGating:bxt */ | |
897 | WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, | |
898 | STALL_DOP_GATING_DISABLE); | |
899 | ||
900 | /* WaDisablePooledEuLoadBalancingFix:bxt */ | |
901 | if (IS_BXT_REVID(dev_priv, BXT_REVID_B0, REVID_FOREVER)) { | |
902 | WA_SET_BIT_MASKED(FF_SLICE_CS_CHICKEN2, | |
903 | GEN9_POOLED_EU_LOAD_BALANCING_FIX_DISABLE); | |
904 | } | |
905 | ||
906 | /* WaDisableSbeCacheDispatchPortSharing:bxt */ | |
907 | if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_B0)) { | |
908 | WA_SET_BIT_MASKED( | |
909 | GEN7_HALF_SLICE_CHICKEN1, | |
910 | GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE); | |
911 | } | |
912 | ||
913 | /* WaDisableObjectLevelPreemptionForTrifanOrPolygon:bxt */ | |
914 | /* WaDisableObjectLevelPreemptionForInstancedDraw:bxt */ | |
915 | /* WaDisableObjectLevelPreemtionForInstanceId:bxt */ | |
916 | /* WaDisableLSQCROPERFforOCL:bxt */ | |
917 | if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) { | |
918 | ret = wa_ring_whitelist_reg(engine, GEN9_CS_DEBUG_MODE1); | |
919 | if (ret) | |
920 | return ret; | |
921 | ||
922 | ret = wa_ring_whitelist_reg(engine, GEN8_L3SQCREG4); | |
923 | if (ret) | |
924 | return ret; | |
925 | } | |
926 | ||
927 | /* WaProgramL3SqcReg1DefaultForPerf:bxt */ | |
928 | if (IS_BXT_REVID(dev_priv, BXT_REVID_B0, REVID_FOREVER)) | |
929 | I915_WRITE(GEN8_L3SQCREG1, L3_GENERAL_PRIO_CREDITS(62) | | |
930 | L3_HIGH_PRIO_CREDITS(2)); | |
931 | ||
932 | /* WaToEnableHwFixForPushConstHWBug:bxt */ | |
933 | if (IS_BXT_REVID(dev_priv, BXT_REVID_C0, REVID_FOREVER)) | |
934 | WA_SET_BIT_MASKED(COMMON_SLICE_CHICKEN2, | |
935 | GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION); | |
936 | ||
937 | /* WaInPlaceDecompressionHang:bxt */ | |
938 | if (IS_BXT_REVID(dev_priv, BXT_REVID_C0, REVID_FOREVER)) | |
939 | WA_SET_BIT(GEN9_GAMT_ECO_REG_RW_IA, | |
940 | GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS); | |
941 | ||
942 | return 0; | |
943 | } | |
944 | ||
945 | static int kbl_init_workarounds(struct intel_engine_cs *engine) | |
946 | { | |
947 | struct drm_i915_private *dev_priv = engine->i915; | |
948 | int ret; | |
949 | ||
950 | ret = gen9_init_workarounds(engine); | |
951 | if (ret) | |
952 | return ret; | |
953 | ||
954 | /* WaEnableGapsTsvCreditFix:kbl */ | |
955 | I915_WRITE(GEN8_GARBCNTL, (I915_READ(GEN8_GARBCNTL) | | |
956 | GEN9_GAPS_TSV_CREDIT_DISABLE)); | |
957 | ||
958 | /* WaDisableDynamicCreditSharing:kbl */ | |
959 | if (IS_KBL_REVID(dev_priv, 0, KBL_REVID_B0)) | |
960 | WA_SET_BIT(GAMT_CHKN_BIT_REG, | |
961 | GAMT_CHKN_DISABLE_DYNAMIC_CREDIT_SHARING); | |
962 | ||
963 | /* WaDisableFenceDestinationToSLM:kbl (pre-prod) */ | |
964 | if (IS_KBL_REVID(dev_priv, KBL_REVID_A0, KBL_REVID_A0)) | |
965 | WA_SET_BIT_MASKED(HDC_CHICKEN0, | |
966 | HDC_FENCE_DEST_SLM_DISABLE); | |
967 | ||
968 | /* WaToEnableHwFixForPushConstHWBug:kbl */ | |
969 | if (IS_KBL_REVID(dev_priv, KBL_REVID_C0, REVID_FOREVER)) | |
970 | WA_SET_BIT_MASKED(COMMON_SLICE_CHICKEN2, | |
971 | GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION); | |
972 | ||
973 | /* WaDisableGafsUnitClkGating:kbl */ | |
974 | WA_SET_BIT(GEN7_UCGCTL4, GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE); | |
975 | ||
976 | /* WaDisableSbeCacheDispatchPortSharing:kbl */ | |
977 | WA_SET_BIT_MASKED( | |
978 | GEN7_HALF_SLICE_CHICKEN1, | |
979 | GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE); | |
980 | ||
981 | /* WaInPlaceDecompressionHang:kbl */ | |
982 | WA_SET_BIT(GEN9_GAMT_ECO_REG_RW_IA, | |
983 | GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS); | |
984 | ||
985 | /* WaDisableLSQCROPERFforOCL:kbl */ | |
986 | ret = wa_ring_whitelist_reg(engine, GEN8_L3SQCREG4); | |
987 | if (ret) | |
988 | return ret; | |
989 | ||
990 | return 0; | |
991 | } | |
992 | ||
993 | static int glk_init_workarounds(struct intel_engine_cs *engine) | |
994 | { | |
995 | struct drm_i915_private *dev_priv = engine->i915; | |
996 | int ret; | |
997 | ||
998 | ret = gen9_init_workarounds(engine); | |
999 | if (ret) | |
1000 | return ret; | |
1001 | ||
1002 | /* WaToEnableHwFixForPushConstHWBug:glk */ | |
1003 | WA_SET_BIT_MASKED(COMMON_SLICE_CHICKEN2, | |
1004 | GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION); | |
1005 | ||
1006 | return 0; | |
1007 | } | |
1008 | ||
1009 | int init_workarounds_ring(struct intel_engine_cs *engine) | |
1010 | { | |
1011 | struct drm_i915_private *dev_priv = engine->i915; | |
02e012f1 | 1012 | int err; |
133b4bd7 TU |
1013 | |
1014 | WARN_ON(engine->id != RCS); | |
1015 | ||
1016 | dev_priv->workarounds.count = 0; | |
02e012f1 | 1017 | dev_priv->workarounds.hw_whitelist_count[engine->id] = 0; |
133b4bd7 TU |
1018 | |
1019 | if (IS_BROADWELL(dev_priv)) | |
02e012f1 CW |
1020 | err = bdw_init_workarounds(engine); |
1021 | else if (IS_CHERRYVIEW(dev_priv)) | |
1022 | err = chv_init_workarounds(engine); | |
1023 | else if (IS_SKYLAKE(dev_priv)) | |
1024 | err = skl_init_workarounds(engine); | |
1025 | else if (IS_BROXTON(dev_priv)) | |
1026 | err = bxt_init_workarounds(engine); | |
1027 | else if (IS_KABYLAKE(dev_priv)) | |
1028 | err = kbl_init_workarounds(engine); | |
1029 | else if (IS_GEMINILAKE(dev_priv)) | |
1030 | err = glk_init_workarounds(engine); | |
1031 | else | |
1032 | err = 0; | |
1033 | if (err) | |
1034 | return err; | |
133b4bd7 | 1035 | |
02e012f1 CW |
1036 | DRM_DEBUG_DRIVER("%s: Number of context specific w/a: %d\n", |
1037 | engine->name, dev_priv->workarounds.count); | |
133b4bd7 TU |
1038 | return 0; |
1039 | } | |
1040 | ||
1041 | int intel_ring_workarounds_emit(struct drm_i915_gem_request *req) | |
1042 | { | |
1043 | struct i915_workarounds *w = &req->i915->workarounds; | |
1044 | u32 *cs; | |
1045 | int ret, i; | |
1046 | ||
1047 | if (w->count == 0) | |
1048 | return 0; | |
1049 | ||
1050 | ret = req->engine->emit_flush(req, EMIT_BARRIER); | |
1051 | if (ret) | |
1052 | return ret; | |
1053 | ||
1054 | cs = intel_ring_begin(req, (w->count * 2 + 2)); | |
1055 | if (IS_ERR(cs)) | |
1056 | return PTR_ERR(cs); | |
1057 | ||
1058 | *cs++ = MI_LOAD_REGISTER_IMM(w->count); | |
1059 | for (i = 0; i < w->count; i++) { | |
1060 | *cs++ = i915_mmio_reg_offset(w->reg[i].addr); | |
1061 | *cs++ = w->reg[i].value; | |
1062 | } | |
1063 | *cs++ = MI_NOOP; | |
1064 | ||
1065 | intel_ring_advance(req, cs); | |
1066 | ||
1067 | ret = req->engine->emit_flush(req, EMIT_BARRIER); | |
1068 | if (ret) | |
1069 | return ret; | |
1070 | ||
133b4bd7 TU |
1071 | return 0; |
1072 | } | |
1073 | ||
5400367a CW |
1074 | /** |
1075 | * intel_engine_is_idle() - Report if the engine has finished process all work | |
1076 | * @engine: the intel_engine_cs | |
1077 | * | |
1078 | * Return true if there are no requests pending, nothing left to be submitted | |
1079 | * to hardware, and that the engine is idle. | |
1080 | */ | |
1081 | bool intel_engine_is_idle(struct intel_engine_cs *engine) | |
1082 | { | |
1083 | struct drm_i915_private *dev_priv = engine->i915; | |
1084 | ||
1085 | /* Any inflight/incomplete requests? */ | |
1086 | if (!i915_seqno_passed(intel_engine_get_seqno(engine), | |
1087 | intel_engine_last_submit(engine))) | |
1088 | return false; | |
1089 | ||
1090 | /* Interrupt/tasklet pending? */ | |
1091 | if (test_bit(ENGINE_IRQ_EXECLIST, &engine->irq_posted)) | |
1092 | return false; | |
1093 | ||
1094 | /* Both ports drained, no more ELSP submission? */ | |
1095 | if (engine->execlist_port[0].request) | |
1096 | return false; | |
1097 | ||
1098 | /* Ring stopped? */ | |
1099 | if (INTEL_GEN(dev_priv) > 2 && !(I915_READ_MODE(engine) & MODE_IDLE)) | |
1100 | return false; | |
1101 | ||
1102 | return true; | |
1103 | } | |
1104 | ||
05425249 CW |
1105 | bool intel_engines_are_idle(struct drm_i915_private *dev_priv) |
1106 | { | |
1107 | struct intel_engine_cs *engine; | |
1108 | enum intel_engine_id id; | |
1109 | ||
1110 | for_each_engine(engine, dev_priv, id) { | |
1111 | if (!intel_engine_is_idle(engine)) | |
1112 | return false; | |
1113 | } | |
1114 | ||
1115 | return true; | |
1116 | } | |
1117 | ||
f97fbf96 CW |
1118 | #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST) |
1119 | #include "selftests/mock_engine.c" | |
1120 | #endif |