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88d2ba2e TU |
1 | /* |
2 | * Copyright © 2016 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | */ | |
24 | ||
25 | #include "i915_drv.h" | |
26 | #include "intel_ringbuffer.h" | |
27 | #include "intel_lrc.h" | |
28 | ||
63ffbcda JL |
29 | /* Haswell does have the CXT_SIZE register however it does not appear to be |
30 | * valid. Now, docs explain in dwords what is in the context object. The full | |
31 | * size is 70720 bytes, however, the power context and execlist context will | |
32 | * never be saved (power context is stored elsewhere, and execlists don't work | |
33 | * on HSW) - so the final size, including the extra state required for the | |
34 | * Resource Streamer, is 66944 bytes, which rounds to 17 pages. | |
35 | */ | |
36 | #define HSW_CXT_TOTAL_SIZE (17 * PAGE_SIZE) | |
37 | /* Same as Haswell, but 72064 bytes now. */ | |
38 | #define GEN8_CXT_TOTAL_SIZE (18 * PAGE_SIZE) | |
39 | ||
40 | #define GEN8_LR_CONTEXT_RENDER_SIZE (20 * PAGE_SIZE) | |
41 | #define GEN9_LR_CONTEXT_RENDER_SIZE (22 * PAGE_SIZE) | |
3cf1934a | 42 | #define GEN10_LR_CONTEXT_RENDER_SIZE (18 * PAGE_SIZE) |
63ffbcda JL |
43 | |
44 | #define GEN8_LR_CONTEXT_OTHER_SIZE ( 2 * PAGE_SIZE) | |
45 | ||
b8400f01 | 46 | struct engine_class_info { |
88d2ba2e | 47 | const char *name; |
b8400f01 OM |
48 | int (*init_legacy)(struct intel_engine_cs *engine); |
49 | int (*init_execlists)(struct intel_engine_cs *engine); | |
50 | }; | |
51 | ||
52 | static const struct engine_class_info intel_engine_classes[] = { | |
53 | [RENDER_CLASS] = { | |
54 | .name = "rcs", | |
55 | .init_execlists = logical_render_ring_init, | |
56 | .init_legacy = intel_init_render_ring_buffer, | |
57 | }, | |
58 | [COPY_ENGINE_CLASS] = { | |
59 | .name = "bcs", | |
60 | .init_execlists = logical_xcs_ring_init, | |
61 | .init_legacy = intel_init_blt_ring_buffer, | |
62 | }, | |
63 | [VIDEO_DECODE_CLASS] = { | |
64 | .name = "vcs", | |
65 | .init_execlists = logical_xcs_ring_init, | |
66 | .init_legacy = intel_init_bsd_ring_buffer, | |
67 | }, | |
68 | [VIDEO_ENHANCEMENT_CLASS] = { | |
69 | .name = "vecs", | |
70 | .init_execlists = logical_xcs_ring_init, | |
71 | .init_legacy = intel_init_vebox_ring_buffer, | |
72 | }, | |
73 | }; | |
74 | ||
75 | struct engine_info { | |
237ae7c7 | 76 | unsigned int hw_id; |
1d39f281 | 77 | unsigned int uabi_id; |
0908180b DCS |
78 | u8 class; |
79 | u8 instance; | |
88d2ba2e TU |
80 | u32 mmio_base; |
81 | unsigned irq_shift; | |
b8400f01 OM |
82 | }; |
83 | ||
84 | static const struct engine_info intel_engines[] = { | |
88d2ba2e | 85 | [RCS] = { |
5ec2cf7e | 86 | .hw_id = RCS_HW, |
1d39f281 | 87 | .uabi_id = I915_EXEC_RENDER, |
0908180b DCS |
88 | .class = RENDER_CLASS, |
89 | .instance = 0, | |
88d2ba2e TU |
90 | .mmio_base = RENDER_RING_BASE, |
91 | .irq_shift = GEN8_RCS_IRQ_SHIFT, | |
88d2ba2e TU |
92 | }, |
93 | [BCS] = { | |
5ec2cf7e | 94 | .hw_id = BCS_HW, |
1d39f281 | 95 | .uabi_id = I915_EXEC_BLT, |
0908180b DCS |
96 | .class = COPY_ENGINE_CLASS, |
97 | .instance = 0, | |
88d2ba2e TU |
98 | .mmio_base = BLT_RING_BASE, |
99 | .irq_shift = GEN8_BCS_IRQ_SHIFT, | |
88d2ba2e TU |
100 | }, |
101 | [VCS] = { | |
5ec2cf7e | 102 | .hw_id = VCS_HW, |
1d39f281 | 103 | .uabi_id = I915_EXEC_BSD, |
0908180b DCS |
104 | .class = VIDEO_DECODE_CLASS, |
105 | .instance = 0, | |
88d2ba2e TU |
106 | .mmio_base = GEN6_BSD_RING_BASE, |
107 | .irq_shift = GEN8_VCS1_IRQ_SHIFT, | |
88d2ba2e TU |
108 | }, |
109 | [VCS2] = { | |
5ec2cf7e | 110 | .hw_id = VCS2_HW, |
1d39f281 | 111 | .uabi_id = I915_EXEC_BSD, |
0908180b DCS |
112 | .class = VIDEO_DECODE_CLASS, |
113 | .instance = 1, | |
88d2ba2e TU |
114 | .mmio_base = GEN8_BSD2_RING_BASE, |
115 | .irq_shift = GEN8_VCS2_IRQ_SHIFT, | |
88d2ba2e TU |
116 | }, |
117 | [VECS] = { | |
5ec2cf7e | 118 | .hw_id = VECS_HW, |
1d39f281 | 119 | .uabi_id = I915_EXEC_VEBOX, |
0908180b DCS |
120 | .class = VIDEO_ENHANCEMENT_CLASS, |
121 | .instance = 0, | |
88d2ba2e TU |
122 | .mmio_base = VEBOX_RING_BASE, |
123 | .irq_shift = GEN8_VECS_IRQ_SHIFT, | |
88d2ba2e TU |
124 | }, |
125 | }; | |
126 | ||
63ffbcda JL |
127 | /** |
128 | * ___intel_engine_context_size() - return the size of the context for an engine | |
129 | * @dev_priv: i915 device private | |
130 | * @class: engine class | |
131 | * | |
132 | * Each engine class may require a different amount of space for a context | |
133 | * image. | |
134 | * | |
135 | * Return: size (in bytes) of an engine class specific context image | |
136 | * | |
137 | * Note: this size includes the HWSP, which is part of the context image | |
138 | * in LRC mode, but does not include the "shared data page" used with | |
139 | * GuC submission. The caller should account for this if using the GuC. | |
140 | */ | |
141 | static u32 | |
142 | __intel_engine_context_size(struct drm_i915_private *dev_priv, u8 class) | |
143 | { | |
144 | u32 cxt_size; | |
145 | ||
146 | BUILD_BUG_ON(I915_GTT_PAGE_SIZE != PAGE_SIZE); | |
147 | ||
148 | switch (class) { | |
149 | case RENDER_CLASS: | |
150 | switch (INTEL_GEN(dev_priv)) { | |
151 | default: | |
152 | MISSING_CASE(INTEL_GEN(dev_priv)); | |
f65f8417 | 153 | case 10: |
7fd0b1a2 | 154 | return GEN10_LR_CONTEXT_RENDER_SIZE; |
63ffbcda JL |
155 | case 9: |
156 | return GEN9_LR_CONTEXT_RENDER_SIZE; | |
157 | case 8: | |
4f044a88 | 158 | return i915_modparams.enable_execlists ? |
63ffbcda JL |
159 | GEN8_LR_CONTEXT_RENDER_SIZE : |
160 | GEN8_CXT_TOTAL_SIZE; | |
161 | case 7: | |
162 | if (IS_HASWELL(dev_priv)) | |
163 | return HSW_CXT_TOTAL_SIZE; | |
164 | ||
165 | cxt_size = I915_READ(GEN7_CXT_SIZE); | |
166 | return round_up(GEN7_CXT_TOTAL_SIZE(cxt_size) * 64, | |
167 | PAGE_SIZE); | |
168 | case 6: | |
169 | cxt_size = I915_READ(CXT_SIZE); | |
170 | return round_up(GEN6_CXT_TOTAL_SIZE(cxt_size) * 64, | |
171 | PAGE_SIZE); | |
172 | case 5: | |
173 | case 4: | |
174 | case 3: | |
175 | case 2: | |
176 | /* For the special day when i810 gets merged. */ | |
177 | case 1: | |
178 | return 0; | |
179 | } | |
180 | break; | |
181 | default: | |
182 | MISSING_CASE(class); | |
183 | case VIDEO_DECODE_CLASS: | |
184 | case VIDEO_ENHANCEMENT_CLASS: | |
185 | case COPY_ENGINE_CLASS: | |
186 | if (INTEL_GEN(dev_priv) < 8) | |
187 | return 0; | |
188 | return GEN8_LR_CONTEXT_OTHER_SIZE; | |
189 | } | |
190 | } | |
191 | ||
3b3f1650 | 192 | static int |
88d2ba2e TU |
193 | intel_engine_setup(struct drm_i915_private *dev_priv, |
194 | enum intel_engine_id id) | |
195 | { | |
196 | const struct engine_info *info = &intel_engines[id]; | |
b8400f01 | 197 | const struct engine_class_info *class_info; |
3b3f1650 AG |
198 | struct intel_engine_cs *engine; |
199 | ||
b8400f01 OM |
200 | GEM_BUG_ON(info->class >= ARRAY_SIZE(intel_engine_classes)); |
201 | class_info = &intel_engine_classes[info->class]; | |
202 | ||
3b3f1650 AG |
203 | GEM_BUG_ON(dev_priv->engine[id]); |
204 | engine = kzalloc(sizeof(*engine), GFP_KERNEL); | |
205 | if (!engine) | |
206 | return -ENOMEM; | |
88d2ba2e TU |
207 | |
208 | engine->id = id; | |
209 | engine->i915 = dev_priv; | |
6e516148 | 210 | WARN_ON(snprintf(engine->name, sizeof(engine->name), "%s%u", |
b8400f01 OM |
211 | class_info->name, info->instance) >= |
212 | sizeof(engine->name)); | |
1d39f281 | 213 | engine->uabi_id = info->uabi_id; |
5ec2cf7e | 214 | engine->hw_id = engine->guc_id = info->hw_id; |
88d2ba2e TU |
215 | engine->mmio_base = info->mmio_base; |
216 | engine->irq_shift = info->irq_shift; | |
0908180b DCS |
217 | engine->class = info->class; |
218 | engine->instance = info->instance; | |
88d2ba2e | 219 | |
63ffbcda JL |
220 | engine->context_size = __intel_engine_context_size(dev_priv, |
221 | engine->class); | |
222 | if (WARN_ON(engine->context_size > BIT(20))) | |
223 | engine->context_size = 0; | |
224 | ||
0de9136d CW |
225 | /* Nothing to do here, execute in order of dependencies */ |
226 | engine->schedule = NULL; | |
227 | ||
3fc03069 CD |
228 | ATOMIC_INIT_NOTIFIER_HEAD(&engine->context_status_notifier); |
229 | ||
3b3f1650 AG |
230 | dev_priv->engine[id] = engine; |
231 | return 0; | |
88d2ba2e TU |
232 | } |
233 | ||
234 | /** | |
63ffbcda | 235 | * intel_engines_init_mmio() - allocate and prepare the Engine Command Streamers |
bf9e8429 | 236 | * @dev_priv: i915 device private |
88d2ba2e TU |
237 | * |
238 | * Return: non-zero if the initialization failed. | |
239 | */ | |
63ffbcda | 240 | int intel_engines_init_mmio(struct drm_i915_private *dev_priv) |
88d2ba2e | 241 | { |
c1bb1145 | 242 | struct intel_device_info *device_info = mkwrite_device_info(dev_priv); |
5f9be054 | 243 | const unsigned int ring_mask = INTEL_INFO(dev_priv)->ring_mask; |
3b3f1650 AG |
244 | struct intel_engine_cs *engine; |
245 | enum intel_engine_id id; | |
5f9be054 | 246 | unsigned int mask = 0; |
88d2ba2e | 247 | unsigned int i; |
bb8f0f5a | 248 | int err; |
88d2ba2e | 249 | |
70006ad6 TU |
250 | WARN_ON(ring_mask == 0); |
251 | WARN_ON(ring_mask & | |
88d2ba2e TU |
252 | GENMASK(sizeof(mask) * BITS_PER_BYTE - 1, I915_NUM_ENGINES)); |
253 | ||
254 | for (i = 0; i < ARRAY_SIZE(intel_engines); i++) { | |
255 | if (!HAS_ENGINE(dev_priv, i)) | |
256 | continue; | |
257 | ||
bb8f0f5a CW |
258 | err = intel_engine_setup(dev_priv, i); |
259 | if (err) | |
260 | goto cleanup; | |
261 | ||
262 | mask |= ENGINE_MASK(i); | |
263 | } | |
264 | ||
265 | /* | |
266 | * Catch failures to update intel_engines table when the new engines | |
267 | * are added to the driver by a warning and disabling the forgotten | |
268 | * engines. | |
269 | */ | |
270 | if (WARN_ON(mask != ring_mask)) | |
271 | device_info->ring_mask = mask; | |
272 | ||
5f9be054 CW |
273 | /* We always presume we have at least RCS available for later probing */ |
274 | if (WARN_ON(!HAS_ENGINE(dev_priv, RCS))) { | |
275 | err = -ENODEV; | |
276 | goto cleanup; | |
277 | } | |
278 | ||
bb8f0f5a CW |
279 | device_info->num_rings = hweight32(mask); |
280 | ||
281 | return 0; | |
282 | ||
283 | cleanup: | |
284 | for_each_engine(engine, dev_priv, id) | |
285 | kfree(engine); | |
286 | return err; | |
287 | } | |
288 | ||
289 | /** | |
63ffbcda | 290 | * intel_engines_init() - init the Engine Command Streamers |
bb8f0f5a CW |
291 | * @dev_priv: i915 device private |
292 | * | |
293 | * Return: non-zero if the initialization failed. | |
294 | */ | |
295 | int intel_engines_init(struct drm_i915_private *dev_priv) | |
296 | { | |
bb8f0f5a CW |
297 | struct intel_engine_cs *engine; |
298 | enum intel_engine_id id, err_id; | |
33def1ff | 299 | int err; |
bb8f0f5a CW |
300 | |
301 | for_each_engine(engine, dev_priv, id) { | |
b8400f01 OM |
302 | const struct engine_class_info *class_info = |
303 | &intel_engine_classes[engine->class]; | |
bb8f0f5a CW |
304 | int (*init)(struct intel_engine_cs *engine); |
305 | ||
4f044a88 | 306 | if (i915_modparams.enable_execlists) |
b8400f01 | 307 | init = class_info->init_execlists; |
88d2ba2e | 308 | else |
b8400f01 | 309 | init = class_info->init_legacy; |
33def1ff TU |
310 | |
311 | err = -EINVAL; | |
312 | err_id = id; | |
313 | ||
314 | if (GEM_WARN_ON(!init)) | |
315 | goto cleanup; | |
88d2ba2e | 316 | |
bb8f0f5a | 317 | err = init(engine); |
33def1ff | 318 | if (err) |
88d2ba2e TU |
319 | goto cleanup; |
320 | ||
ff44ad51 | 321 | GEM_BUG_ON(!engine->submit_request); |
88d2ba2e TU |
322 | } |
323 | ||
88d2ba2e TU |
324 | return 0; |
325 | ||
326 | cleanup: | |
3b3f1650 | 327 | for_each_engine(engine, dev_priv, id) { |
33def1ff | 328 | if (id >= err_id) { |
bb8f0f5a | 329 | kfree(engine); |
33def1ff TU |
330 | dev_priv->engine[id] = NULL; |
331 | } else { | |
8ee7c6e2 | 332 | dev_priv->gt.cleanup_engine(engine); |
33def1ff | 333 | } |
88d2ba2e | 334 | } |
bb8f0f5a | 335 | return err; |
88d2ba2e TU |
336 | } |
337 | ||
73cb9701 | 338 | void intel_engine_init_global_seqno(struct intel_engine_cs *engine, u32 seqno) |
57f275a2 CW |
339 | { |
340 | struct drm_i915_private *dev_priv = engine->i915; | |
341 | ||
342 | /* Our semaphore implementation is strictly monotonic (i.e. we proceed | |
343 | * so long as the semaphore value in the register/page is greater | |
344 | * than the sync value), so whenever we reset the seqno, | |
345 | * so long as we reset the tracking semaphore value to 0, it will | |
346 | * always be before the next request's seqno. If we don't reset | |
347 | * the semaphore value, then when the seqno moves backwards all | |
348 | * future waits will complete instantly (causing rendering corruption). | |
349 | */ | |
350 | if (IS_GEN6(dev_priv) || IS_GEN7(dev_priv)) { | |
351 | I915_WRITE(RING_SYNC_0(engine->mmio_base), 0); | |
352 | I915_WRITE(RING_SYNC_1(engine->mmio_base), 0); | |
353 | if (HAS_VEBOX(dev_priv)) | |
354 | I915_WRITE(RING_SYNC_2(engine->mmio_base), 0); | |
355 | } | |
51d545d0 CW |
356 | if (dev_priv->semaphore) { |
357 | struct page *page = i915_vma_first_page(dev_priv->semaphore); | |
358 | void *semaphores; | |
359 | ||
360 | /* Semaphores are in noncoherent memory, flush to be safe */ | |
24caf655 | 361 | semaphores = kmap_atomic(page); |
57f275a2 CW |
362 | memset(semaphores + GEN8_SEMAPHORE_OFFSET(engine->id, 0), |
363 | 0, I915_NUM_ENGINES * gen8_semaphore_seqno_size); | |
51d545d0 CW |
364 | drm_clflush_virt_range(semaphores + GEN8_SEMAPHORE_OFFSET(engine->id, 0), |
365 | I915_NUM_ENGINES * gen8_semaphore_seqno_size); | |
24caf655 | 366 | kunmap_atomic(semaphores); |
57f275a2 | 367 | } |
57f275a2 CW |
368 | |
369 | intel_write_status_page(engine, I915_GEM_HWS_INDEX, seqno); | |
14a6bbf9 | 370 | clear_bit(ENGINE_IRQ_BREADCRUMB, &engine->irq_posted); |
73cb9701 | 371 | |
57f275a2 CW |
372 | /* After manually advancing the seqno, fake the interrupt in case |
373 | * there are any waiters for that seqno. | |
374 | */ | |
375 | intel_engine_wakeup(engine); | |
2ca9faa5 CW |
376 | |
377 | GEM_BUG_ON(intel_engine_get_seqno(engine) != seqno); | |
57f275a2 CW |
378 | } |
379 | ||
73cb9701 | 380 | static void intel_engine_init_timeline(struct intel_engine_cs *engine) |
dcff85c8 | 381 | { |
73cb9701 | 382 | engine->timeline = &engine->i915->gt.global_timeline.engine[engine->id]; |
dcff85c8 CW |
383 | } |
384 | ||
19df9a57 MK |
385 | static bool csb_force_mmio(struct drm_i915_private *i915) |
386 | { | |
387 | /* GVT emulation depends upon intercepting CSB mmio */ | |
388 | if (intel_vgpu_active(i915)) | |
389 | return true; | |
390 | ||
391 | /* | |
392 | * IOMMU adds unpredictable latency causing the CSB write (from the | |
393 | * GPU into the HWSP) to only be visible some time after the interrupt | |
394 | * (missed breadcrumb syndrome). | |
395 | */ | |
396 | if (intel_vtd_active()) | |
397 | return true; | |
398 | ||
399 | return false; | |
400 | } | |
401 | ||
402 | static void intel_engine_init_execlist(struct intel_engine_cs *engine) | |
403 | { | |
404 | struct intel_engine_execlists * const execlists = &engine->execlists; | |
405 | ||
406 | execlists->csb_use_mmio = csb_force_mmio(engine->i915); | |
407 | ||
76e70087 MK |
408 | execlists->port_mask = 1; |
409 | BUILD_BUG_ON_NOT_POWER_OF_2(execlists_num_ports(execlists)); | |
410 | GEM_BUG_ON(execlists_num_ports(execlists) > EXECLIST_MAX_PORTS); | |
411 | ||
19df9a57 MK |
412 | execlists->queue = RB_ROOT; |
413 | execlists->first = NULL; | |
414 | } | |
415 | ||
019bf277 TU |
416 | /** |
417 | * intel_engines_setup_common - setup engine state not requiring hw access | |
418 | * @engine: Engine to setup. | |
419 | * | |
420 | * Initializes @engine@ structure members shared between legacy and execlists | |
421 | * submission modes which do not require hardware access. | |
422 | * | |
423 | * Typically done early in the submission mode specific engine setup stage. | |
424 | */ | |
425 | void intel_engine_setup_common(struct intel_engine_cs *engine) | |
426 | { | |
19df9a57 | 427 | intel_engine_init_execlist(engine); |
019bf277 | 428 | |
73cb9701 | 429 | intel_engine_init_timeline(engine); |
019bf277 | 430 | intel_engine_init_hangcheck(engine); |
115003e9 | 431 | i915_gem_batch_pool_init(engine, &engine->batch_pool); |
7756e454 CW |
432 | |
433 | intel_engine_init_cmd_parser(engine); | |
019bf277 TU |
434 | } |
435 | ||
adc320c4 CW |
436 | int intel_engine_create_scratch(struct intel_engine_cs *engine, int size) |
437 | { | |
438 | struct drm_i915_gem_object *obj; | |
439 | struct i915_vma *vma; | |
440 | int ret; | |
441 | ||
442 | WARN_ON(engine->scratch); | |
443 | ||
187685cb | 444 | obj = i915_gem_object_create_stolen(engine->i915, size); |
adc320c4 | 445 | if (!obj) |
920cf419 | 446 | obj = i915_gem_object_create_internal(engine->i915, size); |
adc320c4 CW |
447 | if (IS_ERR(obj)) { |
448 | DRM_ERROR("Failed to allocate scratch page\n"); | |
449 | return PTR_ERR(obj); | |
450 | } | |
451 | ||
a01cb37a | 452 | vma = i915_vma_instance(obj, &engine->i915->ggtt.base, NULL); |
adc320c4 CW |
453 | if (IS_ERR(vma)) { |
454 | ret = PTR_ERR(vma); | |
455 | goto err_unref; | |
456 | } | |
457 | ||
458 | ret = i915_vma_pin(vma, 0, 4096, PIN_GLOBAL | PIN_HIGH); | |
459 | if (ret) | |
460 | goto err_unref; | |
461 | ||
462 | engine->scratch = vma; | |
bde13ebd CW |
463 | DRM_DEBUG_DRIVER("%s pipe control offset: 0x%08x\n", |
464 | engine->name, i915_ggtt_offset(vma)); | |
adc320c4 CW |
465 | return 0; |
466 | ||
467 | err_unref: | |
468 | i915_gem_object_put(obj); | |
469 | return ret; | |
470 | } | |
471 | ||
472 | static void intel_engine_cleanup_scratch(struct intel_engine_cs *engine) | |
473 | { | |
19880c4a | 474 | i915_vma_unpin_and_release(&engine->scratch); |
adc320c4 CW |
475 | } |
476 | ||
486e93f7 DCS |
477 | static void cleanup_phys_status_page(struct intel_engine_cs *engine) |
478 | { | |
479 | struct drm_i915_private *dev_priv = engine->i915; | |
480 | ||
481 | if (!dev_priv->status_page_dmah) | |
482 | return; | |
483 | ||
484 | drm_pci_free(&dev_priv->drm, dev_priv->status_page_dmah); | |
485 | engine->status_page.page_addr = NULL; | |
486 | } | |
487 | ||
488 | static void cleanup_status_page(struct intel_engine_cs *engine) | |
489 | { | |
490 | struct i915_vma *vma; | |
491 | struct drm_i915_gem_object *obj; | |
492 | ||
493 | vma = fetch_and_zero(&engine->status_page.vma); | |
494 | if (!vma) | |
495 | return; | |
496 | ||
497 | obj = vma->obj; | |
498 | ||
499 | i915_vma_unpin(vma); | |
500 | i915_vma_close(vma); | |
501 | ||
502 | i915_gem_object_unpin_map(obj); | |
503 | __i915_gem_object_release_unless_active(obj); | |
504 | } | |
505 | ||
506 | static int init_status_page(struct intel_engine_cs *engine) | |
507 | { | |
508 | struct drm_i915_gem_object *obj; | |
509 | struct i915_vma *vma; | |
510 | unsigned int flags; | |
511 | void *vaddr; | |
512 | int ret; | |
513 | ||
514 | obj = i915_gem_object_create_internal(engine->i915, PAGE_SIZE); | |
515 | if (IS_ERR(obj)) { | |
516 | DRM_ERROR("Failed to allocate status page\n"); | |
517 | return PTR_ERR(obj); | |
518 | } | |
519 | ||
520 | ret = i915_gem_object_set_cache_level(obj, I915_CACHE_LLC); | |
521 | if (ret) | |
522 | goto err; | |
523 | ||
524 | vma = i915_vma_instance(obj, &engine->i915->ggtt.base, NULL); | |
525 | if (IS_ERR(vma)) { | |
526 | ret = PTR_ERR(vma); | |
527 | goto err; | |
528 | } | |
529 | ||
530 | flags = PIN_GLOBAL; | |
531 | if (!HAS_LLC(engine->i915)) | |
532 | /* On g33, we cannot place HWS above 256MiB, so | |
533 | * restrict its pinning to the low mappable arena. | |
534 | * Though this restriction is not documented for | |
535 | * gen4, gen5, or byt, they also behave similarly | |
536 | * and hang if the HWS is placed at the top of the | |
537 | * GTT. To generalise, it appears that all !llc | |
538 | * platforms have issues with us placing the HWS | |
539 | * above the mappable region (even though we never | |
540 | * actually map it). | |
541 | */ | |
542 | flags |= PIN_MAPPABLE; | |
34a04e5e CW |
543 | else |
544 | flags |= PIN_HIGH; | |
486e93f7 DCS |
545 | ret = i915_vma_pin(vma, 0, 4096, flags); |
546 | if (ret) | |
547 | goto err; | |
548 | ||
549 | vaddr = i915_gem_object_pin_map(obj, I915_MAP_WB); | |
550 | if (IS_ERR(vaddr)) { | |
551 | ret = PTR_ERR(vaddr); | |
552 | goto err_unpin; | |
553 | } | |
554 | ||
555 | engine->status_page.vma = vma; | |
556 | engine->status_page.ggtt_offset = i915_ggtt_offset(vma); | |
557 | engine->status_page.page_addr = memset(vaddr, 0, PAGE_SIZE); | |
558 | ||
559 | DRM_DEBUG_DRIVER("%s hws offset: 0x%08x\n", | |
560 | engine->name, i915_ggtt_offset(vma)); | |
561 | return 0; | |
562 | ||
563 | err_unpin: | |
564 | i915_vma_unpin(vma); | |
565 | err: | |
566 | i915_gem_object_put(obj); | |
567 | return ret; | |
568 | } | |
569 | ||
570 | static int init_phys_status_page(struct intel_engine_cs *engine) | |
571 | { | |
572 | struct drm_i915_private *dev_priv = engine->i915; | |
573 | ||
574 | GEM_BUG_ON(engine->id != RCS); | |
575 | ||
576 | dev_priv->status_page_dmah = | |
577 | drm_pci_alloc(&dev_priv->drm, PAGE_SIZE, PAGE_SIZE); | |
578 | if (!dev_priv->status_page_dmah) | |
579 | return -ENOMEM; | |
580 | ||
581 | engine->status_page.page_addr = dev_priv->status_page_dmah->vaddr; | |
582 | memset(engine->status_page.page_addr, 0, PAGE_SIZE); | |
583 | ||
584 | return 0; | |
585 | } | |
586 | ||
019bf277 TU |
587 | /** |
588 | * intel_engines_init_common - initialize cengine state which might require hw access | |
589 | * @engine: Engine to initialize. | |
590 | * | |
591 | * Initializes @engine@ structure members shared between legacy and execlists | |
592 | * submission modes which do require hardware access. | |
593 | * | |
594 | * Typcally done at later stages of submission mode specific engine setup. | |
595 | * | |
596 | * Returns zero on success or an error code on failure. | |
597 | */ | |
598 | int intel_engine_init_common(struct intel_engine_cs *engine) | |
599 | { | |
266a240b | 600 | struct intel_ring *ring; |
019bf277 TU |
601 | int ret; |
602 | ||
ff44ad51 CW |
603 | engine->set_default_submission(engine); |
604 | ||
e8a9c58f CW |
605 | /* We may need to do things with the shrinker which |
606 | * require us to immediately switch back to the default | |
607 | * context. This can cause a problem as pinning the | |
608 | * default context also requires GTT space which may not | |
609 | * be available. To avoid this we always pin the default | |
610 | * context. | |
611 | */ | |
266a240b CW |
612 | ring = engine->context_pin(engine, engine->i915->kernel_context); |
613 | if (IS_ERR(ring)) | |
614 | return PTR_ERR(ring); | |
019bf277 | 615 | |
e7af3116 CW |
616 | /* |
617 | * Similarly the preempt context must always be available so that | |
618 | * we can interrupt the engine at any time. | |
619 | */ | |
620 | if (INTEL_INFO(engine->i915)->has_logical_ring_preemption) { | |
621 | ring = engine->context_pin(engine, | |
622 | engine->i915->preempt_context); | |
623 | if (IS_ERR(ring)) { | |
624 | ret = PTR_ERR(ring); | |
625 | goto err_unpin_kernel; | |
626 | } | |
627 | } | |
628 | ||
e8a9c58f CW |
629 | ret = intel_engine_init_breadcrumbs(engine); |
630 | if (ret) | |
e7af3116 | 631 | goto err_unpin_preempt; |
e8a9c58f | 632 | |
4e50f082 CW |
633 | ret = i915_gem_render_state_init(engine); |
634 | if (ret) | |
486e93f7 DCS |
635 | goto err_breadcrumbs; |
636 | ||
637 | if (HWS_NEEDS_PHYSICAL(engine->i915)) | |
638 | ret = init_phys_status_page(engine); | |
639 | else | |
640 | ret = init_status_page(engine); | |
641 | if (ret) | |
642 | goto err_rs_fini; | |
4e50f082 | 643 | |
7756e454 | 644 | return 0; |
e8a9c58f | 645 | |
486e93f7 DCS |
646 | err_rs_fini: |
647 | i915_gem_render_state_fini(engine); | |
648 | err_breadcrumbs: | |
649 | intel_engine_fini_breadcrumbs(engine); | |
e7af3116 CW |
650 | err_unpin_preempt: |
651 | if (INTEL_INFO(engine->i915)->has_logical_ring_preemption) | |
652 | engine->context_unpin(engine, engine->i915->preempt_context); | |
653 | err_unpin_kernel: | |
e8a9c58f CW |
654 | engine->context_unpin(engine, engine->i915->kernel_context); |
655 | return ret; | |
019bf277 | 656 | } |
96a945aa CW |
657 | |
658 | /** | |
659 | * intel_engines_cleanup_common - cleans up the engine state created by | |
660 | * the common initiailizers. | |
661 | * @engine: Engine to cleanup. | |
662 | * | |
663 | * This cleans up everything created by the common helpers. | |
664 | */ | |
665 | void intel_engine_cleanup_common(struct intel_engine_cs *engine) | |
666 | { | |
adc320c4 CW |
667 | intel_engine_cleanup_scratch(engine); |
668 | ||
486e93f7 DCS |
669 | if (HWS_NEEDS_PHYSICAL(engine->i915)) |
670 | cleanup_phys_status_page(engine); | |
671 | else | |
672 | cleanup_status_page(engine); | |
673 | ||
4e50f082 | 674 | i915_gem_render_state_fini(engine); |
96a945aa | 675 | intel_engine_fini_breadcrumbs(engine); |
7756e454 | 676 | intel_engine_cleanup_cmd_parser(engine); |
96a945aa | 677 | i915_gem_batch_pool_fini(&engine->batch_pool); |
e8a9c58f | 678 | |
e7af3116 CW |
679 | if (INTEL_INFO(engine->i915)->has_logical_ring_preemption) |
680 | engine->context_unpin(engine, engine->i915->preempt_context); | |
e8a9c58f | 681 | engine->context_unpin(engine, engine->i915->kernel_context); |
96a945aa | 682 | } |
1b36595f CW |
683 | |
684 | u64 intel_engine_get_active_head(struct intel_engine_cs *engine) | |
685 | { | |
686 | struct drm_i915_private *dev_priv = engine->i915; | |
687 | u64 acthd; | |
688 | ||
689 | if (INTEL_GEN(dev_priv) >= 8) | |
690 | acthd = I915_READ64_2x32(RING_ACTHD(engine->mmio_base), | |
691 | RING_ACTHD_UDW(engine->mmio_base)); | |
692 | else if (INTEL_GEN(dev_priv) >= 4) | |
693 | acthd = I915_READ(RING_ACTHD(engine->mmio_base)); | |
694 | else | |
695 | acthd = I915_READ(ACTHD); | |
696 | ||
697 | return acthd; | |
698 | } | |
699 | ||
700 | u64 intel_engine_get_last_batch_head(struct intel_engine_cs *engine) | |
701 | { | |
702 | struct drm_i915_private *dev_priv = engine->i915; | |
703 | u64 bbaddr; | |
704 | ||
705 | if (INTEL_GEN(dev_priv) >= 8) | |
706 | bbaddr = I915_READ64_2x32(RING_BBADDR(engine->mmio_base), | |
707 | RING_BBADDR_UDW(engine->mmio_base)); | |
708 | else | |
709 | bbaddr = I915_READ(RING_BBADDR(engine->mmio_base)); | |
710 | ||
711 | return bbaddr; | |
712 | } | |
0e704476 CW |
713 | |
714 | const char *i915_cache_level_str(struct drm_i915_private *i915, int type) | |
715 | { | |
716 | switch (type) { | |
717 | case I915_CACHE_NONE: return " uncached"; | |
718 | case I915_CACHE_LLC: return HAS_LLC(i915) ? " LLC" : " snooped"; | |
719 | case I915_CACHE_L3_LLC: return " L3+LLC"; | |
720 | case I915_CACHE_WT: return " WT"; | |
721 | default: return ""; | |
722 | } | |
723 | } | |
724 | ||
725 | static inline uint32_t | |
726 | read_subslice_reg(struct drm_i915_private *dev_priv, int slice, | |
727 | int subslice, i915_reg_t reg) | |
728 | { | |
729 | uint32_t mcr; | |
730 | uint32_t ret; | |
731 | enum forcewake_domains fw_domains; | |
732 | ||
733 | fw_domains = intel_uncore_forcewake_for_reg(dev_priv, reg, | |
734 | FW_REG_READ); | |
735 | fw_domains |= intel_uncore_forcewake_for_reg(dev_priv, | |
736 | GEN8_MCR_SELECTOR, | |
737 | FW_REG_READ | FW_REG_WRITE); | |
738 | ||
739 | spin_lock_irq(&dev_priv->uncore.lock); | |
740 | intel_uncore_forcewake_get__locked(dev_priv, fw_domains); | |
741 | ||
742 | mcr = I915_READ_FW(GEN8_MCR_SELECTOR); | |
743 | /* | |
744 | * The HW expects the slice and sublice selectors to be reset to 0 | |
745 | * after reading out the registers. | |
746 | */ | |
747 | WARN_ON_ONCE(mcr & (GEN8_MCR_SLICE_MASK | GEN8_MCR_SUBSLICE_MASK)); | |
748 | mcr &= ~(GEN8_MCR_SLICE_MASK | GEN8_MCR_SUBSLICE_MASK); | |
749 | mcr |= GEN8_MCR_SLICE(slice) | GEN8_MCR_SUBSLICE(subslice); | |
750 | I915_WRITE_FW(GEN8_MCR_SELECTOR, mcr); | |
751 | ||
752 | ret = I915_READ_FW(reg); | |
753 | ||
754 | mcr &= ~(GEN8_MCR_SLICE_MASK | GEN8_MCR_SUBSLICE_MASK); | |
755 | I915_WRITE_FW(GEN8_MCR_SELECTOR, mcr); | |
756 | ||
757 | intel_uncore_forcewake_put__locked(dev_priv, fw_domains); | |
758 | spin_unlock_irq(&dev_priv->uncore.lock); | |
759 | ||
760 | return ret; | |
761 | } | |
762 | ||
763 | /* NB: please notice the memset */ | |
764 | void intel_engine_get_instdone(struct intel_engine_cs *engine, | |
765 | struct intel_instdone *instdone) | |
766 | { | |
767 | struct drm_i915_private *dev_priv = engine->i915; | |
768 | u32 mmio_base = engine->mmio_base; | |
769 | int slice; | |
770 | int subslice; | |
771 | ||
772 | memset(instdone, 0, sizeof(*instdone)); | |
773 | ||
774 | switch (INTEL_GEN(dev_priv)) { | |
775 | default: | |
776 | instdone->instdone = I915_READ(RING_INSTDONE(mmio_base)); | |
777 | ||
778 | if (engine->id != RCS) | |
779 | break; | |
780 | ||
781 | instdone->slice_common = I915_READ(GEN7_SC_INSTDONE); | |
782 | for_each_instdone_slice_subslice(dev_priv, slice, subslice) { | |
783 | instdone->sampler[slice][subslice] = | |
784 | read_subslice_reg(dev_priv, slice, subslice, | |
785 | GEN7_SAMPLER_INSTDONE); | |
786 | instdone->row[slice][subslice] = | |
787 | read_subslice_reg(dev_priv, slice, subslice, | |
788 | GEN7_ROW_INSTDONE); | |
789 | } | |
790 | break; | |
791 | case 7: | |
792 | instdone->instdone = I915_READ(RING_INSTDONE(mmio_base)); | |
793 | ||
794 | if (engine->id != RCS) | |
795 | break; | |
796 | ||
797 | instdone->slice_common = I915_READ(GEN7_SC_INSTDONE); | |
798 | instdone->sampler[0][0] = I915_READ(GEN7_SAMPLER_INSTDONE); | |
799 | instdone->row[0][0] = I915_READ(GEN7_ROW_INSTDONE); | |
800 | ||
801 | break; | |
802 | case 6: | |
803 | case 5: | |
804 | case 4: | |
805 | instdone->instdone = I915_READ(RING_INSTDONE(mmio_base)); | |
806 | ||
807 | if (engine->id == RCS) | |
808 | /* HACK: Using the wrong struct member */ | |
809 | instdone->slice_common = I915_READ(GEN4_INSTDONE1); | |
810 | break; | |
811 | case 3: | |
812 | case 2: | |
813 | instdone->instdone = I915_READ(GEN2_INSTDONE); | |
814 | break; | |
815 | } | |
816 | } | |
f97fbf96 | 817 | |
133b4bd7 TU |
818 | static int wa_add(struct drm_i915_private *dev_priv, |
819 | i915_reg_t addr, | |
820 | const u32 mask, const u32 val) | |
821 | { | |
822 | const u32 idx = dev_priv->workarounds.count; | |
823 | ||
824 | if (WARN_ON(idx >= I915_MAX_WA_REGS)) | |
825 | return -ENOSPC; | |
826 | ||
827 | dev_priv->workarounds.reg[idx].addr = addr; | |
828 | dev_priv->workarounds.reg[idx].value = val; | |
829 | dev_priv->workarounds.reg[idx].mask = mask; | |
830 | ||
831 | dev_priv->workarounds.count++; | |
832 | ||
833 | return 0; | |
834 | } | |
835 | ||
836 | #define WA_REG(addr, mask, val) do { \ | |
837 | const int r = wa_add(dev_priv, (addr), (mask), (val)); \ | |
838 | if (r) \ | |
839 | return r; \ | |
840 | } while (0) | |
841 | ||
842 | #define WA_SET_BIT_MASKED(addr, mask) \ | |
843 | WA_REG(addr, (mask), _MASKED_BIT_ENABLE(mask)) | |
844 | ||
845 | #define WA_CLR_BIT_MASKED(addr, mask) \ | |
846 | WA_REG(addr, (mask), _MASKED_BIT_DISABLE(mask)) | |
847 | ||
848 | #define WA_SET_FIELD_MASKED(addr, mask, value) \ | |
849 | WA_REG(addr, mask, _MASKED_FIELD(mask, value)) | |
850 | ||
133b4bd7 TU |
851 | static int wa_ring_whitelist_reg(struct intel_engine_cs *engine, |
852 | i915_reg_t reg) | |
853 | { | |
854 | struct drm_i915_private *dev_priv = engine->i915; | |
855 | struct i915_workarounds *wa = &dev_priv->workarounds; | |
856 | const uint32_t index = wa->hw_whitelist_count[engine->id]; | |
857 | ||
858 | if (WARN_ON(index >= RING_MAX_NONPRIV_SLOTS)) | |
859 | return -EINVAL; | |
860 | ||
32ced39c OM |
861 | I915_WRITE(RING_FORCE_TO_NONPRIV(engine->mmio_base, index), |
862 | i915_mmio_reg_offset(reg)); | |
133b4bd7 TU |
863 | wa->hw_whitelist_count[engine->id]++; |
864 | ||
865 | return 0; | |
866 | } | |
867 | ||
868 | static int gen8_init_workarounds(struct intel_engine_cs *engine) | |
869 | { | |
870 | struct drm_i915_private *dev_priv = engine->i915; | |
871 | ||
872 | WA_SET_BIT_MASKED(INSTPM, INSTPM_FORCE_ORDERING); | |
873 | ||
874 | /* WaDisableAsyncFlipPerfMode:bdw,chv */ | |
875 | WA_SET_BIT_MASKED(MI_MODE, ASYNC_FLIP_PERF_DISABLE); | |
876 | ||
877 | /* WaDisablePartialInstShootdown:bdw,chv */ | |
878 | WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, | |
879 | PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE); | |
880 | ||
881 | /* Use Force Non-Coherent whenever executing a 3D context. This is a | |
882 | * workaround for for a possible hang in the unlikely event a TLB | |
883 | * invalidation occurs during a PSD flush. | |
884 | */ | |
885 | /* WaForceEnableNonCoherent:bdw,chv */ | |
886 | /* WaHdcDisableFetchWhenMasked:bdw,chv */ | |
887 | WA_SET_BIT_MASKED(HDC_CHICKEN0, | |
888 | HDC_DONOT_FETCH_MEM_WHEN_MASKED | | |
889 | HDC_FORCE_NON_COHERENT); | |
890 | ||
891 | /* From the Haswell PRM, Command Reference: Registers, CACHE_MODE_0: | |
892 | * "The Hierarchical Z RAW Stall Optimization allows non-overlapping | |
893 | * polygons in the same 8x4 pixel/sample area to be processed without | |
894 | * stalling waiting for the earlier ones to write to Hierarchical Z | |
895 | * buffer." | |
896 | * | |
897 | * This optimization is off by default for BDW and CHV; turn it on. | |
898 | */ | |
899 | WA_CLR_BIT_MASKED(CACHE_MODE_0_GEN7, HIZ_RAW_STALL_OPT_DISABLE); | |
900 | ||
901 | /* Wa4x4STCOptimizationDisable:bdw,chv */ | |
902 | WA_SET_BIT_MASKED(CACHE_MODE_1, GEN8_4x4_STC_OPTIMIZATION_DISABLE); | |
903 | ||
904 | /* | |
905 | * BSpec recommends 8x4 when MSAA is used, | |
906 | * however in practice 16x4 seems fastest. | |
907 | * | |
908 | * Note that PS/WM thread counts depend on the WIZ hashing | |
909 | * disable bit, which we don't touch here, but it's good | |
910 | * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM). | |
911 | */ | |
912 | WA_SET_FIELD_MASKED(GEN7_GT_MODE, | |
913 | GEN6_WIZ_HASHING_MASK, | |
914 | GEN6_WIZ_HASHING_16x4); | |
915 | ||
916 | return 0; | |
917 | } | |
918 | ||
919 | static int bdw_init_workarounds(struct intel_engine_cs *engine) | |
920 | { | |
921 | struct drm_i915_private *dev_priv = engine->i915; | |
922 | int ret; | |
923 | ||
924 | ret = gen8_init_workarounds(engine); | |
925 | if (ret) | |
926 | return ret; | |
927 | ||
928 | /* WaDisableThreadStallDopClockGating:bdw (pre-production) */ | |
929 | WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, STALL_DOP_GATING_DISABLE); | |
930 | ||
931 | /* WaDisableDopClockGating:bdw | |
932 | * | |
933 | * Also see the related UCGTCL1 write in broadwell_init_clock_gating() | |
934 | * to disable EUTC clock gating. | |
935 | */ | |
936 | WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2, | |
937 | DOP_CLOCK_GATING_DISABLE); | |
938 | ||
939 | WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3, | |
940 | GEN8_SAMPLER_POWER_BYPASS_DIS); | |
941 | ||
942 | WA_SET_BIT_MASKED(HDC_CHICKEN0, | |
943 | /* WaForceContextSaveRestoreNonCoherent:bdw */ | |
944 | HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT | | |
945 | /* WaDisableFenceDestinationToSLM:bdw (pre-prod) */ | |
946 | (IS_BDW_GT3(dev_priv) ? HDC_FENCE_DEST_SLM_DISABLE : 0)); | |
947 | ||
948 | return 0; | |
949 | } | |
950 | ||
951 | static int chv_init_workarounds(struct intel_engine_cs *engine) | |
952 | { | |
953 | struct drm_i915_private *dev_priv = engine->i915; | |
954 | int ret; | |
955 | ||
956 | ret = gen8_init_workarounds(engine); | |
957 | if (ret) | |
958 | return ret; | |
959 | ||
960 | /* WaDisableThreadStallDopClockGating:chv */ | |
961 | WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, STALL_DOP_GATING_DISABLE); | |
962 | ||
963 | /* Improve HiZ throughput on CHV. */ | |
964 | WA_SET_BIT_MASKED(HIZ_CHICKEN, CHV_HZ_8X8_MODE_IN_1X); | |
965 | ||
966 | return 0; | |
967 | } | |
968 | ||
969 | static int gen9_init_workarounds(struct intel_engine_cs *engine) | |
970 | { | |
971 | struct drm_i915_private *dev_priv = engine->i915; | |
972 | int ret; | |
973 | ||
46c26662 | 974 | /* WaConextSwitchWithConcurrentTLBInvalidate:skl,bxt,kbl,glk,cfl */ |
133b4bd7 TU |
975 | I915_WRITE(GEN9_CSFE_CHICKEN1_RCS, _MASKED_BIT_ENABLE(GEN9_PREEMPT_GPGPU_SYNC_SWITCH_DISABLE)); |
976 | ||
46c26662 | 977 | /* WaEnableLbsSlaRetryTimerDecrement:skl,bxt,kbl,glk,cfl */ |
133b4bd7 TU |
978 | I915_WRITE(BDW_SCRATCH1, I915_READ(BDW_SCRATCH1) | |
979 | GEN9_LBS_SLA_RETRY_TIMER_DECREMENT_ENABLE); | |
980 | ||
98eed3d1 RV |
981 | /* WaDisableKillLogic:bxt,skl,kbl */ |
982 | if (!IS_COFFEELAKE(dev_priv)) | |
983 | I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | | |
984 | ECOCHK_DIS_TLB); | |
133b4bd7 | 985 | |
93564044 VS |
986 | if (HAS_LLC(dev_priv)) { |
987 | /* WaCompressedResourceSamplerPbeMediaNewHashMode:skl,kbl | |
988 | * | |
989 | * Must match Display Engine. See | |
990 | * WaCompressedResourceDisplayNewHashMode. | |
991 | */ | |
992 | WA_SET_BIT_MASKED(COMMON_SLICE_CHICKEN2, | |
993 | GEN9_PBE_COMPRESSED_HASH_SELECTION); | |
994 | WA_SET_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN7, | |
995 | GEN9_SAMPLER_HASH_COMPRESSED_READ_ADDR); | |
53221e11 CW |
996 | |
997 | I915_WRITE(MMCD_MISC_CTRL, | |
998 | I915_READ(MMCD_MISC_CTRL) | | |
999 | MMCD_PCLA | | |
1000 | MMCD_HOTSPOT_EN); | |
93564044 VS |
1001 | } |
1002 | ||
46c26662 RV |
1003 | /* WaClearFlowControlGpgpuContextSave:skl,bxt,kbl,glk,cfl */ |
1004 | /* WaDisablePartialInstShootdown:skl,bxt,kbl,glk,cfl */ | |
133b4bd7 TU |
1005 | WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, |
1006 | FLOW_CONTROL_ENABLE | | |
1007 | PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE); | |
1008 | ||
1009 | /* Syncing dependencies between camera and graphics:skl,bxt,kbl */ | |
46c26662 RV |
1010 | if (!IS_COFFEELAKE(dev_priv)) |
1011 | WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3, | |
1012 | GEN9_DISABLE_OCL_OOB_SUPPRESS_LOGIC); | |
133b4bd7 TU |
1013 | |
1014 | /* WaDisableDgMirrorFixInHalfSliceChicken5:bxt */ | |
1015 | if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) | |
1016 | WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5, | |
1017 | GEN9_DG_MIRROR_FIX_ENABLE); | |
1018 | ||
1019 | /* WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken:bxt */ | |
1020 | if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) { | |
1021 | WA_SET_BIT_MASKED(GEN7_COMMON_SLICE_CHICKEN1, | |
1022 | GEN9_RHWO_OPTIMIZATION_DISABLE); | |
1023 | /* | |
1024 | * WA also requires GEN9_SLICE_COMMON_ECO_CHICKEN0[14:14] to be set | |
1025 | * but we do that in per ctx batchbuffer as there is an issue | |
1026 | * with this register not getting restored on ctx restore | |
1027 | */ | |
1028 | } | |
1029 | ||
46c26662 RV |
1030 | /* WaEnableYV12BugFixInHalfSliceChicken7:skl,bxt,kbl,glk,cfl */ |
1031 | /* WaEnableSamplerGPGPUPreemptionSupport:skl,bxt,kbl,cfl */ | |
133b4bd7 | 1032 | WA_SET_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN7, |
0b71cea2 | 1033 | GEN9_ENABLE_YV12_BUGFIX | |
133b4bd7 TU |
1034 | GEN9_ENABLE_GPGPU_PREEMPTION); |
1035 | ||
46c26662 RV |
1036 | /* Wa4x4STCOptimizationDisable:skl,bxt,kbl,glk,cfl */ |
1037 | /* WaDisablePartialResolveInVc:skl,bxt,kbl,cfl */ | |
133b4bd7 TU |
1038 | WA_SET_BIT_MASKED(CACHE_MODE_1, (GEN8_4x4_STC_OPTIMIZATION_DISABLE | |
1039 | GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE)); | |
1040 | ||
46c26662 | 1041 | /* WaCcsTlbPrefetchDisable:skl,bxt,kbl,glk,cfl */ |
133b4bd7 TU |
1042 | WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5, |
1043 | GEN9_CCS_TLB_PREFETCH_ENABLE); | |
1044 | ||
1045 | /* WaDisableMaskBasedCammingInRCC:bxt */ | |
1046 | if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) | |
1047 | WA_SET_BIT_MASKED(SLICE_ECO_CHICKEN0, | |
1048 | PIXEL_MASK_CAMMING_DISABLE); | |
1049 | ||
46c26662 | 1050 | /* WaForceContextSaveRestoreNonCoherent:skl,bxt,kbl,cfl */ |
133b4bd7 TU |
1051 | WA_SET_BIT_MASKED(HDC_CHICKEN0, |
1052 | HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT | | |
1053 | HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE); | |
1054 | ||
1055 | /* WaForceEnableNonCoherent and WaDisableHDCInvalidation are | |
1056 | * both tied to WaForceContextSaveRestoreNonCoherent | |
1057 | * in some hsds for skl. We keep the tie for all gen9. The | |
1058 | * documentation is a bit hazy and so we want to get common behaviour, | |
1059 | * even though there is no clear evidence we would need both on kbl/bxt. | |
1060 | * This area has been source of system hangs so we play it safe | |
1061 | * and mimic the skl regardless of what bspec says. | |
1062 | * | |
1063 | * Use Force Non-Coherent whenever executing a 3D context. This | |
1064 | * is a workaround for a possible hang in the unlikely event | |
1065 | * a TLB invalidation occurs during a PSD flush. | |
1066 | */ | |
1067 | ||
46c26662 | 1068 | /* WaForceEnableNonCoherent:skl,bxt,kbl,cfl */ |
133b4bd7 TU |
1069 | WA_SET_BIT_MASKED(HDC_CHICKEN0, |
1070 | HDC_FORCE_NON_COHERENT); | |
1071 | ||
98eed3d1 RV |
1072 | /* WaDisableHDCInvalidation:skl,bxt,kbl,cfl */ |
1073 | I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | | |
1074 | BDW_DISABLE_HDC_INVALIDATION); | |
133b4bd7 | 1075 | |
46c26662 | 1076 | /* WaDisableSamplerPowerBypassForSOPingPong:skl,bxt,kbl,cfl */ |
133b4bd7 TU |
1077 | if (IS_SKYLAKE(dev_priv) || |
1078 | IS_KABYLAKE(dev_priv) || | |
46c26662 | 1079 | IS_COFFEELAKE(dev_priv) || |
133b4bd7 TU |
1080 | IS_BXT_REVID(dev_priv, 0, BXT_REVID_B0)) |
1081 | WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3, | |
1082 | GEN8_SAMPLER_POWER_BYPASS_DIS); | |
1083 | ||
46c26662 | 1084 | /* WaDisableSTUnitPowerOptimization:skl,bxt,kbl,glk,cfl */ |
133b4bd7 TU |
1085 | WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN2, GEN8_ST_PO_DISABLE); |
1086 | ||
46c26662 | 1087 | /* WaOCLCoherentLineFlush:skl,bxt,kbl,cfl */ |
133b4bd7 TU |
1088 | I915_WRITE(GEN8_L3SQCREG4, (I915_READ(GEN8_L3SQCREG4) | |
1089 | GEN8_LQSC_FLUSH_COHERENT_LINES)); | |
1090 | ||
5152defe MW |
1091 | /* |
1092 | * Supporting preemption with fine-granularity requires changes in the | |
1093 | * batch buffer programming. Since we can't break old userspace, we | |
1094 | * need to set our default preemption level to safe value. Userspace is | |
1095 | * still able to use more fine-grained preemption levels, since in | |
1096 | * WaEnablePreemptionGranularityControlByUMD we're whitelisting the | |
1097 | * per-ctx register. As such, WaDisable{3D,GPGPU}MidCmdPreemption are | |
1098 | * not real HW workarounds, but merely a way to start using preemption | |
1099 | * while maintaining old contract with userspace. | |
1100 | */ | |
1101 | ||
1102 | /* WaDisable3DMidCmdPreemption:skl,bxt,glk,cfl,[cnl] */ | |
1103 | WA_CLR_BIT_MASKED(GEN8_CS_CHICKEN1, GEN9_PREEMPT_3D_OBJECT_LEVEL); | |
1104 | ||
1105 | /* WaDisableGPGPUMidCmdPreemption:skl,bxt,blk,cfl,[cnl] */ | |
1106 | WA_SET_FIELD_MASKED(GEN8_CS_CHICKEN1, GEN9_PREEMPT_GPGPU_LEVEL_MASK, | |
1107 | GEN9_PREEMPT_GPGPU_COMMAND_LEVEL); | |
1108 | ||
46c26662 | 1109 | /* WaVFEStateAfterPipeControlwithMediaStateClear:skl,bxt,glk,cfl */ |
133b4bd7 TU |
1110 | ret = wa_ring_whitelist_reg(engine, GEN9_CTX_PREEMPT_REG); |
1111 | if (ret) | |
1112 | return ret; | |
1113 | ||
1e998343 JM |
1114 | /* WaEnablePreemptionGranularityControlByUMD:skl,bxt,kbl,cfl,[cnl] */ |
1115 | I915_WRITE(GEN7_FF_SLICE_CS_CHICKEN1, | |
1116 | _MASKED_BIT_ENABLE(GEN9_FFSC_PERCTX_PREEMPT_CTRL)); | |
1117 | ret = wa_ring_whitelist_reg(engine, GEN8_CS_CHICKEN1); | |
133b4bd7 TU |
1118 | if (ret) |
1119 | return ret; | |
1120 | ||
46c26662 | 1121 | /* WaAllowUMDToModifyHDCChicken1:skl,bxt,kbl,glk,cfl */ |
133b4bd7 TU |
1122 | ret = wa_ring_whitelist_reg(engine, GEN8_HDC_CHICKEN1); |
1123 | if (ret) | |
1124 | return ret; | |
1125 | ||
1126 | return 0; | |
1127 | } | |
1128 | ||
1129 | static int skl_tune_iz_hashing(struct intel_engine_cs *engine) | |
1130 | { | |
1131 | struct drm_i915_private *dev_priv = engine->i915; | |
1132 | u8 vals[3] = { 0, 0, 0 }; | |
1133 | unsigned int i; | |
1134 | ||
1135 | for (i = 0; i < 3; i++) { | |
1136 | u8 ss; | |
1137 | ||
1138 | /* | |
1139 | * Only consider slices where one, and only one, subslice has 7 | |
1140 | * EUs | |
1141 | */ | |
1142 | if (!is_power_of_2(INTEL_INFO(dev_priv)->sseu.subslice_7eu[i])) | |
1143 | continue; | |
1144 | ||
1145 | /* | |
1146 | * subslice_7eu[i] != 0 (because of the check above) and | |
1147 | * ss_max == 4 (maximum number of subslices possible per slice) | |
1148 | * | |
1149 | * -> 0 <= ss <= 3; | |
1150 | */ | |
1151 | ss = ffs(INTEL_INFO(dev_priv)->sseu.subslice_7eu[i]) - 1; | |
1152 | vals[i] = 3 - ss; | |
1153 | } | |
1154 | ||
1155 | if (vals[0] == 0 && vals[1] == 0 && vals[2] == 0) | |
1156 | return 0; | |
1157 | ||
1158 | /* Tune IZ hashing. See intel_device_info_runtime_init() */ | |
1159 | WA_SET_FIELD_MASKED(GEN7_GT_MODE, | |
1160 | GEN9_IZ_HASHING_MASK(2) | | |
1161 | GEN9_IZ_HASHING_MASK(1) | | |
1162 | GEN9_IZ_HASHING_MASK(0), | |
1163 | GEN9_IZ_HASHING(2, vals[2]) | | |
1164 | GEN9_IZ_HASHING(1, vals[1]) | | |
1165 | GEN9_IZ_HASHING(0, vals[0])); | |
1166 | ||
1167 | return 0; | |
1168 | } | |
1169 | ||
1170 | static int skl_init_workarounds(struct intel_engine_cs *engine) | |
1171 | { | |
1172 | struct drm_i915_private *dev_priv = engine->i915; | |
1173 | int ret; | |
1174 | ||
1175 | ret = gen9_init_workarounds(engine); | |
1176 | if (ret) | |
1177 | return ret; | |
1178 | ||
133b4bd7 TU |
1179 | /* WaEnableGapsTsvCreditFix:skl */ |
1180 | I915_WRITE(GEN8_GARBCNTL, (I915_READ(GEN8_GARBCNTL) | | |
1181 | GEN9_GAPS_TSV_CREDIT_DISABLE)); | |
1182 | ||
1183 | /* WaDisableGafsUnitClkGating:skl */ | |
4827c547 OM |
1184 | I915_WRITE(GEN7_UCGCTL4, (I915_READ(GEN7_UCGCTL4) | |
1185 | GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE)); | |
133b4bd7 TU |
1186 | |
1187 | /* WaInPlaceDecompressionHang:skl */ | |
1188 | if (IS_SKL_REVID(dev_priv, SKL_REVID_H0, REVID_FOREVER)) | |
efc886cb OM |
1189 | I915_WRITE(GEN9_GAMT_ECO_REG_RW_IA, |
1190 | (I915_READ(GEN9_GAMT_ECO_REG_RW_IA) | | |
1191 | GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS)); | |
133b4bd7 TU |
1192 | |
1193 | /* WaDisableLSQCROPERFforOCL:skl */ | |
1194 | ret = wa_ring_whitelist_reg(engine, GEN8_L3SQCREG4); | |
1195 | if (ret) | |
1196 | return ret; | |
1197 | ||
1198 | return skl_tune_iz_hashing(engine); | |
1199 | } | |
1200 | ||
1201 | static int bxt_init_workarounds(struct intel_engine_cs *engine) | |
1202 | { | |
1203 | struct drm_i915_private *dev_priv = engine->i915; | |
1204 | int ret; | |
1205 | ||
1206 | ret = gen9_init_workarounds(engine); | |
1207 | if (ret) | |
1208 | return ret; | |
1209 | ||
1210 | /* WaStoreMultiplePTEenable:bxt */ | |
1211 | /* This is a requirement according to Hardware specification */ | |
1212 | if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) | |
1213 | I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_TLBPF); | |
1214 | ||
1215 | /* WaSetClckGatingDisableMedia:bxt */ | |
1216 | if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) { | |
1217 | I915_WRITE(GEN7_MISCCPCTL, (I915_READ(GEN7_MISCCPCTL) & | |
1218 | ~GEN8_DOP_CLOCK_GATE_MEDIA_ENABLE)); | |
1219 | } | |
1220 | ||
1221 | /* WaDisableThreadStallDopClockGating:bxt */ | |
1222 | WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, | |
1223 | STALL_DOP_GATING_DISABLE); | |
1224 | ||
1225 | /* WaDisablePooledEuLoadBalancingFix:bxt */ | |
1226 | if (IS_BXT_REVID(dev_priv, BXT_REVID_B0, REVID_FOREVER)) { | |
212154ba OM |
1227 | I915_WRITE(FF_SLICE_CS_CHICKEN2, |
1228 | _MASKED_BIT_ENABLE(GEN9_POOLED_EU_LOAD_BALANCING_FIX_DISABLE)); | |
133b4bd7 TU |
1229 | } |
1230 | ||
1231 | /* WaDisableSbeCacheDispatchPortSharing:bxt */ | |
1232 | if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_B0)) { | |
1233 | WA_SET_BIT_MASKED( | |
1234 | GEN7_HALF_SLICE_CHICKEN1, | |
1235 | GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE); | |
1236 | } | |
1237 | ||
1238 | /* WaDisableObjectLevelPreemptionForTrifanOrPolygon:bxt */ | |
1239 | /* WaDisableObjectLevelPreemptionForInstancedDraw:bxt */ | |
1240 | /* WaDisableObjectLevelPreemtionForInstanceId:bxt */ | |
1241 | /* WaDisableLSQCROPERFforOCL:bxt */ | |
1242 | if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) { | |
1243 | ret = wa_ring_whitelist_reg(engine, GEN9_CS_DEBUG_MODE1); | |
1244 | if (ret) | |
1245 | return ret; | |
1246 | ||
1247 | ret = wa_ring_whitelist_reg(engine, GEN8_L3SQCREG4); | |
1248 | if (ret) | |
1249 | return ret; | |
1250 | } | |
1251 | ||
1252 | /* WaProgramL3SqcReg1DefaultForPerf:bxt */ | |
1253 | if (IS_BXT_REVID(dev_priv, BXT_REVID_B0, REVID_FOREVER)) | |
1254 | I915_WRITE(GEN8_L3SQCREG1, L3_GENERAL_PRIO_CREDITS(62) | | |
1255 | L3_HIGH_PRIO_CREDITS(2)); | |
1256 | ||
1257 | /* WaToEnableHwFixForPushConstHWBug:bxt */ | |
1258 | if (IS_BXT_REVID(dev_priv, BXT_REVID_C0, REVID_FOREVER)) | |
1259 | WA_SET_BIT_MASKED(COMMON_SLICE_CHICKEN2, | |
1260 | GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION); | |
1261 | ||
1262 | /* WaInPlaceDecompressionHang:bxt */ | |
1263 | if (IS_BXT_REVID(dev_priv, BXT_REVID_C0, REVID_FOREVER)) | |
efc886cb OM |
1264 | I915_WRITE(GEN9_GAMT_ECO_REG_RW_IA, |
1265 | (I915_READ(GEN9_GAMT_ECO_REG_RW_IA) | | |
1266 | GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS)); | |
133b4bd7 TU |
1267 | |
1268 | return 0; | |
1269 | } | |
1270 | ||
90007bca RV |
1271 | static int cnl_init_workarounds(struct intel_engine_cs *engine) |
1272 | { | |
1273 | struct drm_i915_private *dev_priv = engine->i915; | |
1274 | int ret; | |
1275 | ||
6cf20a01 | 1276 | /* WaDisableI2mCycleOnWRPort:cnl (pre-prod) */ |
86ebb015 | 1277 | if (IS_CNL_REVID(dev_priv, CNL_REVID_B0, CNL_REVID_B0)) |
6cf20a01 OM |
1278 | I915_WRITE(GAMT_CHKN_BIT_REG, |
1279 | (I915_READ(GAMT_CHKN_BIT_REG) | | |
1280 | GAMT_CHKN_DISABLE_I2M_CYCLE_ON_WR_PORT)); | |
86ebb015 | 1281 | |
acfb5554 RV |
1282 | /* WaForceContextSaveRestoreNonCoherent:cnl */ |
1283 | WA_SET_BIT_MASKED(CNL_HDC_CHICKEN0, | |
1284 | HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT); | |
1285 | ||
aa9f4c4f RV |
1286 | /* WaThrottleEUPerfToAvoidTDBackPressure:cnl(pre-prod) */ |
1287 | if (IS_CNL_REVID(dev_priv, CNL_REVID_B0, CNL_REVID_B0)) | |
1288 | WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, THROTTLE_12_5); | |
1289 | ||
e6d1a4f6 RV |
1290 | /* WaDisableReplayBufferBankArbitrationOptimization:cnl */ |
1291 | WA_SET_BIT_MASKED(COMMON_SLICE_CHICKEN2, | |
1292 | GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION); | |
1293 | ||
d1d24754 RV |
1294 | /* WaDisableEnhancedSBEVertexCaching:cnl (pre-prod) */ |
1295 | if (IS_CNL_REVID(dev_priv, 0, CNL_REVID_B0)) | |
1296 | WA_SET_BIT_MASKED(COMMON_SLICE_CHICKEN2, | |
1297 | GEN8_CSC2_SBE_VUE_CACHE_CONSERVATIVE); | |
1298 | ||
90007bca | 1299 | /* WaInPlaceDecompressionHang:cnl */ |
efc886cb OM |
1300 | I915_WRITE(GEN9_GAMT_ECO_REG_RW_IA, |
1301 | (I915_READ(GEN9_GAMT_ECO_REG_RW_IA) | | |
1302 | GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS)); | |
90007bca | 1303 | |
2cbecff4 | 1304 | /* WaPushConstantDereferenceHoldDisable:cnl */ |
b27f5901 | 1305 | WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2, PUSH_CONSTANT_DEREF_DISABLE); |
2cbecff4 | 1306 | |
392572fe RV |
1307 | /* FtrEnableFastAnisoL1BankingFix: cnl */ |
1308 | WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3, CNL_FAST_ANISO_L1_BANKING_FIX); | |
1309 | ||
5152defe MW |
1310 | /* WaDisable3DMidCmdPreemption:cnl */ |
1311 | WA_CLR_BIT_MASKED(GEN8_CS_CHICKEN1, GEN9_PREEMPT_3D_OBJECT_LEVEL); | |
1312 | ||
1313 | /* WaDisableGPGPUMidCmdPreemption:cnl */ | |
1314 | WA_SET_FIELD_MASKED(GEN8_CS_CHICKEN1, GEN9_PREEMPT_GPGPU_LEVEL_MASK, | |
1315 | GEN9_PREEMPT_GPGPU_COMMAND_LEVEL); | |
1316 | ||
90007bca | 1317 | /* WaEnablePreemptionGranularityControlByUMD:cnl */ |
1e998343 JM |
1318 | I915_WRITE(GEN7_FF_SLICE_CS_CHICKEN1, |
1319 | _MASKED_BIT_ENABLE(GEN9_FFSC_PERCTX_PREEMPT_CTRL)); | |
90007bca RV |
1320 | ret= wa_ring_whitelist_reg(engine, GEN8_CS_CHICKEN1); |
1321 | if (ret) | |
1322 | return ret; | |
1323 | ||
1324 | return 0; | |
1325 | } | |
1326 | ||
133b4bd7 TU |
1327 | static int kbl_init_workarounds(struct intel_engine_cs *engine) |
1328 | { | |
1329 | struct drm_i915_private *dev_priv = engine->i915; | |
1330 | int ret; | |
1331 | ||
1332 | ret = gen9_init_workarounds(engine); | |
1333 | if (ret) | |
1334 | return ret; | |
1335 | ||
1336 | /* WaEnableGapsTsvCreditFix:kbl */ | |
1337 | I915_WRITE(GEN8_GARBCNTL, (I915_READ(GEN8_GARBCNTL) | | |
1338 | GEN9_GAPS_TSV_CREDIT_DISABLE)); | |
1339 | ||
1340 | /* WaDisableDynamicCreditSharing:kbl */ | |
1341 | if (IS_KBL_REVID(dev_priv, 0, KBL_REVID_B0)) | |
c6ea497c OM |
1342 | I915_WRITE(GAMT_CHKN_BIT_REG, |
1343 | (I915_READ(GAMT_CHKN_BIT_REG) | | |
1344 | GAMT_CHKN_DISABLE_DYNAMIC_CREDIT_SHARING)); | |
133b4bd7 TU |
1345 | |
1346 | /* WaDisableFenceDestinationToSLM:kbl (pre-prod) */ | |
1347 | if (IS_KBL_REVID(dev_priv, KBL_REVID_A0, KBL_REVID_A0)) | |
1348 | WA_SET_BIT_MASKED(HDC_CHICKEN0, | |
1349 | HDC_FENCE_DEST_SLM_DISABLE); | |
1350 | ||
1351 | /* WaToEnableHwFixForPushConstHWBug:kbl */ | |
1352 | if (IS_KBL_REVID(dev_priv, KBL_REVID_C0, REVID_FOREVER)) | |
1353 | WA_SET_BIT_MASKED(COMMON_SLICE_CHICKEN2, | |
1354 | GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION); | |
1355 | ||
1356 | /* WaDisableGafsUnitClkGating:kbl */ | |
4827c547 OM |
1357 | I915_WRITE(GEN7_UCGCTL4, (I915_READ(GEN7_UCGCTL4) | |
1358 | GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE)); | |
133b4bd7 TU |
1359 | |
1360 | /* WaDisableSbeCacheDispatchPortSharing:kbl */ | |
1361 | WA_SET_BIT_MASKED( | |
1362 | GEN7_HALF_SLICE_CHICKEN1, | |
1363 | GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE); | |
1364 | ||
1365 | /* WaInPlaceDecompressionHang:kbl */ | |
efc886cb OM |
1366 | I915_WRITE(GEN9_GAMT_ECO_REG_RW_IA, |
1367 | (I915_READ(GEN9_GAMT_ECO_REG_RW_IA) | | |
1368 | GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS)); | |
133b4bd7 TU |
1369 | |
1370 | /* WaDisableLSQCROPERFforOCL:kbl */ | |
1371 | ret = wa_ring_whitelist_reg(engine, GEN8_L3SQCREG4); | |
1372 | if (ret) | |
1373 | return ret; | |
1374 | ||
1375 | return 0; | |
1376 | } | |
1377 | ||
1378 | static int glk_init_workarounds(struct intel_engine_cs *engine) | |
1379 | { | |
1380 | struct drm_i915_private *dev_priv = engine->i915; | |
1381 | int ret; | |
1382 | ||
1383 | ret = gen9_init_workarounds(engine); | |
1384 | if (ret) | |
1385 | return ret; | |
1386 | ||
1387 | /* WaToEnableHwFixForPushConstHWBug:glk */ | |
1388 | WA_SET_BIT_MASKED(COMMON_SLICE_CHICKEN2, | |
1389 | GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION); | |
1390 | ||
1391 | return 0; | |
1392 | } | |
1393 | ||
46c26662 RV |
1394 | static int cfl_init_workarounds(struct intel_engine_cs *engine) |
1395 | { | |
1396 | struct drm_i915_private *dev_priv = engine->i915; | |
1397 | int ret; | |
1398 | ||
1399 | ret = gen9_init_workarounds(engine); | |
1400 | if (ret) | |
1401 | return ret; | |
1402 | ||
1403 | /* WaEnableGapsTsvCreditFix:cfl */ | |
1404 | I915_WRITE(GEN8_GARBCNTL, (I915_READ(GEN8_GARBCNTL) | | |
1405 | GEN9_GAPS_TSV_CREDIT_DISABLE)); | |
1406 | ||
1407 | /* WaToEnableHwFixForPushConstHWBug:cfl */ | |
1408 | WA_SET_BIT_MASKED(COMMON_SLICE_CHICKEN2, | |
1409 | GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION); | |
1410 | ||
1411 | /* WaDisableGafsUnitClkGating:cfl */ | |
4827c547 OM |
1412 | I915_WRITE(GEN7_UCGCTL4, (I915_READ(GEN7_UCGCTL4) | |
1413 | GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE)); | |
46c26662 RV |
1414 | |
1415 | /* WaDisableSbeCacheDispatchPortSharing:cfl */ | |
1416 | WA_SET_BIT_MASKED( | |
1417 | GEN7_HALF_SLICE_CHICKEN1, | |
1418 | GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE); | |
1419 | ||
1420 | /* WaInPlaceDecompressionHang:cfl */ | |
efc886cb OM |
1421 | I915_WRITE(GEN9_GAMT_ECO_REG_RW_IA, |
1422 | (I915_READ(GEN9_GAMT_ECO_REG_RW_IA) | | |
1423 | GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS)); | |
46c26662 RV |
1424 | |
1425 | return 0; | |
1426 | } | |
1427 | ||
133b4bd7 TU |
1428 | int init_workarounds_ring(struct intel_engine_cs *engine) |
1429 | { | |
1430 | struct drm_i915_private *dev_priv = engine->i915; | |
02e012f1 | 1431 | int err; |
133b4bd7 TU |
1432 | |
1433 | WARN_ON(engine->id != RCS); | |
1434 | ||
1435 | dev_priv->workarounds.count = 0; | |
02e012f1 | 1436 | dev_priv->workarounds.hw_whitelist_count[engine->id] = 0; |
133b4bd7 TU |
1437 | |
1438 | if (IS_BROADWELL(dev_priv)) | |
02e012f1 CW |
1439 | err = bdw_init_workarounds(engine); |
1440 | else if (IS_CHERRYVIEW(dev_priv)) | |
1441 | err = chv_init_workarounds(engine); | |
1442 | else if (IS_SKYLAKE(dev_priv)) | |
1443 | err = skl_init_workarounds(engine); | |
1444 | else if (IS_BROXTON(dev_priv)) | |
1445 | err = bxt_init_workarounds(engine); | |
1446 | else if (IS_KABYLAKE(dev_priv)) | |
1447 | err = kbl_init_workarounds(engine); | |
1448 | else if (IS_GEMINILAKE(dev_priv)) | |
1449 | err = glk_init_workarounds(engine); | |
46c26662 RV |
1450 | else if (IS_COFFEELAKE(dev_priv)) |
1451 | err = cfl_init_workarounds(engine); | |
90007bca RV |
1452 | else if (IS_CANNONLAKE(dev_priv)) |
1453 | err = cnl_init_workarounds(engine); | |
02e012f1 CW |
1454 | else |
1455 | err = 0; | |
1456 | if (err) | |
1457 | return err; | |
133b4bd7 | 1458 | |
02e012f1 CW |
1459 | DRM_DEBUG_DRIVER("%s: Number of context specific w/a: %d\n", |
1460 | engine->name, dev_priv->workarounds.count); | |
133b4bd7 TU |
1461 | return 0; |
1462 | } | |
1463 | ||
1464 | int intel_ring_workarounds_emit(struct drm_i915_gem_request *req) | |
1465 | { | |
1466 | struct i915_workarounds *w = &req->i915->workarounds; | |
1467 | u32 *cs; | |
1468 | int ret, i; | |
1469 | ||
1470 | if (w->count == 0) | |
1471 | return 0; | |
1472 | ||
1473 | ret = req->engine->emit_flush(req, EMIT_BARRIER); | |
1474 | if (ret) | |
1475 | return ret; | |
1476 | ||
1477 | cs = intel_ring_begin(req, (w->count * 2 + 2)); | |
1478 | if (IS_ERR(cs)) | |
1479 | return PTR_ERR(cs); | |
1480 | ||
1481 | *cs++ = MI_LOAD_REGISTER_IMM(w->count); | |
1482 | for (i = 0; i < w->count; i++) { | |
1483 | *cs++ = i915_mmio_reg_offset(w->reg[i].addr); | |
1484 | *cs++ = w->reg[i].value; | |
1485 | } | |
1486 | *cs++ = MI_NOOP; | |
1487 | ||
1488 | intel_ring_advance(req, cs); | |
1489 | ||
1490 | ret = req->engine->emit_flush(req, EMIT_BARRIER); | |
1491 | if (ret) | |
1492 | return ret; | |
1493 | ||
133b4bd7 TU |
1494 | return 0; |
1495 | } | |
1496 | ||
a091d4ee CW |
1497 | static bool ring_is_idle(struct intel_engine_cs *engine) |
1498 | { | |
1499 | struct drm_i915_private *dev_priv = engine->i915; | |
1500 | bool idle = true; | |
1501 | ||
1502 | intel_runtime_pm_get(dev_priv); | |
1503 | ||
aed2fc10 CW |
1504 | /* First check that no commands are left in the ring */ |
1505 | if ((I915_READ_HEAD(engine) & HEAD_ADDR) != | |
1506 | (I915_READ_TAIL(engine) & TAIL_ADDR)) | |
1507 | idle = false; | |
1508 | ||
a091d4ee CW |
1509 | /* No bit for gen2, so assume the CS parser is idle */ |
1510 | if (INTEL_GEN(dev_priv) > 2 && !(I915_READ_MODE(engine) & MODE_IDLE)) | |
1511 | idle = false; | |
1512 | ||
1513 | intel_runtime_pm_put(dev_priv); | |
1514 | ||
1515 | return idle; | |
1516 | } | |
1517 | ||
5400367a CW |
1518 | /** |
1519 | * intel_engine_is_idle() - Report if the engine has finished process all work | |
1520 | * @engine: the intel_engine_cs | |
1521 | * | |
1522 | * Return true if there are no requests pending, nothing left to be submitted | |
1523 | * to hardware, and that the engine is idle. | |
1524 | */ | |
1525 | bool intel_engine_is_idle(struct intel_engine_cs *engine) | |
1526 | { | |
1527 | struct drm_i915_private *dev_priv = engine->i915; | |
1528 | ||
a8e9a419 CW |
1529 | /* More white lies, if wedged, hw state is inconsistent */ |
1530 | if (i915_terminally_wedged(&dev_priv->gpu_error)) | |
1531 | return true; | |
1532 | ||
5400367a CW |
1533 | /* Any inflight/incomplete requests? */ |
1534 | if (!i915_seqno_passed(intel_engine_get_seqno(engine), | |
1535 | intel_engine_last_submit(engine))) | |
1536 | return false; | |
1537 | ||
8968a364 CW |
1538 | if (I915_SELFTEST_ONLY(engine->breadcrumbs.mock)) |
1539 | return true; | |
1540 | ||
5400367a CW |
1541 | /* Interrupt/tasklet pending? */ |
1542 | if (test_bit(ENGINE_IRQ_EXECLIST, &engine->irq_posted)) | |
1543 | return false; | |
1544 | ||
1545 | /* Both ports drained, no more ELSP submission? */ | |
b620e870 | 1546 | if (port_request(&engine->execlists.port[0])) |
5400367a CW |
1547 | return false; |
1548 | ||
d6edb6e3 | 1549 | /* ELSP is empty, but there are ready requests? */ |
b620e870 | 1550 | if (READ_ONCE(engine->execlists.first)) |
d6edb6e3 CW |
1551 | return false; |
1552 | ||
5400367a | 1553 | /* Ring stopped? */ |
a091d4ee | 1554 | if (!ring_is_idle(engine)) |
5400367a CW |
1555 | return false; |
1556 | ||
1557 | return true; | |
1558 | } | |
1559 | ||
05425249 CW |
1560 | bool intel_engines_are_idle(struct drm_i915_private *dev_priv) |
1561 | { | |
1562 | struct intel_engine_cs *engine; | |
1563 | enum intel_engine_id id; | |
1564 | ||
8490ae20 CW |
1565 | if (READ_ONCE(dev_priv->gt.active_requests)) |
1566 | return false; | |
1567 | ||
1568 | /* If the driver is wedged, HW state may be very inconsistent and | |
1569 | * report that it is still busy, even though we have stopped using it. | |
1570 | */ | |
1571 | if (i915_terminally_wedged(&dev_priv->gpu_error)) | |
1572 | return true; | |
1573 | ||
05425249 CW |
1574 | for_each_engine(engine, dev_priv, id) { |
1575 | if (!intel_engine_is_idle(engine)) | |
1576 | return false; | |
1577 | } | |
1578 | ||
1579 | return true; | |
1580 | } | |
1581 | ||
ff44ad51 CW |
1582 | void intel_engines_reset_default_submission(struct drm_i915_private *i915) |
1583 | { | |
1584 | struct intel_engine_cs *engine; | |
1585 | enum intel_engine_id id; | |
1586 | ||
1587 | for_each_engine(engine, i915, id) | |
1588 | engine->set_default_submission(engine); | |
1589 | } | |
1590 | ||
6c067579 CW |
1591 | void intel_engines_mark_idle(struct drm_i915_private *i915) |
1592 | { | |
1593 | struct intel_engine_cs *engine; | |
1594 | enum intel_engine_id id; | |
1595 | ||
1596 | for_each_engine(engine, i915, id) { | |
1597 | intel_engine_disarm_breadcrumbs(engine); | |
1598 | i915_gem_batch_pool_fini(&engine->batch_pool); | |
b620e870 MK |
1599 | tasklet_kill(&engine->execlists.irq_tasklet); |
1600 | engine->execlists.no_priolist = false; | |
6c067579 CW |
1601 | } |
1602 | } | |
1603 | ||
90cad095 CW |
1604 | bool intel_engine_can_store_dword(struct intel_engine_cs *engine) |
1605 | { | |
1606 | switch (INTEL_GEN(engine->i915)) { | |
1607 | case 2: | |
1608 | return false; /* uses physical not virtual addresses */ | |
1609 | case 3: | |
1610 | /* maybe only uses physical not virtual addresses */ | |
1611 | return !(IS_I915G(engine->i915) || IS_I915GM(engine->i915)); | |
1612 | case 6: | |
1613 | return engine->class != VIDEO_DECODE_CLASS; /* b0rked */ | |
1614 | default: | |
1615 | return true; | |
1616 | } | |
1617 | } | |
1618 | ||
f97fbf96 CW |
1619 | #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST) |
1620 | #include "selftests/mock_engine.c" | |
1621 | #endif |