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47339cd9 DV |
1 | /* |
2 | * Copyright © 2014 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Daniel Vetter <daniel.vetter@ffwll.ch> | |
25 | * | |
26 | */ | |
27 | ||
28 | #include "i915_drv.h" | |
29 | #include "intel_drv.h" | |
30 | ||
ef07388e DV |
31 | /** |
32 | * DOC: fifo underrun handling | |
33 | * | |
34 | * The i915 driver checks for display fifo underruns using the interrupt signals | |
35 | * provided by the hardware. This is enabled by default and fairly useful to | |
36 | * debug display issues, especially watermark settings. | |
37 | * | |
38 | * If an underrun is detected this is logged into dmesg. To avoid flooding logs | |
39 | * and occupying the cpu underrun interrupts are disabled after the first | |
40 | * occurrence until the next modeset on a given pipe. | |
41 | * | |
42 | * Note that underrun detection on gmch platforms is a bit more ugly since there | |
43 | * is no interrupt (despite that the signalling bit is in the PIPESTAT pipe | |
44 | * interrupt register). Also on some other platforms underrun interrupts are | |
45 | * shared, which means that if we detect an underrun we need to disable underrun | |
46 | * reporting on all pipes. | |
47 | * | |
48 | * The code also supports underrun detection on the PCH transcoder. | |
49 | */ | |
50 | ||
47339cd9 DV |
51 | static bool ivb_can_enable_err_int(struct drm_device *dev) |
52 | { | |
fac5e23e | 53 | struct drm_i915_private *dev_priv = to_i915(dev); |
47339cd9 DV |
54 | struct intel_crtc *crtc; |
55 | enum pipe pipe; | |
56 | ||
57 | assert_spin_locked(&dev_priv->irq_lock); | |
58 | ||
59 | for_each_pipe(dev_priv, pipe) { | |
98187836 | 60 | crtc = intel_get_crtc_for_pipe(dev_priv, pipe); |
47339cd9 DV |
61 | |
62 | if (crtc->cpu_fifo_underrun_disabled) | |
63 | return false; | |
64 | } | |
65 | ||
66 | return true; | |
67 | } | |
68 | ||
69 | static bool cpt_can_enable_serr_int(struct drm_device *dev) | |
70 | { | |
fac5e23e | 71 | struct drm_i915_private *dev_priv = to_i915(dev); |
47339cd9 DV |
72 | enum pipe pipe; |
73 | struct intel_crtc *crtc; | |
74 | ||
75 | assert_spin_locked(&dev_priv->irq_lock); | |
76 | ||
77 | for_each_pipe(dev_priv, pipe) { | |
98187836 | 78 | crtc = intel_get_crtc_for_pipe(dev_priv, pipe); |
47339cd9 DV |
79 | |
80 | if (crtc->pch_fifo_underrun_disabled) | |
81 | return false; | |
82 | } | |
83 | ||
84 | return true; | |
85 | } | |
86 | ||
aca7b684 | 87 | static void i9xx_check_fifo_underruns(struct intel_crtc *crtc) |
47339cd9 | 88 | { |
aca7b684 | 89 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
f0f59a00 | 90 | i915_reg_t reg = PIPESTAT(crtc->pipe); |
aca7b684 | 91 | u32 pipestat = I915_READ(reg) & 0xffff0000; |
47339cd9 | 92 | |
aca7b684 | 93 | assert_spin_locked(&dev_priv->irq_lock); |
47339cd9 | 94 | |
aca7b684 VS |
95 | if ((pipestat & PIPE_FIFO_UNDERRUN_STATUS) == 0) |
96 | return; | |
47339cd9 | 97 | |
aca7b684 VS |
98 | I915_WRITE(reg, pipestat | PIPE_FIFO_UNDERRUN_STATUS); |
99 | POSTING_READ(reg); | |
47339cd9 | 100 | |
aca7b684 | 101 | DRM_ERROR("pipe %c underrun\n", pipe_name(crtc->pipe)); |
47339cd9 DV |
102 | } |
103 | ||
104 | static void i9xx_set_fifo_underrun_reporting(struct drm_device *dev, | |
105 | enum pipe pipe, | |
106 | bool enable, bool old) | |
107 | { | |
fac5e23e | 108 | struct drm_i915_private *dev_priv = to_i915(dev); |
f0f59a00 | 109 | i915_reg_t reg = PIPESTAT(pipe); |
47339cd9 DV |
110 | u32 pipestat = I915_READ(reg) & 0xffff0000; |
111 | ||
112 | assert_spin_locked(&dev_priv->irq_lock); | |
113 | ||
114 | if (enable) { | |
115 | I915_WRITE(reg, pipestat | PIPE_FIFO_UNDERRUN_STATUS); | |
116 | POSTING_READ(reg); | |
117 | } else { | |
118 | if (old && pipestat & PIPE_FIFO_UNDERRUN_STATUS) | |
119 | DRM_ERROR("pipe %c underrun\n", pipe_name(pipe)); | |
120 | } | |
121 | } | |
122 | ||
123 | static void ironlake_set_fifo_underrun_reporting(struct drm_device *dev, | |
124 | enum pipe pipe, bool enable) | |
125 | { | |
fac5e23e | 126 | struct drm_i915_private *dev_priv = to_i915(dev); |
47339cd9 DV |
127 | uint32_t bit = (pipe == PIPE_A) ? DE_PIPEA_FIFO_UNDERRUN : |
128 | DE_PIPEB_FIFO_UNDERRUN; | |
129 | ||
130 | if (enable) | |
fbdedaea | 131 | ilk_enable_display_irq(dev_priv, bit); |
47339cd9 | 132 | else |
fbdedaea | 133 | ilk_disable_display_irq(dev_priv, bit); |
47339cd9 DV |
134 | } |
135 | ||
aca7b684 VS |
136 | static void ivybridge_check_fifo_underruns(struct intel_crtc *crtc) |
137 | { | |
138 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); | |
139 | enum pipe pipe = crtc->pipe; | |
140 | uint32_t err_int = I915_READ(GEN7_ERR_INT); | |
141 | ||
142 | assert_spin_locked(&dev_priv->irq_lock); | |
143 | ||
144 | if ((err_int & ERR_INT_FIFO_UNDERRUN(pipe)) == 0) | |
145 | return; | |
146 | ||
147 | I915_WRITE(GEN7_ERR_INT, ERR_INT_FIFO_UNDERRUN(pipe)); | |
148 | POSTING_READ(GEN7_ERR_INT); | |
149 | ||
150 | DRM_ERROR("fifo underrun on pipe %c\n", pipe_name(pipe)); | |
151 | } | |
152 | ||
47339cd9 DV |
153 | static void ivybridge_set_fifo_underrun_reporting(struct drm_device *dev, |
154 | enum pipe pipe, | |
155 | bool enable, bool old) | |
156 | { | |
fac5e23e | 157 | struct drm_i915_private *dev_priv = to_i915(dev); |
47339cd9 DV |
158 | if (enable) { |
159 | I915_WRITE(GEN7_ERR_INT, ERR_INT_FIFO_UNDERRUN(pipe)); | |
160 | ||
161 | if (!ivb_can_enable_err_int(dev)) | |
162 | return; | |
163 | ||
fbdedaea | 164 | ilk_enable_display_irq(dev_priv, DE_ERR_INT_IVB); |
47339cd9 | 165 | } else { |
fbdedaea | 166 | ilk_disable_display_irq(dev_priv, DE_ERR_INT_IVB); |
47339cd9 DV |
167 | |
168 | if (old && | |
169 | I915_READ(GEN7_ERR_INT) & ERR_INT_FIFO_UNDERRUN(pipe)) { | |
170 | DRM_ERROR("uncleared fifo underrun on pipe %c\n", | |
171 | pipe_name(pipe)); | |
172 | } | |
173 | } | |
174 | } | |
175 | ||
176 | static void broadwell_set_fifo_underrun_reporting(struct drm_device *dev, | |
177 | enum pipe pipe, bool enable) | |
178 | { | |
fac5e23e | 179 | struct drm_i915_private *dev_priv = to_i915(dev); |
47339cd9 | 180 | |
47339cd9 | 181 | if (enable) |
013d3752 | 182 | bdw_enable_pipe_irq(dev_priv, pipe, GEN8_PIPE_FIFO_UNDERRUN); |
47339cd9 | 183 | else |
013d3752 | 184 | bdw_disable_pipe_irq(dev_priv, pipe, GEN8_PIPE_FIFO_UNDERRUN); |
47339cd9 DV |
185 | } |
186 | ||
187 | static void ibx_set_fifo_underrun_reporting(struct drm_device *dev, | |
188 | enum transcoder pch_transcoder, | |
189 | bool enable) | |
190 | { | |
fac5e23e | 191 | struct drm_i915_private *dev_priv = to_i915(dev); |
47339cd9 DV |
192 | uint32_t bit = (pch_transcoder == TRANSCODER_A) ? |
193 | SDE_TRANSA_FIFO_UNDER : SDE_TRANSB_FIFO_UNDER; | |
194 | ||
195 | if (enable) | |
196 | ibx_enable_display_interrupt(dev_priv, bit); | |
197 | else | |
198 | ibx_disable_display_interrupt(dev_priv, bit); | |
199 | } | |
200 | ||
aca7b684 VS |
201 | static void cpt_check_pch_fifo_underruns(struct intel_crtc *crtc) |
202 | { | |
203 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); | |
204 | enum transcoder pch_transcoder = (enum transcoder) crtc->pipe; | |
205 | uint32_t serr_int = I915_READ(SERR_INT); | |
206 | ||
207 | assert_spin_locked(&dev_priv->irq_lock); | |
208 | ||
209 | if ((serr_int & SERR_INT_TRANS_FIFO_UNDERRUN(pch_transcoder)) == 0) | |
210 | return; | |
211 | ||
212 | I915_WRITE(SERR_INT, SERR_INT_TRANS_FIFO_UNDERRUN(pch_transcoder)); | |
213 | POSTING_READ(SERR_INT); | |
214 | ||
da205630 | 215 | DRM_ERROR("pch fifo underrun on pch transcoder %s\n", |
aca7b684 VS |
216 | transcoder_name(pch_transcoder)); |
217 | } | |
218 | ||
47339cd9 DV |
219 | static void cpt_set_fifo_underrun_reporting(struct drm_device *dev, |
220 | enum transcoder pch_transcoder, | |
221 | bool enable, bool old) | |
222 | { | |
fac5e23e | 223 | struct drm_i915_private *dev_priv = to_i915(dev); |
47339cd9 DV |
224 | |
225 | if (enable) { | |
226 | I915_WRITE(SERR_INT, | |
227 | SERR_INT_TRANS_FIFO_UNDERRUN(pch_transcoder)); | |
228 | ||
229 | if (!cpt_can_enable_serr_int(dev)) | |
230 | return; | |
231 | ||
232 | ibx_enable_display_interrupt(dev_priv, SDE_ERROR_CPT); | |
233 | } else { | |
234 | ibx_disable_display_interrupt(dev_priv, SDE_ERROR_CPT); | |
235 | ||
236 | if (old && I915_READ(SERR_INT) & | |
237 | SERR_INT_TRANS_FIFO_UNDERRUN(pch_transcoder)) { | |
da205630 | 238 | DRM_ERROR("uncleared pch fifo underrun on pch transcoder %s\n", |
47339cd9 DV |
239 | transcoder_name(pch_transcoder)); |
240 | } | |
241 | } | |
242 | } | |
243 | ||
47339cd9 DV |
244 | static bool __intel_set_cpu_fifo_underrun_reporting(struct drm_device *dev, |
245 | enum pipe pipe, bool enable) | |
246 | { | |
fac5e23e | 247 | struct drm_i915_private *dev_priv = to_i915(dev); |
98187836 | 248 | struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe); |
47339cd9 DV |
249 | bool old; |
250 | ||
251 | assert_spin_locked(&dev_priv->irq_lock); | |
252 | ||
e2af48c6 VS |
253 | old = !crtc->cpu_fifo_underrun_disabled; |
254 | crtc->cpu_fifo_underrun_disabled = !enable; | |
47339cd9 | 255 | |
49cff963 | 256 | if (HAS_GMCH_DISPLAY(dev_priv)) |
47339cd9 | 257 | i9xx_set_fifo_underrun_reporting(dev, pipe, enable, old); |
5db94019 | 258 | else if (IS_GEN5(dev_priv) || IS_GEN6(dev_priv)) |
47339cd9 | 259 | ironlake_set_fifo_underrun_reporting(dev, pipe, enable); |
5db94019 | 260 | else if (IS_GEN7(dev_priv)) |
47339cd9 | 261 | ivybridge_set_fifo_underrun_reporting(dev, pipe, enable, old); |
5db94019 | 262 | else if (IS_GEN8(dev_priv) || IS_GEN9(dev_priv)) |
47339cd9 DV |
263 | broadwell_set_fifo_underrun_reporting(dev, pipe, enable); |
264 | ||
265 | return old; | |
266 | } | |
267 | ||
ef07388e DV |
268 | /** |
269 | * intel_set_cpu_fifo_underrun_reporting - set cpu fifo underrrun reporting state | |
270 | * @dev_priv: i915 device instance | |
271 | * @pipe: (CPU) pipe to set state for | |
272 | * @enable: whether underruns should be reported or not | |
273 | * | |
274 | * This function sets the fifo underrun state for @pipe. It is used in the | |
275 | * modeset code to avoid false positives since on many platforms underruns are | |
276 | * expected when disabling or enabling the pipe. | |
277 | * | |
278 | * Notice that on some platforms disabling underrun reports for one pipe | |
279 | * disables for all due to shared interrupts. Actual reporting is still per-pipe | |
280 | * though. | |
281 | * | |
282 | * Returns the previous state of underrun reporting. | |
283 | */ | |
a72e4c9f | 284 | bool intel_set_cpu_fifo_underrun_reporting(struct drm_i915_private *dev_priv, |
47339cd9 DV |
285 | enum pipe pipe, bool enable) |
286 | { | |
47339cd9 DV |
287 | unsigned long flags; |
288 | bool ret; | |
289 | ||
290 | spin_lock_irqsave(&dev_priv->irq_lock, flags); | |
91c8a326 | 291 | ret = __intel_set_cpu_fifo_underrun_reporting(&dev_priv->drm, pipe, |
a72e4c9f | 292 | enable); |
47339cd9 DV |
293 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
294 | ||
295 | return ret; | |
296 | } | |
297 | ||
47339cd9 | 298 | /** |
ef07388e DV |
299 | * intel_set_pch_fifo_underrun_reporting - set PCH fifo underrun reporting state |
300 | * @dev_priv: i915 device instance | |
47339cd9 | 301 | * @pch_transcoder: the PCH transcoder (same as pipe on IVB and older) |
ef07388e | 302 | * @enable: whether underruns should be reported or not |
47339cd9 DV |
303 | * |
304 | * This function makes us disable or enable PCH fifo underruns for a specific | |
305 | * PCH transcoder. Notice that on some PCHs (e.g. CPT/PPT), disabling FIFO | |
306 | * underrun reporting for one transcoder may also disable all the other PCH | |
307 | * error interruts for the other transcoders, due to the fact that there's just | |
308 | * one interrupt mask/enable bit for all the transcoders. | |
309 | * | |
310 | * Returns the previous state of underrun reporting. | |
311 | */ | |
a72e4c9f | 312 | bool intel_set_pch_fifo_underrun_reporting(struct drm_i915_private *dev_priv, |
47339cd9 DV |
313 | enum transcoder pch_transcoder, |
314 | bool enable) | |
315 | { | |
98187836 VS |
316 | struct intel_crtc *crtc = |
317 | intel_get_crtc_for_pipe(dev_priv, (enum pipe) pch_transcoder); | |
47339cd9 DV |
318 | unsigned long flags; |
319 | bool old; | |
320 | ||
321 | /* | |
322 | * NOTE: Pre-LPT has a fixed cpu pipe -> pch transcoder mapping, but LPT | |
323 | * has only one pch transcoder A that all pipes can use. To avoid racy | |
324 | * pch transcoder -> pipe lookups from interrupt code simply store the | |
325 | * underrun statistics in crtc A. Since we never expose this anywhere | |
326 | * nor use it outside of the fifo underrun code here using the "wrong" | |
327 | * crtc on LPT won't cause issues. | |
328 | */ | |
329 | ||
330 | spin_lock_irqsave(&dev_priv->irq_lock, flags); | |
331 | ||
e2af48c6 VS |
332 | old = !crtc->pch_fifo_underrun_disabled; |
333 | crtc->pch_fifo_underrun_disabled = !enable; | |
47339cd9 | 334 | |
2d1fe073 | 335 | if (HAS_PCH_IBX(dev_priv)) |
91c8a326 CW |
336 | ibx_set_fifo_underrun_reporting(&dev_priv->drm, |
337 | pch_transcoder, | |
a72e4c9f | 338 | enable); |
47339cd9 | 339 | else |
91c8a326 CW |
340 | cpt_set_fifo_underrun_reporting(&dev_priv->drm, |
341 | pch_transcoder, | |
a72e4c9f | 342 | enable, old); |
47339cd9 DV |
343 | |
344 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); | |
345 | return old; | |
346 | } | |
1f7247c0 | 347 | |
ef07388e | 348 | /** |
cea3bf81 | 349 | * intel_cpu_fifo_underrun_irq_handler - handle CPU fifo underrun interrupt |
ef07388e DV |
350 | * @dev_priv: i915 device instance |
351 | * @pipe: (CPU) pipe to set state for | |
352 | * | |
353 | * This handles a CPU fifo underrun interrupt, generating an underrun warning | |
354 | * into dmesg if underrun reporting is enabled and then disables the underrun | |
355 | * interrupt to avoid an irq storm. | |
356 | */ | |
1f7247c0 DV |
357 | void intel_cpu_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv, |
358 | enum pipe pipe) | |
359 | { | |
98187836 | 360 | struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe); |
54fc7c1c CW |
361 | |
362 | /* We may be called too early in init, thanks BIOS! */ | |
363 | if (crtc == NULL) | |
364 | return; | |
365 | ||
0f239f4c | 366 | /* GMCH can't disable fifo underruns, filter them. */ |
2d1fe073 | 367 | if (HAS_GMCH_DISPLAY(dev_priv) && |
e2af48c6 | 368 | crtc->cpu_fifo_underrun_disabled) |
0f239f4c DV |
369 | return; |
370 | ||
1f7247c0 DV |
371 | if (intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false)) |
372 | DRM_ERROR("CPU pipe %c FIFO underrun\n", | |
373 | pipe_name(pipe)); | |
61a585d6 PZ |
374 | |
375 | intel_fbc_handle_fifo_underrun_irq(dev_priv); | |
1f7247c0 DV |
376 | } |
377 | ||
ef07388e DV |
378 | /** |
379 | * intel_pch_fifo_underrun_irq_handler - handle PCH fifo underrun interrupt | |
380 | * @dev_priv: i915 device instance | |
381 | * @pch_transcoder: the PCH transcoder (same as pipe on IVB and older) | |
382 | * | |
383 | * This handles a PCH fifo underrun interrupt, generating an underrun warning | |
384 | * into dmesg if underrun reporting is enabled and then disables the underrun | |
385 | * interrupt to avoid an irq storm. | |
386 | */ | |
1f7247c0 DV |
387 | void intel_pch_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv, |
388 | enum transcoder pch_transcoder) | |
389 | { | |
390 | if (intel_set_pch_fifo_underrun_reporting(dev_priv, pch_transcoder, | |
391 | false)) | |
da205630 | 392 | DRM_ERROR("PCH transcoder %s FIFO underrun\n", |
1f7247c0 DV |
393 | transcoder_name(pch_transcoder)); |
394 | } | |
aca7b684 VS |
395 | |
396 | /** | |
397 | * intel_check_cpu_fifo_underruns - check for CPU fifo underruns immediately | |
398 | * @dev_priv: i915 device instance | |
399 | * | |
400 | * Check for CPU fifo underruns immediately. Useful on IVB/HSW where the shared | |
401 | * error interrupt may have been disabled, and so CPU fifo underruns won't | |
402 | * necessarily raise an interrupt, and on GMCH platforms where underruns never | |
403 | * raise an interrupt. | |
404 | */ | |
405 | void intel_check_cpu_fifo_underruns(struct drm_i915_private *dev_priv) | |
406 | { | |
407 | struct intel_crtc *crtc; | |
408 | ||
409 | spin_lock_irq(&dev_priv->irq_lock); | |
410 | ||
91c8a326 | 411 | for_each_intel_crtc(&dev_priv->drm, crtc) { |
aca7b684 VS |
412 | if (crtc->cpu_fifo_underrun_disabled) |
413 | continue; | |
414 | ||
415 | if (HAS_GMCH_DISPLAY(dev_priv)) | |
416 | i9xx_check_fifo_underruns(crtc); | |
417 | else if (IS_GEN7(dev_priv)) | |
418 | ivybridge_check_fifo_underruns(crtc); | |
419 | } | |
420 | ||
421 | spin_unlock_irq(&dev_priv->irq_lock); | |
422 | } | |
423 | ||
424 | /** | |
425 | * intel_check_pch_fifo_underruns - check for PCH fifo underruns immediately | |
426 | * @dev_priv: i915 device instance | |
427 | * | |
428 | * Check for PCH fifo underruns immediately. Useful on CPT/PPT where the shared | |
429 | * error interrupt may have been disabled, and so PCH fifo underruns won't | |
430 | * necessarily raise an interrupt. | |
431 | */ | |
432 | void intel_check_pch_fifo_underruns(struct drm_i915_private *dev_priv) | |
433 | { | |
434 | struct intel_crtc *crtc; | |
435 | ||
436 | spin_lock_irq(&dev_priv->irq_lock); | |
437 | ||
91c8a326 | 438 | for_each_intel_crtc(&dev_priv->drm, crtc) { |
aca7b684 VS |
439 | if (crtc->pch_fifo_underrun_disabled) |
440 | continue; | |
441 | ||
442 | if (HAS_PCH_CPT(dev_priv)) | |
443 | cpt_check_pch_fifo_underruns(crtc); | |
444 | } | |
445 | ||
446 | spin_unlock_irq(&dev_priv->irq_lock); | |
447 | } |