[mirror_ubuntu-hirsute-kernel.git] / drivers / gpu / drm / i915 / intel_guc.h

/*
 * Copyright © 2014-2017 Intel Corporation
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
 * IN THE SOFTWARE.
 *
 */

#ifndef _INTEL_GUC_H_
#define _INTEL_GUC_H_

#include "intel_uncore.h"
#include "intel_guc_fw.h"
#include "intel_guc_fwif.h"
#include "intel_guc_ct.h"
#include "intel_guc_log.h"
#include "intel_guc_reg.h"
#include "intel_uc_fw.h"
#include "i915_vma.h"

struct guc_preempt_work {
	struct work_struct work;
	struct intel_engine_cs *engine;
};

/*
 * Top level structure of GuC. It handles firmware loading and manages client
 * pool and doorbells. intel_guc owns a intel_guc_client to replace the legacy
 * ExecList submission.
 */
struct intel_guc {
	struct intel_uc_fw fw;
	struct intel_guc_log log;
	struct intel_guc_ct ct;

	/* Log snapshot if GuC errors during load */
	struct drm_i915_gem_object *load_err_log;

	/* intel_guc_recv interrupt related state */
	bool interrupts_enabled;

	struct i915_vma *ads_vma;
	struct i915_vma *stage_desc_pool;
	void *stage_desc_pool_vaddr;
	struct ida stage_ids;
	struct i915_vma *shared_data;
	void *shared_data_vaddr;

	struct intel_guc_client *execbuf_client;
	struct intel_guc_client *preempt_client;

	struct guc_preempt_work preempt_work[I915_NUM_ENGINES];
	struct workqueue_struct *preempt_wq;

	DECLARE_BITMAP(doorbell_bitmap, GUC_NUM_DOORBELLS);
	/* Cyclic counter mod pagesize	*/
	u32 db_cacheline;

	/* GuC's FW specific registers used in MMIO send */
	struct {
		u32 base;
		unsigned int count;
		enum forcewake_domains fw_domains;
	} send_regs;

	/* To serialize the intel_guc_send actions */
	struct mutex send_mutex;

	/* GuC's FW specific send function */
	int (*send)(struct intel_guc *guc, const u32 *data, u32 len);

	/* GuC's FW specific notify function */
	void (*notify)(struct intel_guc *guc);
};

static
inline int intel_guc_send(struct intel_guc *guc, const u32 *action, u32 len)
{
	return guc->send(guc, action, len);
}

static inline void intel_guc_notify(struct intel_guc *guc)
{
	guc->notify(guc);
}

/*
 * GuC does not allow any gfx GGTT address that falls into range [0, WOPCM_TOP),
 * which is reserved for Boot ROM, SRAM and WOPCM. Currently this top address is
 * 512K. In order to exclude 0-512K address space from GGTT, all gfx objects
 * used by GuC is pinned with PIN_OFFSET_BIAS along with size of WOPCM.
 */
static inline u32 guc_ggtt_offset(struct i915_vma *vma)
{
	u32 offset = i915_ggtt_offset(vma);

	GEM_BUG_ON(offset < GUC_WOPCM_TOP);
	GEM_BUG_ON(range_overflows_t(u64, offset, vma->size, GUC_GGTT_TOP));

	return offset;
}

void intel_guc_init_early(struct intel_guc *guc);
void intel_guc_init_send_regs(struct intel_guc *guc);
void intel_guc_init_params(struct intel_guc *guc);
int intel_guc_init_wq(struct intel_guc *guc);
void intel_guc_fini_wq(struct intel_guc *guc);
int intel_guc_init(struct intel_guc *guc);
void intel_guc_fini(struct intel_guc *guc);
int intel_guc_send_nop(struct intel_guc *guc, const u32 *action, u32 len);
int intel_guc_send_mmio(struct intel_guc *guc, const u32 *action, u32 len);
int intel_guc_sample_forcewake(struct intel_guc *guc);
int intel_guc_auth_huc(struct intel_guc *guc, u32 rsa_offset);
int intel_guc_suspend(struct drm_i915_private *dev_priv);
int intel_guc_resume(struct drm_i915_private *dev_priv);
struct i915_vma *intel_guc_allocate_vma(struct intel_guc *guc, u32 size);
u32 intel_guc_wopcm_size(struct drm_i915_private *dev_priv);

#endif
Commit	Line	Data
9bf384c5 MW	1	/*
	2	* Copyright © 2014-2017 Intel Corporation
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice (including the next
	12	* paragraph) shall be included in all copies or substantial portions of the
	13	* Software.
	14	*
	15	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	16	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	17	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	18	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	19	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
	20	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
	21	* IN THE SOFTWARE.
	22	*
	23	*/
	24
	25	#ifndef _INTEL_GUC_H_
	26	#define _INTEL_GUC_H_
	27
	28	#include "intel_uncore.h"
e8668bbc	29	#include "intel_guc_fw.h"
9bf384c5 MW	30	#include "intel_guc_fwif.h"
	31	#include "intel_guc_ct.h"
	32	#include "intel_guc_log.h"
3e8f5b08	33	#include "intel_guc_reg.h"
9bf384c5	34	#include "intel_uc_fw.h"
9bf384c5 MW	35	#include "i915_vma.h"
9bf384c5 MW	36
c41937fd MW	37	struct guc_preempt_work {
	38	struct work_struct work;
	39	struct intel_engine_cs *engine;
	40	};
	41
d9e2e014 MW	42	/*
d9e2e014 MW	43	* Top level structure of GuC. It handles firmware loading and manages client
5afc8b49	44	* pool and doorbells. intel_guc owns a intel_guc_client to replace the legacy
d9e2e014 MW	45	* ExecList submission.
d9e2e014 MW	46	*/
9bf384c5 MW	47	struct intel_guc {
	48	struct intel_uc_fw fw;
	49	struct intel_guc_log log;
	50	struct intel_guc_ct ct;
	51
	52	/* Log snapshot if GuC errors during load */
	53	struct drm_i915_gem_object *load_err_log;
	54
	55	/* intel_guc_recv interrupt related state */
	56	bool interrupts_enabled;
	57
	58	struct i915_vma *ads_vma;
	59	struct i915_vma *stage_desc_pool;
	60	void *stage_desc_pool_vaddr;
	61	struct ida stage_ids;
b8e5eb96 MW	62	struct i915_vma *shared_data;
b8e5eb96 MW	63	void *shared_data_vaddr;
9bf384c5	64
5afc8b49 SAK	65	struct intel_guc_client *execbuf_client;
5afc8b49 SAK	66	struct intel_guc_client *preempt_client;
9bf384c5	67
c41937fd MW	68	struct guc_preempt_work preempt_work[I915_NUM_ENGINES];
	69	struct workqueue_struct *preempt_wq;
	70
9bf384c5	71	DECLARE_BITMAP(doorbell_bitmap, GUC_NUM_DOORBELLS);
faf65486 JL	72	/* Cyclic counter mod pagesize */
faf65486 JL	73	u32 db_cacheline;
9bf384c5 MW	74
	75	/* GuC's FW specific registers used in MMIO send */
	76	struct {
	77	u32 base;
	78	unsigned int count;
	79	enum forcewake_domains fw_domains;
	80	} send_regs;
	81
	82	/* To serialize the intel_guc_send actions */
	83	struct mutex send_mutex;
	84
	85	/* GuC's FW specific send function */
	86	int (send)(struct intel_guc guc, const u32 *data, u32 len);
	87
	88	/* GuC's FW specific notify function */
	89	void (notify)(struct intel_guc guc);
	90	};
	91
	92	static
	93	inline int intel_guc_send(struct intel_guc guc, const u32 action, u32 len)
	94	{
	95	return guc->send(guc, action, len);
	96	}
	97
	98	static inline void intel_guc_notify(struct intel_guc *guc)
	99	{
	100	guc->notify(guc);
	101	}
	102
d9e2e014 MW	103	/*
	104	* GuC does not allow any gfx GGTT address that falls into range [0, WOPCM_TOP),
	105	* which is reserved for Boot ROM, SRAM and WOPCM. Currently this top address is
	106	* 512K. In order to exclude 0-512K address space from GGTT, all gfx objects
	107	* used by GuC is pinned with PIN_OFFSET_BIAS along with size of WOPCM.
	108	*/
9bf384c5 MW	109	static inline u32 guc_ggtt_offset(struct i915_vma *vma)
	110	{
	111	u32 offset = i915_ggtt_offset(vma);
	112
	113	GEM_BUG_ON(offset < GUC_WOPCM_TOP);
	114	GEM_BUG_ON(range_overflows_t(u64, offset, vma->size, GUC_GGTT_TOP));
	115
	116	return offset;
	117	}
	118
	119	void intel_guc_init_early(struct intel_guc *guc);
	120	void intel_guc_init_send_regs(struct intel_guc *guc);
5d53be45	121	void intel_guc_init_params(struct intel_guc *guc);
3176ff49 MW	122	int intel_guc_init_wq(struct intel_guc *guc);
3176ff49 MW	123	void intel_guc_fini_wq(struct intel_guc *guc);
1bbbca0d MW	124	int intel_guc_init(struct intel_guc *guc);
1bbbca0d MW	125	void intel_guc_fini(struct intel_guc *guc);
9bf384c5 MW	126	int intel_guc_send_nop(struct intel_guc guc, const u32 action, u32 len);
	127	int intel_guc_send_mmio(struct intel_guc guc, const u32 action, u32 len);
	128	int intel_guc_sample_forcewake(struct intel_guc *guc);
	129	int intel_guc_auth_huc(struct intel_guc *guc, u32 rsa_offset);
	130	int intel_guc_suspend(struct drm_i915_private *dev_priv);
	131	int intel_guc_resume(struct drm_i915_private *dev_priv);
	132	struct i915_vma intel_guc_allocate_vma(struct intel_guc guc, u32 size);
9bf384c5 MW	133	u32 intel_guc_wopcm_size(struct drm_i915_private *dev_priv);
	134
	135	#endif