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33a732f4 AD |
1 | /* |
2 | * Copyright © 2014 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | */ | |
24 | #ifndef _INTEL_GUC_H_ | |
25 | #define _INTEL_GUC_H_ | |
26 | ||
27 | #include "intel_guc_fwif.h" | |
28 | #include "i915_guc_reg.h" | |
0b63bb14 | 29 | #include "intel_ringbuffer.h" |
33a732f4 | 30 | |
e73bdd20 CW |
31 | struct drm_i915_gem_request; |
32 | ||
86e06cc0 DG |
33 | /* |
34 | * This structure primarily describes the GEM object shared with the GuC. | |
35 | * The GEM object is held for the entire lifetime of our interaction with | |
36 | * the GuC, being allocated before the GuC is loaded with its firmware. | |
37 | * Because there's no way to update the address used by the GuC after | |
38 | * initialisation, the shared object must stay pinned into the GGTT as | |
39 | * long as the GuC is in use. We also keep the first page (only) mapped | |
40 | * into kernel address space, as it includes shared data that must be | |
41 | * updated on every request submission. | |
42 | * | |
43 | * The single GEM object described here is actually made up of several | |
44 | * separate areas, as far as the GuC is concerned. The first page (kept | |
45 | * kmap'd) includes the "process decriptor" which holds sequence data for | |
46 | * the doorbell, and one cacheline which actually *is* the doorbell; a | |
47 | * write to this will "ring the doorbell" (i.e. send an interrupt to the | |
48 | * GuC). The subsequent pages of the client object constitute the work | |
49 | * queue (a circular array of work items), again described in the process | |
50 | * descriptor. Work queue pages are mapped momentarily as required. | |
51 | * | |
551aaecd DG |
52 | * We also keep a few statistics on failures. Ideally, these should all |
53 | * be zero! | |
54 | * no_wq_space: times that the submission pre-check found no space was | |
55 | * available in the work queue (note, the queue is shared, | |
56 | * not per-engine). It is OK for this to be nonzero, but | |
57 | * it should not be huge! | |
58 | * q_fail: failed to enqueue a work item. This should never happen, | |
59 | * because we check for space beforehand. | |
60 | * b_fail: failed to ring the doorbell. This should never happen, unless | |
61 | * somehow the hardware misbehaves, or maybe if the GuC firmware | |
62 | * crashes? We probably need to reset the GPU to recover. | |
63 | * retcode: errno from last guc_submit() | |
86e06cc0 | 64 | */ |
44a28b1d | 65 | struct i915_guc_client { |
8b797af1 | 66 | struct i915_vma *vma; |
0d92a6a4 | 67 | void *client_base; /* first page (only) of above */ |
e2efd130 | 68 | struct i915_gem_context *owner; |
44a28b1d | 69 | struct intel_guc *guc; |
e02757d9 DG |
70 | |
71 | uint32_t engines; /* bitmap of (host) engine ids */ | |
44a28b1d DG |
72 | uint32_t priority; |
73 | uint32_t ctx_index; | |
44a28b1d | 74 | uint32_t proc_desc_offset; |
774439e1 | 75 | |
44a28b1d DG |
76 | uint32_t doorbell_offset; |
77 | uint32_t cookie; | |
78 | uint16_t doorbell_id; | |
774439e1 | 79 | uint16_t padding[3]; /* Maintain alignment */ |
44a28b1d | 80 | |
dadd481b | 81 | spinlock_t wq_lock; |
44a28b1d DG |
82 | uint32_t wq_offset; |
83 | uint32_t wq_size; | |
44a28b1d | 84 | uint32_t wq_tail; |
dadd481b | 85 | uint32_t wq_rsvd; |
551aaecd | 86 | uint32_t no_wq_space; |
44a28b1d DG |
87 | uint32_t b_fail; |
88 | int retcode; | |
551aaecd DG |
89 | |
90 | /* Per-engine counts of GuC submissions */ | |
0b63bb14 | 91 | uint64_t submissions[I915_NUM_ENGINES]; |
44a28b1d DG |
92 | }; |
93 | ||
33a732f4 AD |
94 | enum intel_guc_fw_status { |
95 | GUC_FIRMWARE_FAIL = -1, | |
96 | GUC_FIRMWARE_NONE = 0, | |
97 | GUC_FIRMWARE_PENDING, | |
98 | GUC_FIRMWARE_SUCCESS | |
99 | }; | |
100 | ||
101 | /* | |
102 | * This structure encapsulates all the data needed during the process | |
103 | * of fetching, caching, and loading the firmware image into the GuC. | |
104 | */ | |
105 | struct intel_guc_fw { | |
106 | struct drm_device * guc_dev; | |
107 | const char * guc_fw_path; | |
108 | size_t guc_fw_size; | |
109 | struct drm_i915_gem_object * guc_fw_obj; | |
110 | enum intel_guc_fw_status guc_fw_fetch_status; | |
111 | enum intel_guc_fw_status guc_fw_load_status; | |
112 | ||
113 | uint16_t guc_fw_major_wanted; | |
114 | uint16_t guc_fw_minor_wanted; | |
115 | uint16_t guc_fw_major_found; | |
116 | uint16_t guc_fw_minor_found; | |
feda33ef AD |
117 | |
118 | uint32_t header_size; | |
119 | uint32_t header_offset; | |
120 | uint32_t rsa_size; | |
121 | uint32_t rsa_offset; | |
122 | uint32_t ucode_size; | |
123 | uint32_t ucode_offset; | |
33a732f4 AD |
124 | }; |
125 | ||
126 | struct intel_guc { | |
127 | struct intel_guc_fw guc_fw; | |
33a732f4 | 128 | uint32_t log_flags; |
8b797af1 | 129 | struct i915_vma *log_vma; |
bac427f8 | 130 | |
8b797af1 CW |
131 | struct i915_vma *ads_vma; |
132 | struct i915_vma *ctx_pool_vma; | |
bac427f8 | 133 | struct ida ctx_ids; |
44a28b1d DG |
134 | |
135 | struct i915_guc_client *execbuf_client; | |
136 | ||
44a28b1d DG |
137 | DECLARE_BITMAP(doorbell_bitmap, GUC_MAX_DOORBELLS); |
138 | uint32_t db_cacheline; /* Cyclic counter mod pagesize */ | |
139 | ||
140 | /* Action status & statistics */ | |
141 | uint64_t action_count; /* Total commands issued */ | |
142 | uint32_t action_cmd; /* Last command word */ | |
143 | uint32_t action_status; /* Last return status */ | |
144 | uint32_t action_fail; /* Total number of failures */ | |
145 | int32_t action_err; /* Last error code */ | |
146 | ||
0b63bb14 DG |
147 | uint64_t submissions[I915_NUM_ENGINES]; |
148 | uint32_t last_seqno[I915_NUM_ENGINES]; | |
33a732f4 AD |
149 | }; |
150 | ||
151 | /* intel_guc_loader.c */ | |
f09d675f DG |
152 | extern void intel_guc_init(struct drm_device *dev); |
153 | extern int intel_guc_setup(struct drm_device *dev); | |
154 | extern void intel_guc_fini(struct drm_device *dev); | |
33a732f4 | 155 | extern const char *intel_guc_fw_status_repr(enum intel_guc_fw_status status); |
a1c41994 AD |
156 | extern int intel_guc_suspend(struct drm_device *dev); |
157 | extern int intel_guc_resume(struct drm_device *dev); | |
33a732f4 | 158 | |
bac427f8 | 159 | /* i915_guc_submission.c */ |
beffa517 DG |
160 | int i915_guc_submission_init(struct drm_i915_private *dev_priv); |
161 | int i915_guc_submission_enable(struct drm_i915_private *dev_priv); | |
7a9347f9 | 162 | int i915_guc_wq_reserve(struct drm_i915_gem_request *rq); |
beffa517 DG |
163 | void i915_guc_submission_disable(struct drm_i915_private *dev_priv); |
164 | void i915_guc_submission_fini(struct drm_i915_private *dev_priv); | |
bac427f8 | 165 | |
33a732f4 | 166 | #endif |