[mirror_ubuntu-hirsute-kernel.git] / drivers / gpu / drm / i915 / intel_guc_fw.c

/*
 * Copyright © 2014 Intel Corporation
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
 * IN THE SOFTWARE.
 *
 * Authors:
 *    Vinit Azad <vinit.azad@intel.com>
 *    Ben Widawsky <ben@bwidawsk.net>
 *    Dave Gordon <david.s.gordon@intel.com>
 *    Alex Dai <yu.dai@intel.com>
 */

#include "intel_guc_fw.h"
#include "i915_drv.h"

#define SKL_FW_MAJOR 9
#define SKL_FW_MINOR 33

#define BXT_FW_MAJOR 9
#define BXT_FW_MINOR 29

#define KBL_FW_MAJOR 9
#define KBL_FW_MINOR 39

#define GUC_FW_PATH(platform, major, minor) \
       "i915/" __stringify(platform) "_guc_ver" __stringify(major) "_" __stringify(minor) ".bin"

#define I915_SKL_GUC_UCODE GUC_FW_PATH(skl, SKL_FW_MAJOR, SKL_FW_MINOR)
MODULE_FIRMWARE(I915_SKL_GUC_UCODE);

#define I915_BXT_GUC_UCODE GUC_FW_PATH(bxt, BXT_FW_MAJOR, BXT_FW_MINOR)
MODULE_FIRMWARE(I915_BXT_GUC_UCODE);

#define I915_KBL_GUC_UCODE GUC_FW_PATH(kbl, KBL_FW_MAJOR, KBL_FW_MINOR)
MODULE_FIRMWARE(I915_KBL_GUC_UCODE);

static void guc_fw_select(struct intel_uc_fw *guc_fw)
{
	struct intel_guc *guc = container_of(guc_fw, struct intel_guc, fw);
	struct drm_i915_private *dev_priv = guc_to_i915(guc);

	GEM_BUG_ON(guc_fw->type != INTEL_UC_FW_TYPE_GUC);

	if (!HAS_GUC(dev_priv))
		return;

	if (i915_modparams.guc_firmware_path) {
		guc_fw->path = i915_modparams.guc_firmware_path;
		guc_fw->major_ver_wanted = 0;
		guc_fw->minor_ver_wanted = 0;
	} else if (IS_SKYLAKE(dev_priv)) {
		guc_fw->path = I915_SKL_GUC_UCODE;
		guc_fw->major_ver_wanted = SKL_FW_MAJOR;
		guc_fw->minor_ver_wanted = SKL_FW_MINOR;
	} else if (IS_BROXTON(dev_priv)) {
		guc_fw->path = I915_BXT_GUC_UCODE;
		guc_fw->major_ver_wanted = BXT_FW_MAJOR;
		guc_fw->minor_ver_wanted = BXT_FW_MINOR;
	} else if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv)) {
		guc_fw->path = I915_KBL_GUC_UCODE;
		guc_fw->major_ver_wanted = KBL_FW_MAJOR;
		guc_fw->minor_ver_wanted = KBL_FW_MINOR;
	} else {
		DRM_WARN("%s: No firmware known for this platform!\n",
			 intel_uc_fw_type_repr(guc_fw->type));
	}
}

/**
 * intel_guc_fw_init_early() - initializes GuC firmware struct
 * @guc: intel_guc struct
 *
 * On platforms with GuC selects firmware for uploading
 */
void intel_guc_fw_init_early(struct intel_guc *guc)
{
	struct intel_uc_fw *guc_fw = &guc->fw;

	intel_uc_fw_init(guc_fw, INTEL_UC_FW_TYPE_GUC);
	guc_fw_select(guc_fw);
}

static void guc_prepare_xfer(struct intel_guc *guc)
{
	struct drm_i915_private *dev_priv = guc_to_i915(guc);

	/* Must program this register before loading the ucode with DMA */
	I915_WRITE(GUC_SHIM_CONTROL, GUC_DISABLE_SRAM_INIT_TO_ZEROES |
				     GUC_ENABLE_READ_CACHE_LOGIC |
				     GUC_ENABLE_MIA_CACHING |
				     GUC_ENABLE_READ_CACHE_FOR_SRAM_DATA |
				     GUC_ENABLE_READ_CACHE_FOR_WOPCM_DATA |
				     GUC_ENABLE_MIA_CLOCK_GATING);

	if (IS_GEN9_LP(dev_priv))
		I915_WRITE(GEN9LP_GT_PM_CONFIG, GT_DOORBELL_ENABLE);
	else
		I915_WRITE(GEN9_GT_PM_CONFIG, GT_DOORBELL_ENABLE);

	if (IS_GEN9(dev_priv)) {
		/* DOP Clock Gating Enable for GuC clocks */
		I915_WRITE(GEN7_MISCCPCTL, (GEN8_DOP_CLOCK_GATE_GUC_ENABLE |
					    I915_READ(GEN7_MISCCPCTL)));

		/* allows for 5us (in 10ns units) before GT can go to RC6 */
		I915_WRITE(GUC_ARAT_C6DIS, 0x1FF);
	}
}

/* Copy RSA signature from the fw image to HW for verification */
static int guc_xfer_rsa(struct intel_guc *guc, struct i915_vma *vma)
{
	struct drm_i915_private *dev_priv = guc_to_i915(guc);
	struct intel_uc_fw *guc_fw = &guc->fw;
	struct sg_table *sg = vma->pages;
	u32 rsa[UOS_RSA_SCRATCH_COUNT];
	int i;

	if (sg_pcopy_to_buffer(sg->sgl, sg->nents, rsa, sizeof(rsa),
			       guc_fw->rsa_offset) != sizeof(rsa))
		return -EINVAL;

	for (i = 0; i < UOS_RSA_SCRATCH_COUNT; i++)
		I915_WRITE(UOS_RSA_SCRATCH(i), rsa[i]);

	return 0;
}

/*
 * Transfer the firmware image to RAM for execution by the microcontroller.
 *
 * Architecturally, the DMA engine is bidirectional, and can potentially even
 * transfer between GTT locations. This functionality is left out of the API
 * for now as there is no need for it.
 */
static int guc_xfer_ucode(struct intel_guc *guc, struct i915_vma *vma)
{
	struct drm_i915_private *dev_priv = guc_to_i915(guc);
	struct intel_uc_fw *guc_fw = &guc->fw;
	unsigned long offset;
	u32 status;
	int ret;

	/*
	 * The header plus uCode will be copied to WOPCM via DMA, excluding any
	 * other components
	 */
	I915_WRITE(DMA_COPY_SIZE, guc_fw->header_size + guc_fw->ucode_size);

	/* Set the source address for the new blob */
	offset = guc_ggtt_offset(vma) + guc_fw->header_offset;
	I915_WRITE(DMA_ADDR_0_LOW, lower_32_bits(offset));
	I915_WRITE(DMA_ADDR_0_HIGH, upper_32_bits(offset) & 0xFFFF);

	/*
	 * Set the DMA destination. Current uCode expects the code to be
	 * loaded at 8k; locations below this are used for the stack.
	 */
	I915_WRITE(DMA_ADDR_1_LOW, 0x2000);
	I915_WRITE(DMA_ADDR_1_HIGH, DMA_ADDRESS_SPACE_WOPCM);

	/* Finally start the DMA */
	I915_WRITE(DMA_CTRL, _MASKED_BIT_ENABLE(UOS_MOVE | START_DMA));

	/* Wait for DMA to finish */
	ret = __intel_wait_for_register_fw(dev_priv, DMA_CTRL, START_DMA, 0,
					   2, 100, &status);
	DRM_DEBUG_DRIVER("GuC DMA status %#x\n", status);

	return ret;
}

/*
 * Read the GuC status register (GUC_STATUS) and store it in the
 * specified location; then return a boolean indicating whether
 * the value matches either of two values representing completion
 * of the GuC boot process.
 *
 * This is used for polling the GuC status in a wait_for()
 * loop below.
 */
static inline bool guc_ready(struct intel_guc *guc, u32 *status)
{
	struct drm_i915_private *dev_priv = guc_to_i915(guc);
	u32 val = I915_READ(GUC_STATUS);
	u32 uk_val = val & GS_UKERNEL_MASK;

	*status = val;
	return (uk_val == GS_UKERNEL_READY) ||
		((val & GS_MIA_CORE_STATE) && (uk_val == GS_UKERNEL_LAPIC_DONE));
}

static int guc_wait_ucode(struct intel_guc *guc)
{
	u32 status;
	int ret;

	/*
	 * Wait for the GuC to start up.
	 * NB: Docs recommend not using the interrupt for completion.
	 * Measurements indicate this should take no more than 20ms, so a
	 * timeout here indicates that the GuC has failed and is unusable.
	 * (Higher levels of the driver will attempt to fall back to
	 * execlist mode if this happens.)
	 */
	ret = wait_for(guc_ready(guc, &status), 100);
	DRM_DEBUG_DRIVER("GuC status %#x\n", status);

	if ((status & GS_BOOTROM_MASK) == GS_BOOTROM_RSA_FAILED) {
		DRM_ERROR("GuC firmware signature verification failed\n");
		ret = -ENOEXEC;
	}

	return ret;
}

/*
 * Load the GuC firmware blob into the MinuteIA.
 */
static int guc_fw_xfer(struct intel_uc_fw *guc_fw, struct i915_vma *vma)
{
	struct intel_guc *guc = container_of(guc_fw, struct intel_guc, fw);
	struct drm_i915_private *dev_priv = guc_to_i915(guc);
	int ret;

	GEM_BUG_ON(guc_fw->type != INTEL_UC_FW_TYPE_GUC);

	intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);

	guc_prepare_xfer(guc);

	/*
	 * Note that GuC needs the CSS header plus uKernel code to be copied
	 * by the DMA engine in one operation, whereas the RSA signature is
	 * loaded via MMIO.
	 */
	ret = guc_xfer_rsa(guc, vma);
	if (ret)
		DRM_WARN("GuC firmware signature xfer error %d\n", ret);

	ret = guc_xfer_ucode(guc, vma);
	if (ret)
		DRM_WARN("GuC firmware code xfer error %d\n", ret);

	ret = guc_wait_ucode(guc);
	if (ret)
		DRM_ERROR("GuC firmware xfer error %d\n", ret);

	intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);

	return ret;
}

/**
 * intel_guc_fw_upload() - finish preparing the GuC for activity
 * @guc: intel_guc structure
 *
 * Called during driver loading and also after a GPU reset.
 *
 * The main action required here it to load the GuC uCode into the device.
 * The firmware image should have already been fetched into memory by the
 * earlier call to intel_guc_init(), so here we need only check that
 * worked, and then transfer the image to the h/w.
 *
 * Return:	non-zero code on error
 */
int intel_guc_fw_upload(struct intel_guc *guc)
{
	return intel_uc_fw_upload(&guc->fw, guc_fw_xfer);
}
Commit	Line	Data
33a732f4 AD	1	/*
	2	* Copyright © 2014 Intel Corporation
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice (including the next
	12	* paragraph) shall be included in all copies or substantial portions of the
	13	* Software.
	14	*
	15	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	16	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	17	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	18	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	19	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
	20	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
	21	* IN THE SOFTWARE.
	22	*
	23	* Authors:
	24	* Vinit Azad <vinit.azad@intel.com>
	25	* Ben Widawsky <ben@bwidawsk.net>
	26	* Dave Gordon <david.s.gordon@intel.com>
	27	* Alex Dai <yu.dai@intel.com>
	28	*/
e8668bbc MW	29
e8668bbc MW	30	#include "intel_guc_fw.h"
33a732f4	31	#include "i915_drv.h"
33a732f4	32
580b9d05 SAK	33	#define SKL_FW_MAJOR 9
580b9d05 SAK	34	#define SKL_FW_MINOR 33
5e334c19	35
d416ac78 SAK	36	#define BXT_FW_MAJOR 9
d416ac78 SAK	37	#define BXT_FW_MINOR 29
5e334c19 TU	38
5e334c19 TU	39	#define KBL_FW_MAJOR 9
cc440856	40	#define KBL_FW_MINOR 39
5e334c19 TU	41
	42	#define GUC_FW_PATH(platform, major, minor) \
	43	"i915/" __stringify(platform) "_guc_ver" __stringify(major) "_" __stringify(minor) ".bin"
	44
	45	#define I915_SKL_GUC_UCODE GUC_FW_PATH(skl, SKL_FW_MAJOR, SKL_FW_MINOR)
33a732f4 AD	46	MODULE_FIRMWARE(I915_SKL_GUC_UCODE);
33a732f4 AD	47
5e334c19	48	#define I915_BXT_GUC_UCODE GUC_FW_PATH(bxt, BXT_FW_MAJOR, BXT_FW_MINOR)
57bf5c81 NH	49	MODULE_FIRMWARE(I915_BXT_GUC_UCODE);
57bf5c81 NH	50
5e334c19	51	#define I915_KBL_GUC_UCODE GUC_FW_PATH(kbl, KBL_FW_MAJOR, KBL_FW_MINOR)
ff64cc16 PA	52	MODULE_FIRMWARE(I915_KBL_GUC_UCODE);
ff64cc16 PA	53
0dd940c8	54	static void guc_fw_select(struct intel_uc_fw *guc_fw)
cd5a917e	55	{
0dd940c8	56	struct intel_guc *guc = container_of(guc_fw, struct intel_guc, fw);
cd5a917e MW	57	struct drm_i915_private *dev_priv = guc_to_i915(guc);
cd5a917e MW	58
0dd940c8 MW	59	GEM_BUG_ON(guc_fw->type != INTEL_UC_FW_TYPE_GUC);
	60
	61	if (!HAS_GUC(dev_priv))
	62	return;
cd5a917e MW	63
cd5a917e MW	64	if (i915_modparams.guc_firmware_path) {
0dd940c8 MW	65	guc_fw->path = i915_modparams.guc_firmware_path;
	66	guc_fw->major_ver_wanted = 0;
	67	guc_fw->minor_ver_wanted = 0;
cd5a917e	68	} else if (IS_SKYLAKE(dev_priv)) {
0dd940c8 MW	69	guc_fw->path = I915_SKL_GUC_UCODE;
	70	guc_fw->major_ver_wanted = SKL_FW_MAJOR;
	71	guc_fw->minor_ver_wanted = SKL_FW_MINOR;
cd5a917e	72	} else if (IS_BROXTON(dev_priv)) {
0dd940c8 MW	73	guc_fw->path = I915_BXT_GUC_UCODE;
	74	guc_fw->major_ver_wanted = BXT_FW_MAJOR;
	75	guc_fw->minor_ver_wanted = BXT_FW_MINOR;
cd5a917e	76	} else if (IS_KABYLAKE(dev_priv) \|\| IS_COFFEELAKE(dev_priv)) {
0dd940c8 MW	77	guc_fw->path = I915_KBL_GUC_UCODE;
	78	guc_fw->major_ver_wanted = KBL_FW_MAJOR;
	79	guc_fw->minor_ver_wanted = KBL_FW_MINOR;
cd5a917e	80	} else {
0dd940c8 MW	81	DRM_WARN("%s: No firmware known for this platform!\n",
0dd940c8 MW	82	intel_uc_fw_type_repr(guc_fw->type));
cd5a917e	83	}
0dd940c8 MW	84	}
	85
	86	/**
	87	* intel_guc_fw_init_early() - initializes GuC firmware struct
	88	* @guc: intel_guc struct
	89	*
	90	* On platforms with GuC selects firmware for uploading
	91	*/
	92	void intel_guc_fw_init_early(struct intel_guc *guc)
	93	{
	94	struct intel_uc_fw *guc_fw = &guc->fw;
cd5a917e	95
0dd940c8 MW	96	intel_uc_fw_init(guc_fw, INTEL_UC_FW_TYPE_GUC);
0dd940c8 MW	97	guc_fw_select(guc_fw);
cd5a917e MW	98	}
cd5a917e MW	99
2ceddb18	100	static void guc_prepare_xfer(struct intel_guc *guc)
33a732f4	101	{
2ceddb18 MW	102	struct drm_i915_private *dev_priv = guc_to_i915(guc);
2ceddb18 MW	103
b814b074 MW	104	/* Must program this register before loading the ucode with DMA */
	105	I915_WRITE(GUC_SHIM_CONTROL, GUC_DISABLE_SRAM_INIT_TO_ZEROES \|
	106	GUC_ENABLE_READ_CACHE_LOGIC \|
	107	GUC_ENABLE_MIA_CACHING \|
	108	GUC_ENABLE_READ_CACHE_FOR_SRAM_DATA \|
	109	GUC_ENABLE_READ_CACHE_FOR_WOPCM_DATA \|
	110	GUC_ENABLE_MIA_CLOCK_GATING);
2ceddb18	111
2ceddb18 MW	112	if (IS_GEN9_LP(dev_priv))
	113	I915_WRITE(GEN9LP_GT_PM_CONFIG, GT_DOORBELL_ENABLE);
	114	else
	115	I915_WRITE(GEN9_GT_PM_CONFIG, GT_DOORBELL_ENABLE);
	116
	117	if (IS_GEN9(dev_priv)) {
	118	/* DOP Clock Gating Enable for GuC clocks */
	119	I915_WRITE(GEN7_MISCCPCTL, (GEN8_DOP_CLOCK_GATE_GUC_ENABLE \|
	120	I915_READ(GEN7_MISCCPCTL)));
	121
	122	/* allows for 5us (in 10ns units) before GT can go to RC6 */
	123	I915_WRITE(GUC_ARAT_C6DIS, 0x1FF);
	124	}
	125	}
	126
	127	/* Copy RSA signature from the fw image to HW for verification */
	128	static int guc_xfer_rsa(struct intel_guc guc, struct i915_vma vma)
	129	{
	130	struct drm_i915_private *dev_priv = guc_to_i915(guc);
	131	struct intel_uc_fw *guc_fw = &guc->fw;
	132	struct sg_table *sg = vma->pages;
53fa54a6	133	u32 rsa[UOS_RSA_SCRATCH_COUNT];
2ceddb18 MW	134	int i;
	135
	136	if (sg_pcopy_to_buffer(sg->sgl, sg->nents, rsa, sizeof(rsa),
	137	guc_fw->rsa_offset) != sizeof(rsa))
	138	return -EINVAL;
	139
53fa54a6	140	for (i = 0; i < UOS_RSA_SCRATCH_COUNT; i++)
2ceddb18 MW	141	I915_WRITE(UOS_RSA_SCRATCH(i), rsa[i]);
	142
	143	return 0;
33a732f4 AD	144	}
	145
	146	/*
	147	* Transfer the firmware image to RAM for execution by the microcontroller.
	148	*
33a732f4 AD	149	* Architecturally, the DMA engine is bidirectional, and can potentially even
	150	* transfer between GTT locations. This functionality is left out of the API
	151	* for now as there is no need for it.
33a732f4	152	*/
2ceddb18	153	static int guc_xfer_ucode(struct intel_guc guc, struct i915_vma vma)
33a732f4	154	{
2ceddb18 MW	155	struct drm_i915_private *dev_priv = guc_to_i915(guc);
2ceddb18 MW	156	struct intel_uc_fw *guc_fw = &guc->fw;
33a732f4	157	unsigned long offset;
a86af231 MW	158	u32 status;
a86af231 MW	159	int ret;
33a732f4	160
2ceddb18 MW	161	/*
	162	* The header plus uCode will be copied to WOPCM via DMA, excluding any
	163	* other components
	164	*/
feda33ef AD	165	I915_WRITE(DMA_COPY_SIZE, guc_fw->header_size + guc_fw->ucode_size);
feda33ef AD	166
33a732f4	167	/* Set the source address for the new blob */
4741da92	168	offset = guc_ggtt_offset(vma) + guc_fw->header_offset;
33a732f4 AD	169	I915_WRITE(DMA_ADDR_0_LOW, lower_32_bits(offset));
	170	I915_WRITE(DMA_ADDR_0_HIGH, upper_32_bits(offset) & 0xFFFF);
	171
	172	/*
	173	* Set the DMA destination. Current uCode expects the code to be
	174	* loaded at 8k; locations below this are used for the stack.
	175	*/
	176	I915_WRITE(DMA_ADDR_1_LOW, 0x2000);
	177	I915_WRITE(DMA_ADDR_1_HIGH, DMA_ADDRESS_SPACE_WOPCM);
	178
	179	/* Finally start the DMA */
	180	I915_WRITE(DMA_CTRL, _MASKED_BIT_ENABLE(UOS_MOVE \| START_DMA));
	181
a86af231 MW	182	/* Wait for DMA to finish */
	183	ret = __intel_wait_for_register_fw(dev_priv, DMA_CTRL, START_DMA, 0,
	184	2, 100, &status);
	185	DRM_DEBUG_DRIVER("GuC DMA status %#x\n", status);
	186
	187	return ret;
2ceddb18 MW	188	}
	189
	190	/*
	191	* Read the GuC status register (GUC_STATUS) and store it in the
	192	* specified location; then return a boolean indicating whether
	193	* the value matches either of two values representing completion
	194	* of the GuC boot process.
	195	*
	196	* This is used for polling the GuC status in a wait_for()
	197	* loop below.
	198	*/
	199	static inline bool guc_ready(struct intel_guc guc, u32 status)
	200	{
	201	struct drm_i915_private *dev_priv = guc_to_i915(guc);
	202	u32 val = I915_READ(GUC_STATUS);
	203	u32 uk_val = val & GS_UKERNEL_MASK;
	204
	205	*status = val;
	206	return (uk_val == GS_UKERNEL_READY) \|\|
	207	((val & GS_MIA_CORE_STATE) && (uk_val == GS_UKERNEL_LAPIC_DONE));
	208	}
	209
	210	static int guc_wait_ucode(struct intel_guc *guc)
	211	{
	212	u32 status;
	213	int ret;
	214
33a732f4	215	/*
2ceddb18	216	* Wait for the GuC to start up.
33a732f4 AD	217	* NB: Docs recommend not using the interrupt for completion.
	218	* Measurements indicate this should take no more than 20ms, so a
	219	* timeout here indicates that the GuC has failed and is unusable.
	220	* (Higher levels of the driver will attempt to fall back to
	221	* execlist mode if this happens.)
	222	*/
2ceddb18 MW	223	ret = wait_for(guc_ready(guc, &status), 100);
2ceddb18 MW	224	DRM_DEBUG_DRIVER("GuC status %#x\n", status);
33a732f4 AD	225
	226	if ((status & GS_BOOTROM_MASK) == GS_BOOTROM_RSA_FAILED) {
	227	DRM_ERROR("GuC firmware signature verification failed\n");
	228	ret = -ENOEXEC;
	229	}
	230
33a732f4 AD	231	return ret;
	232	}
	233
	234	/*
	235	* Load the GuC firmware blob into the MinuteIA.
	236	*/
2ceddb18	237	static int guc_fw_xfer(struct intel_uc_fw guc_fw, struct i915_vma vma)
33a732f4	238	{
4502e9ec MW	239	struct intel_guc *guc = container_of(guc_fw, struct intel_guc, fw);
4502e9ec MW	240	struct drm_i915_private *dev_priv = guc_to_i915(guc);
33a732f4 AD	241	int ret;
33a732f4 AD	242
4502e9ec	243	GEM_BUG_ON(guc_fw->type != INTEL_UC_FW_TYPE_GUC);
33a732f4	244
33a732f4 AD	245	intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
33a732f4 AD	246
2ceddb18	247	guc_prepare_xfer(guc);
33a732f4	248
2ceddb18 MW	249	/*
	250	* Note that GuC needs the CSS header plus uKernel code to be copied
	251	* by the DMA engine in one operation, whereas the RSA signature is
	252	* loaded via MMIO.
	253	*/
	254	ret = guc_xfer_rsa(guc, vma);
	255	if (ret)
	256	DRM_WARN("GuC firmware signature xfer error %d\n", ret);
33a732f4	257
2ceddb18 MW	258	ret = guc_xfer_ucode(guc, vma);
	259	if (ret)
	260	DRM_WARN("GuC firmware code xfer error %d\n", ret);
33a732f4	261
2ceddb18 MW	262	ret = guc_wait_ucode(guc);
	263	if (ret)
	264	DRM_ERROR("GuC firmware xfer error %d\n", ret);
33a732f4 AD	265
	266	intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
	267
33a732f4 AD	268	return ret;
	269	}
	270
	271	/**
e8668bbc	272	* intel_guc_fw_upload() - finish preparing the GuC for activity
882d1db0	273	* @guc: intel_guc structure
33a732f4	274	*
882d1db0	275	* Called during driver loading and also after a GPU reset.
33a732f4	276	*
f09d675f	277	* The main action required here it to load the GuC uCode into the device.
33a732f4	278	* The firmware image should have already been fetched into memory by the
882d1db0 AH	279	* earlier call to intel_guc_init(), so here we need only check that
882d1db0 AH	280	* worked, and then transfer the image to the h/w.
33a732f4 AD	281	*
	282	* Return: non-zero code on error
	283	*/
e8668bbc	284	int intel_guc_fw_upload(struct intel_guc *guc)
33a732f4	285	{
2ceddb18	286	return intel_uc_fw_upload(&guc->fw, guc_fw_xfer);
33a732f4	287	}