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2617268f DG |
1 | /* |
2 | * Copyright © 2014 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | */ | |
23 | #ifndef _INTEL_GUC_FWIF_H | |
24 | #define _INTEL_GUC_FWIF_H | |
25 | ||
b53af8bb MW |
26 | #define GUC_CORE_FAMILY_GEN9 12 |
27 | #define GUC_CORE_FAMILY_UNKNOWN 0x7fffffff | |
2617268f | 28 | |
b09935a6 OM |
29 | #define GUC_CLIENT_PRIORITY_KMD_HIGH 0 |
30 | #define GUC_CLIENT_PRIORITY_HIGH 1 | |
31 | #define GUC_CLIENT_PRIORITY_KMD_NORMAL 2 | |
32 | #define GUC_CLIENT_PRIORITY_NORMAL 3 | |
33 | #define GUC_CLIENT_PRIORITY_NUM 4 | |
2617268f | 34 | |
b09935a6 OM |
35 | #define GUC_MAX_STAGE_DESCRIPTORS 1024 |
36 | #define GUC_INVALID_STAGE_ID GUC_MAX_STAGE_DESCRIPTORS | |
2617268f | 37 | |
397097b0 AD |
38 | #define GUC_RENDER_ENGINE 0 |
39 | #define GUC_VIDEO_ENGINE 1 | |
40 | #define GUC_BLITTER_ENGINE 2 | |
41 | #define GUC_VIDEOENHANCE_ENGINE 3 | |
42 | #define GUC_VIDEO_ENGINE2 4 | |
43 | #define GUC_MAX_ENGINES_NUM (GUC_VIDEO_ENGINE2 + 1) | |
44 | ||
2617268f DG |
45 | /* Work queue item header definitions */ |
46 | #define WQ_STATUS_ACTIVE 1 | |
47 | #define WQ_STATUS_SUSPENDED 2 | |
48 | #define WQ_STATUS_CMD_ERROR 3 | |
49 | #define WQ_STATUS_ENGINE_ID_NOT_USED 4 | |
50 | #define WQ_STATUS_SUSPENDED_FROM_RESET 5 | |
51 | #define WQ_TYPE_SHIFT 0 | |
52 | #define WQ_TYPE_BATCH_BUF (0x1 << WQ_TYPE_SHIFT) | |
53 | #define WQ_TYPE_PSEUDO (0x2 << WQ_TYPE_SHIFT) | |
54 | #define WQ_TYPE_INORDER (0x3 << WQ_TYPE_SHIFT) | |
55 | #define WQ_TARGET_SHIFT 10 | |
56 | #define WQ_LEN_SHIFT 16 | |
57 | #define WQ_NO_WCFLUSH_WAIT (1 << 27) | |
58 | #define WQ_PRESENT_WORKLOAD (1 << 28) | |
2617268f DG |
59 | |
60 | #define WQ_RING_TAIL_SHIFT 20 | |
0a31afbc DG |
61 | #define WQ_RING_TAIL_MAX 0x7FF /* 2^11 QWords */ |
62 | #define WQ_RING_TAIL_MASK (WQ_RING_TAIL_MAX << WQ_RING_TAIL_SHIFT) | |
2617268f DG |
63 | |
64 | #define GUC_DOORBELL_ENABLED 1 | |
65 | #define GUC_DOORBELL_DISABLED 0 | |
66 | ||
b09935a6 OM |
67 | #define GUC_STAGE_DESC_ATTR_ACTIVE BIT(0) |
68 | #define GUC_STAGE_DESC_ATTR_PENDING_DB BIT(1) | |
69 | #define GUC_STAGE_DESC_ATTR_KERNEL BIT(2) | |
70 | #define GUC_STAGE_DESC_ATTR_PREEMPT BIT(3) | |
71 | #define GUC_STAGE_DESC_ATTR_RESET BIT(4) | |
72 | #define GUC_STAGE_DESC_ATTR_WQLOCKED BIT(5) | |
73 | #define GUC_STAGE_DESC_ATTR_PCH BIT(6) | |
74 | #define GUC_STAGE_DESC_ATTR_TERMINATED BIT(7) | |
2617268f DG |
75 | |
76 | /* The guc control data is 10 DWORDs */ | |
77 | #define GUC_CTL_CTXINFO 0 | |
78 | #define GUC_CTL_CTXNUM_IN16_SHIFT 0 | |
79 | #define GUC_CTL_BASE_ADDR_SHIFT 12 | |
68371a95 | 80 | |
2617268f DG |
81 | #define GUC_CTL_ARAT_HIGH 1 |
82 | #define GUC_CTL_ARAT_LOW 2 | |
68371a95 | 83 | |
2617268f DG |
84 | #define GUC_CTL_DEVICE_INFO 3 |
85 | #define GUC_CTL_GTTYPE_SHIFT 0 | |
86 | #define GUC_CTL_COREFAMILY_SHIFT 7 | |
68371a95 | 87 | |
2617268f DG |
88 | #define GUC_CTL_LOG_PARAMS 4 |
89 | #define GUC_LOG_VALID (1 << 0) | |
90 | #define GUC_LOG_NOTIFY_ON_HALF_FULL (1 << 1) | |
91 | #define GUC_LOG_ALLOC_IN_MEGABYTE (1 << 3) | |
92 | #define GUC_LOG_CRASH_PAGES 1 | |
93 | #define GUC_LOG_CRASH_SHIFT 4 | |
72c0bc66 | 94 | #define GUC_LOG_DPC_PAGES 7 |
2617268f | 95 | #define GUC_LOG_DPC_SHIFT 6 |
72c0bc66 | 96 | #define GUC_LOG_ISR_PAGES 7 |
2617268f DG |
97 | #define GUC_LOG_ISR_SHIFT 9 |
98 | #define GUC_LOG_BUF_ADDR_SHIFT 12 | |
68371a95 | 99 | |
2617268f | 100 | #define GUC_CTL_PAGE_FAULT_CONTROL 5 |
68371a95 | 101 | |
2617268f DG |
102 | #define GUC_CTL_WA 6 |
103 | #define GUC_CTL_WA_UK_BY_DRIVER (1 << 3) | |
68371a95 | 104 | |
2617268f DG |
105 | #define GUC_CTL_FEATURE 7 |
106 | #define GUC_CTL_VCS2_ENABLED (1 << 0) | |
107 | #define GUC_CTL_KERNEL_SUBMISSIONS (1 << 1) | |
108 | #define GUC_CTL_FEATURE2 (1 << 2) | |
109 | #define GUC_CTL_POWER_GATING (1 << 3) | |
110 | #define GUC_CTL_DISABLE_SCHEDULER (1 << 4) | |
111 | #define GUC_CTL_PREEMPTION_LOG (1 << 5) | |
112 | #define GUC_CTL_ENABLE_SLPC (1 << 7) | |
aa557ab0 | 113 | #define GUC_CTL_RESET_ON_PREMPT_FAILURE (1 << 8) |
68371a95 | 114 | |
2617268f DG |
115 | #define GUC_CTL_DEBUG 8 |
116 | #define GUC_LOG_VERBOSITY_SHIFT 0 | |
117 | #define GUC_LOG_VERBOSITY_LOW (0 << GUC_LOG_VERBOSITY_SHIFT) | |
118 | #define GUC_LOG_VERBOSITY_MED (1 << GUC_LOG_VERBOSITY_SHIFT) | |
119 | #define GUC_LOG_VERBOSITY_HIGH (2 << GUC_LOG_VERBOSITY_SHIFT) | |
120 | #define GUC_LOG_VERBOSITY_ULTRA (3 << GUC_LOG_VERBOSITY_SHIFT) | |
121 | /* Verbosity range-check limits, without the shift */ | |
122 | #define GUC_LOG_VERBOSITY_MIN 0 | |
123 | #define GUC_LOG_VERBOSITY_MAX 3 | |
68371a95 AD |
124 | #define GUC_LOG_VERBOSITY_MASK 0x0000000f |
125 | #define GUC_LOG_DESTINATION_MASK (3 << 4) | |
126 | #define GUC_LOG_DISABLED (1 << 6) | |
127 | #define GUC_PROFILE_ENABLED (1 << 7) | |
128 | #define GUC_WQ_TRACK_ENABLED (1 << 8) | |
129 | #define GUC_ADS_ENABLED (1 << 9) | |
130 | #define GUC_DEBUG_RESERVED (1 << 10) | |
131 | #define GUC_ADS_ADDR_SHIFT 11 | |
132 | #define GUC_ADS_ADDR_MASK 0xfffff800 | |
133 | ||
aa557ab0 | 134 | #define GUC_CTL_RSRVD 9 |
2617268f | 135 | |
68371a95 | 136 | #define GUC_CTL_MAX_DWORDS (SOFT_SCRATCH_COUNT - 2) /* [1..14] */ |
2617268f | 137 | |
feda33ef AD |
138 | /** |
139 | * DOC: GuC Firmware Layout | |
140 | * | |
141 | * The GuC firmware layout looks like this: | |
142 | * | |
143 | * +-------------------------------+ | |
fbbad73e | 144 | * | uc_css_header | |
62cacc79 | 145 | * | | |
feda33ef AD |
146 | * | contains major/minor version | |
147 | * +-------------------------------+ | |
148 | * | uCode | | |
149 | * +-------------------------------+ | |
150 | * | RSA signature | | |
151 | * +-------------------------------+ | |
152 | * | modulus key | | |
153 | * +-------------------------------+ | |
154 | * | exponent val | | |
155 | * +-------------------------------+ | |
156 | * | |
157 | * The firmware may or may not have modulus key and exponent data. The header, | |
158 | * uCode and RSA signature are must-have components that will be used by driver. | |
159 | * Length of each components, which is all in dwords, can be found in header. | |
160 | * In the case that modulus and exponent are not present in fw, a.k.a truncated | |
161 | * image, the length value still appears in header. | |
162 | * | |
163 | * Driver will do some basic fw size validation based on the following rules: | |
164 | * | |
165 | * 1. Header, uCode and RSA are must-have components. | |
166 | * 2. All firmware components, if they present, are in the sequence illustrated | |
62cacc79 | 167 | * in the layout table above. |
feda33ef AD |
168 | * 3. Length info of each component can be found in header, in dwords. |
169 | * 4. Modulus and exponent key are not required by driver. They may not appear | |
62cacc79 | 170 | * in fw. So driver will load a truncated firmware in this case. |
fbbad73e AS |
171 | * |
172 | * HuC firmware layout is same as GuC firmware. | |
173 | * | |
174 | * HuC firmware css header is different. However, the only difference is where | |
175 | * the version information is saved. The uc_css_header is unified to support | |
176 | * both. Driver should get HuC version from uc_css_header.huc_sw_version, while | |
177 | * uc_css_header.guc_sw_version for GuC. | |
feda33ef AD |
178 | */ |
179 | ||
fbbad73e | 180 | struct uc_css_header { |
faf65486 | 181 | u32 module_type; |
feda33ef AD |
182 | /* header_size includes all non-uCode bits, including css_header, rsa |
183 | * key, modulus key and exponent data. */ | |
faf65486 JL |
184 | u32 header_size_dw; |
185 | u32 header_version; | |
186 | u32 module_id; | |
187 | u32 module_vendor; | |
feda33ef AD |
188 | union { |
189 | struct { | |
faf65486 JL |
190 | u8 day; |
191 | u8 month; | |
192 | u16 year; | |
feda33ef | 193 | }; |
faf65486 | 194 | u32 date; |
feda33ef | 195 | }; |
faf65486 JL |
196 | u32 size_dw; /* uCode plus header_size_dw */ |
197 | u32 key_size_dw; | |
198 | u32 modulus_size_dw; | |
199 | u32 exponent_size_dw; | |
feda33ef AD |
200 | union { |
201 | struct { | |
faf65486 JL |
202 | u8 hour; |
203 | u8 min; | |
204 | u16 sec; | |
feda33ef | 205 | }; |
faf65486 | 206 | u32 time; |
feda33ef AD |
207 | }; |
208 | ||
209 | char username[8]; | |
210 | char buildnumber[12]; | |
fbbad73e AS |
211 | union { |
212 | struct { | |
faf65486 JL |
213 | u32 branch_client_version; |
214 | u32 sw_version; | |
fbbad73e AS |
215 | } guc; |
216 | struct { | |
faf65486 JL |
217 | u32 sw_version; |
218 | u32 reserved; | |
fbbad73e AS |
219 | } huc; |
220 | }; | |
faf65486 JL |
221 | u32 prod_preprod_fw; |
222 | u32 reserved[12]; | |
223 | u32 header_info; | |
feda33ef AD |
224 | } __packed; |
225 | ||
2617268f DG |
226 | struct guc_doorbell_info { |
227 | u32 db_status; | |
228 | u32 cookie; | |
229 | u32 reserved[14]; | |
230 | } __packed; | |
231 | ||
232 | union guc_doorbell_qw { | |
233 | struct { | |
234 | u32 db_status; | |
235 | u32 cookie; | |
236 | }; | |
237 | u64 value_qw; | |
238 | } __packed; | |
239 | ||
abddffdf JL |
240 | #define GUC_NUM_DOORBELLS 256 |
241 | #define GUC_DOORBELL_INVALID (GUC_NUM_DOORBELLS) | |
2617268f DG |
242 | |
243 | #define GUC_DB_SIZE (PAGE_SIZE) | |
244 | #define GUC_WQ_SIZE (PAGE_SIZE * 2) | |
245 | ||
246 | /* Work item for submitting workloads into work queue of GuC. */ | |
247 | struct guc_wq_item { | |
248 | u32 header; | |
249 | u32 context_desc; | |
0d768126 | 250 | u32 submit_element_info; |
2617268f DG |
251 | u32 fence_id; |
252 | } __packed; | |
253 | ||
254 | struct guc_process_desc { | |
b09935a6 | 255 | u32 stage_id; |
2617268f DG |
256 | u64 db_base_addr; |
257 | u32 head; | |
258 | u32 tail; | |
259 | u32 error_offset; | |
260 | u64 wq_base_addr; | |
261 | u32 wq_size_bytes; | |
262 | u32 wq_status; | |
263 | u32 engine_presence; | |
264 | u32 priority; | |
265 | u32 reserved[30]; | |
266 | } __packed; | |
267 | ||
268 | /* engine id and context id is packed into guc_execlist_context.context_id*/ | |
269 | #define GUC_ELC_CTXID_OFFSET 0 | |
270 | #define GUC_ELC_ENGINE_OFFSET 29 | |
271 | ||
272 | /* The execlist context including software and HW information */ | |
273 | struct guc_execlist_context { | |
274 | u32 context_desc; | |
275 | u32 context_id; | |
276 | u32 ring_status; | |
0d768126 | 277 | u32 ring_lrca; |
2617268f DG |
278 | u32 ring_begin; |
279 | u32 ring_end; | |
280 | u32 ring_next_free_location; | |
281 | u32 ring_current_tail_pointer_value; | |
282 | u8 engine_state_submit_value; | |
283 | u8 engine_state_wait_value; | |
284 | u16 pagefault_count; | |
285 | u16 engine_submit_queue_count; | |
286 | } __packed; | |
287 | ||
b09935a6 OM |
288 | /* |
289 | * This structure describes a stage set arranged for a particular communication | |
290 | * between uKernel (GuC) and Driver (KMD). Technically, this is known as a | |
291 | * "GuC Context descriptor" in the specs, but we use the term "stage descriptor" | |
292 | * to avoid confusion with all the other things already named "context" in the | |
293 | * driver. A static pool of these descriptors are stored inside a GEM object | |
294 | * (stage_desc_pool) which is held for the entire lifetime of our interaction | |
295 | * with the GuC, being allocated before the GuC is loaded with its firmware. | |
296 | */ | |
297 | struct guc_stage_desc { | |
2617268f | 298 | u32 sched_common_area; |
b09935a6 | 299 | u32 stage_id; |
2617268f DG |
300 | u32 pas_id; |
301 | u8 engines_used; | |
302 | u64 db_trigger_cpu; | |
303 | u32 db_trigger_uk; | |
304 | u64 db_trigger_phy; | |
305 | u16 db_id; | |
306 | ||
397097b0 | 307 | struct guc_execlist_context lrc[GUC_MAX_ENGINES_NUM]; |
2617268f DG |
308 | |
309 | u8 attribute; | |
310 | ||
311 | u32 priority; | |
312 | ||
313 | u32 wq_sampled_tail_offset; | |
314 | u32 wq_total_submit_enqueues; | |
315 | ||
316 | u32 process_desc; | |
317 | u32 wq_addr; | |
318 | u32 wq_size; | |
319 | ||
320 | u32 engine_presence; | |
321 | ||
aa557ab0 AD |
322 | u8 engine_suspended; |
323 | ||
324 | u8 reserved0[3]; | |
2617268f DG |
325 | u64 reserved1[1]; |
326 | ||
327 | u64 desc_private; | |
328 | } __packed; | |
329 | ||
f8a58d63 MW |
330 | /* |
331 | * Describes single command transport buffer. | |
332 | * Used by both guc-master and clients. | |
333 | */ | |
334 | struct guc_ct_buffer_desc { | |
335 | u32 addr; /* gfx address */ | |
336 | u64 host_private; /* host private data */ | |
337 | u32 size; /* size in bytes */ | |
338 | u32 head; /* offset updated by GuC*/ | |
339 | u32 tail; /* offset updated by owner */ | |
340 | u32 is_in_error; /* error indicator */ | |
341 | u32 fence; /* fence updated by GuC */ | |
342 | u32 status; /* status updated by GuC */ | |
343 | u32 owner; /* id of the channel owner */ | |
344 | u32 owner_sub_id; /* owner-defined field for extra tracking */ | |
345 | u32 reserved[5]; | |
346 | } __packed; | |
347 | ||
348 | /* Type of command transport buffer */ | |
349 | #define INTEL_GUC_CT_BUFFER_TYPE_SEND 0x0u | |
350 | #define INTEL_GUC_CT_BUFFER_TYPE_RECV 0x1u | |
351 | ||
352 | /* | |
353 | * Definition of the command transport message header (DW0) | |
354 | * | |
355 | * bit[4..0] message len (in dwords) | |
356 | * bit[7..5] reserved | |
357 | * bit[8] write fence to desc | |
358 | * bit[9] write status to H2G buff | |
359 | * bit[10] send status (via G2H) | |
360 | * bit[15..11] reserved | |
361 | * bit[31..16] action code | |
362 | */ | |
363 | #define GUC_CT_MSG_LEN_SHIFT 0 | |
364 | #define GUC_CT_MSG_LEN_MASK 0x1F | |
365 | #define GUC_CT_MSG_WRITE_FENCE_TO_DESC (1 << 8) | |
366 | #define GUC_CT_MSG_WRITE_STATUS_TO_BUFF (1 << 9) | |
367 | #define GUC_CT_MSG_SEND_STATUS (1 << 10) | |
368 | #define GUC_CT_MSG_ACTION_SHIFT 16 | |
369 | #define GUC_CT_MSG_ACTION_MASK 0xFFFF | |
370 | ||
93f25318 AD |
371 | #define GUC_FORCEWAKE_RENDER (1 << 0) |
372 | #define GUC_FORCEWAKE_MEDIA (1 << 1) | |
373 | ||
a1c41994 AD |
374 | #define GUC_POWER_UNSPECIFIED 0 |
375 | #define GUC_POWER_D0 1 | |
376 | #define GUC_POWER_D1 2 | |
377 | #define GUC_POWER_D2 3 | |
378 | #define GUC_POWER_D3 4 | |
379 | ||
463704d0 AD |
380 | /* Scheduling policy settings */ |
381 | ||
382 | /* Reset engine upon preempt failure */ | |
383 | #define POLICY_RESET_ENGINE (1<<0) | |
384 | /* Preempt to idle on quantum expiry */ | |
385 | #define POLICY_PREEMPT_TO_IDLE (1<<1) | |
386 | ||
e9eb8039 OM |
387 | #define POLICY_MAX_NUM_WI 15 |
388 | #define POLICY_DEFAULT_DPC_PROMOTE_TIME_US 500000 | |
389 | #define POLICY_DEFAULT_EXECUTION_QUANTUM_US 1000000 | |
390 | #define POLICY_DEFAULT_PREEMPTION_TIME_US 500000 | |
391 | #define POLICY_DEFAULT_FAULT_TIME_US 250000 | |
463704d0 AD |
392 | |
393 | struct guc_policy { | |
394 | /* Time for one workload to execute. (in micro seconds) */ | |
395 | u32 execution_quantum; | |
396 | u32 reserved1; | |
397 | ||
398 | /* Time to wait for a preemption request to completed before issuing a | |
399 | * reset. (in micro seconds). */ | |
400 | u32 preemption_time; | |
401 | ||
402 | /* How much time to allow to run after the first fault is observed. | |
403 | * Then preempt afterwards. (in micro seconds) */ | |
404 | u32 fault_time; | |
405 | ||
406 | u32 policy_flags; | |
407 | u32 reserved[2]; | |
408 | } __packed; | |
409 | ||
410 | struct guc_policies { | |
b09935a6 | 411 | struct guc_policy policy[GUC_CLIENT_PRIORITY_NUM][GUC_MAX_ENGINES_NUM]; |
463704d0 AD |
412 | |
413 | /* In micro seconds. How much time to allow before DPC processing is | |
414 | * called back via interrupt (to prevent DPC queue drain starving). | |
415 | * Typically 1000s of micro seconds (example only, not granularity). */ | |
416 | u32 dpc_promote_time; | |
417 | ||
418 | /* Must be set to take these new values. */ | |
419 | u32 is_valid; | |
420 | ||
421 | /* Max number of WIs to process per call. A large value may keep CS | |
422 | * idle. */ | |
423 | u32 max_num_work_items; | |
424 | ||
425 | u32 reserved[19]; | |
426 | } __packed; | |
427 | ||
5c148e04 AD |
428 | /* GuC MMIO reg state struct */ |
429 | ||
430 | #define GUC_REGSET_FLAGS_NONE 0x0 | |
431 | #define GUC_REGSET_POWERCYCLE 0x1 | |
432 | #define GUC_REGSET_MASKED 0x2 | |
433 | #define GUC_REGSET_ENGINERESET 0x4 | |
434 | #define GUC_REGSET_SAVE_DEFAULT_VALUE 0x8 | |
435 | #define GUC_REGSET_SAVE_CURRENT_VALUE 0x10 | |
436 | ||
f3272e7a | 437 | #define GUC_REGSET_MAX_REGISTERS 25 |
5c148e04 AD |
438 | #define GUC_MMIO_WHITE_LIST_START 0x24d0 |
439 | #define GUC_MMIO_WHITE_LIST_MAX 12 | |
440 | #define GUC_S3_SAVE_SPACE_PAGES 10 | |
441 | ||
442 | struct guc_mmio_regset { | |
443 | struct __packed { | |
444 | u32 offset; | |
445 | u32 value; | |
446 | u32 flags; | |
447 | } registers[GUC_REGSET_MAX_REGISTERS]; | |
448 | ||
449 | u32 values_valid; | |
450 | u32 number_of_registers; | |
451 | } __packed; | |
452 | ||
35815ea9 OM |
453 | /* MMIO registers that are set as non privileged */ |
454 | struct mmio_white_list { | |
455 | u32 mmio_start; | |
456 | u32 offsets[GUC_MMIO_WHITE_LIST_MAX]; | |
457 | u32 count; | |
458 | } __packed; | |
459 | ||
5c148e04 AD |
460 | struct guc_mmio_reg_state { |
461 | struct guc_mmio_regset global_reg; | |
397097b0 | 462 | struct guc_mmio_regset engine_reg[GUC_MAX_ENGINES_NUM]; |
35815ea9 | 463 | struct mmio_white_list white_list[GUC_MAX_ENGINES_NUM]; |
5c148e04 AD |
464 | } __packed; |
465 | ||
68371a95 AD |
466 | /* GuC Additional Data Struct */ |
467 | ||
468 | struct guc_ads { | |
469 | u32 reg_state_addr; | |
470 | u32 reg_state_buffer; | |
471 | u32 golden_context_lrca; | |
472 | u32 scheduler_policies; | |
473 | u32 reserved0[3]; | |
397097b0 | 474 | u32 eng_state_size[GUC_MAX_ENGINES_NUM]; |
68371a95 AD |
475 | u32 reserved2[4]; |
476 | } __packed; | |
477 | ||
5d34e85a SAK |
478 | /* GuC logging structures */ |
479 | ||
480 | enum guc_log_buffer_type { | |
481 | GUC_ISR_LOG_BUFFER, | |
482 | GUC_DPC_LOG_BUFFER, | |
483 | GUC_CRASH_DUMP_LOG_BUFFER, | |
484 | GUC_MAX_LOG_BUFFER | |
485 | }; | |
486 | ||
487 | /** | |
488 | * DOC: GuC Log buffer Layout | |
489 | * | |
490 | * Page0 +-------------------------------+ | |
491 | * | ISR state header (32 bytes) | | |
492 | * | DPC state header | | |
493 | * | Crash dump state header | | |
494 | * Page1 +-------------------------------+ | |
495 | * | ISR logs | | |
5d34e85a | 496 | * Page9 +-------------------------------+ |
72c0bc66 AG |
497 | * | DPC logs | |
498 | * Page17 +-------------------------------+ | |
5d34e85a SAK |
499 | * | Crash Dump logs | |
500 | * +-------------------------------+ | |
501 | * | |
502 | * Below state structure is used for coordination of retrieval of GuC firmware | |
503 | * logs. Separate state is maintained for each log buffer type. | |
504 | * read_ptr points to the location where i915 read last in log buffer and | |
505 | * is read only for GuC firmware. write_ptr is incremented by GuC with number | |
506 | * of bytes written for each log entry and is read only for i915. | |
507 | * When any type of log buffer becomes half full, GuC sends a flush interrupt. | |
508 | * GuC firmware expects that while it is writing to 2nd half of the buffer, | |
509 | * first half would get consumed by Host and then get a flush completed | |
510 | * acknowledgment from Host, so that it does not end up doing any overwrite | |
511 | * causing loss of logs. So when buffer gets half filled & i915 has requested | |
512 | * for interrupt, GuC will set flush_to_file field, set the sampled_write_ptr | |
513 | * to the value of write_ptr and raise the interrupt. | |
514 | * On receiving the interrupt i915 should read the buffer, clear flush_to_file | |
515 | * field and also update read_ptr with the value of sample_write_ptr, before | |
516 | * sending an acknowledgment to GuC. marker & version fields are for internal | |
517 | * usage of GuC and opaque to i915. buffer_full_cnt field is incremented every | |
518 | * time GuC detects the log buffer overflow. | |
519 | */ | |
520 | struct guc_log_buffer_state { | |
521 | u32 marker[2]; | |
522 | u32 read_ptr; | |
523 | u32 write_ptr; | |
524 | u32 size; | |
525 | u32 sampled_write_ptr; | |
526 | union { | |
527 | struct { | |
528 | u32 flush_to_file:1; | |
529 | u32 buffer_full_cnt:4; | |
530 | u32 reserved:27; | |
531 | }; | |
532 | u32 flags; | |
533 | }; | |
534 | u32 version; | |
535 | } __packed; | |
536 | ||
537 | union guc_log_control { | |
538 | struct { | |
539 | u32 logging_enabled:1; | |
540 | u32 reserved1:3; | |
541 | u32 verbosity:4; | |
542 | u32 reserved2:24; | |
543 | }; | |
544 | u32 value; | |
545 | } __packed; | |
546 | ||
2617268f | 547 | /* This Action will be programmed in C180 - SOFT_SCRATCH_O_REG */ |
a80bc45f AH |
548 | enum intel_guc_action { |
549 | INTEL_GUC_ACTION_DEFAULT = 0x0, | |
550 | INTEL_GUC_ACTION_SAMPLE_FORCEWAKE = 0x6, | |
551 | INTEL_GUC_ACTION_ALLOCATE_DOORBELL = 0x10, | |
552 | INTEL_GUC_ACTION_DEALLOCATE_DOORBELL = 0x20, | |
553 | INTEL_GUC_ACTION_LOG_BUFFER_FILE_FLUSH_COMPLETE = 0x30, | |
554 | INTEL_GUC_ACTION_FORCE_LOG_BUFFER_FLUSH = 0x302, | |
555 | INTEL_GUC_ACTION_ENTER_S_STATE = 0x501, | |
556 | INTEL_GUC_ACTION_EXIT_S_STATE = 0x502, | |
557 | INTEL_GUC_ACTION_SLPC_REQUEST = 0x3003, | |
dac84a38 | 558 | INTEL_GUC_ACTION_AUTHENTICATE_HUC = 0x4000, |
f8a58d63 MW |
559 | INTEL_GUC_ACTION_REGISTER_COMMAND_TRANSPORT_BUFFER = 0x4505, |
560 | INTEL_GUC_ACTION_DEREGISTER_COMMAND_TRANSPORT_BUFFER = 0x4506, | |
a80bc45f AH |
561 | INTEL_GUC_ACTION_UK_LOG_ENABLE_LOGGING = 0x0E000, |
562 | INTEL_GUC_ACTION_LIMIT | |
2617268f DG |
563 | }; |
564 | ||
565 | /* | |
566 | * The GuC sends its response to a command by overwriting the | |
567 | * command in SS0. The response is distinguishable from a command | |
568 | * by the fact that all the MASK bits are set. The remaining bits | |
569 | * give more detail. | |
570 | */ | |
a80bc45f AH |
571 | #define INTEL_GUC_RECV_MASK ((u32)0xF0000000) |
572 | #define INTEL_GUC_RECV_IS_RESPONSE(x) ((u32)(x) >= INTEL_GUC_RECV_MASK) | |
573 | #define INTEL_GUC_RECV_STATUS(x) (INTEL_GUC_RECV_MASK | (x)) | |
2617268f DG |
574 | |
575 | /* GUC will return status back to SOFT_SCRATCH_O_REG */ | |
a80bc45f AH |
576 | enum intel_guc_status { |
577 | INTEL_GUC_STATUS_SUCCESS = INTEL_GUC_RECV_STATUS(0x0), | |
578 | INTEL_GUC_STATUS_ALLOCATE_DOORBELL_FAIL = INTEL_GUC_RECV_STATUS(0x10), | |
579 | INTEL_GUC_STATUS_DEALLOCATE_DOORBELL_FAIL = INTEL_GUC_RECV_STATUS(0x20), | |
580 | INTEL_GUC_STATUS_GENERIC_FAIL = INTEL_GUC_RECV_STATUS(0x0000F000) | |
2617268f DG |
581 | }; |
582 | ||
5d34e85a | 583 | /* This action will be programmed in C1BC - SOFT_SCRATCH_15_REG */ |
a80bc45f AH |
584 | enum intel_guc_recv_message { |
585 | INTEL_GUC_RECV_MSG_CRASH_DUMP_POSTED = BIT(1), | |
586 | INTEL_GUC_RECV_MSG_FLUSH_LOG_BUFFER = BIT(3) | |
5d34e85a SAK |
587 | }; |
588 | ||
2617268f | 589 | #endif |