[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / i915 / intel_guc_loader.c

/*
 * Copyright © 2014 Intel Corporation
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
 * IN THE SOFTWARE.
 *
 * Authors:
 *    Vinit Azad <vinit.azad@intel.com>
 *    Ben Widawsky <ben@bwidawsk.net>
 *    Dave Gordon <david.s.gordon@intel.com>
 *    Alex Dai <yu.dai@intel.com>
 */
#include "i915_drv.h"
#include "intel_uc.h"

/**
 * DOC: GuC-specific firmware loader
 *
 * intel_guc:
 * Top level structure of guc. It handles firmware loading and manages client
 * pool and doorbells. intel_guc owns a i915_guc_client to replace the legacy
 * ExecList submission.
 *
 * Firmware versioning:
 * The firmware build process will generate a version header file with major and
 * minor version defined. The versions are built into CSS header of firmware.
 * i915 kernel driver set the minimal firmware version required per platform.
 * The firmware installation package will install (symbolic link) proper version
 * of firmware.
 *
 * GuC address space:
 * GuC does not allow any gfx GGTT address that falls into range [0, WOPCM_TOP),
 * which is reserved for Boot ROM, SRAM and WOPCM. Currently this top address is
 * 512K. In order to exclude 0-512K address space from GGTT, all gfx objects
 * used by GuC is pinned with PIN_OFFSET_BIAS along with size of WOPCM.
 *
 */

#define SKL_FW_MAJOR 6
#define SKL_FW_MINOR 1

#define BXT_FW_MAJOR 8
#define BXT_FW_MINOR 7

#define KBL_FW_MAJOR 9
#define KBL_FW_MINOR 14

#define GUC_FW_PATH(platform, major, minor) \
       "i915/" __stringify(platform) "_guc_ver" __stringify(major) "_" __stringify(minor) ".bin"

#define I915_SKL_GUC_UCODE GUC_FW_PATH(skl, SKL_FW_MAJOR, SKL_FW_MINOR)
MODULE_FIRMWARE(I915_SKL_GUC_UCODE);

#define I915_BXT_GUC_UCODE GUC_FW_PATH(bxt, BXT_FW_MAJOR, BXT_FW_MINOR)
MODULE_FIRMWARE(I915_BXT_GUC_UCODE);

#define I915_KBL_GUC_UCODE GUC_FW_PATH(kbl, KBL_FW_MAJOR, KBL_FW_MINOR)
MODULE_FIRMWARE(I915_KBL_GUC_UCODE);

/* User-friendly representation of an enum */
const char *intel_uc_fw_status_repr(enum intel_uc_fw_status status)
{
	switch (status) {
	case INTEL_UC_FIRMWARE_FAIL:
		return "FAIL";
	case INTEL_UC_FIRMWARE_NONE:
		return "NONE";
	case INTEL_UC_FIRMWARE_PENDING:
		return "PENDING";
	case INTEL_UC_FIRMWARE_SUCCESS:
		return "SUCCESS";
	default:
		return "UNKNOWN!";
	}
};

static u32 get_gttype(struct drm_i915_private *dev_priv)
{
	/* XXX: GT type based on PCI device ID? field seems unused by fw */
	return 0;
}

static u32 get_core_family(struct drm_i915_private *dev_priv)
{
	u32 gen = INTEL_GEN(dev_priv);

	switch (gen) {
	case 9:
		return GFXCORE_FAMILY_GEN9;

	default:
		WARN(1, "GEN%d does not support GuC operation!\n", gen);
		return GFXCORE_FAMILY_UNKNOWN;
	}
}

/*
 * Initialise the GuC parameter block before starting the firmware
 * transfer. These parameters are read by the firmware on startup
 * and cannot be changed thereafter.
 */
static void guc_params_init(struct drm_i915_private *dev_priv)
{
	struct intel_guc *guc = &dev_priv->guc;
	u32 params[GUC_CTL_MAX_DWORDS];
	int i;

	memset(&params, 0, sizeof(params));

	params[GUC_CTL_DEVICE_INFO] |=
		(get_gttype(dev_priv) << GUC_CTL_GTTYPE_SHIFT) |
		(get_core_family(dev_priv) << GUC_CTL_COREFAMILY_SHIFT);

	/*
	 * GuC ARAT increment is 10 ns. GuC default scheduler quantum is one
	 * second. This ARAR is calculated by:
	 * Scheduler-Quantum-in-ns / ARAT-increment-in-ns = 1000000000 / 10
	 */
	params[GUC_CTL_ARAT_HIGH] = 0;
	params[GUC_CTL_ARAT_LOW] = 100000000;

	params[GUC_CTL_WA] |= GUC_CTL_WA_UK_BY_DRIVER;

	params[GUC_CTL_FEATURE] |= GUC_CTL_DISABLE_SCHEDULER |
			GUC_CTL_VCS2_ENABLED;

	params[GUC_CTL_LOG_PARAMS] = guc->log.flags;

	if (i915.guc_log_level >= 0) {
		params[GUC_CTL_DEBUG] =
			i915.guc_log_level << GUC_LOG_VERBOSITY_SHIFT;
	} else
		params[GUC_CTL_DEBUG] = GUC_LOG_DISABLED;

	if (guc->ads_vma) {
		u32 ads = guc_ggtt_offset(guc->ads_vma) >> PAGE_SHIFT;
		params[GUC_CTL_DEBUG] |= ads << GUC_ADS_ADDR_SHIFT;
		params[GUC_CTL_DEBUG] |= GUC_ADS_ENABLED;
	}

	/* If GuC submission is enabled, set up additional parameters here */
	if (i915.enable_guc_submission) {
		u32 pgs = guc_ggtt_offset(dev_priv->guc.ctx_pool);
		u32 ctx_in_16 = GUC_MAX_GPU_CONTEXTS / 16;

		pgs >>= PAGE_SHIFT;
		params[GUC_CTL_CTXINFO] = (pgs << GUC_CTL_BASE_ADDR_SHIFT) |
			(ctx_in_16 << GUC_CTL_CTXNUM_IN16_SHIFT);

		params[GUC_CTL_FEATURE] |= GUC_CTL_KERNEL_SUBMISSIONS;

		/* Unmask this bit to enable the GuC's internal scheduler */
		params[GUC_CTL_FEATURE] &= ~GUC_CTL_DISABLE_SCHEDULER;
	}

	I915_WRITE(SOFT_SCRATCH(0), 0);

	for (i = 0; i < GUC_CTL_MAX_DWORDS; i++)
		I915_WRITE(SOFT_SCRATCH(1 + i), params[i]);
}

/*
 * Read the GuC status register (GUC_STATUS) and store it in the
 * specified location; then return a boolean indicating whether
 * the value matches either of two values representing completion
 * of the GuC boot process.
 *
 * This is used for polling the GuC status in a wait_for()
 * loop below.
 */
static inline bool guc_ucode_response(struct drm_i915_private *dev_priv,
				      u32 *status)
{
	u32 val = I915_READ(GUC_STATUS);
	u32 uk_val = val & GS_UKERNEL_MASK;
	*status = val;
	return (uk_val == GS_UKERNEL_READY ||
		((val & GS_MIA_CORE_STATE) && uk_val == GS_UKERNEL_LAPIC_DONE));
}

/*
 * Transfer the firmware image to RAM for execution by the microcontroller.
 *
 * Architecturally, the DMA engine is bidirectional, and can potentially even
 * transfer between GTT locations. This functionality is left out of the API
 * for now as there is no need for it.
 *
 * Note that GuC needs the CSS header plus uKernel code to be copied by the
 * DMA engine in one operation, whereas the RSA signature is loaded via MMIO.
 */
static int guc_ucode_xfer_dma(struct drm_i915_private *dev_priv,
			      struct i915_vma *vma)
{
	struct intel_uc_fw *guc_fw = &dev_priv->guc.fw;
	unsigned long offset;
	struct sg_table *sg = vma->pages;
	u32 status, rsa[UOS_RSA_SCRATCH_MAX_COUNT];
	int i, ret = 0;

	/* where RSA signature starts */
	offset = guc_fw->rsa_offset;

	/* Copy RSA signature from the fw image to HW for verification */
	sg_pcopy_to_buffer(sg->sgl, sg->nents, rsa, sizeof(rsa), offset);
	for (i = 0; i < UOS_RSA_SCRATCH_MAX_COUNT; i++)
		I915_WRITE(UOS_RSA_SCRATCH(i), rsa[i]);

	/* The header plus uCode will be copied to WOPCM via DMA, excluding any
	 * other components */
	I915_WRITE(DMA_COPY_SIZE, guc_fw->header_size + guc_fw->ucode_size);

	/* Set the source address for the new blob */
	offset = guc_ggtt_offset(vma) + guc_fw->header_offset;
	I915_WRITE(DMA_ADDR_0_LOW, lower_32_bits(offset));
	I915_WRITE(DMA_ADDR_0_HIGH, upper_32_bits(offset) & 0xFFFF);

	/*
	 * Set the DMA destination. Current uCode expects the code to be
	 * loaded at 8k; locations below this are used for the stack.
	 */
	I915_WRITE(DMA_ADDR_1_LOW, 0x2000);
	I915_WRITE(DMA_ADDR_1_HIGH, DMA_ADDRESS_SPACE_WOPCM);

	/* Finally start the DMA */
	I915_WRITE(DMA_CTRL, _MASKED_BIT_ENABLE(UOS_MOVE | START_DMA));

	/*
	 * Wait for the DMA to complete & the GuC to start up.
	 * NB: Docs recommend not using the interrupt for completion.
	 * Measurements indicate this should take no more than 20ms, so a
	 * timeout here indicates that the GuC has failed and is unusable.
	 * (Higher levels of the driver will attempt to fall back to
	 * execlist mode if this happens.)
	 */
	ret = wait_for(guc_ucode_response(dev_priv, &status), 100);

	DRM_DEBUG_DRIVER("DMA status 0x%x, GuC status 0x%x\n",
			I915_READ(DMA_CTRL), status);

	if ((status & GS_BOOTROM_MASK) == GS_BOOTROM_RSA_FAILED) {
		DRM_ERROR("GuC firmware signature verification failed\n");
		ret = -ENOEXEC;
	}

	DRM_DEBUG_DRIVER("returning %d\n", ret);

	return ret;
}

u32 intel_guc_wopcm_size(struct drm_i915_private *dev_priv)
{
	u32 wopcm_size = GUC_WOPCM_TOP;

	/* On BXT, the top of WOPCM is reserved for RC6 context */
	if (IS_GEN9_LP(dev_priv))
		wopcm_size -= BXT_GUC_WOPCM_RC6_RESERVED;

	return wopcm_size;
}

/*
 * Load the GuC firmware blob into the MinuteIA.
 */
static int guc_ucode_xfer(struct drm_i915_private *dev_priv)
{
	struct intel_uc_fw *guc_fw = &dev_priv->guc.fw;
	struct i915_vma *vma;
	int ret;

	ret = i915_gem_object_set_to_gtt_domain(guc_fw->obj, false);
	if (ret) {
		DRM_DEBUG_DRIVER("set-domain failed %d\n", ret);
		return ret;
	}

	vma = i915_gem_object_ggtt_pin(guc_fw->obj, NULL, 0, 0,
				       PIN_OFFSET_BIAS | GUC_WOPCM_TOP);
	if (IS_ERR(vma)) {
		DRM_DEBUG_DRIVER("pin failed %d\n", (int)PTR_ERR(vma));
		return PTR_ERR(vma);
	}

	intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);

	/* init WOPCM */
	I915_WRITE(GUC_WOPCM_SIZE, intel_guc_wopcm_size(dev_priv));
	I915_WRITE(DMA_GUC_WOPCM_OFFSET, GUC_WOPCM_OFFSET_VALUE);

	/* Enable MIA caching. GuC clock gating is disabled. */
	I915_WRITE(GUC_SHIM_CONTROL, GUC_SHIM_CONTROL_VALUE);

	/* WaDisableMinuteIaClockGating:bxt */
	if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) {
		I915_WRITE(GUC_SHIM_CONTROL, (I915_READ(GUC_SHIM_CONTROL) &
					      ~GUC_ENABLE_MIA_CLOCK_GATING));
	}

	/* WaC6DisallowByGfxPause:bxt */
	if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_B0))
		I915_WRITE(GEN6_GFXPAUSE, 0x30FFF);

	if (IS_GEN9_LP(dev_priv))
		I915_WRITE(GEN9LP_GT_PM_CONFIG, GT_DOORBELL_ENABLE);
	else
		I915_WRITE(GEN9_GT_PM_CONFIG, GT_DOORBELL_ENABLE);

	if (IS_GEN9(dev_priv)) {
		/* DOP Clock Gating Enable for GuC clocks */
		I915_WRITE(GEN7_MISCCPCTL, (GEN8_DOP_CLOCK_GATE_GUC_ENABLE |
					    I915_READ(GEN7_MISCCPCTL)));

		/* allows for 5us (in 10ns units) before GT can go to RC6 */
		I915_WRITE(GUC_ARAT_C6DIS, 0x1FF);
	}

	guc_params_init(dev_priv);

	ret = guc_ucode_xfer_dma(dev_priv, vma);

	intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);

	/*
	 * We keep the object pages for reuse during resume. But we can unpin it
	 * now that DMA has completed, so it doesn't continue to take up space.
	 */
	i915_vma_unpin(vma);

	return ret;
}

/**
 * intel_guc_init_hw() - finish preparing the GuC for activity
 * @guc: intel_guc structure
 *
 * Called during driver loading and also after a GPU reset.
 *
 * The main action required here it to load the GuC uCode into the device.
 * The firmware image should have already been fetched into memory by the
 * earlier call to intel_guc_init(), so here we need only check that
 * worked, and then transfer the image to the h/w.
 *
 * Return:	non-zero code on error
 */
int intel_guc_init_hw(struct intel_guc *guc)
{
	struct drm_i915_private *dev_priv = guc_to_i915(guc);
	const char *fw_path = guc->fw.path;
	int ret;

	DRM_DEBUG_DRIVER("GuC fw status: path %s, fetch %s, load %s\n",
		fw_path,
		intel_uc_fw_status_repr(guc->fw.fetch_status),
		intel_uc_fw_status_repr(guc->fw.load_status));

	if (guc->fw.fetch_status != INTEL_UC_FIRMWARE_SUCCESS)
		return -EIO;

	guc->fw.load_status = INTEL_UC_FIRMWARE_PENDING;

	DRM_DEBUG_DRIVER("GuC fw status: fetch %s, load %s\n",
		intel_uc_fw_status_repr(guc->fw.fetch_status),
		intel_uc_fw_status_repr(guc->fw.load_status));

	ret = guc_ucode_xfer(dev_priv);

	if (ret)
		return -EAGAIN;

	guc->fw.load_status = INTEL_UC_FIRMWARE_SUCCESS;

	DRM_INFO("GuC %s (firmware %s [version %u.%u])\n",
		 i915.enable_guc_submission ? "submission enabled" : "loaded",
		 guc->fw.path,
		 guc->fw.major_ver_found, guc->fw.minor_ver_found);

	return 0;
}

/**
 * intel_guc_select_fw() - selects GuC firmware for loading
 * @guc:	intel_guc struct
 *
 * Return: zero when we know firmware, non-zero in other case
 */
int intel_guc_select_fw(struct intel_guc *guc)
{
	struct drm_i915_private *dev_priv = guc_to_i915(guc);

	guc->fw.path = NULL;
	guc->fw.fetch_status = INTEL_UC_FIRMWARE_NONE;
	guc->fw.load_status = INTEL_UC_FIRMWARE_NONE;
	guc->fw.type = INTEL_UC_FW_TYPE_GUC;

	if (i915.guc_firmware_path) {
		guc->fw.path = i915.guc_firmware_path;
		guc->fw.major_ver_wanted = 0;
		guc->fw.minor_ver_wanted = 0;
	} else if (IS_SKYLAKE(dev_priv)) {
		guc->fw.path = I915_SKL_GUC_UCODE;
		guc->fw.major_ver_wanted = SKL_FW_MAJOR;
		guc->fw.minor_ver_wanted = SKL_FW_MINOR;
	} else if (IS_BROXTON(dev_priv)) {
		guc->fw.path = I915_BXT_GUC_UCODE;
		guc->fw.major_ver_wanted = BXT_FW_MAJOR;
		guc->fw.minor_ver_wanted = BXT_FW_MINOR;
	} else if (IS_KABYLAKE(dev_priv)) {
		guc->fw.path = I915_KBL_GUC_UCODE;
		guc->fw.major_ver_wanted = KBL_FW_MAJOR;
		guc->fw.minor_ver_wanted = KBL_FW_MINOR;
	} else {
		DRM_ERROR("No GuC firmware known for platform with GuC!\n");
		return -ENOENT;
	}

	return 0;
}
Commit	Line	Data
33a732f4 AD	1	/*
	2	* Copyright © 2014 Intel Corporation
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice (including the next
	12	* paragraph) shall be included in all copies or substantial portions of the
	13	* Software.
	14	*
	15	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	16	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	17	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	18	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	19	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
	20	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
	21	* IN THE SOFTWARE.
	22	*
	23	* Authors:
	24	* Vinit Azad <vinit.azad@intel.com>
	25	* Ben Widawsky <ben@bwidawsk.net>
	26	* Dave Gordon <david.s.gordon@intel.com>
	27	* Alex Dai <yu.dai@intel.com>
	28	*/
33a732f4	29	#include "i915_drv.h"
8c4f24f9	30	#include "intel_uc.h"
33a732f4 AD	31
33a732f4 AD	32	/**
feda33ef	33	* DOC: GuC-specific firmware loader
33a732f4 AD	34	*
	35	* intel_guc:
	36	* Top level structure of guc. It handles firmware loading and manages client
	37	* pool and doorbells. intel_guc owns a i915_guc_client to replace the legacy
	38	* ExecList submission.
	39	*
	40	* Firmware versioning:
	41	* The firmware build process will generate a version header file with major and
	42	* minor version defined. The versions are built into CSS header of firmware.
	43	* i915 kernel driver set the minimal firmware version required per platform.
	44	* The firmware installation package will install (symbolic link) proper version
	45	* of firmware.
	46	*
	47	* GuC address space:
	48	* GuC does not allow any gfx GGTT address that falls into range [0, WOPCM_TOP),
	49	* which is reserved for Boot ROM, SRAM and WOPCM. Currently this top address is
	50	* 512K. In order to exclude 0-512K address space from GGTT, all gfx objects
	51	* used by GuC is pinned with PIN_OFFSET_BIAS along with size of WOPCM.
	52	*
33a732f4 AD	53	*/
33a732f4 AD	54
5e334c19 TU	55	#define SKL_FW_MAJOR 6
	56	#define SKL_FW_MINOR 1
	57
	58	#define BXT_FW_MAJOR 8
	59	#define BXT_FW_MINOR 7
	60
	61	#define KBL_FW_MAJOR 9
	62	#define KBL_FW_MINOR 14
	63
	64	#define GUC_FW_PATH(platform, major, minor) \
	65	"i915/" __stringify(platform) "_guc_ver" __stringify(major) "_" __stringify(minor) ".bin"
	66
	67	#define I915_SKL_GUC_UCODE GUC_FW_PATH(skl, SKL_FW_MAJOR, SKL_FW_MINOR)
33a732f4 AD	68	MODULE_FIRMWARE(I915_SKL_GUC_UCODE);
33a732f4 AD	69
5e334c19	70	#define I915_BXT_GUC_UCODE GUC_FW_PATH(bxt, BXT_FW_MAJOR, BXT_FW_MINOR)
57bf5c81 NH	71	MODULE_FIRMWARE(I915_BXT_GUC_UCODE);
57bf5c81 NH	72
5e334c19	73	#define I915_KBL_GUC_UCODE GUC_FW_PATH(kbl, KBL_FW_MAJOR, KBL_FW_MINOR)
ff64cc16 PA	74	MODULE_FIRMWARE(I915_KBL_GUC_UCODE);
ff64cc16 PA	75
33a732f4	76	/* User-friendly representation of an enum */
db0a091b	77	const char *intel_uc_fw_status_repr(enum intel_uc_fw_status status)
33a732f4 AD	78	{
33a732f4 AD	79	switch (status) {
db0a091b	80	case INTEL_UC_FIRMWARE_FAIL:
33a732f4	81	return "FAIL";
db0a091b	82	case INTEL_UC_FIRMWARE_NONE:
33a732f4	83	return "NONE";
db0a091b	84	case INTEL_UC_FIRMWARE_PENDING:
33a732f4	85	return "PENDING";
db0a091b	86	case INTEL_UC_FIRMWARE_SUCCESS:
33a732f4 AD	87	return "SUCCESS";
	88	default:
	89	return "UNKNOWN!";
	90	}
	91	};
	92
	93	static u32 get_gttype(struct drm_i915_private *dev_priv)
	94	{
	95	/* XXX: GT type based on PCI device ID? field seems unused by fw */
	96	return 0;
	97	}
	98
	99	static u32 get_core_family(struct drm_i915_private *dev_priv)
	100	{
fc32de93 DG	101	u32 gen = INTEL_GEN(dev_priv);
	102
	103	switch (gen) {
33a732f4 AD	104	case 9:
	105	return GFXCORE_FAMILY_GEN9;
	106
	107	default:
fc32de93	108	WARN(1, "GEN%d does not support GuC operation!\n", gen);
33a732f4 AD	109	return GFXCORE_FAMILY_UNKNOWN;
	110	}
	111	}
	112
0c5664e4 DG	113	/*
	114	* Initialise the GuC parameter block before starting the firmware
	115	* transfer. These parameters are read by the firmware on startup
	116	* and cannot be changed thereafter.
	117	*/
	118	static void guc_params_init(struct drm_i915_private *dev_priv)
33a732f4 AD	119	{
	120	struct intel_guc *guc = &dev_priv->guc;
	121	u32 params[GUC_CTL_MAX_DWORDS];
	122	int i;
	123
	124	memset(&params, 0, sizeof(params));
	125
	126	params[GUC_CTL_DEVICE_INFO] \|=
	127	(get_gttype(dev_priv) << GUC_CTL_GTTYPE_SHIFT) \|
	128	(get_core_family(dev_priv) << GUC_CTL_COREFAMILY_SHIFT);
	129
	130	/*
	131	* GuC ARAT increment is 10 ns. GuC default scheduler quantum is one
	132	* second. This ARAR is calculated by:
	133	* Scheduler-Quantum-in-ns / ARAT-increment-in-ns = 1000000000 / 10
	134	*/
	135	params[GUC_CTL_ARAT_HIGH] = 0;
	136	params[GUC_CTL_ARAT_LOW] = 100000000;
	137
	138	params[GUC_CTL_WA] \|= GUC_CTL_WA_UK_BY_DRIVER;
	139
	140	params[GUC_CTL_FEATURE] \|= GUC_CTL_DISABLE_SCHEDULER \|
	141	GUC_CTL_VCS2_ENABLED;
	142
d6b40b4b	143	params[GUC_CTL_LOG_PARAMS] = guc->log.flags;
b1e37103	144
33a732f4	145	if (i915.guc_log_level >= 0) {
33a732f4 AD	146	params[GUC_CTL_DEBUG] =
33a732f4 AD	147	i915.guc_log_level << GUC_LOG_VERBOSITY_SHIFT;
b1e37103 SAK	148	} else
b1e37103 SAK	149	params[GUC_CTL_DEBUG] = GUC_LOG_DISABLED;
33a732f4	150
8b797af1	151	if (guc->ads_vma) {
4741da92	152	u32 ads = guc_ggtt_offset(guc->ads_vma) >> PAGE_SHIFT;
b6a5cd7e AD	153	params[GUC_CTL_DEBUG] \|= ads << GUC_ADS_ADDR_SHIFT;
	154	params[GUC_CTL_DEBUG] \|= GUC_ADS_ENABLED;
	155	}
	156
bac427f8 AD	157	/* If GuC submission is enabled, set up additional parameters here */
bac427f8 AD	158	if (i915.enable_guc_submission) {
73b05534	159	u32 pgs = guc_ggtt_offset(dev_priv->guc.ctx_pool);
bac427f8 AD	160	u32 ctx_in_16 = GUC_MAX_GPU_CONTEXTS / 16;
	161
	162	pgs >>= PAGE_SHIFT;
	163	params[GUC_CTL_CTXINFO] = (pgs << GUC_CTL_BASE_ADDR_SHIFT) \|
	164	(ctx_in_16 << GUC_CTL_CTXNUM_IN16_SHIFT);
	165
	166	params[GUC_CTL_FEATURE] \|= GUC_CTL_KERNEL_SUBMISSIONS;
	167
	168	/* Unmask this bit to enable the GuC's internal scheduler */
	169	params[GUC_CTL_FEATURE] &= ~GUC_CTL_DISABLE_SCHEDULER;
	170	}
	171
33a732f4 AD	172	I915_WRITE(SOFT_SCRATCH(0), 0);
	173
	174	for (i = 0; i < GUC_CTL_MAX_DWORDS; i++)
	175	I915_WRITE(SOFT_SCRATCH(1 + i), params[i]);
	176	}
	177
	178	/*
	179	* Read the GuC status register (GUC_STATUS) and store it in the
	180	* specified location; then return a boolean indicating whether
	181	* the value matches either of two values representing completion
	182	* of the GuC boot process.
	183	*
36894e8b	184	* This is used for polling the GuC status in a wait_for()
33a732f4 AD	185	* loop below.
	186	*/
	187	static inline bool guc_ucode_response(struct drm_i915_private *dev_priv,
	188	u32 *status)
	189	{
	190	u32 val = I915_READ(GUC_STATUS);
0d44d3fa	191	u32 uk_val = val & GS_UKERNEL_MASK;
33a732f4	192	*status = val;
0d44d3fa AD	193	return (uk_val == GS_UKERNEL_READY \|\|
0d44d3fa AD	194	((val & GS_MIA_CORE_STATE) && uk_val == GS_UKERNEL_LAPIC_DONE));
33a732f4 AD	195	}
	196
	197	/*
	198	* Transfer the firmware image to RAM for execution by the microcontroller.
	199	*
33a732f4 AD	200	* Architecturally, the DMA engine is bidirectional, and can potentially even
	201	* transfer between GTT locations. This functionality is left out of the API
	202	* for now as there is no need for it.
	203	*
	204	* Note that GuC needs the CSS header plus uKernel code to be copied by the
	205	* DMA engine in one operation, whereas the RSA signature is loaded via MMIO.
	206	*/
058d88c4 CW	207	static int guc_ucode_xfer_dma(struct drm_i915_private *dev_priv,
058d88c4 CW	208	struct i915_vma *vma)
33a732f4	209	{
db0a091b	210	struct intel_uc_fw *guc_fw = &dev_priv->guc.fw;
33a732f4	211	unsigned long offset;
058d88c4	212	struct sg_table *sg = vma->pages;
feda33ef	213	u32 status, rsa[UOS_RSA_SCRATCH_MAX_COUNT];
33a732f4 AD	214	int i, ret = 0;
33a732f4 AD	215
feda33ef AD	216	/* where RSA signature starts */
feda33ef AD	217	offset = guc_fw->rsa_offset;
33a732f4 AD	218
33a732f4 AD	219	/* Copy RSA signature from the fw image to HW for verification */
feda33ef AD	220	sg_pcopy_to_buffer(sg->sgl, sg->nents, rsa, sizeof(rsa), offset);
feda33ef AD	221	for (i = 0; i < UOS_RSA_SCRATCH_MAX_COUNT; i++)
ab9cc558	222	I915_WRITE(UOS_RSA_SCRATCH(i), rsa[i]);
33a732f4	223
feda33ef AD	224	/* The header plus uCode will be copied to WOPCM via DMA, excluding any
	225	* other components */
	226	I915_WRITE(DMA_COPY_SIZE, guc_fw->header_size + guc_fw->ucode_size);
	227
33a732f4	228	/* Set the source address for the new blob */
4741da92	229	offset = guc_ggtt_offset(vma) + guc_fw->header_offset;
33a732f4 AD	230	I915_WRITE(DMA_ADDR_0_LOW, lower_32_bits(offset));
	231	I915_WRITE(DMA_ADDR_0_HIGH, upper_32_bits(offset) & 0xFFFF);
	232
	233	/*
	234	* Set the DMA destination. Current uCode expects the code to be
	235	* loaded at 8k; locations below this are used for the stack.
	236	*/
	237	I915_WRITE(DMA_ADDR_1_LOW, 0x2000);
	238	I915_WRITE(DMA_ADDR_1_HIGH, DMA_ADDRESS_SPACE_WOPCM);
	239
	240	/* Finally start the DMA */
	241	I915_WRITE(DMA_CTRL, _MASKED_BIT_ENABLE(UOS_MOVE \| START_DMA));
	242
	243	/*
36894e8b	244	* Wait for the DMA to complete & the GuC to start up.
33a732f4 AD	245	* NB: Docs recommend not using the interrupt for completion.
	246	* Measurements indicate this should take no more than 20ms, so a
	247	* timeout here indicates that the GuC has failed and is unusable.
	248	* (Higher levels of the driver will attempt to fall back to
	249	* execlist mode if this happens.)
	250	*/
36894e8b	251	ret = wait_for(guc_ucode_response(dev_priv, &status), 100);
33a732f4 AD	252
	253	DRM_DEBUG_DRIVER("DMA status 0x%x, GuC status 0x%x\n",
	254	I915_READ(DMA_CTRL), status);
	255
	256	if ((status & GS_BOOTROM_MASK) == GS_BOOTROM_RSA_FAILED) {
	257	DRM_ERROR("GuC firmware signature verification failed\n");
	258	ret = -ENOEXEC;
	259	}
	260
	261	DRM_DEBUG_DRIVER("returning %d\n", ret);
	262
	263	return ret;
	264	}
	265
bd132858	266	u32 intel_guc_wopcm_size(struct drm_i915_private *dev_priv)
74aa156b PA	267	{
	268	u32 wopcm_size = GUC_WOPCM_TOP;
	269
	270	/* On BXT, the top of WOPCM is reserved for RC6 context */
254e0931	271	if (IS_GEN9_LP(dev_priv))
74aa156b PA	272	wopcm_size -= BXT_GUC_WOPCM_RC6_RESERVED;
	273
	274	return wopcm_size;
	275	}
	276
33a732f4 AD	277	/*
	278	* Load the GuC firmware blob into the MinuteIA.
	279	*/
	280	static int guc_ucode_xfer(struct drm_i915_private *dev_priv)
	281	{
db0a091b	282	struct intel_uc_fw *guc_fw = &dev_priv->guc.fw;
058d88c4	283	struct i915_vma *vma;
33a732f4 AD	284	int ret;
33a732f4 AD	285
db0a091b	286	ret = i915_gem_object_set_to_gtt_domain(guc_fw->obj, false);
33a732f4 AD	287	if (ret) {
	288	DRM_DEBUG_DRIVER("set-domain failed %d\n", ret);
	289	return ret;
	290	}
	291
db0a091b	292	vma = i915_gem_object_ggtt_pin(guc_fw->obj, NULL, 0, 0,
83796f26	293	PIN_OFFSET_BIAS \| GUC_WOPCM_TOP);
058d88c4 CW	294	if (IS_ERR(vma)) {
	295	DRM_DEBUG_DRIVER("pin failed %d\n", (int)PTR_ERR(vma));
	296	return PTR_ERR(vma);
33a732f4 AD	297	}
33a732f4 AD	298
33a732f4 AD	299	intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
	300
	301	/* init WOPCM */
bd132858	302	I915_WRITE(GUC_WOPCM_SIZE, intel_guc_wopcm_size(dev_priv));
33a732f4 AD	303	I915_WRITE(DMA_GUC_WOPCM_OFFSET, GUC_WOPCM_OFFSET_VALUE);
	304
	305	/* Enable MIA caching. GuC clock gating is disabled. */
	306	I915_WRITE(GUC_SHIM_CONTROL, GUC_SHIM_CONTROL_VALUE);
	307
a117f378	308	/* WaDisableMinuteIaClockGating:bxt */
e2d214ae	309	if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) {
b970b486 NH	310	I915_WRITE(GUC_SHIM_CONTROL, (I915_READ(GUC_SHIM_CONTROL) &
	311	~GUC_ENABLE_MIA_CLOCK_GATING));
	312	}
	313
4ff40a41	314	/* WaC6DisallowByGfxPause:bxt */
e2d214ae	315	if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_B0))
65fe29ee	316	I915_WRITE(GEN6_GFXPAUSE, 0x30FFF);
33a732f4	317
254e0931	318	if (IS_GEN9_LP(dev_priv))
33a732f4 AD	319	I915_WRITE(GEN9LP_GT_PM_CONFIG, GT_DOORBELL_ENABLE);
	320	else
	321	I915_WRITE(GEN9_GT_PM_CONFIG, GT_DOORBELL_ENABLE);
	322
5db94019	323	if (IS_GEN9(dev_priv)) {
33a732f4 AD	324	/* DOP Clock Gating Enable for GuC clocks */
	325	I915_WRITE(GEN7_MISCCPCTL, (GEN8_DOP_CLOCK_GATE_GUC_ENABLE \|
	326	I915_READ(GEN7_MISCCPCTL)));
	327
0c5664e4	328	/* allows for 5us (in 10ns units) before GT can go to RC6 */
33a732f4 AD	329	I915_WRITE(GUC_ARAT_C6DIS, 0x1FF);
	330	}
	331
0c5664e4	332	guc_params_init(dev_priv);
33a732f4	333
058d88c4	334	ret = guc_ucode_xfer_dma(dev_priv, vma);
33a732f4 AD	335
	336	intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
	337
	338	/*
	339	* We keep the object pages for reuse during resume. But we can unpin it
	340	* now that DMA has completed, so it doesn't continue to take up space.
	341	*/
058d88c4	342	i915_vma_unpin(vma);
33a732f4 AD	343
	344	return ret;
	345	}
	346
	347	/**
882d1db0 AH	348	* intel_guc_init_hw() - finish preparing the GuC for activity
882d1db0 AH	349	* @guc: intel_guc structure
33a732f4	350	*
882d1db0	351	* Called during driver loading and also after a GPU reset.
33a732f4	352	*
f09d675f	353	* The main action required here it to load the GuC uCode into the device.
33a732f4	354	* The firmware image should have already been fetched into memory by the
882d1db0 AH	355	* earlier call to intel_guc_init(), so here we need only check that
882d1db0 AH	356	* worked, and then transfer the image to the h/w.
33a732f4 AD	357	*
	358	* Return: non-zero code on error
	359	*/
882d1db0	360	int intel_guc_init_hw(struct intel_guc *guc)
33a732f4	361	{
882d1db0 AH	362	struct drm_i915_private *dev_priv = guc_to_i915(guc);
882d1db0 AH	363	const char *fw_path = guc->fw.path;
6cd5a72c	364	int ret;
33a732f4	365
fce91f22 DG	366	DRM_DEBUG_DRIVER("GuC fw status: path %s, fetch %s, load %s\n",
fce91f22 DG	367	fw_path,
882d1db0 AH	368	intel_uc_fw_status_repr(guc->fw.fetch_status),
882d1db0 AH	369	intel_uc_fw_status_repr(guc->fw.load_status));
33a732f4	370
6cd5a72c AH	371	if (guc->fw.fetch_status != INTEL_UC_FIRMWARE_SUCCESS)
6cd5a72c AH	372	return -EIO;
7c3f86b6	373
882d1db0	374	guc->fw.load_status = INTEL_UC_FIRMWARE_PENDING;
fce91f22 DG	375
fce91f22 DG	376	DRM_DEBUG_DRIVER("GuC fw status: fetch %s, load %s\n",
882d1db0 AH	377	intel_uc_fw_status_repr(guc->fw.fetch_status),
882d1db0 AH	378	intel_uc_fw_status_repr(guc->fw.load_status));
fce91f22	379
6cd5a72c	380	ret = guc_ucode_xfer(dev_priv);
bac427f8	381
6cd5a72c AH	382	if (ret)
6cd5a72c AH	383	return -EAGAIN;
33a732f4	384
882d1db0	385	guc->fw.load_status = INTEL_UC_FIRMWARE_SUCCESS;
33a732f4	386
fb51ff40 TU	387	DRM_INFO("GuC %s (firmware %s [version %u.%u])\n",
fb51ff40 TU	388	i915.enable_guc_submission ? "submission enabled" : "loaded",
882d1db0 AH	389	guc->fw.path,
882d1db0 AH	390	guc->fw.major_ver_found, guc->fw.minor_ver_found);
fb51ff40	391
33a732f4	392	return 0;
33a732f4 AD	393	}
33a732f4 AD	394
33a732f4	395	/**
b551f610	396	* intel_guc_select_fw() - selects GuC firmware for loading
29ad6a30	397	* @guc: intel_guc struct
33a732f4	398	*
b551f610	399	* Return: zero when we know firmware, non-zero in other case
33a732f4	400	*/
b551f610	401	int intel_guc_select_fw(struct intel_guc *guc)
33a732f4	402	{
29ad6a30	403	struct drm_i915_private *dev_priv = guc_to_i915(guc);
8fc2a4e4 AH	404
	405	guc->fw.path = NULL;
	406	guc->fw.fetch_status = INTEL_UC_FIRMWARE_NONE;
	407	guc->fw.load_status = INTEL_UC_FIRMWARE_NONE;
6833b82e	408	guc->fw.type = INTEL_UC_FW_TYPE_GUC;
33a732f4	409
b3420dde AH	410	if (i915.guc_firmware_path) {
	411	guc->fw.path = i915.guc_firmware_path;
	412	guc->fw.major_ver_wanted = 0;
	413	guc->fw.minor_ver_wanted = 0;
	414	} else if (IS_SKYLAKE(dev_priv)) {
8fc2a4e4	415	guc->fw.path = I915_SKL_GUC_UCODE;
29ad6a30 AH	416	guc->fw.major_ver_wanted = SKL_FW_MAJOR;
29ad6a30 AH	417	guc->fw.minor_ver_wanted = SKL_FW_MINOR;
e2d214ae	418	} else if (IS_BROXTON(dev_priv)) {
8fc2a4e4	419	guc->fw.path = I915_BXT_GUC_UCODE;
29ad6a30 AH	420	guc->fw.major_ver_wanted = BXT_FW_MAJOR;
29ad6a30 AH	421	guc->fw.minor_ver_wanted = BXT_FW_MINOR;
0853723b	422	} else if (IS_KABYLAKE(dev_priv)) {
8fc2a4e4	423	guc->fw.path = I915_KBL_GUC_UCODE;
29ad6a30 AH	424	guc->fw.major_ver_wanted = KBL_FW_MAJOR;
29ad6a30 AH	425	guc->fw.minor_ver_wanted = KBL_FW_MINOR;
33a732f4	426	} else {
8fc2a4e4	427	DRM_ERROR("No GuC firmware known for platform with GuC!\n");
b551f610	428	return -ENOENT;
8fc2a4e4	429	}
33a732f4	430
b551f610	431	return 0;
33a732f4	432	}