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drm/i915: clarify PMINTRMSK/pm_intr_keep usage
[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / i915 / intel_guc_loader.c
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33a732f4
AD
1/*
2 * Copyright © 2014 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Vinit Azad <vinit.azad@intel.com>
25 * Ben Widawsky <ben@bwidawsk.net>
26 * Dave Gordon <david.s.gordon@intel.com>
27 * Alex Dai <yu.dai@intel.com>
28 */
29#include <linux/firmware.h>
30#include "i915_drv.h"
31#include "intel_guc.h"
32
33/**
feda33ef 34 * DOC: GuC-specific firmware loader
33a732f4
AD
35 *
36 * intel_guc:
37 * Top level structure of guc. It handles firmware loading and manages client
38 * pool and doorbells. intel_guc owns a i915_guc_client to replace the legacy
39 * ExecList submission.
40 *
41 * Firmware versioning:
42 * The firmware build process will generate a version header file with major and
43 * minor version defined. The versions are built into CSS header of firmware.
44 * i915 kernel driver set the minimal firmware version required per platform.
45 * The firmware installation package will install (symbolic link) proper version
46 * of firmware.
47 *
48 * GuC address space:
49 * GuC does not allow any gfx GGTT address that falls into range [0, WOPCM_TOP),
50 * which is reserved for Boot ROM, SRAM and WOPCM. Currently this top address is
51 * 512K. In order to exclude 0-512K address space from GGTT, all gfx objects
52 * used by GuC is pinned with PIN_OFFSET_BIAS along with size of WOPCM.
53 *
54 * Firmware log:
55 * Firmware log is enabled by setting i915.guc_log_level to non-negative level.
56 * Log data is printed out via reading debugfs i915_guc_log_dump. Reading from
57 * i915_guc_load_status will print out firmware loading status and scratch
58 * registers value.
59 *
60 */
61
5e334c19
TU
62#define SKL_FW_MAJOR 6
63#define SKL_FW_MINOR 1
64
65#define BXT_FW_MAJOR 8
66#define BXT_FW_MINOR 7
67
68#define KBL_FW_MAJOR 9
69#define KBL_FW_MINOR 14
70
71#define GUC_FW_PATH(platform, major, minor) \
72 "i915/" __stringify(platform) "_guc_ver" __stringify(major) "_" __stringify(minor) ".bin"
73
74#define I915_SKL_GUC_UCODE GUC_FW_PATH(skl, SKL_FW_MAJOR, SKL_FW_MINOR)
33a732f4
AD
75MODULE_FIRMWARE(I915_SKL_GUC_UCODE);
76
5e334c19 77#define I915_BXT_GUC_UCODE GUC_FW_PATH(bxt, BXT_FW_MAJOR, BXT_FW_MINOR)
57bf5c81
NH
78MODULE_FIRMWARE(I915_BXT_GUC_UCODE);
79
5e334c19 80#define I915_KBL_GUC_UCODE GUC_FW_PATH(kbl, KBL_FW_MAJOR, KBL_FW_MINOR)
ff64cc16
PA
81MODULE_FIRMWARE(I915_KBL_GUC_UCODE);
82
33a732f4
AD
83/* User-friendly representation of an enum */
84const char *intel_guc_fw_status_repr(enum intel_guc_fw_status status)
85{
86 switch (status) {
87 case GUC_FIRMWARE_FAIL:
88 return "FAIL";
89 case GUC_FIRMWARE_NONE:
90 return "NONE";
91 case GUC_FIRMWARE_PENDING:
92 return "PENDING";
93 case GUC_FIRMWARE_SUCCESS:
94 return "SUCCESS";
95 default:
96 return "UNKNOWN!";
97 }
98};
99
4df001d3
DG
100static void direct_interrupts_to_host(struct drm_i915_private *dev_priv)
101{
e2f80391 102 struct intel_engine_cs *engine;
b4ac5afc 103 int irqs;
4df001d3 104
fa7545a4 105 /* tell all command streamers NOT to forward interrupts or vblank to GuC */
4df001d3
DG
106 irqs = _MASKED_FIELD(GFX_FORWARD_VBLANK_MASK, GFX_FORWARD_VBLANK_NEVER);
107 irqs |= _MASKED_BIT_DISABLE(GFX_INTERRUPT_STEERING);
b4ac5afc 108 for_each_engine(engine, dev_priv)
e2f80391 109 I915_WRITE(RING_MODE_GEN7(engine), irqs);
4df001d3 110
4df001d3
DG
111 /* route all GT interrupts to the host */
112 I915_WRITE(GUC_BCS_RCS_IER, 0);
113 I915_WRITE(GUC_VCS2_VCS1_IER, 0);
114 I915_WRITE(GUC_WD_VECS_IER, 0);
115}
116
117static void direct_interrupts_to_guc(struct drm_i915_private *dev_priv)
118{
e2f80391 119 struct intel_engine_cs *engine;
b4ac5afc 120 int irqs;
1800ad25 121 u32 tmp;
4df001d3 122
fa7545a4
DG
123 /* tell all command streamers to forward interrupts (but not vblank) to GuC */
124 irqs = _MASKED_BIT_ENABLE(GFX_INTERRUPT_STEERING);
b4ac5afc 125 for_each_engine(engine, dev_priv)
e2f80391 126 I915_WRITE(RING_MODE_GEN7(engine), irqs);
4df001d3 127
4df001d3
DG
128 /* route USER_INTERRUPT to Host, all others are sent to GuC. */
129 irqs = GT_RENDER_USER_INTERRUPT << GEN8_RCS_IRQ_SHIFT |
130 GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT;
131 /* These three registers have the same bit definitions */
132 I915_WRITE(GUC_BCS_RCS_IER, ~irqs);
133 I915_WRITE(GUC_VCS2_VCS1_IER, ~irqs);
134 I915_WRITE(GUC_WD_VECS_IER, ~irqs);
1800ad25
SAK
135
136 /*
b20e3cfe
DG
137 * The REDIRECT_TO_GUC bit of the PMINTRMSK register directs all
138 * (unmasked) PM interrupts to the GuC. All other bits of this
139 * register *disable* generation of a specific interrupt.
140 *
141 * 'pm_intr_keep' indicates bits that are NOT to be set when
142 * writing to the PM interrupt mask register, i.e. interrupts
143 * that must not be disabled.
144 *
145 * If the GuC is handling these interrupts, then we must not let
146 * the PM code disable ANY interrupt that the GuC is expecting.
147 * So for each ENABLED (0) bit in this register, we must SET the
148 * bit in pm_intr_keep so that it's left enabled for the GuC.
149 *
150 * OTOH the REDIRECT_TO_GUC bit is initially SET in pm_intr_keep
151 * (so interrupts go to the DISPLAY unit at first); but here we
152 * need to CLEAR that bit, which will result in the register bit
153 * being left SET!
154 */
1800ad25 155 tmp = I915_READ(GEN6_PMINTRMSK);
b20e3cfe
DG
156 if (tmp & GEN8_PMINTR_REDIRECT_TO_GUC) {
157 dev_priv->rps.pm_intr_keep |= ~tmp;
158 dev_priv->rps.pm_intr_keep &= ~GEN8_PMINTR_REDIRECT_TO_GUC;
1800ad25 159 }
4df001d3
DG
160}
161
33a732f4
AD
162static u32 get_gttype(struct drm_i915_private *dev_priv)
163{
164 /* XXX: GT type based on PCI device ID? field seems unused by fw */
165 return 0;
166}
167
168static u32 get_core_family(struct drm_i915_private *dev_priv)
169{
fc32de93
DG
170 u32 gen = INTEL_GEN(dev_priv);
171
172 switch (gen) {
33a732f4
AD
173 case 9:
174 return GFXCORE_FAMILY_GEN9;
175
176 default:
fc32de93 177 WARN(1, "GEN%d does not support GuC operation!\n", gen);
33a732f4
AD
178 return GFXCORE_FAMILY_UNKNOWN;
179 }
180}
181
182static void set_guc_init_params(struct drm_i915_private *dev_priv)
183{
184 struct intel_guc *guc = &dev_priv->guc;
185 u32 params[GUC_CTL_MAX_DWORDS];
186 int i;
187
188 memset(&params, 0, sizeof(params));
189
190 params[GUC_CTL_DEVICE_INFO] |=
191 (get_gttype(dev_priv) << GUC_CTL_GTTYPE_SHIFT) |
192 (get_core_family(dev_priv) << GUC_CTL_COREFAMILY_SHIFT);
193
194 /*
195 * GuC ARAT increment is 10 ns. GuC default scheduler quantum is one
196 * second. This ARAR is calculated by:
197 * Scheduler-Quantum-in-ns / ARAT-increment-in-ns = 1000000000 / 10
198 */
199 params[GUC_CTL_ARAT_HIGH] = 0;
200 params[GUC_CTL_ARAT_LOW] = 100000000;
201
202 params[GUC_CTL_WA] |= GUC_CTL_WA_UK_BY_DRIVER;
203
204 params[GUC_CTL_FEATURE] |= GUC_CTL_DISABLE_SCHEDULER |
205 GUC_CTL_VCS2_ENABLED;
206
207 if (i915.guc_log_level >= 0) {
208 params[GUC_CTL_LOG_PARAMS] = guc->log_flags;
209 params[GUC_CTL_DEBUG] =
210 i915.guc_log_level << GUC_LOG_VERBOSITY_SHIFT;
211 }
212
8b797af1 213 if (guc->ads_vma) {
bde13ebd 214 u32 ads = i915_ggtt_offset(guc->ads_vma) >> PAGE_SHIFT;
b6a5cd7e
AD
215 params[GUC_CTL_DEBUG] |= ads << GUC_ADS_ADDR_SHIFT;
216 params[GUC_CTL_DEBUG] |= GUC_ADS_ENABLED;
217 }
218
bac427f8
AD
219 /* If GuC submission is enabled, set up additional parameters here */
220 if (i915.enable_guc_submission) {
bde13ebd 221 u32 pgs = i915_ggtt_offset(dev_priv->guc.ctx_pool_vma);
bac427f8
AD
222 u32 ctx_in_16 = GUC_MAX_GPU_CONTEXTS / 16;
223
224 pgs >>= PAGE_SHIFT;
225 params[GUC_CTL_CTXINFO] = (pgs << GUC_CTL_BASE_ADDR_SHIFT) |
226 (ctx_in_16 << GUC_CTL_CTXNUM_IN16_SHIFT);
227
228 params[GUC_CTL_FEATURE] |= GUC_CTL_KERNEL_SUBMISSIONS;
229
230 /* Unmask this bit to enable the GuC's internal scheduler */
231 params[GUC_CTL_FEATURE] &= ~GUC_CTL_DISABLE_SCHEDULER;
232 }
233
33a732f4
AD
234 I915_WRITE(SOFT_SCRATCH(0), 0);
235
236 for (i = 0; i < GUC_CTL_MAX_DWORDS; i++)
237 I915_WRITE(SOFT_SCRATCH(1 + i), params[i]);
238}
239
240/*
241 * Read the GuC status register (GUC_STATUS) and store it in the
242 * specified location; then return a boolean indicating whether
243 * the value matches either of two values representing completion
244 * of the GuC boot process.
245 *
36894e8b 246 * This is used for polling the GuC status in a wait_for()
33a732f4
AD
247 * loop below.
248 */
249static inline bool guc_ucode_response(struct drm_i915_private *dev_priv,
250 u32 *status)
251{
252 u32 val = I915_READ(GUC_STATUS);
0d44d3fa 253 u32 uk_val = val & GS_UKERNEL_MASK;
33a732f4 254 *status = val;
0d44d3fa
AD
255 return (uk_val == GS_UKERNEL_READY ||
256 ((val & GS_MIA_CORE_STATE) && uk_val == GS_UKERNEL_LAPIC_DONE));
33a732f4
AD
257}
258
259/*
260 * Transfer the firmware image to RAM for execution by the microcontroller.
261 *
33a732f4
AD
262 * Architecturally, the DMA engine is bidirectional, and can potentially even
263 * transfer between GTT locations. This functionality is left out of the API
264 * for now as there is no need for it.
265 *
266 * Note that GuC needs the CSS header plus uKernel code to be copied by the
267 * DMA engine in one operation, whereas the RSA signature is loaded via MMIO.
268 */
058d88c4
CW
269static int guc_ucode_xfer_dma(struct drm_i915_private *dev_priv,
270 struct i915_vma *vma)
33a732f4
AD
271{
272 struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;
33a732f4 273 unsigned long offset;
058d88c4 274 struct sg_table *sg = vma->pages;
feda33ef 275 u32 status, rsa[UOS_RSA_SCRATCH_MAX_COUNT];
33a732f4
AD
276 int i, ret = 0;
277
feda33ef
AD
278 /* where RSA signature starts */
279 offset = guc_fw->rsa_offset;
33a732f4
AD
280
281 /* Copy RSA signature from the fw image to HW for verification */
feda33ef
AD
282 sg_pcopy_to_buffer(sg->sgl, sg->nents, rsa, sizeof(rsa), offset);
283 for (i = 0; i < UOS_RSA_SCRATCH_MAX_COUNT; i++)
ab9cc558 284 I915_WRITE(UOS_RSA_SCRATCH(i), rsa[i]);
33a732f4 285
feda33ef
AD
286 /* The header plus uCode will be copied to WOPCM via DMA, excluding any
287 * other components */
288 I915_WRITE(DMA_COPY_SIZE, guc_fw->header_size + guc_fw->ucode_size);
289
33a732f4 290 /* Set the source address for the new blob */
bde13ebd 291 offset = i915_ggtt_offset(vma) + guc_fw->header_offset;
33a732f4
AD
292 I915_WRITE(DMA_ADDR_0_LOW, lower_32_bits(offset));
293 I915_WRITE(DMA_ADDR_0_HIGH, upper_32_bits(offset) & 0xFFFF);
294
295 /*
296 * Set the DMA destination. Current uCode expects the code to be
297 * loaded at 8k; locations below this are used for the stack.
298 */
299 I915_WRITE(DMA_ADDR_1_LOW, 0x2000);
300 I915_WRITE(DMA_ADDR_1_HIGH, DMA_ADDRESS_SPACE_WOPCM);
301
302 /* Finally start the DMA */
303 I915_WRITE(DMA_CTRL, _MASKED_BIT_ENABLE(UOS_MOVE | START_DMA));
304
305 /*
36894e8b 306 * Wait for the DMA to complete & the GuC to start up.
33a732f4
AD
307 * NB: Docs recommend not using the interrupt for completion.
308 * Measurements indicate this should take no more than 20ms, so a
309 * timeout here indicates that the GuC has failed and is unusable.
310 * (Higher levels of the driver will attempt to fall back to
311 * execlist mode if this happens.)
312 */
36894e8b 313 ret = wait_for(guc_ucode_response(dev_priv, &status), 100);
33a732f4
AD
314
315 DRM_DEBUG_DRIVER("DMA status 0x%x, GuC status 0x%x\n",
316 I915_READ(DMA_CTRL), status);
317
318 if ((status & GS_BOOTROM_MASK) == GS_BOOTROM_RSA_FAILED) {
319 DRM_ERROR("GuC firmware signature verification failed\n");
320 ret = -ENOEXEC;
321 }
322
323 DRM_DEBUG_DRIVER("returning %d\n", ret);
324
325 return ret;
326}
327
74aa156b
PA
328static u32 guc_wopcm_size(struct drm_i915_private *dev_priv)
329{
330 u32 wopcm_size = GUC_WOPCM_TOP;
331
332 /* On BXT, the top of WOPCM is reserved for RC6 context */
333 if (IS_BROXTON(dev_priv))
334 wopcm_size -= BXT_GUC_WOPCM_RC6_RESERVED;
335
336 return wopcm_size;
337}
338
33a732f4
AD
339/*
340 * Load the GuC firmware blob into the MinuteIA.
341 */
342static int guc_ucode_xfer(struct drm_i915_private *dev_priv)
343{
344 struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;
91c8a326 345 struct drm_device *dev = &dev_priv->drm;
058d88c4 346 struct i915_vma *vma;
33a732f4
AD
347 int ret;
348
349 ret = i915_gem_object_set_to_gtt_domain(guc_fw->guc_fw_obj, false);
350 if (ret) {
351 DRM_DEBUG_DRIVER("set-domain failed %d\n", ret);
352 return ret;
353 }
354
058d88c4
CW
355 vma = i915_gem_object_ggtt_pin(guc_fw->guc_fw_obj, NULL, 0, 0, 0);
356 if (IS_ERR(vma)) {
357 DRM_DEBUG_DRIVER("pin failed %d\n", (int)PTR_ERR(vma));
358 return PTR_ERR(vma);
33a732f4
AD
359 }
360
361 /* Invalidate GuC TLB to let GuC take the latest updates to GTT. */
362 I915_WRITE(GEN8_GTCR, GEN8_GTCR_INVALIDATE);
363
364 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
365
366 /* init WOPCM */
74aa156b 367 I915_WRITE(GUC_WOPCM_SIZE, guc_wopcm_size(dev_priv));
33a732f4
AD
368 I915_WRITE(DMA_GUC_WOPCM_OFFSET, GUC_WOPCM_OFFSET_VALUE);
369
370 /* Enable MIA caching. GuC clock gating is disabled. */
371 I915_WRITE(GUC_SHIM_CONTROL, GUC_SHIM_CONTROL_VALUE);
372
b970b486 373 /* WaDisableMinuteIaClockGating:skl,bxt */
e87a005d 374 if (IS_SKL_REVID(dev, 0, SKL_REVID_B0) ||
cbdc12a9 375 IS_BXT_REVID(dev, 0, BXT_REVID_A1)) {
b970b486
NH
376 I915_WRITE(GUC_SHIM_CONTROL, (I915_READ(GUC_SHIM_CONTROL) &
377 ~GUC_ENABLE_MIA_CLOCK_GATING));
378 }
379
33a732f4 380 /* WaC6DisallowByGfxPause*/
65fe29ee
TG
381 if (IS_SKL_REVID(dev, 0, SKL_REVID_C0) ||
382 IS_BXT_REVID(dev, 0, BXT_REVID_B0))
383 I915_WRITE(GEN6_GFXPAUSE, 0x30FFF);
33a732f4
AD
384
385 if (IS_BROXTON(dev))
386 I915_WRITE(GEN9LP_GT_PM_CONFIG, GT_DOORBELL_ENABLE);
387 else
388 I915_WRITE(GEN9_GT_PM_CONFIG, GT_DOORBELL_ENABLE);
389
390 if (IS_GEN9(dev)) {
391 /* DOP Clock Gating Enable for GuC clocks */
392 I915_WRITE(GEN7_MISCCPCTL, (GEN8_DOP_CLOCK_GATE_GUC_ENABLE |
393 I915_READ(GEN7_MISCCPCTL)));
394
395 /* allows for 5us before GT can go to RC6 */
396 I915_WRITE(GUC_ARAT_C6DIS, 0x1FF);
397 }
398
399 set_guc_init_params(dev_priv);
400
058d88c4 401 ret = guc_ucode_xfer_dma(dev_priv, vma);
33a732f4
AD
402
403 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
404
405 /*
406 * We keep the object pages for reuse during resume. But we can unpin it
407 * now that DMA has completed, so it doesn't continue to take up space.
408 */
058d88c4 409 i915_vma_unpin(vma);
33a732f4
AD
410
411 return ret;
412}
413
6b332fa2
AS
414static int i915_reset_guc(struct drm_i915_private *dev_priv)
415{
416 int ret;
417 u32 guc_status;
418
419 ret = intel_guc_reset(dev_priv);
420 if (ret) {
421 DRM_ERROR("GuC reset failed, ret = %d\n", ret);
422 return ret;
423 }
424
425 guc_status = I915_READ(GUC_STATUS);
426 WARN(!(guc_status & GS_MIA_IN_RESET),
427 "GuC status: 0x%x, MIA core expected to be in reset\n", guc_status);
428
429 return ret;
430}
431
33a732f4 432/**
f09d675f 433 * intel_guc_setup() - finish preparing the GuC for activity
33a732f4
AD
434 * @dev: drm device
435 *
436 * Called from gem_init_hw() during driver loading and also after a GPU reset.
437 *
f09d675f 438 * The main action required here it to load the GuC uCode into the device.
33a732f4 439 * The firmware image should have already been fetched into memory by the
f09d675f
DG
440 * earlier call to intel_guc_init(), so here we need only check that worked,
441 * and then transfer the image to the h/w.
33a732f4
AD
442 *
443 * Return: non-zero code on error
444 */
f09d675f 445int intel_guc_setup(struct drm_device *dev)
33a732f4 446{
fac5e23e 447 struct drm_i915_private *dev_priv = to_i915(dev);
33a732f4 448 struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;
fce91f22
DG
449 const char *fw_path = guc_fw->guc_fw_path;
450 int retries, ret, err;
33a732f4 451
fce91f22
DG
452 DRM_DEBUG_DRIVER("GuC fw status: path %s, fetch %s, load %s\n",
453 fw_path,
33a732f4
AD
454 intel_guc_fw_status_repr(guc_fw->guc_fw_fetch_status),
455 intel_guc_fw_status_repr(guc_fw->guc_fw_load_status));
456
fce91f22
DG
457 /* Loading forbidden, or no firmware to load? */
458 if (!i915.enable_guc_loading) {
459 err = 0;
460 goto fail;
e556f7c1
DG
461 } else if (fw_path == NULL) {
462 /* Device is known to have no uCode (e.g. no GuC) */
463 err = -ENXIO;
464 goto fail;
465 } else if (*fw_path == '\0') {
466 /* Device has a GuC but we don't know what f/w to load? */
fc32de93 467 WARN(1, "No GuC firmware known for this platform!\n");
fce91f22
DG
468 err = -ENODEV;
469 goto fail;
470 }
33a732f4 471
fce91f22
DG
472 /* Fetch failed, or already fetched but failed to load? */
473 if (guc_fw->guc_fw_fetch_status != GUC_FIRMWARE_SUCCESS) {
33a732f4
AD
474 err = -EIO;
475 goto fail;
fce91f22
DG
476 } else if (guc_fw->guc_fw_load_status == GUC_FIRMWARE_FAIL) {
477 err = -ENOEXEC;
33a732f4 478 goto fail;
33a732f4
AD
479 }
480
fce91f22
DG
481 direct_interrupts_to_host(dev_priv);
482
483 guc_fw->guc_fw_load_status = GUC_FIRMWARE_PENDING;
484
485 DRM_DEBUG_DRIVER("GuC fw status: fetch %s, load %s\n",
486 intel_guc_fw_status_repr(guc_fw->guc_fw_fetch_status),
487 intel_guc_fw_status_repr(guc_fw->guc_fw_load_status));
488
beffa517 489 err = i915_guc_submission_init(dev_priv);
bac427f8
AD
490 if (err)
491 goto fail;
492
6b332fa2
AS
493 /*
494 * WaEnableuKernelHeaderValidFix:skl,bxt
495 * For BXT, this is only upto B0 but below WA is required for later
496 * steppings also so this is extended as well.
497 */
498 /* WaEnableGuCBootHashCheckNotSet:skl,bxt */
d761701c
DG
499 for (retries = 3; ; ) {
500 /*
501 * Always reset the GuC just before (re)loading, so
502 * that the state and timing are fairly predictable
503 */
504 err = i915_reset_guc(dev_priv);
fc32de93 505 if (err)
6b332fa2 506 goto fail;
d761701c
DG
507
508 err = guc_ucode_xfer(dev_priv);
509 if (!err)
510 break;
511
512 if (--retries == 0)
513 goto fail;
514
fce91f22
DG
515 DRM_INFO("GuC fw load failed: %d; will reset and "
516 "retry %d more time(s)\n", err, retries);
6b332fa2 517 }
33a732f4
AD
518
519 guc_fw->guc_fw_load_status = GUC_FIRMWARE_SUCCESS;
520
521 DRM_DEBUG_DRIVER("GuC fw status: fetch %s, load %s\n",
522 intel_guc_fw_status_repr(guc_fw->guc_fw_fetch_status),
523 intel_guc_fw_status_repr(guc_fw->guc_fw_load_status));
524
44a28b1d 525 if (i915.enable_guc_submission) {
beffa517 526 err = i915_guc_submission_enable(dev_priv);
44a28b1d
DG
527 if (err)
528 goto fail;
4df001d3 529 direct_interrupts_to_guc(dev_priv);
44a28b1d
DG
530 }
531
33a732f4
AD
532 return 0;
533
534fail:
535 if (guc_fw->guc_fw_load_status == GUC_FIRMWARE_PENDING)
536 guc_fw->guc_fw_load_status = GUC_FIRMWARE_FAIL;
537
4df001d3 538 direct_interrupts_to_host(dev_priv);
beffa517
DG
539 i915_guc_submission_disable(dev_priv);
540 i915_guc_submission_fini(dev_priv);
44a28b1d 541
fce91f22
DG
542 /*
543 * We've failed to load the firmware :(
544 *
545 * Decide whether to disable GuC submission and fall back to
546 * execlist mode, and whether to hide the error by returning
547 * zero or to return -EIO, which the caller will treat as a
548 * nonfatal error (i.e. it doesn't prevent driver load, but
549 * marks the GPU as wedged until reset).
550 */
551 if (i915.enable_guc_loading > 1) {
552 ret = -EIO;
553 } else if (i915.enable_guc_submission > 1) {
554 ret = -EIO;
555 } else {
556 ret = 0;
557 }
558
4e50f796
DG
559 if (err == 0 && !HAS_GUC_UCODE(dev))
560 ; /* Don't mention the GuC! */
561 else if (err == 0)
fce91f22 562 DRM_INFO("GuC firmware load skipped\n");
4e50f796 563 else if (ret != -EIO)
fc32de93 564 DRM_NOTE("GuC firmware load failed: %d\n", err);
4e50f796 565 else
fc32de93 566 DRM_WARN("GuC firmware load failed: %d\n", err);
fce91f22
DG
567
568 if (i915.enable_guc_submission) {
569 if (fw_path == NULL)
570 DRM_INFO("GuC submission without firmware not supported\n");
571 if (ret == 0)
fc32de93 572 DRM_NOTE("Falling back from GuC submission to execlist mode\n");
fce91f22
DG
573 else
574 DRM_ERROR("GuC init failed: %d\n", ret);
575 }
576 i915.enable_guc_submission = 0;
577
578 return ret;
33a732f4
AD
579}
580
581static void guc_fw_fetch(struct drm_device *dev, struct intel_guc_fw *guc_fw)
582{
52a05c30 583 struct pci_dev *pdev = dev->pdev;
33a732f4
AD
584 struct drm_i915_gem_object *obj;
585 const struct firmware *fw;
feda33ef
AD
586 struct guc_css_header *css;
587 size_t size;
33a732f4
AD
588 int err;
589
590 DRM_DEBUG_DRIVER("before requesting firmware: GuC fw fetch status %s\n",
591 intel_guc_fw_status_repr(guc_fw->guc_fw_fetch_status));
592
52a05c30 593 err = request_firmware(&fw, guc_fw->guc_fw_path, &pdev->dev);
33a732f4
AD
594 if (err)
595 goto fail;
596 if (!fw)
597 goto fail;
598
599 DRM_DEBUG_DRIVER("fetch GuC fw from %s succeeded, fw %p\n",
600 guc_fw->guc_fw_path, fw);
33a732f4 601
feda33ef
AD
602 /* Check the size of the blob before examining buffer contents */
603 if (fw->size < sizeof(struct guc_css_header)) {
fc32de93 604 DRM_NOTE("Firmware header is missing\n");
33a732f4 605 goto fail;
feda33ef
AD
606 }
607
608 css = (struct guc_css_header *)fw->data;
609
610 /* Firmware bits always start from header */
611 guc_fw->header_offset = 0;
612 guc_fw->header_size = (css->header_size_dw - css->modulus_size_dw -
613 css->key_size_dw - css->exponent_size_dw) * sizeof(u32);
614
615 if (guc_fw->header_size != sizeof(struct guc_css_header)) {
fc32de93 616 DRM_NOTE("CSS header definition mismatch\n");
feda33ef
AD
617 goto fail;
618 }
619
620 /* then, uCode */
621 guc_fw->ucode_offset = guc_fw->header_offset + guc_fw->header_size;
622 guc_fw->ucode_size = (css->size_dw - css->header_size_dw) * sizeof(u32);
623
624 /* now RSA */
625 if (css->key_size_dw != UOS_RSA_SCRATCH_MAX_COUNT) {
fc32de93 626 DRM_NOTE("RSA key size is bad\n");
feda33ef
AD
627 goto fail;
628 }
629 guc_fw->rsa_offset = guc_fw->ucode_offset + guc_fw->ucode_size;
630 guc_fw->rsa_size = css->key_size_dw * sizeof(u32);
631
632 /* At least, it should have header, uCode and RSA. Size of all three. */
633 size = guc_fw->header_size + guc_fw->ucode_size + guc_fw->rsa_size;
634 if (fw->size < size) {
fc32de93 635 DRM_NOTE("Missing firmware components\n");
feda33ef
AD
636 goto fail;
637 }
638
639 /* Header and uCode will be loaded to WOPCM. Size of the two. */
640 size = guc_fw->header_size + guc_fw->ucode_size;
f19ec8cb 641 if (size > guc_wopcm_size(to_i915(dev))) {
fc32de93 642 DRM_NOTE("Firmware is too large to fit in WOPCM\n");
feda33ef
AD
643 goto fail;
644 }
33a732f4
AD
645
646 /*
647 * The GuC firmware image has the version number embedded at a well-known
648 * offset within the firmware blob; note that major / minor version are
649 * TWO bytes each (i.e. u16), although all pointers and offsets are defined
650 * in terms of bytes (u8).
651 */
feda33ef
AD
652 guc_fw->guc_fw_major_found = css->guc_sw_version >> 16;
653 guc_fw->guc_fw_minor_found = css->guc_sw_version & 0xFFFF;
33a732f4
AD
654
655 if (guc_fw->guc_fw_major_found != guc_fw->guc_fw_major_wanted ||
656 guc_fw->guc_fw_minor_found < guc_fw->guc_fw_minor_wanted) {
fc32de93 657 DRM_NOTE("GuC firmware version %d.%d, required %d.%d\n",
33a732f4
AD
658 guc_fw->guc_fw_major_found, guc_fw->guc_fw_minor_found,
659 guc_fw->guc_fw_major_wanted, guc_fw->guc_fw_minor_wanted);
660 err = -ENOEXEC;
661 goto fail;
662 }
663
664 DRM_DEBUG_DRIVER("firmware version %d.%d OK (minimum %d.%d)\n",
665 guc_fw->guc_fw_major_found, guc_fw->guc_fw_minor_found,
666 guc_fw->guc_fw_major_wanted, guc_fw->guc_fw_minor_wanted);
667
bf248ca1 668 mutex_lock(&dev->struct_mutex);
33a732f4 669 obj = i915_gem_object_create_from_data(dev, fw->data, fw->size);
bf248ca1 670 mutex_unlock(&dev->struct_mutex);
33a732f4
AD
671 if (IS_ERR_OR_NULL(obj)) {
672 err = obj ? PTR_ERR(obj) : -ENOMEM;
673 goto fail;
674 }
675
676 guc_fw->guc_fw_obj = obj;
677 guc_fw->guc_fw_size = fw->size;
678
679 DRM_DEBUG_DRIVER("GuC fw fetch status SUCCESS, obj %p\n",
680 guc_fw->guc_fw_obj);
681
682 release_firmware(fw);
683 guc_fw->guc_fw_fetch_status = GUC_FIRMWARE_SUCCESS;
684 return;
685
686fail:
fc32de93
DG
687 DRM_WARN("Failed to fetch valid GuC firmware from %s (error %d)\n",
688 guc_fw->guc_fw_path, err);
33a732f4
AD
689 DRM_DEBUG_DRIVER("GuC fw fetch status FAIL; err %d, fw %p, obj %p\n",
690 err, fw, guc_fw->guc_fw_obj);
33a732f4 691
a9d8adad 692 mutex_lock(&dev->struct_mutex);
33a732f4
AD
693 obj = guc_fw->guc_fw_obj;
694 if (obj)
f8c417cd 695 i915_gem_object_put(obj);
33a732f4 696 guc_fw->guc_fw_obj = NULL;
a9d8adad 697 mutex_unlock(&dev->struct_mutex);
33a732f4
AD
698
699 release_firmware(fw); /* OK even if fw is NULL */
700 guc_fw->guc_fw_fetch_status = GUC_FIRMWARE_FAIL;
701}
702
703/**
f09d675f 704 * intel_guc_init() - define parameters and fetch firmware
33a732f4
AD
705 * @dev: drm device
706 *
707 * Called early during driver load, but after GEM is initialised.
33a732f4
AD
708 *
709 * The firmware will be transferred to the GuC's memory later,
f09d675f 710 * when intel_guc_setup() is called.
33a732f4 711 */
f09d675f 712void intel_guc_init(struct drm_device *dev)
33a732f4 713{
fac5e23e 714 struct drm_i915_private *dev_priv = to_i915(dev);
33a732f4
AD
715 struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;
716 const char *fw_path;
717
fce91f22
DG
718 /* A negative value means "use platform default" */
719 if (i915.enable_guc_loading < 0)
720 i915.enable_guc_loading = HAS_GUC_UCODE(dev);
721 if (i915.enable_guc_submission < 0)
722 i915.enable_guc_submission = HAS_GUC_SCHED(dev);
33a732f4
AD
723
724 if (!HAS_GUC_UCODE(dev)) {
725 fw_path = NULL;
726 } else if (IS_SKYLAKE(dev)) {
727 fw_path = I915_SKL_GUC_UCODE;
5e334c19
TU
728 guc_fw->guc_fw_major_wanted = SKL_FW_MAJOR;
729 guc_fw->guc_fw_minor_wanted = SKL_FW_MINOR;
57bf5c81
NH
730 } else if (IS_BROXTON(dev)) {
731 fw_path = I915_BXT_GUC_UCODE;
5e334c19
TU
732 guc_fw->guc_fw_major_wanted = BXT_FW_MAJOR;
733 guc_fw->guc_fw_minor_wanted = BXT_FW_MINOR;
ff64cc16
PA
734 } else if (IS_KABYLAKE(dev)) {
735 fw_path = I915_KBL_GUC_UCODE;
5e334c19
TU
736 guc_fw->guc_fw_major_wanted = KBL_FW_MAJOR;
737 guc_fw->guc_fw_minor_wanted = KBL_FW_MINOR;
33a732f4 738 } else {
33a732f4
AD
739 fw_path = ""; /* unknown device */
740 }
741
742 guc_fw->guc_dev = dev;
743 guc_fw->guc_fw_path = fw_path;
744 guc_fw->guc_fw_fetch_status = GUC_FIRMWARE_NONE;
745 guc_fw->guc_fw_load_status = GUC_FIRMWARE_NONE;
746
fce91f22
DG
747 /* Early (and silent) return if GuC loading is disabled */
748 if (!i915.enable_guc_loading)
749 return;
33a732f4
AD
750 if (fw_path == NULL)
751 return;
fce91f22 752 if (*fw_path == '\0')
33a732f4 753 return;
33a732f4
AD
754
755 guc_fw->guc_fw_fetch_status = GUC_FIRMWARE_PENDING;
756 DRM_DEBUG_DRIVER("GuC firmware pending, path %s\n", fw_path);
757 guc_fw_fetch(dev, guc_fw);
758 /* status must now be FAIL or SUCCESS */
759}
760
761/**
f09d675f 762 * intel_guc_fini() - clean up all allocated resources
33a732f4
AD
763 * @dev: drm device
764 */
f09d675f 765void intel_guc_fini(struct drm_device *dev)
33a732f4 766{
fac5e23e 767 struct drm_i915_private *dev_priv = to_i915(dev);
33a732f4
AD
768 struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;
769
a9d8adad 770 mutex_lock(&dev->struct_mutex);
4df001d3 771 direct_interrupts_to_host(dev_priv);
beffa517
DG
772 i915_guc_submission_disable(dev_priv);
773 i915_guc_submission_fini(dev_priv);
bac427f8 774
33a732f4 775 if (guc_fw->guc_fw_obj)
f8c417cd 776 i915_gem_object_put(guc_fw->guc_fw_obj);
33a732f4 777 guc_fw->guc_fw_obj = NULL;
bf248ca1 778 mutex_unlock(&dev->struct_mutex);
33a732f4
AD
779
780 guc_fw->guc_fw_fetch_status = GUC_FIRMWARE_NONE;
781}