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33a732f4 AD |
1 | /* |
2 | * Copyright © 2014 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Vinit Azad <vinit.azad@intel.com> | |
25 | * Ben Widawsky <ben@bwidawsk.net> | |
26 | * Dave Gordon <david.s.gordon@intel.com> | |
27 | * Alex Dai <yu.dai@intel.com> | |
28 | */ | |
29 | #include <linux/firmware.h> | |
30 | #include "i915_drv.h" | |
31 | #include "intel_guc.h" | |
32 | ||
33 | /** | |
feda33ef | 34 | * DOC: GuC-specific firmware loader |
33a732f4 AD |
35 | * |
36 | * intel_guc: | |
37 | * Top level structure of guc. It handles firmware loading and manages client | |
38 | * pool and doorbells. intel_guc owns a i915_guc_client to replace the legacy | |
39 | * ExecList submission. | |
40 | * | |
41 | * Firmware versioning: | |
42 | * The firmware build process will generate a version header file with major and | |
43 | * minor version defined. The versions are built into CSS header of firmware. | |
44 | * i915 kernel driver set the minimal firmware version required per platform. | |
45 | * The firmware installation package will install (symbolic link) proper version | |
46 | * of firmware. | |
47 | * | |
48 | * GuC address space: | |
49 | * GuC does not allow any gfx GGTT address that falls into range [0, WOPCM_TOP), | |
50 | * which is reserved for Boot ROM, SRAM and WOPCM. Currently this top address is | |
51 | * 512K. In order to exclude 0-512K address space from GGTT, all gfx objects | |
52 | * used by GuC is pinned with PIN_OFFSET_BIAS along with size of WOPCM. | |
53 | * | |
54 | * Firmware log: | |
55 | * Firmware log is enabled by setting i915.guc_log_level to non-negative level. | |
56 | * Log data is printed out via reading debugfs i915_guc_log_dump. Reading from | |
57 | * i915_guc_load_status will print out firmware loading status and scratch | |
58 | * registers value. | |
59 | * | |
60 | */ | |
61 | ||
5e334c19 TU |
62 | #define SKL_FW_MAJOR 6 |
63 | #define SKL_FW_MINOR 1 | |
64 | ||
65 | #define BXT_FW_MAJOR 8 | |
66 | #define BXT_FW_MINOR 7 | |
67 | ||
68 | #define KBL_FW_MAJOR 9 | |
69 | #define KBL_FW_MINOR 14 | |
70 | ||
71 | #define GUC_FW_PATH(platform, major, minor) \ | |
72 | "i915/" __stringify(platform) "_guc_ver" __stringify(major) "_" __stringify(minor) ".bin" | |
73 | ||
74 | #define I915_SKL_GUC_UCODE GUC_FW_PATH(skl, SKL_FW_MAJOR, SKL_FW_MINOR) | |
33a732f4 AD |
75 | MODULE_FIRMWARE(I915_SKL_GUC_UCODE); |
76 | ||
5e334c19 | 77 | #define I915_BXT_GUC_UCODE GUC_FW_PATH(bxt, BXT_FW_MAJOR, BXT_FW_MINOR) |
57bf5c81 NH |
78 | MODULE_FIRMWARE(I915_BXT_GUC_UCODE); |
79 | ||
5e334c19 | 80 | #define I915_KBL_GUC_UCODE GUC_FW_PATH(kbl, KBL_FW_MAJOR, KBL_FW_MINOR) |
ff64cc16 PA |
81 | MODULE_FIRMWARE(I915_KBL_GUC_UCODE); |
82 | ||
33a732f4 AD |
83 | /* User-friendly representation of an enum */ |
84 | const char *intel_guc_fw_status_repr(enum intel_guc_fw_status status) | |
85 | { | |
86 | switch (status) { | |
87 | case GUC_FIRMWARE_FAIL: | |
88 | return "FAIL"; | |
89 | case GUC_FIRMWARE_NONE: | |
90 | return "NONE"; | |
91 | case GUC_FIRMWARE_PENDING: | |
92 | return "PENDING"; | |
93 | case GUC_FIRMWARE_SUCCESS: | |
94 | return "SUCCESS"; | |
95 | default: | |
96 | return "UNKNOWN!"; | |
97 | } | |
98 | }; | |
99 | ||
0c5664e4 | 100 | static void guc_interrupts_release(struct drm_i915_private *dev_priv) |
4df001d3 | 101 | { |
e2f80391 | 102 | struct intel_engine_cs *engine; |
3b3f1650 | 103 | enum intel_engine_id id; |
b4ac5afc | 104 | int irqs; |
4df001d3 | 105 | |
fa7545a4 | 106 | /* tell all command streamers NOT to forward interrupts or vblank to GuC */ |
4df001d3 DG |
107 | irqs = _MASKED_FIELD(GFX_FORWARD_VBLANK_MASK, GFX_FORWARD_VBLANK_NEVER); |
108 | irqs |= _MASKED_BIT_DISABLE(GFX_INTERRUPT_STEERING); | |
3b3f1650 | 109 | for_each_engine(engine, dev_priv, id) |
e2f80391 | 110 | I915_WRITE(RING_MODE_GEN7(engine), irqs); |
4df001d3 | 111 | |
4df001d3 DG |
112 | /* route all GT interrupts to the host */ |
113 | I915_WRITE(GUC_BCS_RCS_IER, 0); | |
114 | I915_WRITE(GUC_VCS2_VCS1_IER, 0); | |
115 | I915_WRITE(GUC_WD_VECS_IER, 0); | |
116 | } | |
117 | ||
0c5664e4 | 118 | static void guc_interrupts_capture(struct drm_i915_private *dev_priv) |
4df001d3 | 119 | { |
e2f80391 | 120 | struct intel_engine_cs *engine; |
3b3f1650 | 121 | enum intel_engine_id id; |
b4ac5afc | 122 | int irqs; |
1800ad25 | 123 | u32 tmp; |
4df001d3 | 124 | |
fa7545a4 DG |
125 | /* tell all command streamers to forward interrupts (but not vblank) to GuC */ |
126 | irqs = _MASKED_BIT_ENABLE(GFX_INTERRUPT_STEERING); | |
3b3f1650 | 127 | for_each_engine(engine, dev_priv, id) |
e2f80391 | 128 | I915_WRITE(RING_MODE_GEN7(engine), irqs); |
4df001d3 | 129 | |
4df001d3 DG |
130 | /* route USER_INTERRUPT to Host, all others are sent to GuC. */ |
131 | irqs = GT_RENDER_USER_INTERRUPT << GEN8_RCS_IRQ_SHIFT | | |
132 | GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT; | |
133 | /* These three registers have the same bit definitions */ | |
134 | I915_WRITE(GUC_BCS_RCS_IER, ~irqs); | |
135 | I915_WRITE(GUC_VCS2_VCS1_IER, ~irqs); | |
136 | I915_WRITE(GUC_WD_VECS_IER, ~irqs); | |
1800ad25 SAK |
137 | |
138 | /* | |
b20e3cfe DG |
139 | * The REDIRECT_TO_GUC bit of the PMINTRMSK register directs all |
140 | * (unmasked) PM interrupts to the GuC. All other bits of this | |
141 | * register *disable* generation of a specific interrupt. | |
142 | * | |
143 | * 'pm_intr_keep' indicates bits that are NOT to be set when | |
144 | * writing to the PM interrupt mask register, i.e. interrupts | |
145 | * that must not be disabled. | |
146 | * | |
147 | * If the GuC is handling these interrupts, then we must not let | |
148 | * the PM code disable ANY interrupt that the GuC is expecting. | |
149 | * So for each ENABLED (0) bit in this register, we must SET the | |
150 | * bit in pm_intr_keep so that it's left enabled for the GuC. | |
151 | * | |
152 | * OTOH the REDIRECT_TO_GUC bit is initially SET in pm_intr_keep | |
153 | * (so interrupts go to the DISPLAY unit at first); but here we | |
154 | * need to CLEAR that bit, which will result in the register bit | |
155 | * being left SET! | |
156 | */ | |
1800ad25 | 157 | tmp = I915_READ(GEN6_PMINTRMSK); |
b20e3cfe DG |
158 | if (tmp & GEN8_PMINTR_REDIRECT_TO_GUC) { |
159 | dev_priv->rps.pm_intr_keep |= ~tmp; | |
160 | dev_priv->rps.pm_intr_keep &= ~GEN8_PMINTR_REDIRECT_TO_GUC; | |
1800ad25 | 161 | } |
4df001d3 DG |
162 | } |
163 | ||
33a732f4 AD |
164 | static u32 get_gttype(struct drm_i915_private *dev_priv) |
165 | { | |
166 | /* XXX: GT type based on PCI device ID? field seems unused by fw */ | |
167 | return 0; | |
168 | } | |
169 | ||
170 | static u32 get_core_family(struct drm_i915_private *dev_priv) | |
171 | { | |
fc32de93 DG |
172 | u32 gen = INTEL_GEN(dev_priv); |
173 | ||
174 | switch (gen) { | |
33a732f4 AD |
175 | case 9: |
176 | return GFXCORE_FAMILY_GEN9; | |
177 | ||
178 | default: | |
fc32de93 | 179 | WARN(1, "GEN%d does not support GuC operation!\n", gen); |
33a732f4 AD |
180 | return GFXCORE_FAMILY_UNKNOWN; |
181 | } | |
182 | } | |
183 | ||
0c5664e4 DG |
184 | /* |
185 | * Initialise the GuC parameter block before starting the firmware | |
186 | * transfer. These parameters are read by the firmware on startup | |
187 | * and cannot be changed thereafter. | |
188 | */ | |
189 | static void guc_params_init(struct drm_i915_private *dev_priv) | |
33a732f4 AD |
190 | { |
191 | struct intel_guc *guc = &dev_priv->guc; | |
192 | u32 params[GUC_CTL_MAX_DWORDS]; | |
193 | int i; | |
194 | ||
195 | memset(¶ms, 0, sizeof(params)); | |
196 | ||
197 | params[GUC_CTL_DEVICE_INFO] |= | |
198 | (get_gttype(dev_priv) << GUC_CTL_GTTYPE_SHIFT) | | |
199 | (get_core_family(dev_priv) << GUC_CTL_COREFAMILY_SHIFT); | |
200 | ||
201 | /* | |
202 | * GuC ARAT increment is 10 ns. GuC default scheduler quantum is one | |
203 | * second. This ARAR is calculated by: | |
204 | * Scheduler-Quantum-in-ns / ARAT-increment-in-ns = 1000000000 / 10 | |
205 | */ | |
206 | params[GUC_CTL_ARAT_HIGH] = 0; | |
207 | params[GUC_CTL_ARAT_LOW] = 100000000; | |
208 | ||
209 | params[GUC_CTL_WA] |= GUC_CTL_WA_UK_BY_DRIVER; | |
210 | ||
211 | params[GUC_CTL_FEATURE] |= GUC_CTL_DISABLE_SCHEDULER | | |
212 | GUC_CTL_VCS2_ENABLED; | |
213 | ||
d6b40b4b | 214 | params[GUC_CTL_LOG_PARAMS] = guc->log.flags; |
b1e37103 | 215 | |
33a732f4 | 216 | if (i915.guc_log_level >= 0) { |
33a732f4 AD |
217 | params[GUC_CTL_DEBUG] = |
218 | i915.guc_log_level << GUC_LOG_VERBOSITY_SHIFT; | |
b1e37103 SAK |
219 | } else |
220 | params[GUC_CTL_DEBUG] = GUC_LOG_DISABLED; | |
33a732f4 | 221 | |
8b797af1 | 222 | if (guc->ads_vma) { |
bde13ebd | 223 | u32 ads = i915_ggtt_offset(guc->ads_vma) >> PAGE_SHIFT; |
b6a5cd7e AD |
224 | params[GUC_CTL_DEBUG] |= ads << GUC_ADS_ADDR_SHIFT; |
225 | params[GUC_CTL_DEBUG] |= GUC_ADS_ENABLED; | |
226 | } | |
227 | ||
bac427f8 AD |
228 | /* If GuC submission is enabled, set up additional parameters here */ |
229 | if (i915.enable_guc_submission) { | |
bde13ebd | 230 | u32 pgs = i915_ggtt_offset(dev_priv->guc.ctx_pool_vma); |
bac427f8 AD |
231 | u32 ctx_in_16 = GUC_MAX_GPU_CONTEXTS / 16; |
232 | ||
233 | pgs >>= PAGE_SHIFT; | |
234 | params[GUC_CTL_CTXINFO] = (pgs << GUC_CTL_BASE_ADDR_SHIFT) | | |
235 | (ctx_in_16 << GUC_CTL_CTXNUM_IN16_SHIFT); | |
236 | ||
237 | params[GUC_CTL_FEATURE] |= GUC_CTL_KERNEL_SUBMISSIONS; | |
238 | ||
239 | /* Unmask this bit to enable the GuC's internal scheduler */ | |
240 | params[GUC_CTL_FEATURE] &= ~GUC_CTL_DISABLE_SCHEDULER; | |
241 | } | |
242 | ||
33a732f4 AD |
243 | I915_WRITE(SOFT_SCRATCH(0), 0); |
244 | ||
245 | for (i = 0; i < GUC_CTL_MAX_DWORDS; i++) | |
246 | I915_WRITE(SOFT_SCRATCH(1 + i), params[i]); | |
247 | } | |
248 | ||
249 | /* | |
250 | * Read the GuC status register (GUC_STATUS) and store it in the | |
251 | * specified location; then return a boolean indicating whether | |
252 | * the value matches either of two values representing completion | |
253 | * of the GuC boot process. | |
254 | * | |
36894e8b | 255 | * This is used for polling the GuC status in a wait_for() |
33a732f4 AD |
256 | * loop below. |
257 | */ | |
258 | static inline bool guc_ucode_response(struct drm_i915_private *dev_priv, | |
259 | u32 *status) | |
260 | { | |
261 | u32 val = I915_READ(GUC_STATUS); | |
0d44d3fa | 262 | u32 uk_val = val & GS_UKERNEL_MASK; |
33a732f4 | 263 | *status = val; |
0d44d3fa AD |
264 | return (uk_val == GS_UKERNEL_READY || |
265 | ((val & GS_MIA_CORE_STATE) && uk_val == GS_UKERNEL_LAPIC_DONE)); | |
33a732f4 AD |
266 | } |
267 | ||
268 | /* | |
269 | * Transfer the firmware image to RAM for execution by the microcontroller. | |
270 | * | |
33a732f4 AD |
271 | * Architecturally, the DMA engine is bidirectional, and can potentially even |
272 | * transfer between GTT locations. This functionality is left out of the API | |
273 | * for now as there is no need for it. | |
274 | * | |
275 | * Note that GuC needs the CSS header plus uKernel code to be copied by the | |
276 | * DMA engine in one operation, whereas the RSA signature is loaded via MMIO. | |
277 | */ | |
058d88c4 CW |
278 | static int guc_ucode_xfer_dma(struct drm_i915_private *dev_priv, |
279 | struct i915_vma *vma) | |
33a732f4 AD |
280 | { |
281 | struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw; | |
33a732f4 | 282 | unsigned long offset; |
058d88c4 | 283 | struct sg_table *sg = vma->pages; |
feda33ef | 284 | u32 status, rsa[UOS_RSA_SCRATCH_MAX_COUNT]; |
33a732f4 AD |
285 | int i, ret = 0; |
286 | ||
feda33ef AD |
287 | /* where RSA signature starts */ |
288 | offset = guc_fw->rsa_offset; | |
33a732f4 AD |
289 | |
290 | /* Copy RSA signature from the fw image to HW for verification */ | |
feda33ef AD |
291 | sg_pcopy_to_buffer(sg->sgl, sg->nents, rsa, sizeof(rsa), offset); |
292 | for (i = 0; i < UOS_RSA_SCRATCH_MAX_COUNT; i++) | |
ab9cc558 | 293 | I915_WRITE(UOS_RSA_SCRATCH(i), rsa[i]); |
33a732f4 | 294 | |
feda33ef AD |
295 | /* The header plus uCode will be copied to WOPCM via DMA, excluding any |
296 | * other components */ | |
297 | I915_WRITE(DMA_COPY_SIZE, guc_fw->header_size + guc_fw->ucode_size); | |
298 | ||
33a732f4 | 299 | /* Set the source address for the new blob */ |
bde13ebd | 300 | offset = i915_ggtt_offset(vma) + guc_fw->header_offset; |
33a732f4 AD |
301 | I915_WRITE(DMA_ADDR_0_LOW, lower_32_bits(offset)); |
302 | I915_WRITE(DMA_ADDR_0_HIGH, upper_32_bits(offset) & 0xFFFF); | |
303 | ||
304 | /* | |
305 | * Set the DMA destination. Current uCode expects the code to be | |
306 | * loaded at 8k; locations below this are used for the stack. | |
307 | */ | |
308 | I915_WRITE(DMA_ADDR_1_LOW, 0x2000); | |
309 | I915_WRITE(DMA_ADDR_1_HIGH, DMA_ADDRESS_SPACE_WOPCM); | |
310 | ||
311 | /* Finally start the DMA */ | |
312 | I915_WRITE(DMA_CTRL, _MASKED_BIT_ENABLE(UOS_MOVE | START_DMA)); | |
313 | ||
314 | /* | |
36894e8b | 315 | * Wait for the DMA to complete & the GuC to start up. |
33a732f4 AD |
316 | * NB: Docs recommend not using the interrupt for completion. |
317 | * Measurements indicate this should take no more than 20ms, so a | |
318 | * timeout here indicates that the GuC has failed and is unusable. | |
319 | * (Higher levels of the driver will attempt to fall back to | |
320 | * execlist mode if this happens.) | |
321 | */ | |
36894e8b | 322 | ret = wait_for(guc_ucode_response(dev_priv, &status), 100); |
33a732f4 AD |
323 | |
324 | DRM_DEBUG_DRIVER("DMA status 0x%x, GuC status 0x%x\n", | |
325 | I915_READ(DMA_CTRL), status); | |
326 | ||
327 | if ((status & GS_BOOTROM_MASK) == GS_BOOTROM_RSA_FAILED) { | |
328 | DRM_ERROR("GuC firmware signature verification failed\n"); | |
329 | ret = -ENOEXEC; | |
330 | } | |
331 | ||
332 | DRM_DEBUG_DRIVER("returning %d\n", ret); | |
333 | ||
334 | return ret; | |
335 | } | |
336 | ||
74aa156b PA |
337 | static u32 guc_wopcm_size(struct drm_i915_private *dev_priv) |
338 | { | |
339 | u32 wopcm_size = GUC_WOPCM_TOP; | |
340 | ||
341 | /* On BXT, the top of WOPCM is reserved for RC6 context */ | |
342 | if (IS_BROXTON(dev_priv)) | |
343 | wopcm_size -= BXT_GUC_WOPCM_RC6_RESERVED; | |
344 | ||
345 | return wopcm_size; | |
346 | } | |
347 | ||
33a732f4 AD |
348 | /* |
349 | * Load the GuC firmware blob into the MinuteIA. | |
350 | */ | |
351 | static int guc_ucode_xfer(struct drm_i915_private *dev_priv) | |
352 | { | |
353 | struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw; | |
058d88c4 | 354 | struct i915_vma *vma; |
33a732f4 AD |
355 | int ret; |
356 | ||
357 | ret = i915_gem_object_set_to_gtt_domain(guc_fw->guc_fw_obj, false); | |
358 | if (ret) { | |
359 | DRM_DEBUG_DRIVER("set-domain failed %d\n", ret); | |
360 | return ret; | |
361 | } | |
362 | ||
058d88c4 CW |
363 | vma = i915_gem_object_ggtt_pin(guc_fw->guc_fw_obj, NULL, 0, 0, 0); |
364 | if (IS_ERR(vma)) { | |
365 | DRM_DEBUG_DRIVER("pin failed %d\n", (int)PTR_ERR(vma)); | |
366 | return PTR_ERR(vma); | |
33a732f4 AD |
367 | } |
368 | ||
369 | /* Invalidate GuC TLB to let GuC take the latest updates to GTT. */ | |
370 | I915_WRITE(GEN8_GTCR, GEN8_GTCR_INVALIDATE); | |
371 | ||
372 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); | |
373 | ||
374 | /* init WOPCM */ | |
74aa156b | 375 | I915_WRITE(GUC_WOPCM_SIZE, guc_wopcm_size(dev_priv)); |
33a732f4 AD |
376 | I915_WRITE(DMA_GUC_WOPCM_OFFSET, GUC_WOPCM_OFFSET_VALUE); |
377 | ||
378 | /* Enable MIA caching. GuC clock gating is disabled. */ | |
379 | I915_WRITE(GUC_SHIM_CONTROL, GUC_SHIM_CONTROL_VALUE); | |
380 | ||
a117f378 | 381 | /* WaDisableMinuteIaClockGating:bxt */ |
e2d214ae | 382 | if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) { |
b970b486 NH |
383 | I915_WRITE(GUC_SHIM_CONTROL, (I915_READ(GUC_SHIM_CONTROL) & |
384 | ~GUC_ENABLE_MIA_CLOCK_GATING)); | |
385 | } | |
386 | ||
4ff40a41 | 387 | /* WaC6DisallowByGfxPause:bxt */ |
e2d214ae | 388 | if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_B0)) |
65fe29ee | 389 | I915_WRITE(GEN6_GFXPAUSE, 0x30FFF); |
33a732f4 | 390 | |
e2d214ae | 391 | if (IS_BROXTON(dev_priv)) |
33a732f4 AD |
392 | I915_WRITE(GEN9LP_GT_PM_CONFIG, GT_DOORBELL_ENABLE); |
393 | else | |
394 | I915_WRITE(GEN9_GT_PM_CONFIG, GT_DOORBELL_ENABLE); | |
395 | ||
5db94019 | 396 | if (IS_GEN9(dev_priv)) { |
33a732f4 AD |
397 | /* DOP Clock Gating Enable for GuC clocks */ |
398 | I915_WRITE(GEN7_MISCCPCTL, (GEN8_DOP_CLOCK_GATE_GUC_ENABLE | | |
399 | I915_READ(GEN7_MISCCPCTL))); | |
400 | ||
0c5664e4 | 401 | /* allows for 5us (in 10ns units) before GT can go to RC6 */ |
33a732f4 AD |
402 | I915_WRITE(GUC_ARAT_C6DIS, 0x1FF); |
403 | } | |
404 | ||
0c5664e4 | 405 | guc_params_init(dev_priv); |
33a732f4 | 406 | |
058d88c4 | 407 | ret = guc_ucode_xfer_dma(dev_priv, vma); |
33a732f4 AD |
408 | |
409 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); | |
410 | ||
411 | /* | |
412 | * We keep the object pages for reuse during resume. But we can unpin it | |
413 | * now that DMA has completed, so it doesn't continue to take up space. | |
414 | */ | |
058d88c4 | 415 | i915_vma_unpin(vma); |
33a732f4 AD |
416 | |
417 | return ret; | |
418 | } | |
419 | ||
0c5664e4 | 420 | static int guc_hw_reset(struct drm_i915_private *dev_priv) |
6b332fa2 AS |
421 | { |
422 | int ret; | |
423 | u32 guc_status; | |
424 | ||
425 | ret = intel_guc_reset(dev_priv); | |
426 | if (ret) { | |
427 | DRM_ERROR("GuC reset failed, ret = %d\n", ret); | |
428 | return ret; | |
429 | } | |
430 | ||
431 | guc_status = I915_READ(GUC_STATUS); | |
432 | WARN(!(guc_status & GS_MIA_IN_RESET), | |
433 | "GuC status: 0x%x, MIA core expected to be in reset\n", guc_status); | |
434 | ||
435 | return ret; | |
436 | } | |
437 | ||
33a732f4 | 438 | /** |
f09d675f | 439 | * intel_guc_setup() - finish preparing the GuC for activity |
33a732f4 AD |
440 | * @dev: drm device |
441 | * | |
442 | * Called from gem_init_hw() during driver loading and also after a GPU reset. | |
443 | * | |
f09d675f | 444 | * The main action required here it to load the GuC uCode into the device. |
33a732f4 | 445 | * The firmware image should have already been fetched into memory by the |
f09d675f DG |
446 | * earlier call to intel_guc_init(), so here we need only check that worked, |
447 | * and then transfer the image to the h/w. | |
33a732f4 AD |
448 | * |
449 | * Return: non-zero code on error | |
450 | */ | |
f09d675f | 451 | int intel_guc_setup(struct drm_device *dev) |
33a732f4 | 452 | { |
fac5e23e | 453 | struct drm_i915_private *dev_priv = to_i915(dev); |
33a732f4 | 454 | struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw; |
fce91f22 DG |
455 | const char *fw_path = guc_fw->guc_fw_path; |
456 | int retries, ret, err; | |
33a732f4 | 457 | |
fce91f22 DG |
458 | DRM_DEBUG_DRIVER("GuC fw status: path %s, fetch %s, load %s\n", |
459 | fw_path, | |
33a732f4 AD |
460 | intel_guc_fw_status_repr(guc_fw->guc_fw_fetch_status), |
461 | intel_guc_fw_status_repr(guc_fw->guc_fw_load_status)); | |
462 | ||
fce91f22 DG |
463 | /* Loading forbidden, or no firmware to load? */ |
464 | if (!i915.enable_guc_loading) { | |
465 | err = 0; | |
466 | goto fail; | |
e556f7c1 DG |
467 | } else if (fw_path == NULL) { |
468 | /* Device is known to have no uCode (e.g. no GuC) */ | |
469 | err = -ENXIO; | |
470 | goto fail; | |
471 | } else if (*fw_path == '\0') { | |
472 | /* Device has a GuC but we don't know what f/w to load? */ | |
fc32de93 | 473 | WARN(1, "No GuC firmware known for this platform!\n"); |
fce91f22 DG |
474 | err = -ENODEV; |
475 | goto fail; | |
476 | } | |
33a732f4 | 477 | |
fce91f22 DG |
478 | /* Fetch failed, or already fetched but failed to load? */ |
479 | if (guc_fw->guc_fw_fetch_status != GUC_FIRMWARE_SUCCESS) { | |
33a732f4 AD |
480 | err = -EIO; |
481 | goto fail; | |
fce91f22 DG |
482 | } else if (guc_fw->guc_fw_load_status == GUC_FIRMWARE_FAIL) { |
483 | err = -ENOEXEC; | |
33a732f4 | 484 | goto fail; |
33a732f4 AD |
485 | } |
486 | ||
0c5664e4 | 487 | guc_interrupts_release(dev_priv); |
fce91f22 DG |
488 | |
489 | guc_fw->guc_fw_load_status = GUC_FIRMWARE_PENDING; | |
490 | ||
491 | DRM_DEBUG_DRIVER("GuC fw status: fetch %s, load %s\n", | |
492 | intel_guc_fw_status_repr(guc_fw->guc_fw_fetch_status), | |
493 | intel_guc_fw_status_repr(guc_fw->guc_fw_load_status)); | |
494 | ||
beffa517 | 495 | err = i915_guc_submission_init(dev_priv); |
bac427f8 AD |
496 | if (err) |
497 | goto fail; | |
498 | ||
6b332fa2 AS |
499 | /* |
500 | * WaEnableuKernelHeaderValidFix:skl,bxt | |
501 | * For BXT, this is only upto B0 but below WA is required for later | |
502 | * steppings also so this is extended as well. | |
503 | */ | |
504 | /* WaEnableGuCBootHashCheckNotSet:skl,bxt */ | |
d761701c DG |
505 | for (retries = 3; ; ) { |
506 | /* | |
507 | * Always reset the GuC just before (re)loading, so | |
508 | * that the state and timing are fairly predictable | |
509 | */ | |
0c5664e4 | 510 | err = guc_hw_reset(dev_priv); |
fc32de93 | 511 | if (err) |
6b332fa2 | 512 | goto fail; |
d761701c DG |
513 | |
514 | err = guc_ucode_xfer(dev_priv); | |
515 | if (!err) | |
516 | break; | |
517 | ||
518 | if (--retries == 0) | |
519 | goto fail; | |
520 | ||
fce91f22 DG |
521 | DRM_INFO("GuC fw load failed: %d; will reset and " |
522 | "retry %d more time(s)\n", err, retries); | |
6b332fa2 | 523 | } |
33a732f4 AD |
524 | |
525 | guc_fw->guc_fw_load_status = GUC_FIRMWARE_SUCCESS; | |
526 | ||
527 | DRM_DEBUG_DRIVER("GuC fw status: fetch %s, load %s\n", | |
528 | intel_guc_fw_status_repr(guc_fw->guc_fw_fetch_status), | |
529 | intel_guc_fw_status_repr(guc_fw->guc_fw_load_status)); | |
530 | ||
44a28b1d | 531 | if (i915.enable_guc_submission) { |
beffa517 | 532 | err = i915_guc_submission_enable(dev_priv); |
44a28b1d DG |
533 | if (err) |
534 | goto fail; | |
0c5664e4 | 535 | guc_interrupts_capture(dev_priv); |
44a28b1d DG |
536 | } |
537 | ||
33a732f4 AD |
538 | return 0; |
539 | ||
540 | fail: | |
541 | if (guc_fw->guc_fw_load_status == GUC_FIRMWARE_PENDING) | |
542 | guc_fw->guc_fw_load_status = GUC_FIRMWARE_FAIL; | |
543 | ||
0c5664e4 | 544 | guc_interrupts_release(dev_priv); |
beffa517 DG |
545 | i915_guc_submission_disable(dev_priv); |
546 | i915_guc_submission_fini(dev_priv); | |
44a28b1d | 547 | |
fce91f22 DG |
548 | /* |
549 | * We've failed to load the firmware :( | |
550 | * | |
551 | * Decide whether to disable GuC submission and fall back to | |
552 | * execlist mode, and whether to hide the error by returning | |
553 | * zero or to return -EIO, which the caller will treat as a | |
554 | * nonfatal error (i.e. it doesn't prevent driver load, but | |
555 | * marks the GPU as wedged until reset). | |
556 | */ | |
557 | if (i915.enable_guc_loading > 1) { | |
558 | ret = -EIO; | |
559 | } else if (i915.enable_guc_submission > 1) { | |
560 | ret = -EIO; | |
561 | } else { | |
562 | ret = 0; | |
563 | } | |
564 | ||
4e50f796 DG |
565 | if (err == 0 && !HAS_GUC_UCODE(dev)) |
566 | ; /* Don't mention the GuC! */ | |
567 | else if (err == 0) | |
fce91f22 | 568 | DRM_INFO("GuC firmware load skipped\n"); |
4e50f796 | 569 | else if (ret != -EIO) |
fc32de93 | 570 | DRM_NOTE("GuC firmware load failed: %d\n", err); |
4e50f796 | 571 | else |
fc32de93 | 572 | DRM_WARN("GuC firmware load failed: %d\n", err); |
fce91f22 DG |
573 | |
574 | if (i915.enable_guc_submission) { | |
575 | if (fw_path == NULL) | |
576 | DRM_INFO("GuC submission without firmware not supported\n"); | |
577 | if (ret == 0) | |
fc32de93 | 578 | DRM_NOTE("Falling back from GuC submission to execlist mode\n"); |
fce91f22 DG |
579 | else |
580 | DRM_ERROR("GuC init failed: %d\n", ret); | |
581 | } | |
582 | i915.enable_guc_submission = 0; | |
583 | ||
584 | return ret; | |
33a732f4 AD |
585 | } |
586 | ||
587 | static void guc_fw_fetch(struct drm_device *dev, struct intel_guc_fw *guc_fw) | |
588 | { | |
52a05c30 | 589 | struct pci_dev *pdev = dev->pdev; |
33a732f4 AD |
590 | struct drm_i915_gem_object *obj; |
591 | const struct firmware *fw; | |
feda33ef AD |
592 | struct guc_css_header *css; |
593 | size_t size; | |
33a732f4 AD |
594 | int err; |
595 | ||
596 | DRM_DEBUG_DRIVER("before requesting firmware: GuC fw fetch status %s\n", | |
597 | intel_guc_fw_status_repr(guc_fw->guc_fw_fetch_status)); | |
598 | ||
52a05c30 | 599 | err = request_firmware(&fw, guc_fw->guc_fw_path, &pdev->dev); |
33a732f4 AD |
600 | if (err) |
601 | goto fail; | |
602 | if (!fw) | |
603 | goto fail; | |
604 | ||
605 | DRM_DEBUG_DRIVER("fetch GuC fw from %s succeeded, fw %p\n", | |
606 | guc_fw->guc_fw_path, fw); | |
33a732f4 | 607 | |
feda33ef AD |
608 | /* Check the size of the blob before examining buffer contents */ |
609 | if (fw->size < sizeof(struct guc_css_header)) { | |
fc32de93 | 610 | DRM_NOTE("Firmware header is missing\n"); |
33a732f4 | 611 | goto fail; |
feda33ef AD |
612 | } |
613 | ||
614 | css = (struct guc_css_header *)fw->data; | |
615 | ||
616 | /* Firmware bits always start from header */ | |
617 | guc_fw->header_offset = 0; | |
618 | guc_fw->header_size = (css->header_size_dw - css->modulus_size_dw - | |
619 | css->key_size_dw - css->exponent_size_dw) * sizeof(u32); | |
620 | ||
621 | if (guc_fw->header_size != sizeof(struct guc_css_header)) { | |
fc32de93 | 622 | DRM_NOTE("CSS header definition mismatch\n"); |
feda33ef AD |
623 | goto fail; |
624 | } | |
625 | ||
626 | /* then, uCode */ | |
627 | guc_fw->ucode_offset = guc_fw->header_offset + guc_fw->header_size; | |
628 | guc_fw->ucode_size = (css->size_dw - css->header_size_dw) * sizeof(u32); | |
629 | ||
630 | /* now RSA */ | |
631 | if (css->key_size_dw != UOS_RSA_SCRATCH_MAX_COUNT) { | |
fc32de93 | 632 | DRM_NOTE("RSA key size is bad\n"); |
feda33ef AD |
633 | goto fail; |
634 | } | |
635 | guc_fw->rsa_offset = guc_fw->ucode_offset + guc_fw->ucode_size; | |
636 | guc_fw->rsa_size = css->key_size_dw * sizeof(u32); | |
637 | ||
638 | /* At least, it should have header, uCode and RSA. Size of all three. */ | |
639 | size = guc_fw->header_size + guc_fw->ucode_size + guc_fw->rsa_size; | |
640 | if (fw->size < size) { | |
fc32de93 | 641 | DRM_NOTE("Missing firmware components\n"); |
feda33ef AD |
642 | goto fail; |
643 | } | |
644 | ||
645 | /* Header and uCode will be loaded to WOPCM. Size of the two. */ | |
646 | size = guc_fw->header_size + guc_fw->ucode_size; | |
f19ec8cb | 647 | if (size > guc_wopcm_size(to_i915(dev))) { |
fc32de93 | 648 | DRM_NOTE("Firmware is too large to fit in WOPCM\n"); |
feda33ef AD |
649 | goto fail; |
650 | } | |
33a732f4 AD |
651 | |
652 | /* | |
653 | * The GuC firmware image has the version number embedded at a well-known | |
654 | * offset within the firmware blob; note that major / minor version are | |
655 | * TWO bytes each (i.e. u16), although all pointers and offsets are defined | |
656 | * in terms of bytes (u8). | |
657 | */ | |
feda33ef AD |
658 | guc_fw->guc_fw_major_found = css->guc_sw_version >> 16; |
659 | guc_fw->guc_fw_minor_found = css->guc_sw_version & 0xFFFF; | |
33a732f4 AD |
660 | |
661 | if (guc_fw->guc_fw_major_found != guc_fw->guc_fw_major_wanted || | |
662 | guc_fw->guc_fw_minor_found < guc_fw->guc_fw_minor_wanted) { | |
fc32de93 | 663 | DRM_NOTE("GuC firmware version %d.%d, required %d.%d\n", |
33a732f4 AD |
664 | guc_fw->guc_fw_major_found, guc_fw->guc_fw_minor_found, |
665 | guc_fw->guc_fw_major_wanted, guc_fw->guc_fw_minor_wanted); | |
666 | err = -ENOEXEC; | |
667 | goto fail; | |
668 | } | |
669 | ||
670 | DRM_DEBUG_DRIVER("firmware version %d.%d OK (minimum %d.%d)\n", | |
671 | guc_fw->guc_fw_major_found, guc_fw->guc_fw_minor_found, | |
672 | guc_fw->guc_fw_major_wanted, guc_fw->guc_fw_minor_wanted); | |
673 | ||
bf248ca1 | 674 | mutex_lock(&dev->struct_mutex); |
33a732f4 | 675 | obj = i915_gem_object_create_from_data(dev, fw->data, fw->size); |
bf248ca1 | 676 | mutex_unlock(&dev->struct_mutex); |
33a732f4 AD |
677 | if (IS_ERR_OR_NULL(obj)) { |
678 | err = obj ? PTR_ERR(obj) : -ENOMEM; | |
679 | goto fail; | |
680 | } | |
681 | ||
682 | guc_fw->guc_fw_obj = obj; | |
683 | guc_fw->guc_fw_size = fw->size; | |
684 | ||
685 | DRM_DEBUG_DRIVER("GuC fw fetch status SUCCESS, obj %p\n", | |
686 | guc_fw->guc_fw_obj); | |
687 | ||
688 | release_firmware(fw); | |
689 | guc_fw->guc_fw_fetch_status = GUC_FIRMWARE_SUCCESS; | |
690 | return; | |
691 | ||
692 | fail: | |
fc32de93 DG |
693 | DRM_WARN("Failed to fetch valid GuC firmware from %s (error %d)\n", |
694 | guc_fw->guc_fw_path, err); | |
33a732f4 AD |
695 | DRM_DEBUG_DRIVER("GuC fw fetch status FAIL; err %d, fw %p, obj %p\n", |
696 | err, fw, guc_fw->guc_fw_obj); | |
33a732f4 | 697 | |
a9d8adad | 698 | mutex_lock(&dev->struct_mutex); |
33a732f4 AD |
699 | obj = guc_fw->guc_fw_obj; |
700 | if (obj) | |
f8c417cd | 701 | i915_gem_object_put(obj); |
33a732f4 | 702 | guc_fw->guc_fw_obj = NULL; |
a9d8adad | 703 | mutex_unlock(&dev->struct_mutex); |
33a732f4 AD |
704 | |
705 | release_firmware(fw); /* OK even if fw is NULL */ | |
706 | guc_fw->guc_fw_fetch_status = GUC_FIRMWARE_FAIL; | |
707 | } | |
708 | ||
709 | /** | |
f09d675f | 710 | * intel_guc_init() - define parameters and fetch firmware |
33a732f4 AD |
711 | * @dev: drm device |
712 | * | |
713 | * Called early during driver load, but after GEM is initialised. | |
33a732f4 AD |
714 | * |
715 | * The firmware will be transferred to the GuC's memory later, | |
f09d675f | 716 | * when intel_guc_setup() is called. |
33a732f4 | 717 | */ |
f09d675f | 718 | void intel_guc_init(struct drm_device *dev) |
33a732f4 | 719 | { |
fac5e23e | 720 | struct drm_i915_private *dev_priv = to_i915(dev); |
33a732f4 AD |
721 | struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw; |
722 | const char *fw_path; | |
723 | ||
21e33021 AS |
724 | if (!HAS_GUC(dev)) { |
725 | i915.enable_guc_loading = 0; | |
726 | i915.enable_guc_submission = 0; | |
727 | } else { | |
728 | /* A negative value means "use platform default" */ | |
729 | if (i915.enable_guc_loading < 0) | |
730 | i915.enable_guc_loading = HAS_GUC_UCODE(dev); | |
731 | if (i915.enable_guc_submission < 0) | |
732 | i915.enable_guc_submission = HAS_GUC_SCHED(dev); | |
733 | } | |
33a732f4 AD |
734 | |
735 | if (!HAS_GUC_UCODE(dev)) { | |
736 | fw_path = NULL; | |
d9486e65 | 737 | } else if (IS_SKYLAKE(dev_priv)) { |
33a732f4 | 738 | fw_path = I915_SKL_GUC_UCODE; |
5e334c19 TU |
739 | guc_fw->guc_fw_major_wanted = SKL_FW_MAJOR; |
740 | guc_fw->guc_fw_minor_wanted = SKL_FW_MINOR; | |
e2d214ae | 741 | } else if (IS_BROXTON(dev_priv)) { |
57bf5c81 | 742 | fw_path = I915_BXT_GUC_UCODE; |
5e334c19 TU |
743 | guc_fw->guc_fw_major_wanted = BXT_FW_MAJOR; |
744 | guc_fw->guc_fw_minor_wanted = BXT_FW_MINOR; | |
0853723b | 745 | } else if (IS_KABYLAKE(dev_priv)) { |
ff64cc16 | 746 | fw_path = I915_KBL_GUC_UCODE; |
5e334c19 TU |
747 | guc_fw->guc_fw_major_wanted = KBL_FW_MAJOR; |
748 | guc_fw->guc_fw_minor_wanted = KBL_FW_MINOR; | |
33a732f4 | 749 | } else { |
33a732f4 AD |
750 | fw_path = ""; /* unknown device */ |
751 | } | |
752 | ||
753 | guc_fw->guc_dev = dev; | |
754 | guc_fw->guc_fw_path = fw_path; | |
755 | guc_fw->guc_fw_fetch_status = GUC_FIRMWARE_NONE; | |
756 | guc_fw->guc_fw_load_status = GUC_FIRMWARE_NONE; | |
757 | ||
fce91f22 DG |
758 | /* Early (and silent) return if GuC loading is disabled */ |
759 | if (!i915.enable_guc_loading) | |
760 | return; | |
33a732f4 AD |
761 | if (fw_path == NULL) |
762 | return; | |
fce91f22 | 763 | if (*fw_path == '\0') |
33a732f4 | 764 | return; |
33a732f4 AD |
765 | |
766 | guc_fw->guc_fw_fetch_status = GUC_FIRMWARE_PENDING; | |
767 | DRM_DEBUG_DRIVER("GuC firmware pending, path %s\n", fw_path); | |
768 | guc_fw_fetch(dev, guc_fw); | |
769 | /* status must now be FAIL or SUCCESS */ | |
770 | } | |
771 | ||
772 | /** | |
f09d675f | 773 | * intel_guc_fini() - clean up all allocated resources |
33a732f4 AD |
774 | * @dev: drm device |
775 | */ | |
f09d675f | 776 | void intel_guc_fini(struct drm_device *dev) |
33a732f4 | 777 | { |
fac5e23e | 778 | struct drm_i915_private *dev_priv = to_i915(dev); |
33a732f4 AD |
779 | struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw; |
780 | ||
a9d8adad | 781 | mutex_lock(&dev->struct_mutex); |
0c5664e4 | 782 | guc_interrupts_release(dev_priv); |
beffa517 DG |
783 | i915_guc_submission_disable(dev_priv); |
784 | i915_guc_submission_fini(dev_priv); | |
bac427f8 | 785 | |
33a732f4 | 786 | if (guc_fw->guc_fw_obj) |
f8c417cd | 787 | i915_gem_object_put(guc_fw->guc_fw_obj); |
33a732f4 | 788 | guc_fw->guc_fw_obj = NULL; |
bf248ca1 | 789 | mutex_unlock(&dev->struct_mutex); |
33a732f4 AD |
790 | |
791 | guc_fw->guc_fw_fetch_status = GUC_FIRMWARE_NONE; | |
792 | } |