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33a732f4 AD |
1 | /* |
2 | * Copyright © 2014 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Vinit Azad <vinit.azad@intel.com> | |
25 | * Ben Widawsky <ben@bwidawsk.net> | |
26 | * Dave Gordon <david.s.gordon@intel.com> | |
27 | * Alex Dai <yu.dai@intel.com> | |
28 | */ | |
29 | #include <linux/firmware.h> | |
30 | #include "i915_drv.h" | |
8c4f24f9 | 31 | #include "intel_uc.h" |
33a732f4 AD |
32 | |
33 | /** | |
feda33ef | 34 | * DOC: GuC-specific firmware loader |
33a732f4 AD |
35 | * |
36 | * intel_guc: | |
37 | * Top level structure of guc. It handles firmware loading and manages client | |
38 | * pool and doorbells. intel_guc owns a i915_guc_client to replace the legacy | |
39 | * ExecList submission. | |
40 | * | |
41 | * Firmware versioning: | |
42 | * The firmware build process will generate a version header file with major and | |
43 | * minor version defined. The versions are built into CSS header of firmware. | |
44 | * i915 kernel driver set the minimal firmware version required per platform. | |
45 | * The firmware installation package will install (symbolic link) proper version | |
46 | * of firmware. | |
47 | * | |
48 | * GuC address space: | |
49 | * GuC does not allow any gfx GGTT address that falls into range [0, WOPCM_TOP), | |
50 | * which is reserved for Boot ROM, SRAM and WOPCM. Currently this top address is | |
51 | * 512K. In order to exclude 0-512K address space from GGTT, all gfx objects | |
52 | * used by GuC is pinned with PIN_OFFSET_BIAS along with size of WOPCM. | |
53 | * | |
33a732f4 AD |
54 | */ |
55 | ||
5e334c19 TU |
56 | #define SKL_FW_MAJOR 6 |
57 | #define SKL_FW_MINOR 1 | |
58 | ||
59 | #define BXT_FW_MAJOR 8 | |
60 | #define BXT_FW_MINOR 7 | |
61 | ||
62 | #define KBL_FW_MAJOR 9 | |
63 | #define KBL_FW_MINOR 14 | |
64 | ||
65 | #define GUC_FW_PATH(platform, major, minor) \ | |
66 | "i915/" __stringify(platform) "_guc_ver" __stringify(major) "_" __stringify(minor) ".bin" | |
67 | ||
68 | #define I915_SKL_GUC_UCODE GUC_FW_PATH(skl, SKL_FW_MAJOR, SKL_FW_MINOR) | |
33a732f4 AD |
69 | MODULE_FIRMWARE(I915_SKL_GUC_UCODE); |
70 | ||
5e334c19 | 71 | #define I915_BXT_GUC_UCODE GUC_FW_PATH(bxt, BXT_FW_MAJOR, BXT_FW_MINOR) |
57bf5c81 NH |
72 | MODULE_FIRMWARE(I915_BXT_GUC_UCODE); |
73 | ||
5e334c19 | 74 | #define I915_KBL_GUC_UCODE GUC_FW_PATH(kbl, KBL_FW_MAJOR, KBL_FW_MINOR) |
ff64cc16 PA |
75 | MODULE_FIRMWARE(I915_KBL_GUC_UCODE); |
76 | ||
33a732f4 | 77 | /* User-friendly representation of an enum */ |
db0a091b | 78 | const char *intel_uc_fw_status_repr(enum intel_uc_fw_status status) |
33a732f4 AD |
79 | { |
80 | switch (status) { | |
db0a091b | 81 | case INTEL_UC_FIRMWARE_FAIL: |
33a732f4 | 82 | return "FAIL"; |
db0a091b | 83 | case INTEL_UC_FIRMWARE_NONE: |
33a732f4 | 84 | return "NONE"; |
db0a091b | 85 | case INTEL_UC_FIRMWARE_PENDING: |
33a732f4 | 86 | return "PENDING"; |
db0a091b | 87 | case INTEL_UC_FIRMWARE_SUCCESS: |
33a732f4 AD |
88 | return "SUCCESS"; |
89 | default: | |
90 | return "UNKNOWN!"; | |
91 | } | |
92 | }; | |
93 | ||
0c5664e4 | 94 | static void guc_interrupts_release(struct drm_i915_private *dev_priv) |
4df001d3 | 95 | { |
e2f80391 | 96 | struct intel_engine_cs *engine; |
3b3f1650 | 97 | enum intel_engine_id id; |
b4ac5afc | 98 | int irqs; |
4df001d3 | 99 | |
fa7545a4 | 100 | /* tell all command streamers NOT to forward interrupts or vblank to GuC */ |
4df001d3 DG |
101 | irqs = _MASKED_FIELD(GFX_FORWARD_VBLANK_MASK, GFX_FORWARD_VBLANK_NEVER); |
102 | irqs |= _MASKED_BIT_DISABLE(GFX_INTERRUPT_STEERING); | |
3b3f1650 | 103 | for_each_engine(engine, dev_priv, id) |
e2f80391 | 104 | I915_WRITE(RING_MODE_GEN7(engine), irqs); |
4df001d3 | 105 | |
4df001d3 DG |
106 | /* route all GT interrupts to the host */ |
107 | I915_WRITE(GUC_BCS_RCS_IER, 0); | |
108 | I915_WRITE(GUC_VCS2_VCS1_IER, 0); | |
109 | I915_WRITE(GUC_WD_VECS_IER, 0); | |
110 | } | |
111 | ||
0c5664e4 | 112 | static void guc_interrupts_capture(struct drm_i915_private *dev_priv) |
4df001d3 | 113 | { |
e2f80391 | 114 | struct intel_engine_cs *engine; |
3b3f1650 | 115 | enum intel_engine_id id; |
b4ac5afc | 116 | int irqs; |
1800ad25 | 117 | u32 tmp; |
4df001d3 | 118 | |
fa7545a4 DG |
119 | /* tell all command streamers to forward interrupts (but not vblank) to GuC */ |
120 | irqs = _MASKED_BIT_ENABLE(GFX_INTERRUPT_STEERING); | |
3b3f1650 | 121 | for_each_engine(engine, dev_priv, id) |
e2f80391 | 122 | I915_WRITE(RING_MODE_GEN7(engine), irqs); |
4df001d3 | 123 | |
4df001d3 DG |
124 | /* route USER_INTERRUPT to Host, all others are sent to GuC. */ |
125 | irqs = GT_RENDER_USER_INTERRUPT << GEN8_RCS_IRQ_SHIFT | | |
126 | GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT; | |
127 | /* These three registers have the same bit definitions */ | |
128 | I915_WRITE(GUC_BCS_RCS_IER, ~irqs); | |
129 | I915_WRITE(GUC_VCS2_VCS1_IER, ~irqs); | |
130 | I915_WRITE(GUC_WD_VECS_IER, ~irqs); | |
1800ad25 SAK |
131 | |
132 | /* | |
b20e3cfe DG |
133 | * The REDIRECT_TO_GUC bit of the PMINTRMSK register directs all |
134 | * (unmasked) PM interrupts to the GuC. All other bits of this | |
135 | * register *disable* generation of a specific interrupt. | |
136 | * | |
137 | * 'pm_intr_keep' indicates bits that are NOT to be set when | |
138 | * writing to the PM interrupt mask register, i.e. interrupts | |
139 | * that must not be disabled. | |
140 | * | |
141 | * If the GuC is handling these interrupts, then we must not let | |
142 | * the PM code disable ANY interrupt that the GuC is expecting. | |
143 | * So for each ENABLED (0) bit in this register, we must SET the | |
144 | * bit in pm_intr_keep so that it's left enabled for the GuC. | |
145 | * | |
146 | * OTOH the REDIRECT_TO_GUC bit is initially SET in pm_intr_keep | |
147 | * (so interrupts go to the DISPLAY unit at first); but here we | |
148 | * need to CLEAR that bit, which will result in the register bit | |
149 | * being left SET! | |
150 | */ | |
1800ad25 | 151 | tmp = I915_READ(GEN6_PMINTRMSK); |
b20e3cfe DG |
152 | if (tmp & GEN8_PMINTR_REDIRECT_TO_GUC) { |
153 | dev_priv->rps.pm_intr_keep |= ~tmp; | |
154 | dev_priv->rps.pm_intr_keep &= ~GEN8_PMINTR_REDIRECT_TO_GUC; | |
1800ad25 | 155 | } |
4df001d3 DG |
156 | } |
157 | ||
33a732f4 AD |
158 | static u32 get_gttype(struct drm_i915_private *dev_priv) |
159 | { | |
160 | /* XXX: GT type based on PCI device ID? field seems unused by fw */ | |
161 | return 0; | |
162 | } | |
163 | ||
164 | static u32 get_core_family(struct drm_i915_private *dev_priv) | |
165 | { | |
fc32de93 DG |
166 | u32 gen = INTEL_GEN(dev_priv); |
167 | ||
168 | switch (gen) { | |
33a732f4 AD |
169 | case 9: |
170 | return GFXCORE_FAMILY_GEN9; | |
171 | ||
172 | default: | |
fc32de93 | 173 | WARN(1, "GEN%d does not support GuC operation!\n", gen); |
33a732f4 AD |
174 | return GFXCORE_FAMILY_UNKNOWN; |
175 | } | |
176 | } | |
177 | ||
0c5664e4 DG |
178 | /* |
179 | * Initialise the GuC parameter block before starting the firmware | |
180 | * transfer. These parameters are read by the firmware on startup | |
181 | * and cannot be changed thereafter. | |
182 | */ | |
183 | static void guc_params_init(struct drm_i915_private *dev_priv) | |
33a732f4 AD |
184 | { |
185 | struct intel_guc *guc = &dev_priv->guc; | |
186 | u32 params[GUC_CTL_MAX_DWORDS]; | |
187 | int i; | |
188 | ||
189 | memset(¶ms, 0, sizeof(params)); | |
190 | ||
191 | params[GUC_CTL_DEVICE_INFO] |= | |
192 | (get_gttype(dev_priv) << GUC_CTL_GTTYPE_SHIFT) | | |
193 | (get_core_family(dev_priv) << GUC_CTL_COREFAMILY_SHIFT); | |
194 | ||
195 | /* | |
196 | * GuC ARAT increment is 10 ns. GuC default scheduler quantum is one | |
197 | * second. This ARAR is calculated by: | |
198 | * Scheduler-Quantum-in-ns / ARAT-increment-in-ns = 1000000000 / 10 | |
199 | */ | |
200 | params[GUC_CTL_ARAT_HIGH] = 0; | |
201 | params[GUC_CTL_ARAT_LOW] = 100000000; | |
202 | ||
203 | params[GUC_CTL_WA] |= GUC_CTL_WA_UK_BY_DRIVER; | |
204 | ||
205 | params[GUC_CTL_FEATURE] |= GUC_CTL_DISABLE_SCHEDULER | | |
206 | GUC_CTL_VCS2_ENABLED; | |
207 | ||
d6b40b4b | 208 | params[GUC_CTL_LOG_PARAMS] = guc->log.flags; |
b1e37103 | 209 | |
33a732f4 | 210 | if (i915.guc_log_level >= 0) { |
33a732f4 AD |
211 | params[GUC_CTL_DEBUG] = |
212 | i915.guc_log_level << GUC_LOG_VERBOSITY_SHIFT; | |
b1e37103 SAK |
213 | } else |
214 | params[GUC_CTL_DEBUG] = GUC_LOG_DISABLED; | |
33a732f4 | 215 | |
8b797af1 | 216 | if (guc->ads_vma) { |
4741da92 | 217 | u32 ads = guc_ggtt_offset(guc->ads_vma) >> PAGE_SHIFT; |
b6a5cd7e AD |
218 | params[GUC_CTL_DEBUG] |= ads << GUC_ADS_ADDR_SHIFT; |
219 | params[GUC_CTL_DEBUG] |= GUC_ADS_ENABLED; | |
220 | } | |
221 | ||
bac427f8 AD |
222 | /* If GuC submission is enabled, set up additional parameters here */ |
223 | if (i915.enable_guc_submission) { | |
4741da92 | 224 | u32 pgs = guc_ggtt_offset(dev_priv->guc.ctx_pool_vma); |
bac427f8 AD |
225 | u32 ctx_in_16 = GUC_MAX_GPU_CONTEXTS / 16; |
226 | ||
227 | pgs >>= PAGE_SHIFT; | |
228 | params[GUC_CTL_CTXINFO] = (pgs << GUC_CTL_BASE_ADDR_SHIFT) | | |
229 | (ctx_in_16 << GUC_CTL_CTXNUM_IN16_SHIFT); | |
230 | ||
231 | params[GUC_CTL_FEATURE] |= GUC_CTL_KERNEL_SUBMISSIONS; | |
232 | ||
233 | /* Unmask this bit to enable the GuC's internal scheduler */ | |
234 | params[GUC_CTL_FEATURE] &= ~GUC_CTL_DISABLE_SCHEDULER; | |
235 | } | |
236 | ||
33a732f4 AD |
237 | I915_WRITE(SOFT_SCRATCH(0), 0); |
238 | ||
239 | for (i = 0; i < GUC_CTL_MAX_DWORDS; i++) | |
240 | I915_WRITE(SOFT_SCRATCH(1 + i), params[i]); | |
241 | } | |
242 | ||
243 | /* | |
244 | * Read the GuC status register (GUC_STATUS) and store it in the | |
245 | * specified location; then return a boolean indicating whether | |
246 | * the value matches either of two values representing completion | |
247 | * of the GuC boot process. | |
248 | * | |
36894e8b | 249 | * This is used for polling the GuC status in a wait_for() |
33a732f4 AD |
250 | * loop below. |
251 | */ | |
252 | static inline bool guc_ucode_response(struct drm_i915_private *dev_priv, | |
253 | u32 *status) | |
254 | { | |
255 | u32 val = I915_READ(GUC_STATUS); | |
0d44d3fa | 256 | u32 uk_val = val & GS_UKERNEL_MASK; |
33a732f4 | 257 | *status = val; |
0d44d3fa AD |
258 | return (uk_val == GS_UKERNEL_READY || |
259 | ((val & GS_MIA_CORE_STATE) && uk_val == GS_UKERNEL_LAPIC_DONE)); | |
33a732f4 AD |
260 | } |
261 | ||
262 | /* | |
263 | * Transfer the firmware image to RAM for execution by the microcontroller. | |
264 | * | |
33a732f4 AD |
265 | * Architecturally, the DMA engine is bidirectional, and can potentially even |
266 | * transfer between GTT locations. This functionality is left out of the API | |
267 | * for now as there is no need for it. | |
268 | * | |
269 | * Note that GuC needs the CSS header plus uKernel code to be copied by the | |
270 | * DMA engine in one operation, whereas the RSA signature is loaded via MMIO. | |
271 | */ | |
058d88c4 CW |
272 | static int guc_ucode_xfer_dma(struct drm_i915_private *dev_priv, |
273 | struct i915_vma *vma) | |
33a732f4 | 274 | { |
db0a091b | 275 | struct intel_uc_fw *guc_fw = &dev_priv->guc.fw; |
33a732f4 | 276 | unsigned long offset; |
058d88c4 | 277 | struct sg_table *sg = vma->pages; |
feda33ef | 278 | u32 status, rsa[UOS_RSA_SCRATCH_MAX_COUNT]; |
33a732f4 AD |
279 | int i, ret = 0; |
280 | ||
feda33ef AD |
281 | /* where RSA signature starts */ |
282 | offset = guc_fw->rsa_offset; | |
33a732f4 AD |
283 | |
284 | /* Copy RSA signature from the fw image to HW for verification */ | |
feda33ef AD |
285 | sg_pcopy_to_buffer(sg->sgl, sg->nents, rsa, sizeof(rsa), offset); |
286 | for (i = 0; i < UOS_RSA_SCRATCH_MAX_COUNT; i++) | |
ab9cc558 | 287 | I915_WRITE(UOS_RSA_SCRATCH(i), rsa[i]); |
33a732f4 | 288 | |
feda33ef AD |
289 | /* The header plus uCode will be copied to WOPCM via DMA, excluding any |
290 | * other components */ | |
291 | I915_WRITE(DMA_COPY_SIZE, guc_fw->header_size + guc_fw->ucode_size); | |
292 | ||
33a732f4 | 293 | /* Set the source address for the new blob */ |
4741da92 | 294 | offset = guc_ggtt_offset(vma) + guc_fw->header_offset; |
33a732f4 AD |
295 | I915_WRITE(DMA_ADDR_0_LOW, lower_32_bits(offset)); |
296 | I915_WRITE(DMA_ADDR_0_HIGH, upper_32_bits(offset) & 0xFFFF); | |
297 | ||
298 | /* | |
299 | * Set the DMA destination. Current uCode expects the code to be | |
300 | * loaded at 8k; locations below this are used for the stack. | |
301 | */ | |
302 | I915_WRITE(DMA_ADDR_1_LOW, 0x2000); | |
303 | I915_WRITE(DMA_ADDR_1_HIGH, DMA_ADDRESS_SPACE_WOPCM); | |
304 | ||
305 | /* Finally start the DMA */ | |
306 | I915_WRITE(DMA_CTRL, _MASKED_BIT_ENABLE(UOS_MOVE | START_DMA)); | |
307 | ||
308 | /* | |
36894e8b | 309 | * Wait for the DMA to complete & the GuC to start up. |
33a732f4 AD |
310 | * NB: Docs recommend not using the interrupt for completion. |
311 | * Measurements indicate this should take no more than 20ms, so a | |
312 | * timeout here indicates that the GuC has failed and is unusable. | |
313 | * (Higher levels of the driver will attempt to fall back to | |
314 | * execlist mode if this happens.) | |
315 | */ | |
36894e8b | 316 | ret = wait_for(guc_ucode_response(dev_priv, &status), 100); |
33a732f4 AD |
317 | |
318 | DRM_DEBUG_DRIVER("DMA status 0x%x, GuC status 0x%x\n", | |
319 | I915_READ(DMA_CTRL), status); | |
320 | ||
321 | if ((status & GS_BOOTROM_MASK) == GS_BOOTROM_RSA_FAILED) { | |
322 | DRM_ERROR("GuC firmware signature verification failed\n"); | |
323 | ret = -ENOEXEC; | |
324 | } | |
325 | ||
326 | DRM_DEBUG_DRIVER("returning %d\n", ret); | |
327 | ||
328 | return ret; | |
329 | } | |
330 | ||
bd132858 | 331 | u32 intel_guc_wopcm_size(struct drm_i915_private *dev_priv) |
74aa156b PA |
332 | { |
333 | u32 wopcm_size = GUC_WOPCM_TOP; | |
334 | ||
335 | /* On BXT, the top of WOPCM is reserved for RC6 context */ | |
254e0931 | 336 | if (IS_GEN9_LP(dev_priv)) |
74aa156b PA |
337 | wopcm_size -= BXT_GUC_WOPCM_RC6_RESERVED; |
338 | ||
339 | return wopcm_size; | |
340 | } | |
341 | ||
33a732f4 AD |
342 | /* |
343 | * Load the GuC firmware blob into the MinuteIA. | |
344 | */ | |
345 | static int guc_ucode_xfer(struct drm_i915_private *dev_priv) | |
346 | { | |
db0a091b | 347 | struct intel_uc_fw *guc_fw = &dev_priv->guc.fw; |
058d88c4 | 348 | struct i915_vma *vma; |
33a732f4 AD |
349 | int ret; |
350 | ||
db0a091b | 351 | ret = i915_gem_object_set_to_gtt_domain(guc_fw->obj, false); |
33a732f4 AD |
352 | if (ret) { |
353 | DRM_DEBUG_DRIVER("set-domain failed %d\n", ret); | |
354 | return ret; | |
355 | } | |
356 | ||
db0a091b | 357 | vma = i915_gem_object_ggtt_pin(guc_fw->obj, NULL, 0, 0, |
83796f26 | 358 | PIN_OFFSET_BIAS | GUC_WOPCM_TOP); |
058d88c4 CW |
359 | if (IS_ERR(vma)) { |
360 | DRM_DEBUG_DRIVER("pin failed %d\n", (int)PTR_ERR(vma)); | |
361 | return PTR_ERR(vma); | |
33a732f4 AD |
362 | } |
363 | ||
33a732f4 AD |
364 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); |
365 | ||
366 | /* init WOPCM */ | |
bd132858 | 367 | I915_WRITE(GUC_WOPCM_SIZE, intel_guc_wopcm_size(dev_priv)); |
33a732f4 AD |
368 | I915_WRITE(DMA_GUC_WOPCM_OFFSET, GUC_WOPCM_OFFSET_VALUE); |
369 | ||
370 | /* Enable MIA caching. GuC clock gating is disabled. */ | |
371 | I915_WRITE(GUC_SHIM_CONTROL, GUC_SHIM_CONTROL_VALUE); | |
372 | ||
a117f378 | 373 | /* WaDisableMinuteIaClockGating:bxt */ |
e2d214ae | 374 | if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) { |
b970b486 NH |
375 | I915_WRITE(GUC_SHIM_CONTROL, (I915_READ(GUC_SHIM_CONTROL) & |
376 | ~GUC_ENABLE_MIA_CLOCK_GATING)); | |
377 | } | |
378 | ||
4ff40a41 | 379 | /* WaC6DisallowByGfxPause:bxt */ |
e2d214ae | 380 | if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_B0)) |
65fe29ee | 381 | I915_WRITE(GEN6_GFXPAUSE, 0x30FFF); |
33a732f4 | 382 | |
254e0931 | 383 | if (IS_GEN9_LP(dev_priv)) |
33a732f4 AD |
384 | I915_WRITE(GEN9LP_GT_PM_CONFIG, GT_DOORBELL_ENABLE); |
385 | else | |
386 | I915_WRITE(GEN9_GT_PM_CONFIG, GT_DOORBELL_ENABLE); | |
387 | ||
5db94019 | 388 | if (IS_GEN9(dev_priv)) { |
33a732f4 AD |
389 | /* DOP Clock Gating Enable for GuC clocks */ |
390 | I915_WRITE(GEN7_MISCCPCTL, (GEN8_DOP_CLOCK_GATE_GUC_ENABLE | | |
391 | I915_READ(GEN7_MISCCPCTL))); | |
392 | ||
0c5664e4 | 393 | /* allows for 5us (in 10ns units) before GT can go to RC6 */ |
33a732f4 AD |
394 | I915_WRITE(GUC_ARAT_C6DIS, 0x1FF); |
395 | } | |
396 | ||
0c5664e4 | 397 | guc_params_init(dev_priv); |
33a732f4 | 398 | |
058d88c4 | 399 | ret = guc_ucode_xfer_dma(dev_priv, vma); |
33a732f4 AD |
400 | |
401 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); | |
402 | ||
403 | /* | |
404 | * We keep the object pages for reuse during resume. But we can unpin it | |
405 | * now that DMA has completed, so it doesn't continue to take up space. | |
406 | */ | |
058d88c4 | 407 | i915_vma_unpin(vma); |
33a732f4 AD |
408 | |
409 | return ret; | |
410 | } | |
411 | ||
0c5664e4 | 412 | static int guc_hw_reset(struct drm_i915_private *dev_priv) |
6b332fa2 AS |
413 | { |
414 | int ret; | |
415 | u32 guc_status; | |
416 | ||
417 | ret = intel_guc_reset(dev_priv); | |
418 | if (ret) { | |
419 | DRM_ERROR("GuC reset failed, ret = %d\n", ret); | |
420 | return ret; | |
421 | } | |
422 | ||
423 | guc_status = I915_READ(GUC_STATUS); | |
424 | WARN(!(guc_status & GS_MIA_IN_RESET), | |
425 | "GuC status: 0x%x, MIA core expected to be in reset\n", guc_status); | |
426 | ||
427 | return ret; | |
428 | } | |
429 | ||
33a732f4 | 430 | /** |
f09d675f | 431 | * intel_guc_setup() - finish preparing the GuC for activity |
bf9e8429 | 432 | * @dev_priv: i915 device private |
33a732f4 AD |
433 | * |
434 | * Called from gem_init_hw() during driver loading and also after a GPU reset. | |
435 | * | |
f09d675f | 436 | * The main action required here it to load the GuC uCode into the device. |
33a732f4 | 437 | * The firmware image should have already been fetched into memory by the |
f09d675f DG |
438 | * earlier call to intel_guc_init(), so here we need only check that worked, |
439 | * and then transfer the image to the h/w. | |
33a732f4 AD |
440 | * |
441 | * Return: non-zero code on error | |
442 | */ | |
bf9e8429 | 443 | int intel_guc_setup(struct drm_i915_private *dev_priv) |
33a732f4 | 444 | { |
db0a091b AS |
445 | struct intel_uc_fw *guc_fw = &dev_priv->guc.fw; |
446 | const char *fw_path = guc_fw->path; | |
fce91f22 | 447 | int retries, ret, err; |
33a732f4 | 448 | |
fce91f22 DG |
449 | DRM_DEBUG_DRIVER("GuC fw status: path %s, fetch %s, load %s\n", |
450 | fw_path, | |
db0a091b AS |
451 | intel_uc_fw_status_repr(guc_fw->fetch_status), |
452 | intel_uc_fw_status_repr(guc_fw->load_status)); | |
33a732f4 | 453 | |
fce91f22 DG |
454 | /* Loading forbidden, or no firmware to load? */ |
455 | if (!i915.enable_guc_loading) { | |
456 | err = 0; | |
457 | goto fail; | |
e556f7c1 DG |
458 | } else if (fw_path == NULL) { |
459 | /* Device is known to have no uCode (e.g. no GuC) */ | |
460 | err = -ENXIO; | |
461 | goto fail; | |
462 | } else if (*fw_path == '\0') { | |
463 | /* Device has a GuC but we don't know what f/w to load? */ | |
fc32de93 | 464 | WARN(1, "No GuC firmware known for this platform!\n"); |
fce91f22 DG |
465 | err = -ENODEV; |
466 | goto fail; | |
467 | } | |
33a732f4 | 468 | |
fce91f22 | 469 | /* Fetch failed, or already fetched but failed to load? */ |
db0a091b | 470 | if (guc_fw->fetch_status != INTEL_UC_FIRMWARE_SUCCESS) { |
33a732f4 AD |
471 | err = -EIO; |
472 | goto fail; | |
db0a091b | 473 | } else if (guc_fw->load_status == INTEL_UC_FIRMWARE_FAIL) { |
fce91f22 | 474 | err = -ENOEXEC; |
33a732f4 | 475 | goto fail; |
33a732f4 AD |
476 | } |
477 | ||
0c5664e4 | 478 | guc_interrupts_release(dev_priv); |
26705e20 | 479 | gen9_reset_guc_interrupts(dev_priv); |
fce91f22 | 480 | |
7c3f86b6 CW |
481 | /* We need to notify the guc whenever we change the GGTT */ |
482 | i915_ggtt_enable_guc(dev_priv); | |
483 | ||
db0a091b | 484 | guc_fw->load_status = INTEL_UC_FIRMWARE_PENDING; |
fce91f22 DG |
485 | |
486 | DRM_DEBUG_DRIVER("GuC fw status: fetch %s, load %s\n", | |
db0a091b AS |
487 | intel_uc_fw_status_repr(guc_fw->fetch_status), |
488 | intel_uc_fw_status_repr(guc_fw->load_status)); | |
fce91f22 | 489 | |
beffa517 | 490 | err = i915_guc_submission_init(dev_priv); |
bac427f8 AD |
491 | if (err) |
492 | goto fail; | |
493 | ||
6b332fa2 AS |
494 | /* |
495 | * WaEnableuKernelHeaderValidFix:skl,bxt | |
496 | * For BXT, this is only upto B0 but below WA is required for later | |
497 | * steppings also so this is extended as well. | |
498 | */ | |
499 | /* WaEnableGuCBootHashCheckNotSet:skl,bxt */ | |
d761701c DG |
500 | for (retries = 3; ; ) { |
501 | /* | |
502 | * Always reset the GuC just before (re)loading, so | |
503 | * that the state and timing are fairly predictable | |
504 | */ | |
0c5664e4 | 505 | err = guc_hw_reset(dev_priv); |
fc32de93 | 506 | if (err) |
6b332fa2 | 507 | goto fail; |
d761701c | 508 | |
bd132858 | 509 | intel_huc_load(dev_priv); |
d761701c DG |
510 | err = guc_ucode_xfer(dev_priv); |
511 | if (!err) | |
512 | break; | |
513 | ||
514 | if (--retries == 0) | |
515 | goto fail; | |
516 | ||
fce91f22 DG |
517 | DRM_INFO("GuC fw load failed: %d; will reset and " |
518 | "retry %d more time(s)\n", err, retries); | |
6b332fa2 | 519 | } |
33a732f4 | 520 | |
db0a091b | 521 | guc_fw->load_status = INTEL_UC_FIRMWARE_SUCCESS; |
33a732f4 | 522 | |
dac84a38 AS |
523 | intel_guc_auth_huc(dev_priv); |
524 | ||
44a28b1d | 525 | if (i915.enable_guc_submission) { |
26705e20 SAK |
526 | if (i915.guc_log_level >= 0) |
527 | gen9_enable_guc_interrupts(dev_priv); | |
528 | ||
beffa517 | 529 | err = i915_guc_submission_enable(dev_priv); |
44a28b1d DG |
530 | if (err) |
531 | goto fail; | |
0c5664e4 | 532 | guc_interrupts_capture(dev_priv); |
44a28b1d DG |
533 | } |
534 | ||
fb51ff40 TU |
535 | DRM_INFO("GuC %s (firmware %s [version %u.%u])\n", |
536 | i915.enable_guc_submission ? "submission enabled" : "loaded", | |
537 | guc_fw->path, | |
538 | guc_fw->major_ver_found, guc_fw->minor_ver_found); | |
539 | ||
33a732f4 AD |
540 | return 0; |
541 | ||
542 | fail: | |
db0a091b AS |
543 | if (guc_fw->load_status == INTEL_UC_FIRMWARE_PENDING) |
544 | guc_fw->load_status = INTEL_UC_FIRMWARE_FAIL; | |
33a732f4 | 545 | |
0c5664e4 | 546 | guc_interrupts_release(dev_priv); |
beffa517 DG |
547 | i915_guc_submission_disable(dev_priv); |
548 | i915_guc_submission_fini(dev_priv); | |
7c3f86b6 | 549 | i915_ggtt_disable_guc(dev_priv); |
44a28b1d | 550 | |
fce91f22 DG |
551 | /* |
552 | * We've failed to load the firmware :( | |
553 | * | |
554 | * Decide whether to disable GuC submission and fall back to | |
555 | * execlist mode, and whether to hide the error by returning | |
556 | * zero or to return -EIO, which the caller will treat as a | |
557 | * nonfatal error (i.e. it doesn't prevent driver load, but | |
558 | * marks the GPU as wedged until reset). | |
559 | */ | |
560 | if (i915.enable_guc_loading > 1) { | |
561 | ret = -EIO; | |
562 | } else if (i915.enable_guc_submission > 1) { | |
563 | ret = -EIO; | |
564 | } else { | |
565 | ret = 0; | |
566 | } | |
567 | ||
4805fe82 | 568 | if (err == 0 && !HAS_GUC_UCODE(dev_priv)) |
4e50f796 DG |
569 | ; /* Don't mention the GuC! */ |
570 | else if (err == 0) | |
fce91f22 | 571 | DRM_INFO("GuC firmware load skipped\n"); |
4e50f796 | 572 | else if (ret != -EIO) |
fc32de93 | 573 | DRM_NOTE("GuC firmware load failed: %d\n", err); |
4e50f796 | 574 | else |
fc32de93 | 575 | DRM_WARN("GuC firmware load failed: %d\n", err); |
fce91f22 DG |
576 | |
577 | if (i915.enable_guc_submission) { | |
578 | if (fw_path == NULL) | |
579 | DRM_INFO("GuC submission without firmware not supported\n"); | |
580 | if (ret == 0) | |
fc32de93 | 581 | DRM_NOTE("Falling back from GuC submission to execlist mode\n"); |
fce91f22 DG |
582 | else |
583 | DRM_ERROR("GuC init failed: %d\n", ret); | |
584 | } | |
585 | i915.enable_guc_submission = 0; | |
586 | ||
587 | return ret; | |
33a732f4 AD |
588 | } |
589 | ||
db0a091b AS |
590 | void intel_uc_fw_fetch(struct drm_i915_private *dev_priv, |
591 | struct intel_uc_fw *uc_fw) | |
33a732f4 | 592 | { |
bf9e8429 | 593 | struct pci_dev *pdev = dev_priv->drm.pdev; |
33a732f4 | 594 | struct drm_i915_gem_object *obj; |
3aaa8aba | 595 | const struct firmware *fw = NULL; |
fbbad73e | 596 | struct uc_css_header *css; |
feda33ef | 597 | size_t size; |
33a732f4 AD |
598 | int err; |
599 | ||
db0a091b AS |
600 | DRM_DEBUG_DRIVER("before requesting firmware: uC fw fetch status %s\n", |
601 | intel_uc_fw_status_repr(uc_fw->fetch_status)); | |
33a732f4 | 602 | |
db0a091b | 603 | err = request_firmware(&fw, uc_fw->path, &pdev->dev); |
33a732f4 AD |
604 | if (err) |
605 | goto fail; | |
606 | if (!fw) | |
607 | goto fail; | |
608 | ||
db0a091b AS |
609 | DRM_DEBUG_DRIVER("fetch uC fw from %s succeeded, fw %p\n", |
610 | uc_fw->path, fw); | |
33a732f4 | 611 | |
feda33ef | 612 | /* Check the size of the blob before examining buffer contents */ |
fbbad73e | 613 | if (fw->size < sizeof(struct uc_css_header)) { |
fc32de93 | 614 | DRM_NOTE("Firmware header is missing\n"); |
33a732f4 | 615 | goto fail; |
feda33ef AD |
616 | } |
617 | ||
fbbad73e | 618 | css = (struct uc_css_header *)fw->data; |
feda33ef AD |
619 | |
620 | /* Firmware bits always start from header */ | |
db0a091b AS |
621 | uc_fw->header_offset = 0; |
622 | uc_fw->header_size = (css->header_size_dw - css->modulus_size_dw - | |
feda33ef AD |
623 | css->key_size_dw - css->exponent_size_dw) * sizeof(u32); |
624 | ||
fbbad73e | 625 | if (uc_fw->header_size != sizeof(struct uc_css_header)) { |
fc32de93 | 626 | DRM_NOTE("CSS header definition mismatch\n"); |
feda33ef AD |
627 | goto fail; |
628 | } | |
629 | ||
630 | /* then, uCode */ | |
db0a091b AS |
631 | uc_fw->ucode_offset = uc_fw->header_offset + uc_fw->header_size; |
632 | uc_fw->ucode_size = (css->size_dw - css->header_size_dw) * sizeof(u32); | |
feda33ef AD |
633 | |
634 | /* now RSA */ | |
635 | if (css->key_size_dw != UOS_RSA_SCRATCH_MAX_COUNT) { | |
fc32de93 | 636 | DRM_NOTE("RSA key size is bad\n"); |
feda33ef AD |
637 | goto fail; |
638 | } | |
db0a091b AS |
639 | uc_fw->rsa_offset = uc_fw->ucode_offset + uc_fw->ucode_size; |
640 | uc_fw->rsa_size = css->key_size_dw * sizeof(u32); | |
feda33ef AD |
641 | |
642 | /* At least, it should have header, uCode and RSA. Size of all three. */ | |
db0a091b | 643 | size = uc_fw->header_size + uc_fw->ucode_size + uc_fw->rsa_size; |
feda33ef | 644 | if (fw->size < size) { |
fc32de93 | 645 | DRM_NOTE("Missing firmware components\n"); |
feda33ef AD |
646 | goto fail; |
647 | } | |
648 | ||
33a732f4 AD |
649 | /* |
650 | * The GuC firmware image has the version number embedded at a well-known | |
651 | * offset within the firmware blob; note that major / minor version are | |
652 | * TWO bytes each (i.e. u16), although all pointers and offsets are defined | |
653 | * in terms of bytes (u8). | |
654 | */ | |
fbbad73e AS |
655 | switch (uc_fw->fw) { |
656 | case INTEL_UC_FW_TYPE_GUC: | |
657 | /* Header and uCode will be loaded to WOPCM. Size of the two. */ | |
658 | size = uc_fw->header_size + uc_fw->ucode_size; | |
659 | ||
660 | /* Top 32k of WOPCM is reserved (8K stack + 24k RC6 context). */ | |
bd132858 | 661 | if (size > intel_guc_wopcm_size(dev_priv)) { |
fbbad73e AS |
662 | DRM_ERROR("Firmware is too large to fit in WOPCM\n"); |
663 | goto fail; | |
664 | } | |
665 | uc_fw->major_ver_found = css->guc.sw_version >> 16; | |
666 | uc_fw->minor_ver_found = css->guc.sw_version & 0xFFFF; | |
667 | break; | |
668 | ||
669 | case INTEL_UC_FW_TYPE_HUC: | |
670 | uc_fw->major_ver_found = css->huc.sw_version >> 16; | |
671 | uc_fw->minor_ver_found = css->huc.sw_version & 0xFFFF; | |
672 | break; | |
673 | ||
674 | default: | |
675 | DRM_ERROR("Unknown firmware type %d\n", uc_fw->fw); | |
676 | err = -ENOEXEC; | |
677 | goto fail; | |
678 | } | |
db0a091b AS |
679 | |
680 | if (uc_fw->major_ver_found != uc_fw->major_ver_wanted || | |
681 | uc_fw->minor_ver_found < uc_fw->minor_ver_wanted) { | |
682 | DRM_NOTE("uC firmware version %d.%d, required %d.%d\n", | |
683 | uc_fw->major_ver_found, uc_fw->minor_ver_found, | |
684 | uc_fw->major_ver_wanted, uc_fw->minor_ver_wanted); | |
33a732f4 AD |
685 | err = -ENOEXEC; |
686 | goto fail; | |
687 | } | |
688 | ||
689 | DRM_DEBUG_DRIVER("firmware version %d.%d OK (minimum %d.%d)\n", | |
db0a091b AS |
690 | uc_fw->major_ver_found, uc_fw->minor_ver_found, |
691 | uc_fw->major_ver_wanted, uc_fw->minor_ver_wanted); | |
33a732f4 | 692 | |
bf9e8429 | 693 | mutex_lock(&dev_priv->drm.struct_mutex); |
12d79d78 | 694 | obj = i915_gem_object_create_from_data(dev_priv, fw->data, fw->size); |
bf9e8429 | 695 | mutex_unlock(&dev_priv->drm.struct_mutex); |
33a732f4 AD |
696 | if (IS_ERR_OR_NULL(obj)) { |
697 | err = obj ? PTR_ERR(obj) : -ENOMEM; | |
698 | goto fail; | |
699 | } | |
700 | ||
db0a091b AS |
701 | uc_fw->obj = obj; |
702 | uc_fw->size = fw->size; | |
33a732f4 | 703 | |
db0a091b AS |
704 | DRM_DEBUG_DRIVER("uC fw fetch status SUCCESS, obj %p\n", |
705 | uc_fw->obj); | |
33a732f4 AD |
706 | |
707 | release_firmware(fw); | |
db0a091b | 708 | uc_fw->fetch_status = INTEL_UC_FIRMWARE_SUCCESS; |
33a732f4 AD |
709 | return; |
710 | ||
711 | fail: | |
db0a091b AS |
712 | DRM_WARN("Failed to fetch valid uC firmware from %s (error %d)\n", |
713 | uc_fw->path, err); | |
714 | DRM_DEBUG_DRIVER("uC fw fetch status FAIL; err %d, fw %p, obj %p\n", | |
715 | err, fw, uc_fw->obj); | |
33a732f4 | 716 | |
bf9e8429 | 717 | mutex_lock(&dev_priv->drm.struct_mutex); |
db0a091b | 718 | obj = uc_fw->obj; |
33a732f4 | 719 | if (obj) |
f8c417cd | 720 | i915_gem_object_put(obj); |
db0a091b | 721 | uc_fw->obj = NULL; |
bf9e8429 | 722 | mutex_unlock(&dev_priv->drm.struct_mutex); |
33a732f4 AD |
723 | |
724 | release_firmware(fw); /* OK even if fw is NULL */ | |
db0a091b | 725 | uc_fw->fetch_status = INTEL_UC_FIRMWARE_FAIL; |
33a732f4 AD |
726 | } |
727 | ||
728 | /** | |
f09d675f | 729 | * intel_guc_init() - define parameters and fetch firmware |
bf9e8429 | 730 | * @dev_priv: i915 device private |
33a732f4 AD |
731 | * |
732 | * Called early during driver load, but after GEM is initialised. | |
33a732f4 AD |
733 | * |
734 | * The firmware will be transferred to the GuC's memory later, | |
f09d675f | 735 | * when intel_guc_setup() is called. |
33a732f4 | 736 | */ |
bf9e8429 | 737 | void intel_guc_init(struct drm_i915_private *dev_priv) |
33a732f4 | 738 | { |
db0a091b | 739 | struct intel_uc_fw *guc_fw = &dev_priv->guc.fw; |
33a732f4 AD |
740 | const char *fw_path; |
741 | ||
4805fe82 | 742 | if (!HAS_GUC(dev_priv)) { |
21e33021 AS |
743 | i915.enable_guc_loading = 0; |
744 | i915.enable_guc_submission = 0; | |
745 | } else { | |
746 | /* A negative value means "use platform default" */ | |
747 | if (i915.enable_guc_loading < 0) | |
4805fe82 | 748 | i915.enable_guc_loading = HAS_GUC_UCODE(dev_priv); |
21e33021 | 749 | if (i915.enable_guc_submission < 0) |
4805fe82 | 750 | i915.enable_guc_submission = HAS_GUC_SCHED(dev_priv); |
21e33021 | 751 | } |
33a732f4 | 752 | |
4805fe82 | 753 | if (!HAS_GUC_UCODE(dev_priv)) { |
33a732f4 | 754 | fw_path = NULL; |
d9486e65 | 755 | } else if (IS_SKYLAKE(dev_priv)) { |
33a732f4 | 756 | fw_path = I915_SKL_GUC_UCODE; |
db0a091b AS |
757 | guc_fw->major_ver_wanted = SKL_FW_MAJOR; |
758 | guc_fw->minor_ver_wanted = SKL_FW_MINOR; | |
e2d214ae | 759 | } else if (IS_BROXTON(dev_priv)) { |
57bf5c81 | 760 | fw_path = I915_BXT_GUC_UCODE; |
db0a091b AS |
761 | guc_fw->major_ver_wanted = BXT_FW_MAJOR; |
762 | guc_fw->minor_ver_wanted = BXT_FW_MINOR; | |
0853723b | 763 | } else if (IS_KABYLAKE(dev_priv)) { |
ff64cc16 | 764 | fw_path = I915_KBL_GUC_UCODE; |
db0a091b AS |
765 | guc_fw->major_ver_wanted = KBL_FW_MAJOR; |
766 | guc_fw->minor_ver_wanted = KBL_FW_MINOR; | |
33a732f4 | 767 | } else { |
33a732f4 AD |
768 | fw_path = ""; /* unknown device */ |
769 | } | |
770 | ||
db0a091b AS |
771 | guc_fw->path = fw_path; |
772 | guc_fw->fetch_status = INTEL_UC_FIRMWARE_NONE; | |
773 | guc_fw->load_status = INTEL_UC_FIRMWARE_NONE; | |
33a732f4 | 774 | |
fce91f22 DG |
775 | /* Early (and silent) return if GuC loading is disabled */ |
776 | if (!i915.enable_guc_loading) | |
777 | return; | |
33a732f4 AD |
778 | if (fw_path == NULL) |
779 | return; | |
fce91f22 | 780 | if (*fw_path == '\0') |
33a732f4 | 781 | return; |
33a732f4 | 782 | |
db0a091b | 783 | guc_fw->fetch_status = INTEL_UC_FIRMWARE_PENDING; |
33a732f4 | 784 | DRM_DEBUG_DRIVER("GuC firmware pending, path %s\n", fw_path); |
db0a091b | 785 | intel_uc_fw_fetch(dev_priv, guc_fw); |
33a732f4 AD |
786 | /* status must now be FAIL or SUCCESS */ |
787 | } | |
788 | ||
789 | /** | |
f09d675f | 790 | * intel_guc_fini() - clean up all allocated resources |
b6ea8b4a | 791 | * @dev_priv: i915 device private |
33a732f4 | 792 | */ |
bf9e8429 | 793 | void intel_guc_fini(struct drm_i915_private *dev_priv) |
33a732f4 | 794 | { |
db0a091b | 795 | struct intel_uc_fw *guc_fw = &dev_priv->guc.fw; |
33a732f4 | 796 | |
bf9e8429 | 797 | mutex_lock(&dev_priv->drm.struct_mutex); |
0c5664e4 | 798 | guc_interrupts_release(dev_priv); |
beffa517 DG |
799 | i915_guc_submission_disable(dev_priv); |
800 | i915_guc_submission_fini(dev_priv); | |
bac427f8 | 801 | |
db0a091b AS |
802 | if (guc_fw->obj) |
803 | i915_gem_object_put(guc_fw->obj); | |
804 | guc_fw->obj = NULL; | |
bf9e8429 | 805 | mutex_unlock(&dev_priv->drm.struct_mutex); |
33a732f4 | 806 | |
db0a091b | 807 | guc_fw->fetch_status = INTEL_UC_FIRMWARE_NONE; |
33a732f4 | 808 | } |