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7d57382e EA |
1 | /* |
2 | * Copyright 2006 Dave Airlie <airlied@linux.ie> | |
3 | * Copyright © 2006-2009 Intel Corporation | |
4 | * | |
5 | * Permission is hereby granted, free of charge, to any person obtaining a | |
6 | * copy of this software and associated documentation files (the "Software"), | |
7 | * to deal in the Software without restriction, including without limitation | |
8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
9 | * and/or sell copies of the Software, and to permit persons to whom the | |
10 | * Software is furnished to do so, subject to the following conditions: | |
11 | * | |
12 | * The above copyright notice and this permission notice (including the next | |
13 | * paragraph) shall be included in all copies or substantial portions of the | |
14 | * Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
21 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
22 | * DEALINGS IN THE SOFTWARE. | |
23 | * | |
24 | * Authors: | |
25 | * Eric Anholt <eric@anholt.net> | |
26 | * Jesse Barnes <jesse.barnes@intel.com> | |
27 | */ | |
28 | ||
29 | #include <linux/i2c.h> | |
5a0e3ad6 | 30 | #include <linux/slab.h> |
7d57382e EA |
31 | #include <linux/delay.h> |
32 | #include "drmP.h" | |
33 | #include "drm.h" | |
34 | #include "drm_crtc.h" | |
aa93d632 | 35 | #include "drm_edid.h" |
7d57382e EA |
36 | #include "intel_drv.h" |
37 | #include "i915_drm.h" | |
38 | #include "i915_drv.h" | |
39 | ||
f5bbfca3 | 40 | struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder) |
ea5b213a | 41 | { |
4ef69c7a | 42 | return container_of(encoder, struct intel_hdmi, base.base); |
ea5b213a CW |
43 | } |
44 | ||
df0e9248 CW |
45 | static struct intel_hdmi *intel_attached_hdmi(struct drm_connector *connector) |
46 | { | |
47 | return container_of(intel_attached_encoder(connector), | |
48 | struct intel_hdmi, base); | |
49 | } | |
50 | ||
45187ace | 51 | void intel_dip_infoframe_csum(struct dip_infoframe *frame) |
3c17fe4b | 52 | { |
45187ace | 53 | uint8_t *data = (uint8_t *)frame; |
3c17fe4b DH |
54 | uint8_t sum = 0; |
55 | unsigned i; | |
56 | ||
45187ace JB |
57 | frame->checksum = 0; |
58 | frame->ecc = 0; | |
3c17fe4b | 59 | |
64a8fc01 | 60 | for (i = 0; i < frame->len + DIP_HEADER_SIZE; i++) |
3c17fe4b DH |
61 | sum += data[i]; |
62 | ||
45187ace | 63 | frame->checksum = 0x100 - sum; |
3c17fe4b DH |
64 | } |
65 | ||
bc2481f3 | 66 | static u32 g4x_infoframe_index(struct dip_infoframe *frame) |
3c17fe4b | 67 | { |
45187ace JB |
68 | switch (frame->type) { |
69 | case DIP_TYPE_AVI: | |
ed517fbb | 70 | return VIDEO_DIP_SELECT_AVI; |
45187ace | 71 | case DIP_TYPE_SPD: |
ed517fbb | 72 | return VIDEO_DIP_SELECT_SPD; |
45187ace JB |
73 | default: |
74 | DRM_DEBUG_DRIVER("unknown info frame type %d\n", frame->type); | |
ed517fbb | 75 | return 0; |
45187ace | 76 | } |
45187ace JB |
77 | } |
78 | ||
bc2481f3 | 79 | static u32 g4x_infoframe_enable(struct dip_infoframe *frame) |
45187ace | 80 | { |
45187ace JB |
81 | switch (frame->type) { |
82 | case DIP_TYPE_AVI: | |
ed517fbb | 83 | return VIDEO_DIP_ENABLE_AVI; |
45187ace | 84 | case DIP_TYPE_SPD: |
ed517fbb | 85 | return VIDEO_DIP_ENABLE_SPD; |
fa193ff7 PZ |
86 | default: |
87 | DRM_DEBUG_DRIVER("unknown info frame type %d\n", frame->type); | |
ed517fbb | 88 | return 0; |
fa193ff7 | 89 | } |
fa193ff7 PZ |
90 | } |
91 | ||
2da8af54 PZ |
92 | static u32 hsw_infoframe_enable(struct dip_infoframe *frame) |
93 | { | |
94 | switch (frame->type) { | |
95 | case DIP_TYPE_AVI: | |
96 | return VIDEO_DIP_ENABLE_AVI_HSW; | |
97 | case DIP_TYPE_SPD: | |
98 | return VIDEO_DIP_ENABLE_SPD_HSW; | |
99 | default: | |
100 | DRM_DEBUG_DRIVER("unknown info frame type %d\n", frame->type); | |
101 | return 0; | |
102 | } | |
103 | } | |
104 | ||
105 | static u32 hsw_infoframe_data_reg(struct dip_infoframe *frame, enum pipe pipe) | |
106 | { | |
107 | switch (frame->type) { | |
108 | case DIP_TYPE_AVI: | |
109 | return HSW_TVIDEO_DIP_AVI_DATA(pipe); | |
110 | case DIP_TYPE_SPD: | |
111 | return HSW_TVIDEO_DIP_SPD_DATA(pipe); | |
112 | default: | |
113 | DRM_DEBUG_DRIVER("unknown info frame type %d\n", frame->type); | |
114 | return 0; | |
115 | } | |
116 | } | |
117 | ||
a3da1df7 DV |
118 | static void g4x_write_infoframe(struct drm_encoder *encoder, |
119 | struct dip_infoframe *frame) | |
45187ace JB |
120 | { |
121 | uint32_t *data = (uint32_t *)frame; | |
3c17fe4b DH |
122 | struct drm_device *dev = encoder->dev; |
123 | struct drm_i915_private *dev_priv = dev->dev_private; | |
124 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); | |
22509ec8 | 125 | u32 val = I915_READ(VIDEO_DIP_CTL); |
45187ace | 126 | unsigned i, len = DIP_HEADER_SIZE + frame->len; |
3c17fe4b | 127 | |
3e6e6395 | 128 | val &= ~VIDEO_DIP_PORT_MASK; |
3c17fe4b | 129 | if (intel_hdmi->sdvox_reg == SDVOB) |
22509ec8 | 130 | val |= VIDEO_DIP_PORT_B; |
3c17fe4b | 131 | else if (intel_hdmi->sdvox_reg == SDVOC) |
22509ec8 | 132 | val |= VIDEO_DIP_PORT_C; |
3c17fe4b DH |
133 | else |
134 | return; | |
135 | ||
1d4f85ac | 136 | val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ |
bc2481f3 | 137 | val |= g4x_infoframe_index(frame); |
22509ec8 | 138 | |
bc2481f3 | 139 | val &= ~g4x_infoframe_enable(frame); |
22509ec8 | 140 | val |= VIDEO_DIP_ENABLE; |
45187ace | 141 | |
22509ec8 | 142 | I915_WRITE(VIDEO_DIP_CTL, val); |
3c17fe4b | 143 | |
45187ace | 144 | for (i = 0; i < len; i += 4) { |
3c17fe4b DH |
145 | I915_WRITE(VIDEO_DIP_DATA, *data); |
146 | data++; | |
147 | } | |
148 | ||
bc2481f3 | 149 | val |= g4x_infoframe_enable(frame); |
60c5ea2d | 150 | val &= ~VIDEO_DIP_FREQ_MASK; |
4b24c933 | 151 | val |= VIDEO_DIP_FREQ_VSYNC; |
45187ace | 152 | |
22509ec8 | 153 | I915_WRITE(VIDEO_DIP_CTL, val); |
3c17fe4b DH |
154 | } |
155 | ||
fdf1250a PZ |
156 | static void ibx_write_infoframe(struct drm_encoder *encoder, |
157 | struct dip_infoframe *frame) | |
158 | { | |
159 | uint32_t *data = (uint32_t *)frame; | |
160 | struct drm_device *dev = encoder->dev; | |
161 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ed517fbb | 162 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); |
4e89ee17 | 163 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); |
fdf1250a PZ |
164 | int reg = TVIDEO_DIP_CTL(intel_crtc->pipe); |
165 | unsigned i, len = DIP_HEADER_SIZE + frame->len; | |
166 | u32 val = I915_READ(reg); | |
167 | ||
4e89ee17 PZ |
168 | val &= ~VIDEO_DIP_PORT_MASK; |
169 | switch (intel_hdmi->sdvox_reg) { | |
170 | case HDMIB: | |
171 | val |= VIDEO_DIP_PORT_B; | |
172 | break; | |
173 | case HDMIC: | |
174 | val |= VIDEO_DIP_PORT_C; | |
175 | break; | |
176 | case HDMID: | |
177 | val |= VIDEO_DIP_PORT_D; | |
178 | break; | |
179 | default: | |
180 | return; | |
181 | } | |
182 | ||
fdf1250a PZ |
183 | intel_wait_for_vblank(dev, intel_crtc->pipe); |
184 | ||
185 | val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ | |
bc2481f3 | 186 | val |= g4x_infoframe_index(frame); |
fdf1250a | 187 | |
bc2481f3 | 188 | val &= ~g4x_infoframe_enable(frame); |
fdf1250a PZ |
189 | val |= VIDEO_DIP_ENABLE; |
190 | ||
191 | I915_WRITE(reg, val); | |
192 | ||
193 | for (i = 0; i < len; i += 4) { | |
194 | I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data); | |
195 | data++; | |
196 | } | |
197 | ||
bc2481f3 | 198 | val |= g4x_infoframe_enable(frame); |
fdf1250a | 199 | val &= ~VIDEO_DIP_FREQ_MASK; |
4b24c933 | 200 | val |= VIDEO_DIP_FREQ_VSYNC; |
fdf1250a PZ |
201 | |
202 | I915_WRITE(reg, val); | |
203 | } | |
204 | ||
205 | static void cpt_write_infoframe(struct drm_encoder *encoder, | |
206 | struct dip_infoframe *frame) | |
b055c8f3 | 207 | { |
45187ace | 208 | uint32_t *data = (uint32_t *)frame; |
b055c8f3 JB |
209 | struct drm_device *dev = encoder->dev; |
210 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ed517fbb | 211 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); |
b055c8f3 | 212 | int reg = TVIDEO_DIP_CTL(intel_crtc->pipe); |
45187ace | 213 | unsigned i, len = DIP_HEADER_SIZE + frame->len; |
22509ec8 | 214 | u32 val = I915_READ(reg); |
b055c8f3 JB |
215 | |
216 | intel_wait_for_vblank(dev, intel_crtc->pipe); | |
217 | ||
64a8fc01 | 218 | val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ |
bc2481f3 | 219 | val |= g4x_infoframe_index(frame); |
45187ace | 220 | |
ecb97851 PZ |
221 | /* The DIP control register spec says that we need to update the AVI |
222 | * infoframe without clearing its enable bit */ | |
223 | if (frame->type == DIP_TYPE_AVI) | |
224 | val |= VIDEO_DIP_ENABLE_AVI; | |
225 | else | |
bc2481f3 | 226 | val &= ~g4x_infoframe_enable(frame); |
ecb97851 | 227 | |
22509ec8 PZ |
228 | val |= VIDEO_DIP_ENABLE; |
229 | ||
230 | I915_WRITE(reg, val); | |
45187ace JB |
231 | |
232 | for (i = 0; i < len; i += 4) { | |
b055c8f3 JB |
233 | I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data); |
234 | data++; | |
235 | } | |
236 | ||
bc2481f3 | 237 | val |= g4x_infoframe_enable(frame); |
60c5ea2d | 238 | val &= ~VIDEO_DIP_FREQ_MASK; |
4b24c933 | 239 | val |= VIDEO_DIP_FREQ_VSYNC; |
45187ace | 240 | |
22509ec8 | 241 | I915_WRITE(reg, val); |
45187ace | 242 | } |
90b107c8 SK |
243 | |
244 | static void vlv_write_infoframe(struct drm_encoder *encoder, | |
245 | struct dip_infoframe *frame) | |
246 | { | |
247 | uint32_t *data = (uint32_t *)frame; | |
248 | struct drm_device *dev = encoder->dev; | |
249 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ed517fbb | 250 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); |
90b107c8 SK |
251 | int reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe); |
252 | unsigned i, len = DIP_HEADER_SIZE + frame->len; | |
22509ec8 | 253 | u32 val = I915_READ(reg); |
90b107c8 SK |
254 | |
255 | intel_wait_for_vblank(dev, intel_crtc->pipe); | |
256 | ||
90b107c8 | 257 | val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ |
bc2481f3 | 258 | val |= g4x_infoframe_index(frame); |
22509ec8 | 259 | |
bc2481f3 | 260 | val &= ~g4x_infoframe_enable(frame); |
22509ec8 | 261 | val |= VIDEO_DIP_ENABLE; |
90b107c8 | 262 | |
22509ec8 | 263 | I915_WRITE(reg, val); |
90b107c8 SK |
264 | |
265 | for (i = 0; i < len; i += 4) { | |
266 | I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), *data); | |
267 | data++; | |
268 | } | |
269 | ||
bc2481f3 | 270 | val |= g4x_infoframe_enable(frame); |
60c5ea2d | 271 | val &= ~VIDEO_DIP_FREQ_MASK; |
4b24c933 | 272 | val |= VIDEO_DIP_FREQ_VSYNC; |
90b107c8 | 273 | |
22509ec8 | 274 | I915_WRITE(reg, val); |
90b107c8 SK |
275 | } |
276 | ||
8c5f5f7c | 277 | static void hsw_write_infoframe(struct drm_encoder *encoder, |
ed517fbb | 278 | struct dip_infoframe *frame) |
8c5f5f7c | 279 | { |
2da8af54 PZ |
280 | uint32_t *data = (uint32_t *)frame; |
281 | struct drm_device *dev = encoder->dev; | |
282 | struct drm_i915_private *dev_priv = dev->dev_private; | |
283 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); | |
284 | u32 ctl_reg = HSW_TVIDEO_DIP_CTL(intel_crtc->pipe); | |
285 | u32 data_reg = hsw_infoframe_data_reg(frame, intel_crtc->pipe); | |
286 | unsigned int i, len = DIP_HEADER_SIZE + frame->len; | |
287 | u32 val = I915_READ(ctl_reg); | |
8c5f5f7c | 288 | |
2da8af54 PZ |
289 | if (data_reg == 0) |
290 | return; | |
291 | ||
292 | intel_wait_for_vblank(dev, intel_crtc->pipe); | |
293 | ||
294 | val &= ~hsw_infoframe_enable(frame); | |
295 | I915_WRITE(ctl_reg, val); | |
296 | ||
297 | for (i = 0; i < len; i += 4) { | |
298 | I915_WRITE(data_reg + i, *data); | |
299 | data++; | |
300 | } | |
8c5f5f7c | 301 | |
2da8af54 PZ |
302 | val |= hsw_infoframe_enable(frame); |
303 | I915_WRITE(ctl_reg, val); | |
8c5f5f7c ED |
304 | } |
305 | ||
45187ace JB |
306 | static void intel_set_infoframe(struct drm_encoder *encoder, |
307 | struct dip_infoframe *frame) | |
308 | { | |
309 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); | |
310 | ||
311 | if (!intel_hdmi->has_hdmi_sink) | |
312 | return; | |
313 | ||
314 | intel_dip_infoframe_csum(frame); | |
315 | intel_hdmi->write_infoframe(encoder, frame); | |
316 | } | |
317 | ||
f5bbfca3 | 318 | void intel_hdmi_set_avi_infoframe(struct drm_encoder *encoder, |
c846b619 | 319 | struct drm_display_mode *adjusted_mode) |
45187ace JB |
320 | { |
321 | struct dip_infoframe avi_if = { | |
322 | .type = DIP_TYPE_AVI, | |
323 | .ver = DIP_VERSION_AVI, | |
324 | .len = DIP_LEN_AVI, | |
325 | }; | |
326 | ||
c846b619 PZ |
327 | if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK) |
328 | avi_if.body.avi.YQ_CN_PR |= DIP_AVI_PR_2; | |
329 | ||
45187ace | 330 | intel_set_infoframe(encoder, &avi_if); |
b055c8f3 JB |
331 | } |
332 | ||
f5bbfca3 | 333 | void intel_hdmi_set_spd_infoframe(struct drm_encoder *encoder) |
c0864cb3 JB |
334 | { |
335 | struct dip_infoframe spd_if; | |
336 | ||
337 | memset(&spd_if, 0, sizeof(spd_if)); | |
338 | spd_if.type = DIP_TYPE_SPD; | |
339 | spd_if.ver = DIP_VERSION_SPD; | |
340 | spd_if.len = DIP_LEN_SPD; | |
341 | strcpy(spd_if.body.spd.vn, "Intel"); | |
342 | strcpy(spd_if.body.spd.pd, "Integrated gfx"); | |
343 | spd_if.body.spd.sdi = DIP_SPD_PC; | |
344 | ||
345 | intel_set_infoframe(encoder, &spd_if); | |
346 | } | |
347 | ||
7d57382e EA |
348 | static void intel_hdmi_mode_set(struct drm_encoder *encoder, |
349 | struct drm_display_mode *mode, | |
350 | struct drm_display_mode *adjusted_mode) | |
351 | { | |
352 | struct drm_device *dev = encoder->dev; | |
353 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ed517fbb | 354 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); |
ea5b213a | 355 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); |
7d57382e EA |
356 | u32 sdvox; |
357 | ||
b599c0bc | 358 | sdvox = SDVO_ENCODING_HDMI | SDVO_BORDER_ENABLE; |
5d4fac97 JB |
359 | if (!HAS_PCH_SPLIT(dev)) |
360 | sdvox |= intel_hdmi->color_range; | |
b599c0bc AJ |
361 | if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) |
362 | sdvox |= SDVO_VSYNC_ACTIVE_HIGH; | |
363 | if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) | |
364 | sdvox |= SDVO_HSYNC_ACTIVE_HIGH; | |
7d57382e | 365 | |
020f6704 JB |
366 | if (intel_crtc->bpp > 24) |
367 | sdvox |= COLOR_FORMAT_12bpc; | |
368 | else | |
369 | sdvox |= COLOR_FORMAT_8bpc; | |
370 | ||
2e3d6006 ZW |
371 | /* Required on CPT */ |
372 | if (intel_hdmi->has_hdmi_sink && HAS_PCH_CPT(dev)) | |
373 | sdvox |= HDMI_MODE_SELECT; | |
374 | ||
3c17fe4b | 375 | if (intel_hdmi->has_audio) { |
e0dac65e WF |
376 | DRM_DEBUG_DRIVER("Enabling HDMI audio on pipe %c\n", |
377 | pipe_name(intel_crtc->pipe)); | |
7d57382e | 378 | sdvox |= SDVO_AUDIO_ENABLE; |
3c17fe4b | 379 | sdvox |= SDVO_NULL_PACKETS_DURING_VSYNC; |
e0dac65e | 380 | intel_write_eld(encoder, adjusted_mode); |
3c17fe4b | 381 | } |
7d57382e | 382 | |
75770564 JB |
383 | if (HAS_PCH_CPT(dev)) |
384 | sdvox |= PORT_TRANS_SEL_CPT(intel_crtc->pipe); | |
385 | else if (intel_crtc->pipe == 1) | |
386 | sdvox |= SDVO_PIPE_B_SELECT; | |
7d57382e | 387 | |
ea5b213a CW |
388 | I915_WRITE(intel_hdmi->sdvox_reg, sdvox); |
389 | POSTING_READ(intel_hdmi->sdvox_reg); | |
3c17fe4b | 390 | |
c846b619 | 391 | intel_hdmi_set_avi_infoframe(encoder, adjusted_mode); |
c0864cb3 | 392 | intel_hdmi_set_spd_infoframe(encoder); |
7d57382e EA |
393 | } |
394 | ||
395 | static void intel_hdmi_dpms(struct drm_encoder *encoder, int mode) | |
396 | { | |
397 | struct drm_device *dev = encoder->dev; | |
398 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ea5b213a | 399 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); |
7d57382e | 400 | u32 temp; |
2deed761 WF |
401 | u32 enable_bits = SDVO_ENABLE; |
402 | ||
403 | if (intel_hdmi->has_audio) | |
404 | enable_bits |= SDVO_AUDIO_ENABLE; | |
7d57382e | 405 | |
ea5b213a | 406 | temp = I915_READ(intel_hdmi->sdvox_reg); |
d8a2d0e0 ZW |
407 | |
408 | /* HW workaround, need to toggle enable bit off and on for 12bpc, but | |
409 | * we do this anyway which shows more stable in testing. | |
410 | */ | |
c619eed4 | 411 | if (HAS_PCH_SPLIT(dev)) { |
ea5b213a CW |
412 | I915_WRITE(intel_hdmi->sdvox_reg, temp & ~SDVO_ENABLE); |
413 | POSTING_READ(intel_hdmi->sdvox_reg); | |
d8a2d0e0 ZW |
414 | } |
415 | ||
416 | if (mode != DRM_MODE_DPMS_ON) { | |
2deed761 | 417 | temp &= ~enable_bits; |
7d57382e | 418 | } else { |
2deed761 | 419 | temp |= enable_bits; |
7d57382e | 420 | } |
d8a2d0e0 | 421 | |
ea5b213a CW |
422 | I915_WRITE(intel_hdmi->sdvox_reg, temp); |
423 | POSTING_READ(intel_hdmi->sdvox_reg); | |
d8a2d0e0 ZW |
424 | |
425 | /* HW workaround, need to write this twice for issue that may result | |
426 | * in first write getting masked. | |
427 | */ | |
c619eed4 | 428 | if (HAS_PCH_SPLIT(dev)) { |
ea5b213a CW |
429 | I915_WRITE(intel_hdmi->sdvox_reg, temp); |
430 | POSTING_READ(intel_hdmi->sdvox_reg); | |
d8a2d0e0 | 431 | } |
7d57382e EA |
432 | } |
433 | ||
7d57382e EA |
434 | static int intel_hdmi_mode_valid(struct drm_connector *connector, |
435 | struct drm_display_mode *mode) | |
436 | { | |
437 | if (mode->clock > 165000) | |
438 | return MODE_CLOCK_HIGH; | |
439 | if (mode->clock < 20000) | |
5cbba41d | 440 | return MODE_CLOCK_LOW; |
7d57382e EA |
441 | |
442 | if (mode->flags & DRM_MODE_FLAG_DBLSCAN) | |
443 | return MODE_NO_DBLESCAN; | |
444 | ||
445 | return MODE_OK; | |
446 | } | |
447 | ||
448 | static bool intel_hdmi_mode_fixup(struct drm_encoder *encoder, | |
449 | struct drm_display_mode *mode, | |
450 | struct drm_display_mode *adjusted_mode) | |
451 | { | |
452 | return true; | |
453 | } | |
454 | ||
aa93d632 | 455 | static enum drm_connector_status |
930a9e28 | 456 | intel_hdmi_detect(struct drm_connector *connector, bool force) |
9dff6af8 | 457 | { |
df0e9248 | 458 | struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); |
f899fc64 CW |
459 | struct drm_i915_private *dev_priv = connector->dev->dev_private; |
460 | struct edid *edid; | |
aa93d632 | 461 | enum drm_connector_status status = connector_status_disconnected; |
9dff6af8 | 462 | |
ea5b213a | 463 | intel_hdmi->has_hdmi_sink = false; |
2e3d6006 | 464 | intel_hdmi->has_audio = false; |
f899fc64 | 465 | edid = drm_get_edid(connector, |
3bd7d909 DK |
466 | intel_gmbus_get_adapter(dev_priv, |
467 | intel_hdmi->ddc_bus)); | |
2ded9e27 | 468 | |
aa93d632 | 469 | if (edid) { |
be9f1c4f | 470 | if (edid->input & DRM_EDID_INPUT_DIGITAL) { |
aa93d632 | 471 | status = connector_status_connected; |
b1d7e4b4 WF |
472 | if (intel_hdmi->force_audio != HDMI_AUDIO_OFF_DVI) |
473 | intel_hdmi->has_hdmi_sink = | |
474 | drm_detect_hdmi_monitor(edid); | |
2e3d6006 | 475 | intel_hdmi->has_audio = drm_detect_monitor_audio(edid); |
aa93d632 | 476 | } |
674e2d08 | 477 | connector->display_info.raw_edid = NULL; |
aa93d632 | 478 | kfree(edid); |
9dff6af8 | 479 | } |
30ad48b7 | 480 | |
55b7d6e8 | 481 | if (status == connector_status_connected) { |
b1d7e4b4 WF |
482 | if (intel_hdmi->force_audio != HDMI_AUDIO_AUTO) |
483 | intel_hdmi->has_audio = | |
484 | (intel_hdmi->force_audio == HDMI_AUDIO_ON); | |
55b7d6e8 CW |
485 | } |
486 | ||
2ded9e27 | 487 | return status; |
7d57382e EA |
488 | } |
489 | ||
490 | static int intel_hdmi_get_modes(struct drm_connector *connector) | |
491 | { | |
df0e9248 | 492 | struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); |
f899fc64 | 493 | struct drm_i915_private *dev_priv = connector->dev->dev_private; |
7d57382e EA |
494 | |
495 | /* We should parse the EDID data and find out if it's an HDMI sink so | |
496 | * we can send audio to it. | |
497 | */ | |
498 | ||
f899fc64 | 499 | return intel_ddc_get_modes(connector, |
3bd7d909 DK |
500 | intel_gmbus_get_adapter(dev_priv, |
501 | intel_hdmi->ddc_bus)); | |
7d57382e EA |
502 | } |
503 | ||
1aad7ac0 CW |
504 | static bool |
505 | intel_hdmi_detect_audio(struct drm_connector *connector) | |
506 | { | |
507 | struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); | |
508 | struct drm_i915_private *dev_priv = connector->dev->dev_private; | |
509 | struct edid *edid; | |
510 | bool has_audio = false; | |
511 | ||
512 | edid = drm_get_edid(connector, | |
3bd7d909 DK |
513 | intel_gmbus_get_adapter(dev_priv, |
514 | intel_hdmi->ddc_bus)); | |
1aad7ac0 CW |
515 | if (edid) { |
516 | if (edid->input & DRM_EDID_INPUT_DIGITAL) | |
517 | has_audio = drm_detect_monitor_audio(edid); | |
518 | ||
519 | connector->display_info.raw_edid = NULL; | |
520 | kfree(edid); | |
521 | } | |
522 | ||
523 | return has_audio; | |
524 | } | |
525 | ||
55b7d6e8 CW |
526 | static int |
527 | intel_hdmi_set_property(struct drm_connector *connector, | |
ed517fbb PZ |
528 | struct drm_property *property, |
529 | uint64_t val) | |
55b7d6e8 CW |
530 | { |
531 | struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); | |
e953fd7b | 532 | struct drm_i915_private *dev_priv = connector->dev->dev_private; |
55b7d6e8 CW |
533 | int ret; |
534 | ||
535 | ret = drm_connector_property_set_value(connector, property, val); | |
536 | if (ret) | |
537 | return ret; | |
538 | ||
3f43c48d | 539 | if (property == dev_priv->force_audio_property) { |
b1d7e4b4 | 540 | enum hdmi_force_audio i = val; |
1aad7ac0 CW |
541 | bool has_audio; |
542 | ||
543 | if (i == intel_hdmi->force_audio) | |
55b7d6e8 CW |
544 | return 0; |
545 | ||
1aad7ac0 | 546 | intel_hdmi->force_audio = i; |
55b7d6e8 | 547 | |
b1d7e4b4 | 548 | if (i == HDMI_AUDIO_AUTO) |
1aad7ac0 CW |
549 | has_audio = intel_hdmi_detect_audio(connector); |
550 | else | |
b1d7e4b4 | 551 | has_audio = (i == HDMI_AUDIO_ON); |
1aad7ac0 | 552 | |
b1d7e4b4 WF |
553 | if (i == HDMI_AUDIO_OFF_DVI) |
554 | intel_hdmi->has_hdmi_sink = 0; | |
55b7d6e8 | 555 | |
1aad7ac0 | 556 | intel_hdmi->has_audio = has_audio; |
55b7d6e8 CW |
557 | goto done; |
558 | } | |
559 | ||
e953fd7b CW |
560 | if (property == dev_priv->broadcast_rgb_property) { |
561 | if (val == !!intel_hdmi->color_range) | |
562 | return 0; | |
563 | ||
564 | intel_hdmi->color_range = val ? SDVO_COLOR_RANGE_16_235 : 0; | |
565 | goto done; | |
566 | } | |
567 | ||
55b7d6e8 CW |
568 | return -EINVAL; |
569 | ||
570 | done: | |
571 | if (intel_hdmi->base.base.crtc) { | |
572 | struct drm_crtc *crtc = intel_hdmi->base.base.crtc; | |
573 | drm_crtc_helper_set_mode(crtc, &crtc->mode, | |
574 | crtc->x, crtc->y, | |
575 | crtc->fb); | |
576 | } | |
577 | ||
578 | return 0; | |
579 | } | |
580 | ||
7d57382e EA |
581 | static void intel_hdmi_destroy(struct drm_connector *connector) |
582 | { | |
7d57382e EA |
583 | drm_sysfs_connector_remove(connector); |
584 | drm_connector_cleanup(connector); | |
674e2d08 | 585 | kfree(connector); |
7d57382e EA |
586 | } |
587 | ||
72662e10 ED |
588 | static const struct drm_encoder_helper_funcs intel_hdmi_helper_funcs_hsw = { |
589 | .dpms = intel_ddi_dpms, | |
590 | .mode_fixup = intel_hdmi_mode_fixup, | |
591 | .prepare = intel_encoder_prepare, | |
592 | .mode_set = intel_ddi_mode_set, | |
593 | .commit = intel_encoder_commit, | |
594 | }; | |
595 | ||
7d57382e EA |
596 | static const struct drm_encoder_helper_funcs intel_hdmi_helper_funcs = { |
597 | .dpms = intel_hdmi_dpms, | |
598 | .mode_fixup = intel_hdmi_mode_fixup, | |
599 | .prepare = intel_encoder_prepare, | |
600 | .mode_set = intel_hdmi_mode_set, | |
601 | .commit = intel_encoder_commit, | |
602 | }; | |
603 | ||
604 | static const struct drm_connector_funcs intel_hdmi_connector_funcs = { | |
c9fb15f6 | 605 | .dpms = drm_helper_connector_dpms, |
7d57382e EA |
606 | .detect = intel_hdmi_detect, |
607 | .fill_modes = drm_helper_probe_single_connector_modes, | |
55b7d6e8 | 608 | .set_property = intel_hdmi_set_property, |
7d57382e EA |
609 | .destroy = intel_hdmi_destroy, |
610 | }; | |
611 | ||
612 | static const struct drm_connector_helper_funcs intel_hdmi_connector_helper_funcs = { | |
613 | .get_modes = intel_hdmi_get_modes, | |
614 | .mode_valid = intel_hdmi_mode_valid, | |
df0e9248 | 615 | .best_encoder = intel_best_encoder, |
7d57382e EA |
616 | }; |
617 | ||
7d57382e | 618 | static const struct drm_encoder_funcs intel_hdmi_enc_funcs = { |
ea5b213a | 619 | .destroy = intel_encoder_destroy, |
7d57382e EA |
620 | }; |
621 | ||
55b7d6e8 CW |
622 | static void |
623 | intel_hdmi_add_properties(struct intel_hdmi *intel_hdmi, struct drm_connector *connector) | |
624 | { | |
3f43c48d | 625 | intel_attach_force_audio_property(connector); |
e953fd7b | 626 | intel_attach_broadcast_rgb_property(connector); |
55b7d6e8 CW |
627 | } |
628 | ||
7d57382e EA |
629 | void intel_hdmi_init(struct drm_device *dev, int sdvox_reg) |
630 | { | |
631 | struct drm_i915_private *dev_priv = dev->dev_private; | |
632 | struct drm_connector *connector; | |
21d40d37 | 633 | struct intel_encoder *intel_encoder; |
674e2d08 | 634 | struct intel_connector *intel_connector; |
ea5b213a | 635 | struct intel_hdmi *intel_hdmi; |
64a8fc01 | 636 | int i; |
7d57382e | 637 | |
ea5b213a CW |
638 | intel_hdmi = kzalloc(sizeof(struct intel_hdmi), GFP_KERNEL); |
639 | if (!intel_hdmi) | |
7d57382e | 640 | return; |
674e2d08 ZW |
641 | |
642 | intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL); | |
643 | if (!intel_connector) { | |
ea5b213a | 644 | kfree(intel_hdmi); |
674e2d08 ZW |
645 | return; |
646 | } | |
647 | ||
ea5b213a | 648 | intel_encoder = &intel_hdmi->base; |
373a3cf7 CW |
649 | drm_encoder_init(dev, &intel_encoder->base, &intel_hdmi_enc_funcs, |
650 | DRM_MODE_ENCODER_TMDS); | |
651 | ||
674e2d08 | 652 | connector = &intel_connector->base; |
7d57382e | 653 | drm_connector_init(dev, connector, &intel_hdmi_connector_funcs, |
8d91104a | 654 | DRM_MODE_CONNECTOR_HDMIA); |
7d57382e EA |
655 | drm_connector_helper_add(connector, &intel_hdmi_connector_helper_funcs); |
656 | ||
21d40d37 | 657 | intel_encoder->type = INTEL_OUTPUT_HDMI; |
7d57382e | 658 | |
eb1f8e4f | 659 | connector->polled = DRM_CONNECTOR_POLL_HPD; |
c3febcc4 | 660 | connector->interlace_allowed = 1; |
7d57382e | 661 | connector->doublescan_allowed = 0; |
27f8227b | 662 | intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2); |
7d57382e EA |
663 | |
664 | /* Set up the DDC bus. */ | |
f8aed700 | 665 | if (sdvox_reg == SDVOB) { |
21d40d37 | 666 | intel_encoder->clone_mask = (1 << INTEL_HDMIB_CLONE_BIT); |
f899fc64 | 667 | intel_hdmi->ddc_bus = GMBUS_PORT_DPB; |
b01f2c3a | 668 | dev_priv->hotplug_supported_mask |= HDMIB_HOTPLUG_INT_STATUS; |
f8aed700 | 669 | } else if (sdvox_reg == SDVOC) { |
21d40d37 | 670 | intel_encoder->clone_mask = (1 << INTEL_HDMIC_CLONE_BIT); |
f899fc64 | 671 | intel_hdmi->ddc_bus = GMBUS_PORT_DPC; |
b01f2c3a | 672 | dev_priv->hotplug_supported_mask |= HDMIC_HOTPLUG_INT_STATUS; |
f8aed700 | 673 | } else if (sdvox_reg == HDMIB) { |
21d40d37 | 674 | intel_encoder->clone_mask = (1 << INTEL_HDMID_CLONE_BIT); |
f899fc64 | 675 | intel_hdmi->ddc_bus = GMBUS_PORT_DPB; |
b01f2c3a | 676 | dev_priv->hotplug_supported_mask |= HDMIB_HOTPLUG_INT_STATUS; |
f8aed700 | 677 | } else if (sdvox_reg == HDMIC) { |
21d40d37 | 678 | intel_encoder->clone_mask = (1 << INTEL_HDMIE_CLONE_BIT); |
f899fc64 | 679 | intel_hdmi->ddc_bus = GMBUS_PORT_DPC; |
b01f2c3a | 680 | dev_priv->hotplug_supported_mask |= HDMIC_HOTPLUG_INT_STATUS; |
f8aed700 | 681 | } else if (sdvox_reg == HDMID) { |
21d40d37 | 682 | intel_encoder->clone_mask = (1 << INTEL_HDMIF_CLONE_BIT); |
f899fc64 | 683 | intel_hdmi->ddc_bus = GMBUS_PORT_DPD; |
b01f2c3a | 684 | dev_priv->hotplug_supported_mask |= HDMID_HOTPLUG_INT_STATUS; |
7ceae0a5 ED |
685 | } else if (sdvox_reg == DDI_BUF_CTL(PORT_B)) { |
686 | DRM_DEBUG_DRIVER("LPT: detected output on DDI B\n"); | |
687 | intel_encoder->clone_mask = (1 << INTEL_HDMIB_CLONE_BIT); | |
688 | intel_hdmi->ddc_bus = GMBUS_PORT_DPB; | |
689 | intel_hdmi->ddi_port = PORT_B; | |
690 | dev_priv->hotplug_supported_mask |= HDMIB_HOTPLUG_INT_STATUS; | |
691 | } else if (sdvox_reg == DDI_BUF_CTL(PORT_C)) { | |
692 | DRM_DEBUG_DRIVER("LPT: detected output on DDI C\n"); | |
693 | intel_encoder->clone_mask = (1 << INTEL_HDMIC_CLONE_BIT); | |
694 | intel_hdmi->ddc_bus = GMBUS_PORT_DPC; | |
695 | intel_hdmi->ddi_port = PORT_C; | |
696 | dev_priv->hotplug_supported_mask |= HDMIC_HOTPLUG_INT_STATUS; | |
697 | } else if (sdvox_reg == DDI_BUF_CTL(PORT_D)) { | |
698 | DRM_DEBUG_DRIVER("LPT: detected output on DDI D\n"); | |
699 | intel_encoder->clone_mask = (1 << INTEL_HDMID_CLONE_BIT); | |
700 | intel_hdmi->ddc_bus = GMBUS_PORT_DPD; | |
701 | intel_hdmi->ddi_port = PORT_D; | |
702 | dev_priv->hotplug_supported_mask |= HDMID_HOTPLUG_INT_STATUS; | |
6e4c1677 ED |
703 | } else { |
704 | /* If we got an unknown sdvox_reg, things are pretty much broken | |
705 | * in a way that we should let the kernel know about it */ | |
706 | BUG(); | |
f8aed700 | 707 | } |
7d57382e | 708 | |
ea5b213a | 709 | intel_hdmi->sdvox_reg = sdvox_reg; |
7d57382e | 710 | |
64a8fc01 | 711 | if (!HAS_PCH_SPLIT(dev)) { |
a3da1df7 | 712 | intel_hdmi->write_infoframe = g4x_write_infoframe; |
64a8fc01 | 713 | I915_WRITE(VIDEO_DIP_CTL, 0); |
90b107c8 SK |
714 | } else if (IS_VALLEYVIEW(dev)) { |
715 | intel_hdmi->write_infoframe = vlv_write_infoframe; | |
716 | for_each_pipe(i) | |
717 | I915_WRITE(VLV_TVIDEO_DIP_CTL(i), 0); | |
8c5f5f7c ED |
718 | } else if (IS_HASWELL(dev)) { |
719 | /* FIXME: Haswell has a new set of DIP frame registers, but we are | |
720 | * just doing the minimal required for HDMI to work at this stage. | |
721 | */ | |
722 | intel_hdmi->write_infoframe = hsw_write_infoframe; | |
723 | for_each_pipe(i) | |
724 | I915_WRITE(HSW_TVIDEO_DIP_CTL(i), 0); | |
fdf1250a PZ |
725 | } else if (HAS_PCH_IBX(dev)) { |
726 | intel_hdmi->write_infoframe = ibx_write_infoframe; | |
727 | for_each_pipe(i) | |
728 | I915_WRITE(TVIDEO_DIP_CTL(i), 0); | |
729 | } else { | |
730 | intel_hdmi->write_infoframe = cpt_write_infoframe; | |
64a8fc01 JB |
731 | for_each_pipe(i) |
732 | I915_WRITE(TVIDEO_DIP_CTL(i), 0); | |
733 | } | |
45187ace | 734 | |
72662e10 ED |
735 | if (IS_HASWELL(dev)) |
736 | drm_encoder_helper_add(&intel_encoder->base, &intel_hdmi_helper_funcs_hsw); | |
737 | else | |
738 | drm_encoder_helper_add(&intel_encoder->base, &intel_hdmi_helper_funcs); | |
7d57382e | 739 | |
55b7d6e8 CW |
740 | intel_hdmi_add_properties(intel_hdmi, connector); |
741 | ||
df0e9248 | 742 | intel_connector_attach_encoder(intel_connector, intel_encoder); |
7d57382e EA |
743 | drm_sysfs_connector_add(connector); |
744 | ||
745 | /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written | |
746 | * 0xd. Failure to do so will result in spurious interrupts being | |
747 | * generated on the port when a cable is not attached. | |
748 | */ | |
749 | if (IS_G4X(dev) && !IS_GM45(dev)) { | |
750 | u32 temp = I915_READ(PEG_BAND_GAP_DATA); | |
751 | I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd); | |
752 | } | |
7d57382e | 753 | } |