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7d57382e EA |
1 | /* |
2 | * Copyright 2006 Dave Airlie <airlied@linux.ie> | |
3 | * Copyright © 2006-2009 Intel Corporation | |
4 | * | |
5 | * Permission is hereby granted, free of charge, to any person obtaining a | |
6 | * copy of this software and associated documentation files (the "Software"), | |
7 | * to deal in the Software without restriction, including without limitation | |
8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
9 | * and/or sell copies of the Software, and to permit persons to whom the | |
10 | * Software is furnished to do so, subject to the following conditions: | |
11 | * | |
12 | * The above copyright notice and this permission notice (including the next | |
13 | * paragraph) shall be included in all copies or substantial portions of the | |
14 | * Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
21 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
22 | * DEALINGS IN THE SOFTWARE. | |
23 | * | |
24 | * Authors: | |
25 | * Eric Anholt <eric@anholt.net> | |
26 | * Jesse Barnes <jesse.barnes@intel.com> | |
27 | */ | |
28 | ||
29 | #include <linux/i2c.h> | |
5a0e3ad6 | 30 | #include <linux/slab.h> |
7d57382e | 31 | #include <linux/delay.h> |
178f736a | 32 | #include <linux/hdmi.h> |
760285e7 DH |
33 | #include <drm/drmP.h> |
34 | #include <drm/drm_crtc.h> | |
35 | #include <drm/drm_edid.h> | |
7d57382e | 36 | #include "intel_drv.h" |
760285e7 | 37 | #include <drm/i915_drm.h> |
7d57382e EA |
38 | #include "i915_drv.h" |
39 | ||
30add22d PZ |
40 | static struct drm_device *intel_hdmi_to_dev(struct intel_hdmi *intel_hdmi) |
41 | { | |
da63a9f2 | 42 | return hdmi_to_dig_port(intel_hdmi)->base.base.dev; |
30add22d PZ |
43 | } |
44 | ||
afba0188 DV |
45 | static void |
46 | assert_hdmi_port_disabled(struct intel_hdmi *intel_hdmi) | |
47 | { | |
30add22d | 48 | struct drm_device *dev = intel_hdmi_to_dev(intel_hdmi); |
afba0188 DV |
49 | struct drm_i915_private *dev_priv = dev->dev_private; |
50 | uint32_t enabled_bits; | |
51 | ||
affa9354 | 52 | enabled_bits = HAS_DDI(dev) ? DDI_BUF_CTL_ENABLE : SDVO_ENABLE; |
afba0188 | 53 | |
b242b7f7 | 54 | WARN(I915_READ(intel_hdmi->hdmi_reg) & enabled_bits, |
afba0188 DV |
55 | "HDMI port enabled, expecting disabled\n"); |
56 | } | |
57 | ||
f5bbfca3 | 58 | struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder) |
ea5b213a | 59 | { |
da63a9f2 PZ |
60 | struct intel_digital_port *intel_dig_port = |
61 | container_of(encoder, struct intel_digital_port, base.base); | |
62 | return &intel_dig_port->hdmi; | |
ea5b213a CW |
63 | } |
64 | ||
df0e9248 CW |
65 | static struct intel_hdmi *intel_attached_hdmi(struct drm_connector *connector) |
66 | { | |
da63a9f2 | 67 | return enc_to_intel_hdmi(&intel_attached_encoder(connector)->base); |
df0e9248 CW |
68 | } |
69 | ||
178f736a | 70 | static u32 g4x_infoframe_index(enum hdmi_infoframe_type type) |
3c17fe4b | 71 | { |
178f736a DL |
72 | switch (type) { |
73 | case HDMI_INFOFRAME_TYPE_AVI: | |
ed517fbb | 74 | return VIDEO_DIP_SELECT_AVI; |
178f736a | 75 | case HDMI_INFOFRAME_TYPE_SPD: |
ed517fbb | 76 | return VIDEO_DIP_SELECT_SPD; |
c8bb75af LD |
77 | case HDMI_INFOFRAME_TYPE_VENDOR: |
78 | return VIDEO_DIP_SELECT_VENDOR; | |
45187ace | 79 | default: |
178f736a | 80 | DRM_DEBUG_DRIVER("unknown info frame type %d\n", type); |
ed517fbb | 81 | return 0; |
45187ace | 82 | } |
45187ace JB |
83 | } |
84 | ||
178f736a | 85 | static u32 g4x_infoframe_enable(enum hdmi_infoframe_type type) |
45187ace | 86 | { |
178f736a DL |
87 | switch (type) { |
88 | case HDMI_INFOFRAME_TYPE_AVI: | |
ed517fbb | 89 | return VIDEO_DIP_ENABLE_AVI; |
178f736a | 90 | case HDMI_INFOFRAME_TYPE_SPD: |
ed517fbb | 91 | return VIDEO_DIP_ENABLE_SPD; |
c8bb75af LD |
92 | case HDMI_INFOFRAME_TYPE_VENDOR: |
93 | return VIDEO_DIP_ENABLE_VENDOR; | |
fa193ff7 | 94 | default: |
178f736a | 95 | DRM_DEBUG_DRIVER("unknown info frame type %d\n", type); |
ed517fbb | 96 | return 0; |
fa193ff7 | 97 | } |
fa193ff7 PZ |
98 | } |
99 | ||
178f736a | 100 | static u32 hsw_infoframe_enable(enum hdmi_infoframe_type type) |
2da8af54 | 101 | { |
178f736a DL |
102 | switch (type) { |
103 | case HDMI_INFOFRAME_TYPE_AVI: | |
2da8af54 | 104 | return VIDEO_DIP_ENABLE_AVI_HSW; |
178f736a | 105 | case HDMI_INFOFRAME_TYPE_SPD: |
2da8af54 | 106 | return VIDEO_DIP_ENABLE_SPD_HSW; |
c8bb75af LD |
107 | case HDMI_INFOFRAME_TYPE_VENDOR: |
108 | return VIDEO_DIP_ENABLE_VS_HSW; | |
2da8af54 | 109 | default: |
178f736a | 110 | DRM_DEBUG_DRIVER("unknown info frame type %d\n", type); |
2da8af54 PZ |
111 | return 0; |
112 | } | |
113 | } | |
114 | ||
178f736a | 115 | static u32 hsw_infoframe_data_reg(enum hdmi_infoframe_type type, |
7d9bcebe | 116 | enum transcoder cpu_transcoder) |
2da8af54 | 117 | { |
178f736a DL |
118 | switch (type) { |
119 | case HDMI_INFOFRAME_TYPE_AVI: | |
7d9bcebe | 120 | return HSW_TVIDEO_DIP_AVI_DATA(cpu_transcoder); |
178f736a | 121 | case HDMI_INFOFRAME_TYPE_SPD: |
7d9bcebe | 122 | return HSW_TVIDEO_DIP_SPD_DATA(cpu_transcoder); |
c8bb75af LD |
123 | case HDMI_INFOFRAME_TYPE_VENDOR: |
124 | return HSW_TVIDEO_DIP_VS_DATA(cpu_transcoder); | |
2da8af54 | 125 | default: |
178f736a | 126 | DRM_DEBUG_DRIVER("unknown info frame type %d\n", type); |
2da8af54 PZ |
127 | return 0; |
128 | } | |
129 | } | |
130 | ||
a3da1df7 | 131 | static void g4x_write_infoframe(struct drm_encoder *encoder, |
178f736a DL |
132 | enum hdmi_infoframe_type type, |
133 | const uint8_t *frame, ssize_t len) | |
45187ace JB |
134 | { |
135 | uint32_t *data = (uint32_t *)frame; | |
3c17fe4b DH |
136 | struct drm_device *dev = encoder->dev; |
137 | struct drm_i915_private *dev_priv = dev->dev_private; | |
22509ec8 | 138 | u32 val = I915_READ(VIDEO_DIP_CTL); |
178f736a | 139 | int i; |
3c17fe4b | 140 | |
822974ae PZ |
141 | WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n"); |
142 | ||
1d4f85ac | 143 | val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ |
178f736a | 144 | val |= g4x_infoframe_index(type); |
22509ec8 | 145 | |
178f736a | 146 | val &= ~g4x_infoframe_enable(type); |
45187ace | 147 | |
22509ec8 | 148 | I915_WRITE(VIDEO_DIP_CTL, val); |
3c17fe4b | 149 | |
9d9740f0 | 150 | mmiowb(); |
45187ace | 151 | for (i = 0; i < len; i += 4) { |
3c17fe4b DH |
152 | I915_WRITE(VIDEO_DIP_DATA, *data); |
153 | data++; | |
154 | } | |
adf00b26 PZ |
155 | /* Write every possible data byte to force correct ECC calculation. */ |
156 | for (; i < VIDEO_DIP_DATA_SIZE; i += 4) | |
157 | I915_WRITE(VIDEO_DIP_DATA, 0); | |
9d9740f0 | 158 | mmiowb(); |
3c17fe4b | 159 | |
178f736a | 160 | val |= g4x_infoframe_enable(type); |
60c5ea2d | 161 | val &= ~VIDEO_DIP_FREQ_MASK; |
4b24c933 | 162 | val |= VIDEO_DIP_FREQ_VSYNC; |
45187ace | 163 | |
22509ec8 | 164 | I915_WRITE(VIDEO_DIP_CTL, val); |
9d9740f0 | 165 | POSTING_READ(VIDEO_DIP_CTL); |
3c17fe4b DH |
166 | } |
167 | ||
fdf1250a | 168 | static void ibx_write_infoframe(struct drm_encoder *encoder, |
178f736a DL |
169 | enum hdmi_infoframe_type type, |
170 | const uint8_t *frame, ssize_t len) | |
fdf1250a PZ |
171 | { |
172 | uint32_t *data = (uint32_t *)frame; | |
173 | struct drm_device *dev = encoder->dev; | |
174 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ed517fbb | 175 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); |
178f736a | 176 | int i, reg = TVIDEO_DIP_CTL(intel_crtc->pipe); |
fdf1250a PZ |
177 | u32 val = I915_READ(reg); |
178 | ||
822974ae PZ |
179 | WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n"); |
180 | ||
fdf1250a | 181 | val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ |
178f736a | 182 | val |= g4x_infoframe_index(type); |
fdf1250a | 183 | |
178f736a | 184 | val &= ~g4x_infoframe_enable(type); |
fdf1250a PZ |
185 | |
186 | I915_WRITE(reg, val); | |
187 | ||
9d9740f0 | 188 | mmiowb(); |
fdf1250a PZ |
189 | for (i = 0; i < len; i += 4) { |
190 | I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data); | |
191 | data++; | |
192 | } | |
adf00b26 PZ |
193 | /* Write every possible data byte to force correct ECC calculation. */ |
194 | for (; i < VIDEO_DIP_DATA_SIZE; i += 4) | |
195 | I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0); | |
9d9740f0 | 196 | mmiowb(); |
fdf1250a | 197 | |
178f736a | 198 | val |= g4x_infoframe_enable(type); |
fdf1250a | 199 | val &= ~VIDEO_DIP_FREQ_MASK; |
4b24c933 | 200 | val |= VIDEO_DIP_FREQ_VSYNC; |
fdf1250a PZ |
201 | |
202 | I915_WRITE(reg, val); | |
9d9740f0 | 203 | POSTING_READ(reg); |
fdf1250a PZ |
204 | } |
205 | ||
206 | static void cpt_write_infoframe(struct drm_encoder *encoder, | |
178f736a DL |
207 | enum hdmi_infoframe_type type, |
208 | const uint8_t *frame, ssize_t len) | |
b055c8f3 | 209 | { |
45187ace | 210 | uint32_t *data = (uint32_t *)frame; |
b055c8f3 JB |
211 | struct drm_device *dev = encoder->dev; |
212 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ed517fbb | 213 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); |
178f736a | 214 | int i, reg = TVIDEO_DIP_CTL(intel_crtc->pipe); |
22509ec8 | 215 | u32 val = I915_READ(reg); |
b055c8f3 | 216 | |
822974ae PZ |
217 | WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n"); |
218 | ||
64a8fc01 | 219 | val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ |
178f736a | 220 | val |= g4x_infoframe_index(type); |
45187ace | 221 | |
ecb97851 PZ |
222 | /* The DIP control register spec says that we need to update the AVI |
223 | * infoframe without clearing its enable bit */ | |
178f736a DL |
224 | if (type != HDMI_INFOFRAME_TYPE_AVI) |
225 | val &= ~g4x_infoframe_enable(type); | |
ecb97851 | 226 | |
22509ec8 | 227 | I915_WRITE(reg, val); |
45187ace | 228 | |
9d9740f0 | 229 | mmiowb(); |
45187ace | 230 | for (i = 0; i < len; i += 4) { |
b055c8f3 JB |
231 | I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data); |
232 | data++; | |
233 | } | |
adf00b26 PZ |
234 | /* Write every possible data byte to force correct ECC calculation. */ |
235 | for (; i < VIDEO_DIP_DATA_SIZE; i += 4) | |
236 | I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0); | |
9d9740f0 | 237 | mmiowb(); |
b055c8f3 | 238 | |
178f736a | 239 | val |= g4x_infoframe_enable(type); |
60c5ea2d | 240 | val &= ~VIDEO_DIP_FREQ_MASK; |
4b24c933 | 241 | val |= VIDEO_DIP_FREQ_VSYNC; |
45187ace | 242 | |
22509ec8 | 243 | I915_WRITE(reg, val); |
9d9740f0 | 244 | POSTING_READ(reg); |
45187ace | 245 | } |
90b107c8 SK |
246 | |
247 | static void vlv_write_infoframe(struct drm_encoder *encoder, | |
178f736a DL |
248 | enum hdmi_infoframe_type type, |
249 | const uint8_t *frame, ssize_t len) | |
90b107c8 SK |
250 | { |
251 | uint32_t *data = (uint32_t *)frame; | |
252 | struct drm_device *dev = encoder->dev; | |
253 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ed517fbb | 254 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); |
178f736a | 255 | int i, reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe); |
22509ec8 | 256 | u32 val = I915_READ(reg); |
90b107c8 | 257 | |
822974ae PZ |
258 | WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n"); |
259 | ||
90b107c8 | 260 | val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ |
178f736a | 261 | val |= g4x_infoframe_index(type); |
22509ec8 | 262 | |
178f736a | 263 | val &= ~g4x_infoframe_enable(type); |
90b107c8 | 264 | |
22509ec8 | 265 | I915_WRITE(reg, val); |
90b107c8 | 266 | |
9d9740f0 | 267 | mmiowb(); |
90b107c8 SK |
268 | for (i = 0; i < len; i += 4) { |
269 | I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), *data); | |
270 | data++; | |
271 | } | |
adf00b26 PZ |
272 | /* Write every possible data byte to force correct ECC calculation. */ |
273 | for (; i < VIDEO_DIP_DATA_SIZE; i += 4) | |
274 | I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), 0); | |
9d9740f0 | 275 | mmiowb(); |
90b107c8 | 276 | |
178f736a | 277 | val |= g4x_infoframe_enable(type); |
60c5ea2d | 278 | val &= ~VIDEO_DIP_FREQ_MASK; |
4b24c933 | 279 | val |= VIDEO_DIP_FREQ_VSYNC; |
90b107c8 | 280 | |
22509ec8 | 281 | I915_WRITE(reg, val); |
9d9740f0 | 282 | POSTING_READ(reg); |
90b107c8 SK |
283 | } |
284 | ||
8c5f5f7c | 285 | static void hsw_write_infoframe(struct drm_encoder *encoder, |
178f736a DL |
286 | enum hdmi_infoframe_type type, |
287 | const uint8_t *frame, ssize_t len) | |
8c5f5f7c | 288 | { |
2da8af54 PZ |
289 | uint32_t *data = (uint32_t *)frame; |
290 | struct drm_device *dev = encoder->dev; | |
291 | struct drm_i915_private *dev_priv = dev->dev_private; | |
292 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); | |
3b117c8f | 293 | u32 ctl_reg = HSW_TVIDEO_DIP_CTL(intel_crtc->config.cpu_transcoder); |
178f736a DL |
294 | u32 data_reg; |
295 | int i; | |
2da8af54 | 296 | u32 val = I915_READ(ctl_reg); |
8c5f5f7c | 297 | |
178f736a DL |
298 | data_reg = hsw_infoframe_data_reg(type, |
299 | intel_crtc->config.cpu_transcoder); | |
2da8af54 PZ |
300 | if (data_reg == 0) |
301 | return; | |
302 | ||
178f736a | 303 | val &= ~hsw_infoframe_enable(type); |
2da8af54 PZ |
304 | I915_WRITE(ctl_reg, val); |
305 | ||
9d9740f0 | 306 | mmiowb(); |
2da8af54 PZ |
307 | for (i = 0; i < len; i += 4) { |
308 | I915_WRITE(data_reg + i, *data); | |
309 | data++; | |
310 | } | |
adf00b26 PZ |
311 | /* Write every possible data byte to force correct ECC calculation. */ |
312 | for (; i < VIDEO_DIP_DATA_SIZE; i += 4) | |
313 | I915_WRITE(data_reg + i, 0); | |
9d9740f0 | 314 | mmiowb(); |
8c5f5f7c | 315 | |
178f736a | 316 | val |= hsw_infoframe_enable(type); |
2da8af54 | 317 | I915_WRITE(ctl_reg, val); |
9d9740f0 | 318 | POSTING_READ(ctl_reg); |
8c5f5f7c ED |
319 | } |
320 | ||
5adaea79 DL |
321 | /* |
322 | * The data we write to the DIP data buffer registers is 1 byte bigger than the | |
323 | * HDMI infoframe size because of an ECC/reserved byte at position 3 (starting | |
324 | * at 0). It's also a byte used by DisplayPort so the same DIP registers can be | |
325 | * used for both technologies. | |
326 | * | |
327 | * DW0: Reserved/ECC/DP | HB2 | HB1 | HB0 | |
328 | * DW1: DB3 | DB2 | DB1 | DB0 | |
329 | * DW2: DB7 | DB6 | DB5 | DB4 | |
330 | * DW3: ... | |
331 | * | |
332 | * (HB is Header Byte, DB is Data Byte) | |
333 | * | |
334 | * The hdmi pack() functions don't know about that hardware specific hole so we | |
335 | * trick them by giving an offset into the buffer and moving back the header | |
336 | * bytes by one. | |
337 | */ | |
9198ee5b DL |
338 | static void intel_write_infoframe(struct drm_encoder *encoder, |
339 | union hdmi_infoframe *frame) | |
45187ace JB |
340 | { |
341 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); | |
5adaea79 DL |
342 | uint8_t buffer[VIDEO_DIP_DATA_SIZE]; |
343 | ssize_t len; | |
45187ace | 344 | |
5adaea79 DL |
345 | /* see comment above for the reason for this offset */ |
346 | len = hdmi_infoframe_pack(frame, buffer + 1, sizeof(buffer) - 1); | |
347 | if (len < 0) | |
348 | return; | |
349 | ||
350 | /* Insert the 'hole' (see big comment above) at position 3 */ | |
351 | buffer[0] = buffer[1]; | |
352 | buffer[1] = buffer[2]; | |
353 | buffer[2] = buffer[3]; | |
354 | buffer[3] = 0; | |
355 | len++; | |
45187ace | 356 | |
5adaea79 | 357 | intel_hdmi->write_infoframe(encoder, frame->any.type, buffer, len); |
45187ace JB |
358 | } |
359 | ||
687f4d06 | 360 | static void intel_hdmi_set_avi_infoframe(struct drm_encoder *encoder, |
c846b619 | 361 | struct drm_display_mode *adjusted_mode) |
45187ace | 362 | { |
abedc077 | 363 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); |
50f3b016 | 364 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); |
5adaea79 DL |
365 | union hdmi_infoframe frame; |
366 | int ret; | |
45187ace | 367 | |
5adaea79 DL |
368 | ret = drm_hdmi_avi_infoframe_from_display_mode(&frame.avi, |
369 | adjusted_mode); | |
370 | if (ret < 0) { | |
371 | DRM_ERROR("couldn't fill AVI infoframe\n"); | |
372 | return; | |
373 | } | |
c846b619 | 374 | |
abedc077 | 375 | if (intel_hdmi->rgb_quant_range_selectable) { |
50f3b016 | 376 | if (intel_crtc->config.limited_color_range) |
5adaea79 DL |
377 | frame.avi.quantization_range = |
378 | HDMI_QUANTIZATION_RANGE_LIMITED; | |
abedc077 | 379 | else |
5adaea79 DL |
380 | frame.avi.quantization_range = |
381 | HDMI_QUANTIZATION_RANGE_FULL; | |
abedc077 VS |
382 | } |
383 | ||
9198ee5b | 384 | intel_write_infoframe(encoder, &frame); |
b055c8f3 JB |
385 | } |
386 | ||
687f4d06 | 387 | static void intel_hdmi_set_spd_infoframe(struct drm_encoder *encoder) |
c0864cb3 | 388 | { |
5adaea79 DL |
389 | union hdmi_infoframe frame; |
390 | int ret; | |
391 | ||
392 | ret = hdmi_spd_infoframe_init(&frame.spd, "Intel", "Integrated gfx"); | |
393 | if (ret < 0) { | |
394 | DRM_ERROR("couldn't fill SPD infoframe\n"); | |
395 | return; | |
396 | } | |
c0864cb3 | 397 | |
5adaea79 | 398 | frame.spd.sdi = HDMI_SPD_SDI_PC; |
c0864cb3 | 399 | |
9198ee5b | 400 | intel_write_infoframe(encoder, &frame); |
c0864cb3 JB |
401 | } |
402 | ||
c8bb75af LD |
403 | static void |
404 | intel_hdmi_set_hdmi_infoframe(struct drm_encoder *encoder, | |
405 | struct drm_display_mode *adjusted_mode) | |
406 | { | |
407 | union hdmi_infoframe frame; | |
408 | int ret; | |
409 | ||
410 | ret = drm_hdmi_vendor_infoframe_from_display_mode(&frame.vendor.hdmi, | |
411 | adjusted_mode); | |
412 | if (ret < 0) | |
413 | return; | |
414 | ||
415 | intel_write_infoframe(encoder, &frame); | |
416 | } | |
417 | ||
687f4d06 PZ |
418 | static void g4x_set_infoframes(struct drm_encoder *encoder, |
419 | struct drm_display_mode *adjusted_mode) | |
420 | { | |
0c14c7f9 | 421 | struct drm_i915_private *dev_priv = encoder->dev->dev_private; |
69fde0a6 VS |
422 | struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); |
423 | struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi; | |
0c14c7f9 PZ |
424 | u32 reg = VIDEO_DIP_CTL; |
425 | u32 val = I915_READ(reg); | |
72b78c9d | 426 | u32 port; |
0c14c7f9 | 427 | |
afba0188 DV |
428 | assert_hdmi_port_disabled(intel_hdmi); |
429 | ||
0c14c7f9 PZ |
430 | /* If the registers were not initialized yet, they might be zeroes, |
431 | * which means we're selecting the AVI DIP and we're setting its | |
432 | * frequency to once. This seems to really confuse the HW and make | |
433 | * things stop working (the register spec says the AVI always needs to | |
434 | * be sent every VSync). So here we avoid writing to the register more | |
435 | * than we need and also explicitly select the AVI DIP and explicitly | |
436 | * set its frequency to every VSync. Avoiding to write it twice seems to | |
437 | * be enough to solve the problem, but being defensive shouldn't hurt us | |
438 | * either. */ | |
439 | val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; | |
440 | ||
441 | if (!intel_hdmi->has_hdmi_sink) { | |
442 | if (!(val & VIDEO_DIP_ENABLE)) | |
443 | return; | |
444 | val &= ~VIDEO_DIP_ENABLE; | |
445 | I915_WRITE(reg, val); | |
9d9740f0 | 446 | POSTING_READ(reg); |
0c14c7f9 PZ |
447 | return; |
448 | } | |
449 | ||
69fde0a6 VS |
450 | switch (intel_dig_port->port) { |
451 | case PORT_B: | |
72b78c9d | 452 | port = VIDEO_DIP_PORT_B; |
f278d972 | 453 | break; |
69fde0a6 | 454 | case PORT_C: |
72b78c9d | 455 | port = VIDEO_DIP_PORT_C; |
f278d972 PZ |
456 | break; |
457 | default: | |
57df2ae9 | 458 | BUG(); |
f278d972 PZ |
459 | return; |
460 | } | |
461 | ||
72b78c9d PZ |
462 | if (port != (val & VIDEO_DIP_PORT_MASK)) { |
463 | if (val & VIDEO_DIP_ENABLE) { | |
464 | val &= ~VIDEO_DIP_ENABLE; | |
465 | I915_WRITE(reg, val); | |
9d9740f0 | 466 | POSTING_READ(reg); |
72b78c9d PZ |
467 | } |
468 | val &= ~VIDEO_DIP_PORT_MASK; | |
469 | val |= port; | |
470 | } | |
471 | ||
822974ae | 472 | val |= VIDEO_DIP_ENABLE; |
0dd87d20 | 473 | val &= ~VIDEO_DIP_ENABLE_VENDOR; |
822974ae | 474 | |
f278d972 | 475 | I915_WRITE(reg, val); |
9d9740f0 | 476 | POSTING_READ(reg); |
f278d972 | 477 | |
687f4d06 PZ |
478 | intel_hdmi_set_avi_infoframe(encoder, adjusted_mode); |
479 | intel_hdmi_set_spd_infoframe(encoder); | |
c8bb75af | 480 | intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode); |
687f4d06 PZ |
481 | } |
482 | ||
483 | static void ibx_set_infoframes(struct drm_encoder *encoder, | |
484 | struct drm_display_mode *adjusted_mode) | |
485 | { | |
0c14c7f9 PZ |
486 | struct drm_i915_private *dev_priv = encoder->dev->dev_private; |
487 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); | |
69fde0a6 VS |
488 | struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); |
489 | struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi; | |
0c14c7f9 PZ |
490 | u32 reg = TVIDEO_DIP_CTL(intel_crtc->pipe); |
491 | u32 val = I915_READ(reg); | |
72b78c9d | 492 | u32 port; |
0c14c7f9 | 493 | |
afba0188 DV |
494 | assert_hdmi_port_disabled(intel_hdmi); |
495 | ||
0c14c7f9 PZ |
496 | /* See the big comment in g4x_set_infoframes() */ |
497 | val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; | |
498 | ||
499 | if (!intel_hdmi->has_hdmi_sink) { | |
500 | if (!(val & VIDEO_DIP_ENABLE)) | |
501 | return; | |
502 | val &= ~VIDEO_DIP_ENABLE; | |
503 | I915_WRITE(reg, val); | |
9d9740f0 | 504 | POSTING_READ(reg); |
0c14c7f9 PZ |
505 | return; |
506 | } | |
507 | ||
69fde0a6 VS |
508 | switch (intel_dig_port->port) { |
509 | case PORT_B: | |
72b78c9d | 510 | port = VIDEO_DIP_PORT_B; |
f278d972 | 511 | break; |
69fde0a6 | 512 | case PORT_C: |
72b78c9d | 513 | port = VIDEO_DIP_PORT_C; |
f278d972 | 514 | break; |
69fde0a6 | 515 | case PORT_D: |
72b78c9d | 516 | port = VIDEO_DIP_PORT_D; |
f278d972 PZ |
517 | break; |
518 | default: | |
57df2ae9 | 519 | BUG(); |
f278d972 PZ |
520 | return; |
521 | } | |
522 | ||
72b78c9d PZ |
523 | if (port != (val & VIDEO_DIP_PORT_MASK)) { |
524 | if (val & VIDEO_DIP_ENABLE) { | |
525 | val &= ~VIDEO_DIP_ENABLE; | |
526 | I915_WRITE(reg, val); | |
9d9740f0 | 527 | POSTING_READ(reg); |
72b78c9d PZ |
528 | } |
529 | val &= ~VIDEO_DIP_PORT_MASK; | |
530 | val |= port; | |
531 | } | |
532 | ||
822974ae | 533 | val |= VIDEO_DIP_ENABLE; |
0dd87d20 PZ |
534 | val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | |
535 | VIDEO_DIP_ENABLE_GCP); | |
822974ae | 536 | |
f278d972 | 537 | I915_WRITE(reg, val); |
9d9740f0 | 538 | POSTING_READ(reg); |
f278d972 | 539 | |
687f4d06 PZ |
540 | intel_hdmi_set_avi_infoframe(encoder, adjusted_mode); |
541 | intel_hdmi_set_spd_infoframe(encoder); | |
c8bb75af | 542 | intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode); |
687f4d06 PZ |
543 | } |
544 | ||
545 | static void cpt_set_infoframes(struct drm_encoder *encoder, | |
546 | struct drm_display_mode *adjusted_mode) | |
547 | { | |
0c14c7f9 PZ |
548 | struct drm_i915_private *dev_priv = encoder->dev->dev_private; |
549 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); | |
550 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); | |
551 | u32 reg = TVIDEO_DIP_CTL(intel_crtc->pipe); | |
552 | u32 val = I915_READ(reg); | |
553 | ||
afba0188 DV |
554 | assert_hdmi_port_disabled(intel_hdmi); |
555 | ||
0c14c7f9 PZ |
556 | /* See the big comment in g4x_set_infoframes() */ |
557 | val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; | |
558 | ||
559 | if (!intel_hdmi->has_hdmi_sink) { | |
560 | if (!(val & VIDEO_DIP_ENABLE)) | |
561 | return; | |
562 | val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI); | |
563 | I915_WRITE(reg, val); | |
9d9740f0 | 564 | POSTING_READ(reg); |
0c14c7f9 PZ |
565 | return; |
566 | } | |
567 | ||
822974ae PZ |
568 | /* Set both together, unset both together: see the spec. */ |
569 | val |= VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI; | |
0dd87d20 PZ |
570 | val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | |
571 | VIDEO_DIP_ENABLE_GCP); | |
822974ae PZ |
572 | |
573 | I915_WRITE(reg, val); | |
9d9740f0 | 574 | POSTING_READ(reg); |
822974ae | 575 | |
687f4d06 PZ |
576 | intel_hdmi_set_avi_infoframe(encoder, adjusted_mode); |
577 | intel_hdmi_set_spd_infoframe(encoder); | |
c8bb75af | 578 | intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode); |
687f4d06 PZ |
579 | } |
580 | ||
581 | static void vlv_set_infoframes(struct drm_encoder *encoder, | |
582 | struct drm_display_mode *adjusted_mode) | |
583 | { | |
0c14c7f9 PZ |
584 | struct drm_i915_private *dev_priv = encoder->dev->dev_private; |
585 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); | |
586 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); | |
587 | u32 reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe); | |
588 | u32 val = I915_READ(reg); | |
589 | ||
afba0188 DV |
590 | assert_hdmi_port_disabled(intel_hdmi); |
591 | ||
0c14c7f9 PZ |
592 | /* See the big comment in g4x_set_infoframes() */ |
593 | val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; | |
594 | ||
595 | if (!intel_hdmi->has_hdmi_sink) { | |
596 | if (!(val & VIDEO_DIP_ENABLE)) | |
597 | return; | |
598 | val &= ~VIDEO_DIP_ENABLE; | |
599 | I915_WRITE(reg, val); | |
9d9740f0 | 600 | POSTING_READ(reg); |
0c14c7f9 PZ |
601 | return; |
602 | } | |
603 | ||
822974ae | 604 | val |= VIDEO_DIP_ENABLE; |
0dd87d20 PZ |
605 | val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | |
606 | VIDEO_DIP_ENABLE_GCP); | |
822974ae PZ |
607 | |
608 | I915_WRITE(reg, val); | |
9d9740f0 | 609 | POSTING_READ(reg); |
822974ae | 610 | |
687f4d06 PZ |
611 | intel_hdmi_set_avi_infoframe(encoder, adjusted_mode); |
612 | intel_hdmi_set_spd_infoframe(encoder); | |
c8bb75af | 613 | intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode); |
687f4d06 PZ |
614 | } |
615 | ||
616 | static void hsw_set_infoframes(struct drm_encoder *encoder, | |
617 | struct drm_display_mode *adjusted_mode) | |
618 | { | |
0c14c7f9 PZ |
619 | struct drm_i915_private *dev_priv = encoder->dev->dev_private; |
620 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); | |
621 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); | |
3b117c8f | 622 | u32 reg = HSW_TVIDEO_DIP_CTL(intel_crtc->config.cpu_transcoder); |
0dd87d20 | 623 | u32 val = I915_READ(reg); |
0c14c7f9 | 624 | |
afba0188 DV |
625 | assert_hdmi_port_disabled(intel_hdmi); |
626 | ||
0c14c7f9 PZ |
627 | if (!intel_hdmi->has_hdmi_sink) { |
628 | I915_WRITE(reg, 0); | |
9d9740f0 | 629 | POSTING_READ(reg); |
0c14c7f9 PZ |
630 | return; |
631 | } | |
632 | ||
0dd87d20 PZ |
633 | val &= ~(VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_GCP_HSW | |
634 | VIDEO_DIP_ENABLE_VS_HSW | VIDEO_DIP_ENABLE_GMP_HSW); | |
635 | ||
636 | I915_WRITE(reg, val); | |
9d9740f0 | 637 | POSTING_READ(reg); |
0dd87d20 | 638 | |
687f4d06 PZ |
639 | intel_hdmi_set_avi_infoframe(encoder, adjusted_mode); |
640 | intel_hdmi_set_spd_infoframe(encoder); | |
c8bb75af | 641 | intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode); |
687f4d06 PZ |
642 | } |
643 | ||
c59423a3 | 644 | static void intel_hdmi_mode_set(struct intel_encoder *encoder) |
7d57382e | 645 | { |
c59423a3 | 646 | struct drm_device *dev = encoder->base.dev; |
7d57382e | 647 | struct drm_i915_private *dev_priv = dev->dev_private; |
c59423a3 DV |
648 | struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); |
649 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); | |
650 | struct drm_display_mode *adjusted_mode = &crtc->config.adjusted_mode; | |
b242b7f7 | 651 | u32 hdmi_val; |
7d57382e | 652 | |
b242b7f7 | 653 | hdmi_val = SDVO_ENCODING_HDMI; |
2af2c490 | 654 | if (!HAS_PCH_SPLIT(dev)) |
b242b7f7 | 655 | hdmi_val |= intel_hdmi->color_range; |
b599c0bc | 656 | if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) |
b242b7f7 | 657 | hdmi_val |= SDVO_VSYNC_ACTIVE_HIGH; |
b599c0bc | 658 | if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) |
b242b7f7 | 659 | hdmi_val |= SDVO_HSYNC_ACTIVE_HIGH; |
7d57382e | 660 | |
c59423a3 | 661 | if (crtc->config.pipe_bpp > 24) |
4f3a8bc7 | 662 | hdmi_val |= HDMI_COLOR_FORMAT_12bpc; |
020f6704 | 663 | else |
4f3a8bc7 | 664 | hdmi_val |= SDVO_COLOR_FORMAT_8bpc; |
020f6704 | 665 | |
2e3d6006 ZW |
666 | /* Required on CPT */ |
667 | if (intel_hdmi->has_hdmi_sink && HAS_PCH_CPT(dev)) | |
dc0fa718 | 668 | hdmi_val |= HDMI_MODE_SELECT_HDMI; |
2e3d6006 | 669 | |
3c17fe4b | 670 | if (intel_hdmi->has_audio) { |
e0dac65e | 671 | DRM_DEBUG_DRIVER("Enabling HDMI audio on pipe %c\n", |
c59423a3 | 672 | pipe_name(crtc->pipe)); |
b242b7f7 | 673 | hdmi_val |= SDVO_AUDIO_ENABLE; |
dc0fa718 | 674 | hdmi_val |= HDMI_MODE_SELECT_HDMI; |
c59423a3 | 675 | intel_write_eld(&encoder->base, adjusted_mode); |
3c17fe4b | 676 | } |
7d57382e | 677 | |
75770564 | 678 | if (HAS_PCH_CPT(dev)) |
c59423a3 | 679 | hdmi_val |= SDVO_PIPE_SEL_CPT(crtc->pipe); |
dc0fa718 | 680 | else |
c59423a3 | 681 | hdmi_val |= SDVO_PIPE_SEL(crtc->pipe); |
7d57382e | 682 | |
b242b7f7 PZ |
683 | I915_WRITE(intel_hdmi->hdmi_reg, hdmi_val); |
684 | POSTING_READ(intel_hdmi->hdmi_reg); | |
3c17fe4b | 685 | |
c59423a3 | 686 | intel_hdmi->set_infoframes(&encoder->base, adjusted_mode); |
7d57382e EA |
687 | } |
688 | ||
85234cdc DV |
689 | static bool intel_hdmi_get_hw_state(struct intel_encoder *encoder, |
690 | enum pipe *pipe) | |
7d57382e | 691 | { |
85234cdc | 692 | struct drm_device *dev = encoder->base.dev; |
7d57382e | 693 | struct drm_i915_private *dev_priv = dev->dev_private; |
85234cdc DV |
694 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); |
695 | u32 tmp; | |
696 | ||
b242b7f7 | 697 | tmp = I915_READ(intel_hdmi->hdmi_reg); |
85234cdc DV |
698 | |
699 | if (!(tmp & SDVO_ENABLE)) | |
700 | return false; | |
701 | ||
702 | if (HAS_PCH_CPT(dev)) | |
703 | *pipe = PORT_TO_PIPE_CPT(tmp); | |
704 | else | |
705 | *pipe = PORT_TO_PIPE(tmp); | |
706 | ||
707 | return true; | |
708 | } | |
709 | ||
045ac3b5 JB |
710 | static void intel_hdmi_get_config(struct intel_encoder *encoder, |
711 | struct intel_crtc_config *pipe_config) | |
712 | { | |
713 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); | |
714 | struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; | |
715 | u32 tmp, flags = 0; | |
18442d08 | 716 | int dotclock; |
045ac3b5 JB |
717 | |
718 | tmp = I915_READ(intel_hdmi->hdmi_reg); | |
719 | ||
720 | if (tmp & SDVO_HSYNC_ACTIVE_HIGH) | |
721 | flags |= DRM_MODE_FLAG_PHSYNC; | |
722 | else | |
723 | flags |= DRM_MODE_FLAG_NHSYNC; | |
724 | ||
725 | if (tmp & SDVO_VSYNC_ACTIVE_HIGH) | |
726 | flags |= DRM_MODE_FLAG_PVSYNC; | |
727 | else | |
728 | flags |= DRM_MODE_FLAG_NVSYNC; | |
729 | ||
730 | pipe_config->adjusted_mode.flags |= flags; | |
18442d08 VS |
731 | |
732 | if ((tmp & SDVO_COLOR_FORMAT_MASK) == HDMI_COLOR_FORMAT_12bpc) | |
733 | dotclock = pipe_config->port_clock * 2 / 3; | |
734 | else | |
735 | dotclock = pipe_config->port_clock; | |
736 | ||
737 | if (HAS_PCH_SPLIT(dev_priv->dev)) | |
738 | ironlake_check_encoder_dotclock(pipe_config, dotclock); | |
739 | ||
740 | pipe_config->adjusted_mode.clock = dotclock; | |
045ac3b5 JB |
741 | } |
742 | ||
5ab432ef | 743 | static void intel_enable_hdmi(struct intel_encoder *encoder) |
7d57382e | 744 | { |
5ab432ef | 745 | struct drm_device *dev = encoder->base.dev; |
7d57382e | 746 | struct drm_i915_private *dev_priv = dev->dev_private; |
dc0fa718 | 747 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); |
5ab432ef | 748 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); |
7d57382e | 749 | u32 temp; |
2deed761 WF |
750 | u32 enable_bits = SDVO_ENABLE; |
751 | ||
752 | if (intel_hdmi->has_audio) | |
753 | enable_bits |= SDVO_AUDIO_ENABLE; | |
7d57382e | 754 | |
b242b7f7 | 755 | temp = I915_READ(intel_hdmi->hdmi_reg); |
d8a2d0e0 | 756 | |
7a87c289 | 757 | /* HW workaround for IBX, we need to move the port to transcoder A |
dc0fa718 PZ |
758 | * before disabling it, so restore the transcoder select bit here. */ |
759 | if (HAS_PCH_IBX(dev)) | |
760 | enable_bits |= SDVO_PIPE_SEL(intel_crtc->pipe); | |
7a87c289 | 761 | |
d8a2d0e0 ZW |
762 | /* HW workaround, need to toggle enable bit off and on for 12bpc, but |
763 | * we do this anyway which shows more stable in testing. | |
764 | */ | |
c619eed4 | 765 | if (HAS_PCH_SPLIT(dev)) { |
b242b7f7 PZ |
766 | I915_WRITE(intel_hdmi->hdmi_reg, temp & ~SDVO_ENABLE); |
767 | POSTING_READ(intel_hdmi->hdmi_reg); | |
d8a2d0e0 ZW |
768 | } |
769 | ||
5ab432ef DV |
770 | temp |= enable_bits; |
771 | ||
b242b7f7 PZ |
772 | I915_WRITE(intel_hdmi->hdmi_reg, temp); |
773 | POSTING_READ(intel_hdmi->hdmi_reg); | |
5ab432ef DV |
774 | |
775 | /* HW workaround, need to write this twice for issue that may result | |
776 | * in first write getting masked. | |
777 | */ | |
778 | if (HAS_PCH_SPLIT(dev)) { | |
b242b7f7 PZ |
779 | I915_WRITE(intel_hdmi->hdmi_reg, temp); |
780 | POSTING_READ(intel_hdmi->hdmi_reg); | |
7d57382e | 781 | } |
b76cf76b | 782 | } |
89b667f8 | 783 | |
b76cf76b JN |
784 | static void vlv_enable_hdmi(struct intel_encoder *encoder) |
785 | { | |
5ab432ef DV |
786 | } |
787 | ||
788 | static void intel_disable_hdmi(struct intel_encoder *encoder) | |
789 | { | |
790 | struct drm_device *dev = encoder->base.dev; | |
791 | struct drm_i915_private *dev_priv = dev->dev_private; | |
792 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); | |
793 | u32 temp; | |
3cce574f | 794 | u32 enable_bits = SDVO_ENABLE | SDVO_AUDIO_ENABLE; |
5ab432ef | 795 | |
b242b7f7 | 796 | temp = I915_READ(intel_hdmi->hdmi_reg); |
5ab432ef DV |
797 | |
798 | /* HW workaround for IBX, we need to move the port to transcoder A | |
799 | * before disabling it. */ | |
800 | if (HAS_PCH_IBX(dev)) { | |
801 | struct drm_crtc *crtc = encoder->base.crtc; | |
802 | int pipe = crtc ? to_intel_crtc(crtc)->pipe : -1; | |
803 | ||
804 | if (temp & SDVO_PIPE_B_SELECT) { | |
805 | temp &= ~SDVO_PIPE_B_SELECT; | |
b242b7f7 PZ |
806 | I915_WRITE(intel_hdmi->hdmi_reg, temp); |
807 | POSTING_READ(intel_hdmi->hdmi_reg); | |
5ab432ef DV |
808 | |
809 | /* Again we need to write this twice. */ | |
b242b7f7 PZ |
810 | I915_WRITE(intel_hdmi->hdmi_reg, temp); |
811 | POSTING_READ(intel_hdmi->hdmi_reg); | |
5ab432ef DV |
812 | |
813 | /* Transcoder selection bits only update | |
814 | * effectively on vblank. */ | |
815 | if (crtc) | |
816 | intel_wait_for_vblank(dev, pipe); | |
817 | else | |
818 | msleep(50); | |
819 | } | |
7d57382e | 820 | } |
d8a2d0e0 | 821 | |
5ab432ef DV |
822 | /* HW workaround, need to toggle enable bit off and on for 12bpc, but |
823 | * we do this anyway which shows more stable in testing. | |
824 | */ | |
825 | if (HAS_PCH_SPLIT(dev)) { | |
b242b7f7 PZ |
826 | I915_WRITE(intel_hdmi->hdmi_reg, temp & ~SDVO_ENABLE); |
827 | POSTING_READ(intel_hdmi->hdmi_reg); | |
5ab432ef DV |
828 | } |
829 | ||
830 | temp &= ~enable_bits; | |
d8a2d0e0 | 831 | |
b242b7f7 PZ |
832 | I915_WRITE(intel_hdmi->hdmi_reg, temp); |
833 | POSTING_READ(intel_hdmi->hdmi_reg); | |
d8a2d0e0 ZW |
834 | |
835 | /* HW workaround, need to write this twice for issue that may result | |
836 | * in first write getting masked. | |
837 | */ | |
c619eed4 | 838 | if (HAS_PCH_SPLIT(dev)) { |
b242b7f7 PZ |
839 | I915_WRITE(intel_hdmi->hdmi_reg, temp); |
840 | POSTING_READ(intel_hdmi->hdmi_reg); | |
d8a2d0e0 | 841 | } |
7d57382e EA |
842 | } |
843 | ||
7d148ef5 DV |
844 | static int hdmi_portclock_limit(struct intel_hdmi *hdmi) |
845 | { | |
846 | struct drm_device *dev = intel_hdmi_to_dev(hdmi); | |
847 | ||
848 | if (IS_G4X(dev)) | |
849 | return 165000; | |
850 | else if (IS_HASWELL(dev)) | |
851 | return 300000; | |
852 | else | |
853 | return 225000; | |
854 | } | |
855 | ||
7d57382e EA |
856 | static int intel_hdmi_mode_valid(struct drm_connector *connector, |
857 | struct drm_display_mode *mode) | |
858 | { | |
7d148ef5 | 859 | if (mode->clock > hdmi_portclock_limit(intel_attached_hdmi(connector))) |
7d57382e EA |
860 | return MODE_CLOCK_HIGH; |
861 | if (mode->clock < 20000) | |
5cbba41d | 862 | return MODE_CLOCK_LOW; |
7d57382e EA |
863 | |
864 | if (mode->flags & DRM_MODE_FLAG_DBLSCAN) | |
865 | return MODE_NO_DBLESCAN; | |
866 | ||
867 | return MODE_OK; | |
868 | } | |
869 | ||
5bfe2ac0 DV |
870 | bool intel_hdmi_compute_config(struct intel_encoder *encoder, |
871 | struct intel_crtc_config *pipe_config) | |
7d57382e | 872 | { |
5bfe2ac0 DV |
873 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); |
874 | struct drm_device *dev = encoder->base.dev; | |
875 | struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode; | |
d68e7c3c | 876 | int clock_12bpc = pipe_config->adjusted_mode.clock * 3 / 2; |
7d148ef5 | 877 | int portclock_limit = hdmi_portclock_limit(intel_hdmi); |
e29c22c0 | 878 | int desired_bpp; |
3685a8f3 | 879 | |
55bc60db VS |
880 | if (intel_hdmi->color_range_auto) { |
881 | /* See CEA-861-E - 5.1 Default Encoding Parameters */ | |
882 | if (intel_hdmi->has_hdmi_sink && | |
18316c8c | 883 | drm_match_cea_mode(adjusted_mode) > 1) |
4f3a8bc7 | 884 | intel_hdmi->color_range = HDMI_COLOR_RANGE_16_235; |
55bc60db VS |
885 | else |
886 | intel_hdmi->color_range = 0; | |
887 | } | |
888 | ||
3685a8f3 | 889 | if (intel_hdmi->color_range) |
50f3b016 | 890 | pipe_config->limited_color_range = true; |
3685a8f3 | 891 | |
5bfe2ac0 DV |
892 | if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev)) |
893 | pipe_config->has_pch_encoder = true; | |
894 | ||
4e53c2e0 DV |
895 | /* |
896 | * HDMI is either 12 or 8, so if the display lets 10bpc sneak | |
897 | * through, clamp it down. Note that g4x/vlv don't support 12bpc hdmi | |
325b9d04 DV |
898 | * outputs. We also need to check that the higher clock still fits |
899 | * within limits. | |
4e53c2e0 | 900 | */ |
7d148ef5 | 901 | if (pipe_config->pipe_bpp > 8*3 && clock_12bpc <= portclock_limit |
325b9d04 | 902 | && HAS_PCH_SPLIT(dev)) { |
e29c22c0 DV |
903 | DRM_DEBUG_KMS("picking bpc to 12 for HDMI output\n"); |
904 | desired_bpp = 12*3; | |
325b9d04 DV |
905 | |
906 | /* Need to adjust the port link by 1.5x for 12bpc. */ | |
ff9a6750 | 907 | pipe_config->port_clock = clock_12bpc; |
4e53c2e0 | 908 | } else { |
e29c22c0 DV |
909 | DRM_DEBUG_KMS("picking bpc to 8 for HDMI output\n"); |
910 | desired_bpp = 8*3; | |
911 | } | |
912 | ||
913 | if (!pipe_config->bw_constrained) { | |
914 | DRM_DEBUG_KMS("forcing pipe bpc to %i for HDMI\n", desired_bpp); | |
915 | pipe_config->pipe_bpp = desired_bpp; | |
4e53c2e0 DV |
916 | } |
917 | ||
7d148ef5 | 918 | if (adjusted_mode->clock > portclock_limit) { |
325b9d04 DV |
919 | DRM_DEBUG_KMS("too high HDMI clock, rejecting mode\n"); |
920 | return false; | |
921 | } | |
922 | ||
7d57382e EA |
923 | return true; |
924 | } | |
925 | ||
aa93d632 | 926 | static enum drm_connector_status |
930a9e28 | 927 | intel_hdmi_detect(struct drm_connector *connector, bool force) |
9dff6af8 | 928 | { |
b0ea7d37 | 929 | struct drm_device *dev = connector->dev; |
df0e9248 | 930 | struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); |
d63885da PZ |
931 | struct intel_digital_port *intel_dig_port = |
932 | hdmi_to_dig_port(intel_hdmi); | |
933 | struct intel_encoder *intel_encoder = &intel_dig_port->base; | |
b0ea7d37 | 934 | struct drm_i915_private *dev_priv = dev->dev_private; |
f899fc64 | 935 | struct edid *edid; |
aa93d632 | 936 | enum drm_connector_status status = connector_status_disconnected; |
9dff6af8 | 937 | |
164c8598 CW |
938 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", |
939 | connector->base.id, drm_get_connector_name(connector)); | |
940 | ||
ea5b213a | 941 | intel_hdmi->has_hdmi_sink = false; |
2e3d6006 | 942 | intel_hdmi->has_audio = false; |
abedc077 | 943 | intel_hdmi->rgb_quant_range_selectable = false; |
f899fc64 | 944 | edid = drm_get_edid(connector, |
3bd7d909 DK |
945 | intel_gmbus_get_adapter(dev_priv, |
946 | intel_hdmi->ddc_bus)); | |
2ded9e27 | 947 | |
aa93d632 | 948 | if (edid) { |
be9f1c4f | 949 | if (edid->input & DRM_EDID_INPUT_DIGITAL) { |
aa93d632 | 950 | status = connector_status_connected; |
b1d7e4b4 WF |
951 | if (intel_hdmi->force_audio != HDMI_AUDIO_OFF_DVI) |
952 | intel_hdmi->has_hdmi_sink = | |
953 | drm_detect_hdmi_monitor(edid); | |
2e3d6006 | 954 | intel_hdmi->has_audio = drm_detect_monitor_audio(edid); |
abedc077 VS |
955 | intel_hdmi->rgb_quant_range_selectable = |
956 | drm_rgb_quant_range_selectable(edid); | |
aa93d632 | 957 | } |
aa93d632 | 958 | kfree(edid); |
9dff6af8 | 959 | } |
30ad48b7 | 960 | |
55b7d6e8 | 961 | if (status == connector_status_connected) { |
b1d7e4b4 WF |
962 | if (intel_hdmi->force_audio != HDMI_AUDIO_AUTO) |
963 | intel_hdmi->has_audio = | |
964 | (intel_hdmi->force_audio == HDMI_AUDIO_ON); | |
d63885da | 965 | intel_encoder->type = INTEL_OUTPUT_HDMI; |
55b7d6e8 CW |
966 | } |
967 | ||
2ded9e27 | 968 | return status; |
7d57382e EA |
969 | } |
970 | ||
971 | static int intel_hdmi_get_modes(struct drm_connector *connector) | |
972 | { | |
df0e9248 | 973 | struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); |
f899fc64 | 974 | struct drm_i915_private *dev_priv = connector->dev->dev_private; |
7d57382e EA |
975 | |
976 | /* We should parse the EDID data and find out if it's an HDMI sink so | |
977 | * we can send audio to it. | |
978 | */ | |
979 | ||
f899fc64 | 980 | return intel_ddc_get_modes(connector, |
3bd7d909 DK |
981 | intel_gmbus_get_adapter(dev_priv, |
982 | intel_hdmi->ddc_bus)); | |
7d57382e EA |
983 | } |
984 | ||
1aad7ac0 CW |
985 | static bool |
986 | intel_hdmi_detect_audio(struct drm_connector *connector) | |
987 | { | |
988 | struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); | |
989 | struct drm_i915_private *dev_priv = connector->dev->dev_private; | |
990 | struct edid *edid; | |
991 | bool has_audio = false; | |
992 | ||
993 | edid = drm_get_edid(connector, | |
3bd7d909 DK |
994 | intel_gmbus_get_adapter(dev_priv, |
995 | intel_hdmi->ddc_bus)); | |
1aad7ac0 CW |
996 | if (edid) { |
997 | if (edid->input & DRM_EDID_INPUT_DIGITAL) | |
998 | has_audio = drm_detect_monitor_audio(edid); | |
1aad7ac0 CW |
999 | kfree(edid); |
1000 | } | |
1001 | ||
1002 | return has_audio; | |
1003 | } | |
1004 | ||
55b7d6e8 CW |
1005 | static int |
1006 | intel_hdmi_set_property(struct drm_connector *connector, | |
ed517fbb PZ |
1007 | struct drm_property *property, |
1008 | uint64_t val) | |
55b7d6e8 CW |
1009 | { |
1010 | struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); | |
da63a9f2 PZ |
1011 | struct intel_digital_port *intel_dig_port = |
1012 | hdmi_to_dig_port(intel_hdmi); | |
e953fd7b | 1013 | struct drm_i915_private *dev_priv = connector->dev->dev_private; |
55b7d6e8 CW |
1014 | int ret; |
1015 | ||
662595df | 1016 | ret = drm_object_property_set_value(&connector->base, property, val); |
55b7d6e8 CW |
1017 | if (ret) |
1018 | return ret; | |
1019 | ||
3f43c48d | 1020 | if (property == dev_priv->force_audio_property) { |
b1d7e4b4 | 1021 | enum hdmi_force_audio i = val; |
1aad7ac0 CW |
1022 | bool has_audio; |
1023 | ||
1024 | if (i == intel_hdmi->force_audio) | |
55b7d6e8 CW |
1025 | return 0; |
1026 | ||
1aad7ac0 | 1027 | intel_hdmi->force_audio = i; |
55b7d6e8 | 1028 | |
b1d7e4b4 | 1029 | if (i == HDMI_AUDIO_AUTO) |
1aad7ac0 CW |
1030 | has_audio = intel_hdmi_detect_audio(connector); |
1031 | else | |
b1d7e4b4 | 1032 | has_audio = (i == HDMI_AUDIO_ON); |
1aad7ac0 | 1033 | |
b1d7e4b4 WF |
1034 | if (i == HDMI_AUDIO_OFF_DVI) |
1035 | intel_hdmi->has_hdmi_sink = 0; | |
55b7d6e8 | 1036 | |
1aad7ac0 | 1037 | intel_hdmi->has_audio = has_audio; |
55b7d6e8 CW |
1038 | goto done; |
1039 | } | |
1040 | ||
e953fd7b | 1041 | if (property == dev_priv->broadcast_rgb_property) { |
ae4edb80 DV |
1042 | bool old_auto = intel_hdmi->color_range_auto; |
1043 | uint32_t old_range = intel_hdmi->color_range; | |
1044 | ||
55bc60db VS |
1045 | switch (val) { |
1046 | case INTEL_BROADCAST_RGB_AUTO: | |
1047 | intel_hdmi->color_range_auto = true; | |
1048 | break; | |
1049 | case INTEL_BROADCAST_RGB_FULL: | |
1050 | intel_hdmi->color_range_auto = false; | |
1051 | intel_hdmi->color_range = 0; | |
1052 | break; | |
1053 | case INTEL_BROADCAST_RGB_LIMITED: | |
1054 | intel_hdmi->color_range_auto = false; | |
4f3a8bc7 | 1055 | intel_hdmi->color_range = HDMI_COLOR_RANGE_16_235; |
55bc60db VS |
1056 | break; |
1057 | default: | |
1058 | return -EINVAL; | |
1059 | } | |
ae4edb80 DV |
1060 | |
1061 | if (old_auto == intel_hdmi->color_range_auto && | |
1062 | old_range == intel_hdmi->color_range) | |
1063 | return 0; | |
1064 | ||
e953fd7b CW |
1065 | goto done; |
1066 | } | |
1067 | ||
55b7d6e8 CW |
1068 | return -EINVAL; |
1069 | ||
1070 | done: | |
c0c36b94 CW |
1071 | if (intel_dig_port->base.base.crtc) |
1072 | intel_crtc_restore_mode(intel_dig_port->base.base.crtc); | |
55b7d6e8 CW |
1073 | |
1074 | return 0; | |
1075 | } | |
1076 | ||
89b667f8 JB |
1077 | static void intel_hdmi_pre_enable(struct intel_encoder *encoder) |
1078 | { | |
1079 | struct intel_digital_port *dport = enc_to_dig_port(&encoder->base); | |
1080 | struct drm_device *dev = encoder->base.dev; | |
1081 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1082 | struct intel_crtc *intel_crtc = | |
1083 | to_intel_crtc(encoder->base.crtc); | |
1084 | int port = vlv_dport_to_channel(dport); | |
1085 | int pipe = intel_crtc->pipe; | |
1086 | u32 val; | |
1087 | ||
1088 | if (!IS_VALLEYVIEW(dev)) | |
1089 | return; | |
1090 | ||
89b667f8 | 1091 | /* Enable clock channels for this port */ |
0980a60f | 1092 | mutex_lock(&dev_priv->dpio_lock); |
5e69f97f | 1093 | val = vlv_dpio_read(dev_priv, pipe, DPIO_DATA_LANE_A(port)); |
89b667f8 JB |
1094 | val = 0; |
1095 | if (pipe) | |
1096 | val |= (1<<21); | |
1097 | else | |
1098 | val &= ~(1<<21); | |
1099 | val |= 0x001000c4; | |
5e69f97f | 1100 | vlv_dpio_write(dev_priv, pipe, DPIO_DATA_CHANNEL(port), val); |
89b667f8 JB |
1101 | |
1102 | /* HDMI 1.0V-2dB */ | |
5e69f97f CML |
1103 | vlv_dpio_write(dev_priv, pipe, DPIO_TX_OCALINIT(port), 0); |
1104 | vlv_dpio_write(dev_priv, pipe, DPIO_TX_SWING_CTL4(port), | |
89b667f8 | 1105 | 0x2b245f5f); |
5e69f97f | 1106 | vlv_dpio_write(dev_priv, pipe, DPIO_TX_SWING_CTL2(port), |
89b667f8 | 1107 | 0x5578b83a); |
5e69f97f | 1108 | vlv_dpio_write(dev_priv, pipe, DPIO_TX_SWING_CTL3(port), |
89b667f8 | 1109 | 0x0c782040); |
5e69f97f | 1110 | vlv_dpio_write(dev_priv, pipe, DPIO_TX3_SWING_CTL4(port), |
89b667f8 | 1111 | 0x2b247878); |
5e69f97f CML |
1112 | vlv_dpio_write(dev_priv, pipe, DPIO_PCS_STAGGER0(port), 0x00030000); |
1113 | vlv_dpio_write(dev_priv, pipe, DPIO_PCS_CTL_OVER1(port), | |
89b667f8 | 1114 | 0x00002000); |
5e69f97f | 1115 | vlv_dpio_write(dev_priv, pipe, DPIO_TX_OCALINIT(port), |
89b667f8 JB |
1116 | DPIO_TX_OCALINIT_EN); |
1117 | ||
1118 | /* Program lane clock */ | |
5e69f97f | 1119 | vlv_dpio_write(dev_priv, pipe, DPIO_PCS_CLOCKBUF0(port), |
89b667f8 | 1120 | 0x00760018); |
5e69f97f | 1121 | vlv_dpio_write(dev_priv, pipe, DPIO_PCS_CLOCKBUF8(port), |
89b667f8 | 1122 | 0x00400888); |
0980a60f | 1123 | mutex_unlock(&dev_priv->dpio_lock); |
b76cf76b JN |
1124 | |
1125 | intel_enable_hdmi(encoder); | |
1126 | ||
1127 | vlv_wait_port_ready(dev_priv, port); | |
89b667f8 JB |
1128 | } |
1129 | ||
1130 | static void intel_hdmi_pre_pll_enable(struct intel_encoder *encoder) | |
1131 | { | |
1132 | struct intel_digital_port *dport = enc_to_dig_port(&encoder->base); | |
1133 | struct drm_device *dev = encoder->base.dev; | |
1134 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5e69f97f CML |
1135 | struct intel_crtc *intel_crtc = |
1136 | to_intel_crtc(encoder->base.crtc); | |
89b667f8 | 1137 | int port = vlv_dport_to_channel(dport); |
5e69f97f | 1138 | int pipe = intel_crtc->pipe; |
89b667f8 JB |
1139 | |
1140 | if (!IS_VALLEYVIEW(dev)) | |
1141 | return; | |
1142 | ||
89b667f8 | 1143 | /* Program Tx lane resets to default */ |
0980a60f | 1144 | mutex_lock(&dev_priv->dpio_lock); |
5e69f97f | 1145 | vlv_dpio_write(dev_priv, pipe, DPIO_PCS_TX(port), |
89b667f8 JB |
1146 | DPIO_PCS_TX_LANE2_RESET | |
1147 | DPIO_PCS_TX_LANE1_RESET); | |
5e69f97f | 1148 | vlv_dpio_write(dev_priv, pipe, DPIO_PCS_CLK(port), |
89b667f8 JB |
1149 | DPIO_PCS_CLK_CRI_RXEB_EIOS_EN | |
1150 | DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN | | |
1151 | (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) | | |
1152 | DPIO_PCS_CLK_SOFT_RESET); | |
1153 | ||
1154 | /* Fix up inter-pair skew failure */ | |
5e69f97f CML |
1155 | vlv_dpio_write(dev_priv, pipe, DPIO_PCS_STAGGER1(port), 0x00750f00); |
1156 | vlv_dpio_write(dev_priv, pipe, DPIO_TX_CTL(port), 0x00001500); | |
1157 | vlv_dpio_write(dev_priv, pipe, DPIO_TX_LANE(port), 0x40400000); | |
89b667f8 | 1158 | |
5e69f97f | 1159 | vlv_dpio_write(dev_priv, pipe, DPIO_PCS_CTL_OVER1(port), |
89b667f8 | 1160 | 0x00002000); |
5e69f97f | 1161 | vlv_dpio_write(dev_priv, pipe, DPIO_TX_OCALINIT(port), |
89b667f8 | 1162 | DPIO_TX_OCALINIT_EN); |
0980a60f | 1163 | mutex_unlock(&dev_priv->dpio_lock); |
89b667f8 JB |
1164 | } |
1165 | ||
1166 | static void intel_hdmi_post_disable(struct intel_encoder *encoder) | |
1167 | { | |
1168 | struct intel_digital_port *dport = enc_to_dig_port(&encoder->base); | |
1169 | struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; | |
5e69f97f CML |
1170 | struct intel_crtc *intel_crtc = |
1171 | to_intel_crtc(encoder->base.crtc); | |
89b667f8 | 1172 | int port = vlv_dport_to_channel(dport); |
5e69f97f | 1173 | int pipe = intel_crtc->pipe; |
89b667f8 JB |
1174 | |
1175 | /* Reset lanes to avoid HDMI flicker (VLV w/a) */ | |
1176 | mutex_lock(&dev_priv->dpio_lock); | |
5e69f97f CML |
1177 | vlv_dpio_write(dev_priv, pipe, DPIO_PCS_TX(port), 0x00000000); |
1178 | vlv_dpio_write(dev_priv, pipe, DPIO_PCS_CLK(port), 0x00e00060); | |
89b667f8 JB |
1179 | mutex_unlock(&dev_priv->dpio_lock); |
1180 | } | |
1181 | ||
7d57382e EA |
1182 | static void intel_hdmi_destroy(struct drm_connector *connector) |
1183 | { | |
7d57382e EA |
1184 | drm_sysfs_connector_remove(connector); |
1185 | drm_connector_cleanup(connector); | |
674e2d08 | 1186 | kfree(connector); |
7d57382e EA |
1187 | } |
1188 | ||
7d57382e | 1189 | static const struct drm_connector_funcs intel_hdmi_connector_funcs = { |
5ab432ef | 1190 | .dpms = intel_connector_dpms, |
7d57382e EA |
1191 | .detect = intel_hdmi_detect, |
1192 | .fill_modes = drm_helper_probe_single_connector_modes, | |
55b7d6e8 | 1193 | .set_property = intel_hdmi_set_property, |
7d57382e EA |
1194 | .destroy = intel_hdmi_destroy, |
1195 | }; | |
1196 | ||
1197 | static const struct drm_connector_helper_funcs intel_hdmi_connector_helper_funcs = { | |
1198 | .get_modes = intel_hdmi_get_modes, | |
1199 | .mode_valid = intel_hdmi_mode_valid, | |
df0e9248 | 1200 | .best_encoder = intel_best_encoder, |
7d57382e EA |
1201 | }; |
1202 | ||
7d57382e | 1203 | static const struct drm_encoder_funcs intel_hdmi_enc_funcs = { |
ea5b213a | 1204 | .destroy = intel_encoder_destroy, |
7d57382e EA |
1205 | }; |
1206 | ||
55b7d6e8 CW |
1207 | static void |
1208 | intel_hdmi_add_properties(struct intel_hdmi *intel_hdmi, struct drm_connector *connector) | |
1209 | { | |
3f43c48d | 1210 | intel_attach_force_audio_property(connector); |
e953fd7b | 1211 | intel_attach_broadcast_rgb_property(connector); |
55bc60db | 1212 | intel_hdmi->color_range_auto = true; |
55b7d6e8 CW |
1213 | } |
1214 | ||
00c09d70 PZ |
1215 | void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port, |
1216 | struct intel_connector *intel_connector) | |
7d57382e | 1217 | { |
b9cb234c PZ |
1218 | struct drm_connector *connector = &intel_connector->base; |
1219 | struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi; | |
1220 | struct intel_encoder *intel_encoder = &intel_dig_port->base; | |
1221 | struct drm_device *dev = intel_encoder->base.dev; | |
7d57382e | 1222 | struct drm_i915_private *dev_priv = dev->dev_private; |
174edf1f | 1223 | enum port port = intel_dig_port->port; |
373a3cf7 | 1224 | |
7d57382e | 1225 | drm_connector_init(dev, connector, &intel_hdmi_connector_funcs, |
8d91104a | 1226 | DRM_MODE_CONNECTOR_HDMIA); |
7d57382e EA |
1227 | drm_connector_helper_add(connector, &intel_hdmi_connector_helper_funcs); |
1228 | ||
c3febcc4 | 1229 | connector->interlace_allowed = 1; |
7d57382e | 1230 | connector->doublescan_allowed = 0; |
66a9278e | 1231 | |
08d644ad DV |
1232 | switch (port) { |
1233 | case PORT_B: | |
f899fc64 | 1234 | intel_hdmi->ddc_bus = GMBUS_PORT_DPB; |
1d843f9d | 1235 | intel_encoder->hpd_pin = HPD_PORT_B; |
08d644ad DV |
1236 | break; |
1237 | case PORT_C: | |
7ceae0a5 | 1238 | intel_hdmi->ddc_bus = GMBUS_PORT_DPC; |
1d843f9d | 1239 | intel_encoder->hpd_pin = HPD_PORT_C; |
08d644ad DV |
1240 | break; |
1241 | case PORT_D: | |
7ceae0a5 | 1242 | intel_hdmi->ddc_bus = GMBUS_PORT_DPD; |
1d843f9d | 1243 | intel_encoder->hpd_pin = HPD_PORT_D; |
08d644ad DV |
1244 | break; |
1245 | case PORT_A: | |
1d843f9d | 1246 | intel_encoder->hpd_pin = HPD_PORT_A; |
08d644ad DV |
1247 | /* Internal port only for eDP. */ |
1248 | default: | |
6e4c1677 | 1249 | BUG(); |
f8aed700 | 1250 | } |
7d57382e | 1251 | |
7637bfdb | 1252 | if (IS_VALLEYVIEW(dev)) { |
90b107c8 | 1253 | intel_hdmi->write_infoframe = vlv_write_infoframe; |
687f4d06 | 1254 | intel_hdmi->set_infoframes = vlv_set_infoframes; |
7637bfdb JB |
1255 | } else if (!HAS_PCH_SPLIT(dev)) { |
1256 | intel_hdmi->write_infoframe = g4x_write_infoframe; | |
1257 | intel_hdmi->set_infoframes = g4x_set_infoframes; | |
22b8bf17 | 1258 | } else if (HAS_DDI(dev)) { |
8c5f5f7c | 1259 | intel_hdmi->write_infoframe = hsw_write_infoframe; |
687f4d06 | 1260 | intel_hdmi->set_infoframes = hsw_set_infoframes; |
fdf1250a PZ |
1261 | } else if (HAS_PCH_IBX(dev)) { |
1262 | intel_hdmi->write_infoframe = ibx_write_infoframe; | |
687f4d06 | 1263 | intel_hdmi->set_infoframes = ibx_set_infoframes; |
fdf1250a PZ |
1264 | } else { |
1265 | intel_hdmi->write_infoframe = cpt_write_infoframe; | |
687f4d06 | 1266 | intel_hdmi->set_infoframes = cpt_set_infoframes; |
64a8fc01 | 1267 | } |
45187ace | 1268 | |
affa9354 | 1269 | if (HAS_DDI(dev)) |
bcbc889b PZ |
1270 | intel_connector->get_hw_state = intel_ddi_connector_get_hw_state; |
1271 | else | |
1272 | intel_connector->get_hw_state = intel_connector_get_hw_state; | |
b9cb234c PZ |
1273 | |
1274 | intel_hdmi_add_properties(intel_hdmi, connector); | |
1275 | ||
1276 | intel_connector_attach_encoder(intel_connector, intel_encoder); | |
1277 | drm_sysfs_connector_add(connector); | |
1278 | ||
1279 | /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written | |
1280 | * 0xd. Failure to do so will result in spurious interrupts being | |
1281 | * generated on the port when a cable is not attached. | |
1282 | */ | |
1283 | if (IS_G4X(dev) && !IS_GM45(dev)) { | |
1284 | u32 temp = I915_READ(PEG_BAND_GAP_DATA); | |
1285 | I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd); | |
1286 | } | |
1287 | } | |
1288 | ||
b242b7f7 | 1289 | void intel_hdmi_init(struct drm_device *dev, int hdmi_reg, enum port port) |
b9cb234c PZ |
1290 | { |
1291 | struct intel_digital_port *intel_dig_port; | |
1292 | struct intel_encoder *intel_encoder; | |
b9cb234c PZ |
1293 | struct intel_connector *intel_connector; |
1294 | ||
b14c5679 | 1295 | intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL); |
b9cb234c PZ |
1296 | if (!intel_dig_port) |
1297 | return; | |
1298 | ||
b14c5679 | 1299 | intel_connector = kzalloc(sizeof(*intel_connector), GFP_KERNEL); |
b9cb234c PZ |
1300 | if (!intel_connector) { |
1301 | kfree(intel_dig_port); | |
1302 | return; | |
1303 | } | |
1304 | ||
1305 | intel_encoder = &intel_dig_port->base; | |
b9cb234c PZ |
1306 | |
1307 | drm_encoder_init(dev, &intel_encoder->base, &intel_hdmi_enc_funcs, | |
1308 | DRM_MODE_ENCODER_TMDS); | |
00c09d70 | 1309 | |
5bfe2ac0 | 1310 | intel_encoder->compute_config = intel_hdmi_compute_config; |
c59423a3 | 1311 | intel_encoder->mode_set = intel_hdmi_mode_set; |
00c09d70 PZ |
1312 | intel_encoder->disable = intel_disable_hdmi; |
1313 | intel_encoder->get_hw_state = intel_hdmi_get_hw_state; | |
045ac3b5 | 1314 | intel_encoder->get_config = intel_hdmi_get_config; |
89b667f8 | 1315 | if (IS_VALLEYVIEW(dev)) { |
89b667f8 | 1316 | intel_encoder->pre_pll_enable = intel_hdmi_pre_pll_enable; |
b76cf76b JN |
1317 | intel_encoder->pre_enable = intel_hdmi_pre_enable; |
1318 | intel_encoder->enable = vlv_enable_hdmi; | |
89b667f8 | 1319 | intel_encoder->post_disable = intel_hdmi_post_disable; |
b76cf76b JN |
1320 | } else { |
1321 | intel_encoder->enable = intel_enable_hdmi; | |
89b667f8 | 1322 | } |
5ab432ef | 1323 | |
b9cb234c PZ |
1324 | intel_encoder->type = INTEL_OUTPUT_HDMI; |
1325 | intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2); | |
1326 | intel_encoder->cloneable = false; | |
7d57382e | 1327 | |
174edf1f | 1328 | intel_dig_port->port = port; |
b242b7f7 | 1329 | intel_dig_port->hdmi.hdmi_reg = hdmi_reg; |
b9cb234c | 1330 | intel_dig_port->dp.output_reg = 0; |
55b7d6e8 | 1331 | |
b9cb234c | 1332 | intel_hdmi_init_connector(intel_dig_port, intel_connector); |
7d57382e | 1333 | } |