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7d57382e EA |
1 | /* |
2 | * Copyright 2006 Dave Airlie <airlied@linux.ie> | |
3 | * Copyright © 2006-2009 Intel Corporation | |
4 | * | |
5 | * Permission is hereby granted, free of charge, to any person obtaining a | |
6 | * copy of this software and associated documentation files (the "Software"), | |
7 | * to deal in the Software without restriction, including without limitation | |
8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
9 | * and/or sell copies of the Software, and to permit persons to whom the | |
10 | * Software is furnished to do so, subject to the following conditions: | |
11 | * | |
12 | * The above copyright notice and this permission notice (including the next | |
13 | * paragraph) shall be included in all copies or substantial portions of the | |
14 | * Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
21 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
22 | * DEALINGS IN THE SOFTWARE. | |
23 | * | |
24 | * Authors: | |
25 | * Eric Anholt <eric@anholt.net> | |
26 | * Jesse Barnes <jesse.barnes@intel.com> | |
27 | */ | |
28 | ||
29 | #include <linux/i2c.h> | |
5a0e3ad6 | 30 | #include <linux/slab.h> |
7d57382e | 31 | #include <linux/delay.h> |
178f736a | 32 | #include <linux/hdmi.h> |
760285e7 | 33 | #include <drm/drmP.h> |
c6f95f27 | 34 | #include <drm/drm_atomic_helper.h> |
760285e7 DH |
35 | #include <drm/drm_crtc.h> |
36 | #include <drm/drm_edid.h> | |
7d57382e | 37 | #include "intel_drv.h" |
760285e7 | 38 | #include <drm/i915_drm.h> |
7d57382e EA |
39 | #include "i915_drv.h" |
40 | ||
30add22d PZ |
41 | static struct drm_device *intel_hdmi_to_dev(struct intel_hdmi *intel_hdmi) |
42 | { | |
da63a9f2 | 43 | return hdmi_to_dig_port(intel_hdmi)->base.base.dev; |
30add22d PZ |
44 | } |
45 | ||
afba0188 DV |
46 | static void |
47 | assert_hdmi_port_disabled(struct intel_hdmi *intel_hdmi) | |
48 | { | |
30add22d | 49 | struct drm_device *dev = intel_hdmi_to_dev(intel_hdmi); |
afba0188 DV |
50 | struct drm_i915_private *dev_priv = dev->dev_private; |
51 | uint32_t enabled_bits; | |
52 | ||
affa9354 | 53 | enabled_bits = HAS_DDI(dev) ? DDI_BUF_CTL_ENABLE : SDVO_ENABLE; |
afba0188 | 54 | |
b242b7f7 | 55 | WARN(I915_READ(intel_hdmi->hdmi_reg) & enabled_bits, |
afba0188 DV |
56 | "HDMI port enabled, expecting disabled\n"); |
57 | } | |
58 | ||
f5bbfca3 | 59 | struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder) |
ea5b213a | 60 | { |
da63a9f2 PZ |
61 | struct intel_digital_port *intel_dig_port = |
62 | container_of(encoder, struct intel_digital_port, base.base); | |
63 | return &intel_dig_port->hdmi; | |
ea5b213a CW |
64 | } |
65 | ||
df0e9248 CW |
66 | static struct intel_hdmi *intel_attached_hdmi(struct drm_connector *connector) |
67 | { | |
da63a9f2 | 68 | return enc_to_intel_hdmi(&intel_attached_encoder(connector)->base); |
df0e9248 CW |
69 | } |
70 | ||
178f736a | 71 | static u32 g4x_infoframe_index(enum hdmi_infoframe_type type) |
3c17fe4b | 72 | { |
178f736a DL |
73 | switch (type) { |
74 | case HDMI_INFOFRAME_TYPE_AVI: | |
ed517fbb | 75 | return VIDEO_DIP_SELECT_AVI; |
178f736a | 76 | case HDMI_INFOFRAME_TYPE_SPD: |
ed517fbb | 77 | return VIDEO_DIP_SELECT_SPD; |
c8bb75af LD |
78 | case HDMI_INFOFRAME_TYPE_VENDOR: |
79 | return VIDEO_DIP_SELECT_VENDOR; | |
45187ace | 80 | default: |
178f736a | 81 | DRM_DEBUG_DRIVER("unknown info frame type %d\n", type); |
ed517fbb | 82 | return 0; |
45187ace | 83 | } |
45187ace JB |
84 | } |
85 | ||
178f736a | 86 | static u32 g4x_infoframe_enable(enum hdmi_infoframe_type type) |
45187ace | 87 | { |
178f736a DL |
88 | switch (type) { |
89 | case HDMI_INFOFRAME_TYPE_AVI: | |
ed517fbb | 90 | return VIDEO_DIP_ENABLE_AVI; |
178f736a | 91 | case HDMI_INFOFRAME_TYPE_SPD: |
ed517fbb | 92 | return VIDEO_DIP_ENABLE_SPD; |
c8bb75af LD |
93 | case HDMI_INFOFRAME_TYPE_VENDOR: |
94 | return VIDEO_DIP_ENABLE_VENDOR; | |
fa193ff7 | 95 | default: |
178f736a | 96 | DRM_DEBUG_DRIVER("unknown info frame type %d\n", type); |
ed517fbb | 97 | return 0; |
fa193ff7 | 98 | } |
fa193ff7 PZ |
99 | } |
100 | ||
178f736a | 101 | static u32 hsw_infoframe_enable(enum hdmi_infoframe_type type) |
2da8af54 | 102 | { |
178f736a DL |
103 | switch (type) { |
104 | case HDMI_INFOFRAME_TYPE_AVI: | |
2da8af54 | 105 | return VIDEO_DIP_ENABLE_AVI_HSW; |
178f736a | 106 | case HDMI_INFOFRAME_TYPE_SPD: |
2da8af54 | 107 | return VIDEO_DIP_ENABLE_SPD_HSW; |
c8bb75af LD |
108 | case HDMI_INFOFRAME_TYPE_VENDOR: |
109 | return VIDEO_DIP_ENABLE_VS_HSW; | |
2da8af54 | 110 | default: |
178f736a | 111 | DRM_DEBUG_DRIVER("unknown info frame type %d\n", type); |
2da8af54 PZ |
112 | return 0; |
113 | } | |
114 | } | |
115 | ||
178f736a | 116 | static u32 hsw_infoframe_data_reg(enum hdmi_infoframe_type type, |
a57c774a AK |
117 | enum transcoder cpu_transcoder, |
118 | struct drm_i915_private *dev_priv) | |
2da8af54 | 119 | { |
178f736a DL |
120 | switch (type) { |
121 | case HDMI_INFOFRAME_TYPE_AVI: | |
7d9bcebe | 122 | return HSW_TVIDEO_DIP_AVI_DATA(cpu_transcoder); |
178f736a | 123 | case HDMI_INFOFRAME_TYPE_SPD: |
7d9bcebe | 124 | return HSW_TVIDEO_DIP_SPD_DATA(cpu_transcoder); |
c8bb75af LD |
125 | case HDMI_INFOFRAME_TYPE_VENDOR: |
126 | return HSW_TVIDEO_DIP_VS_DATA(cpu_transcoder); | |
2da8af54 | 127 | default: |
178f736a | 128 | DRM_DEBUG_DRIVER("unknown info frame type %d\n", type); |
2da8af54 PZ |
129 | return 0; |
130 | } | |
131 | } | |
132 | ||
a3da1df7 | 133 | static void g4x_write_infoframe(struct drm_encoder *encoder, |
178f736a | 134 | enum hdmi_infoframe_type type, |
fff63867 | 135 | const void *frame, ssize_t len) |
45187ace | 136 | { |
fff63867 | 137 | const uint32_t *data = frame; |
3c17fe4b DH |
138 | struct drm_device *dev = encoder->dev; |
139 | struct drm_i915_private *dev_priv = dev->dev_private; | |
22509ec8 | 140 | u32 val = I915_READ(VIDEO_DIP_CTL); |
178f736a | 141 | int i; |
3c17fe4b | 142 | |
822974ae PZ |
143 | WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n"); |
144 | ||
1d4f85ac | 145 | val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ |
178f736a | 146 | val |= g4x_infoframe_index(type); |
22509ec8 | 147 | |
178f736a | 148 | val &= ~g4x_infoframe_enable(type); |
45187ace | 149 | |
22509ec8 | 150 | I915_WRITE(VIDEO_DIP_CTL, val); |
3c17fe4b | 151 | |
9d9740f0 | 152 | mmiowb(); |
45187ace | 153 | for (i = 0; i < len; i += 4) { |
3c17fe4b DH |
154 | I915_WRITE(VIDEO_DIP_DATA, *data); |
155 | data++; | |
156 | } | |
adf00b26 PZ |
157 | /* Write every possible data byte to force correct ECC calculation. */ |
158 | for (; i < VIDEO_DIP_DATA_SIZE; i += 4) | |
159 | I915_WRITE(VIDEO_DIP_DATA, 0); | |
9d9740f0 | 160 | mmiowb(); |
3c17fe4b | 161 | |
178f736a | 162 | val |= g4x_infoframe_enable(type); |
60c5ea2d | 163 | val &= ~VIDEO_DIP_FREQ_MASK; |
4b24c933 | 164 | val |= VIDEO_DIP_FREQ_VSYNC; |
45187ace | 165 | |
22509ec8 | 166 | I915_WRITE(VIDEO_DIP_CTL, val); |
9d9740f0 | 167 | POSTING_READ(VIDEO_DIP_CTL); |
3c17fe4b DH |
168 | } |
169 | ||
e43823ec JB |
170 | static bool g4x_infoframe_enabled(struct drm_encoder *encoder) |
171 | { | |
172 | struct drm_device *dev = encoder->dev; | |
173 | struct drm_i915_private *dev_priv = dev->dev_private; | |
89a35ecd | 174 | struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); |
e43823ec JB |
175 | u32 val = I915_READ(VIDEO_DIP_CTL); |
176 | ||
ec1dc603 VS |
177 | if ((val & VIDEO_DIP_ENABLE) == 0) |
178 | return false; | |
89a35ecd | 179 | |
ec1dc603 VS |
180 | if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(intel_dig_port->port)) |
181 | return false; | |
182 | ||
183 | return val & (VIDEO_DIP_ENABLE_AVI | | |
184 | VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD); | |
e43823ec JB |
185 | } |
186 | ||
fdf1250a | 187 | static void ibx_write_infoframe(struct drm_encoder *encoder, |
178f736a | 188 | enum hdmi_infoframe_type type, |
fff63867 | 189 | const void *frame, ssize_t len) |
fdf1250a | 190 | { |
fff63867 | 191 | const uint32_t *data = frame; |
fdf1250a PZ |
192 | struct drm_device *dev = encoder->dev; |
193 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ed517fbb | 194 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); |
178f736a | 195 | int i, reg = TVIDEO_DIP_CTL(intel_crtc->pipe); |
fdf1250a PZ |
196 | u32 val = I915_READ(reg); |
197 | ||
822974ae PZ |
198 | WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n"); |
199 | ||
fdf1250a | 200 | val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ |
178f736a | 201 | val |= g4x_infoframe_index(type); |
fdf1250a | 202 | |
178f736a | 203 | val &= ~g4x_infoframe_enable(type); |
fdf1250a PZ |
204 | |
205 | I915_WRITE(reg, val); | |
206 | ||
9d9740f0 | 207 | mmiowb(); |
fdf1250a PZ |
208 | for (i = 0; i < len; i += 4) { |
209 | I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data); | |
210 | data++; | |
211 | } | |
adf00b26 PZ |
212 | /* Write every possible data byte to force correct ECC calculation. */ |
213 | for (; i < VIDEO_DIP_DATA_SIZE; i += 4) | |
214 | I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0); | |
9d9740f0 | 215 | mmiowb(); |
fdf1250a | 216 | |
178f736a | 217 | val |= g4x_infoframe_enable(type); |
fdf1250a | 218 | val &= ~VIDEO_DIP_FREQ_MASK; |
4b24c933 | 219 | val |= VIDEO_DIP_FREQ_VSYNC; |
fdf1250a PZ |
220 | |
221 | I915_WRITE(reg, val); | |
9d9740f0 | 222 | POSTING_READ(reg); |
fdf1250a PZ |
223 | } |
224 | ||
e43823ec JB |
225 | static bool ibx_infoframe_enabled(struct drm_encoder *encoder) |
226 | { | |
227 | struct drm_device *dev = encoder->dev; | |
228 | struct drm_i915_private *dev_priv = dev->dev_private; | |
229 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); | |
052f62f7 | 230 | struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); |
e43823ec JB |
231 | int reg = TVIDEO_DIP_CTL(intel_crtc->pipe); |
232 | u32 val = I915_READ(reg); | |
233 | ||
ec1dc603 VS |
234 | if ((val & VIDEO_DIP_ENABLE) == 0) |
235 | return false; | |
236 | ||
237 | if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(intel_dig_port->port)) | |
238 | return false; | |
052f62f7 | 239 | |
ec1dc603 VS |
240 | return val & (VIDEO_DIP_ENABLE_AVI | |
241 | VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | | |
242 | VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); | |
e43823ec JB |
243 | } |
244 | ||
fdf1250a | 245 | static void cpt_write_infoframe(struct drm_encoder *encoder, |
178f736a | 246 | enum hdmi_infoframe_type type, |
fff63867 | 247 | const void *frame, ssize_t len) |
b055c8f3 | 248 | { |
fff63867 | 249 | const uint32_t *data = frame; |
b055c8f3 JB |
250 | struct drm_device *dev = encoder->dev; |
251 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ed517fbb | 252 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); |
178f736a | 253 | int i, reg = TVIDEO_DIP_CTL(intel_crtc->pipe); |
22509ec8 | 254 | u32 val = I915_READ(reg); |
b055c8f3 | 255 | |
822974ae PZ |
256 | WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n"); |
257 | ||
64a8fc01 | 258 | val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ |
178f736a | 259 | val |= g4x_infoframe_index(type); |
45187ace | 260 | |
ecb97851 PZ |
261 | /* The DIP control register spec says that we need to update the AVI |
262 | * infoframe without clearing its enable bit */ | |
178f736a DL |
263 | if (type != HDMI_INFOFRAME_TYPE_AVI) |
264 | val &= ~g4x_infoframe_enable(type); | |
ecb97851 | 265 | |
22509ec8 | 266 | I915_WRITE(reg, val); |
45187ace | 267 | |
9d9740f0 | 268 | mmiowb(); |
45187ace | 269 | for (i = 0; i < len; i += 4) { |
b055c8f3 JB |
270 | I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data); |
271 | data++; | |
272 | } | |
adf00b26 PZ |
273 | /* Write every possible data byte to force correct ECC calculation. */ |
274 | for (; i < VIDEO_DIP_DATA_SIZE; i += 4) | |
275 | I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0); | |
9d9740f0 | 276 | mmiowb(); |
b055c8f3 | 277 | |
178f736a | 278 | val |= g4x_infoframe_enable(type); |
60c5ea2d | 279 | val &= ~VIDEO_DIP_FREQ_MASK; |
4b24c933 | 280 | val |= VIDEO_DIP_FREQ_VSYNC; |
45187ace | 281 | |
22509ec8 | 282 | I915_WRITE(reg, val); |
9d9740f0 | 283 | POSTING_READ(reg); |
45187ace | 284 | } |
90b107c8 | 285 | |
e43823ec JB |
286 | static bool cpt_infoframe_enabled(struct drm_encoder *encoder) |
287 | { | |
288 | struct drm_device *dev = encoder->dev; | |
289 | struct drm_i915_private *dev_priv = dev->dev_private; | |
290 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); | |
291 | int reg = TVIDEO_DIP_CTL(intel_crtc->pipe); | |
292 | u32 val = I915_READ(reg); | |
293 | ||
ec1dc603 VS |
294 | if ((val & VIDEO_DIP_ENABLE) == 0) |
295 | return false; | |
296 | ||
297 | return val & (VIDEO_DIP_ENABLE_AVI | | |
298 | VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | | |
299 | VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); | |
e43823ec JB |
300 | } |
301 | ||
90b107c8 | 302 | static void vlv_write_infoframe(struct drm_encoder *encoder, |
178f736a | 303 | enum hdmi_infoframe_type type, |
fff63867 | 304 | const void *frame, ssize_t len) |
90b107c8 | 305 | { |
fff63867 | 306 | const uint32_t *data = frame; |
90b107c8 SK |
307 | struct drm_device *dev = encoder->dev; |
308 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ed517fbb | 309 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); |
178f736a | 310 | int i, reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe); |
22509ec8 | 311 | u32 val = I915_READ(reg); |
90b107c8 | 312 | |
822974ae PZ |
313 | WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n"); |
314 | ||
90b107c8 | 315 | val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ |
178f736a | 316 | val |= g4x_infoframe_index(type); |
22509ec8 | 317 | |
178f736a | 318 | val &= ~g4x_infoframe_enable(type); |
90b107c8 | 319 | |
22509ec8 | 320 | I915_WRITE(reg, val); |
90b107c8 | 321 | |
9d9740f0 | 322 | mmiowb(); |
90b107c8 SK |
323 | for (i = 0; i < len; i += 4) { |
324 | I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), *data); | |
325 | data++; | |
326 | } | |
adf00b26 PZ |
327 | /* Write every possible data byte to force correct ECC calculation. */ |
328 | for (; i < VIDEO_DIP_DATA_SIZE; i += 4) | |
329 | I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), 0); | |
9d9740f0 | 330 | mmiowb(); |
90b107c8 | 331 | |
178f736a | 332 | val |= g4x_infoframe_enable(type); |
60c5ea2d | 333 | val &= ~VIDEO_DIP_FREQ_MASK; |
4b24c933 | 334 | val |= VIDEO_DIP_FREQ_VSYNC; |
90b107c8 | 335 | |
22509ec8 | 336 | I915_WRITE(reg, val); |
9d9740f0 | 337 | POSTING_READ(reg); |
90b107c8 SK |
338 | } |
339 | ||
e43823ec JB |
340 | static bool vlv_infoframe_enabled(struct drm_encoder *encoder) |
341 | { | |
342 | struct drm_device *dev = encoder->dev; | |
343 | struct drm_i915_private *dev_priv = dev->dev_private; | |
344 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); | |
535afa2e | 345 | struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); |
e43823ec JB |
346 | int reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe); |
347 | u32 val = I915_READ(reg); | |
348 | ||
ec1dc603 VS |
349 | if ((val & VIDEO_DIP_ENABLE) == 0) |
350 | return false; | |
351 | ||
352 | if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(intel_dig_port->port)) | |
353 | return false; | |
535afa2e | 354 | |
ec1dc603 VS |
355 | return val & (VIDEO_DIP_ENABLE_AVI | |
356 | VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | | |
357 | VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); | |
e43823ec JB |
358 | } |
359 | ||
8c5f5f7c | 360 | static void hsw_write_infoframe(struct drm_encoder *encoder, |
178f736a | 361 | enum hdmi_infoframe_type type, |
fff63867 | 362 | const void *frame, ssize_t len) |
8c5f5f7c | 363 | { |
fff63867 | 364 | const uint32_t *data = frame; |
2da8af54 PZ |
365 | struct drm_device *dev = encoder->dev; |
366 | struct drm_i915_private *dev_priv = dev->dev_private; | |
367 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); | |
6e3c9717 | 368 | u32 ctl_reg = HSW_TVIDEO_DIP_CTL(intel_crtc->config->cpu_transcoder); |
178f736a DL |
369 | u32 data_reg; |
370 | int i; | |
2da8af54 | 371 | u32 val = I915_READ(ctl_reg); |
8c5f5f7c | 372 | |
178f736a | 373 | data_reg = hsw_infoframe_data_reg(type, |
6e3c9717 | 374 | intel_crtc->config->cpu_transcoder, |
a57c774a | 375 | dev_priv); |
2da8af54 PZ |
376 | if (data_reg == 0) |
377 | return; | |
378 | ||
178f736a | 379 | val &= ~hsw_infoframe_enable(type); |
2da8af54 PZ |
380 | I915_WRITE(ctl_reg, val); |
381 | ||
9d9740f0 | 382 | mmiowb(); |
2da8af54 PZ |
383 | for (i = 0; i < len; i += 4) { |
384 | I915_WRITE(data_reg + i, *data); | |
385 | data++; | |
386 | } | |
adf00b26 PZ |
387 | /* Write every possible data byte to force correct ECC calculation. */ |
388 | for (; i < VIDEO_DIP_DATA_SIZE; i += 4) | |
389 | I915_WRITE(data_reg + i, 0); | |
9d9740f0 | 390 | mmiowb(); |
8c5f5f7c | 391 | |
178f736a | 392 | val |= hsw_infoframe_enable(type); |
2da8af54 | 393 | I915_WRITE(ctl_reg, val); |
9d9740f0 | 394 | POSTING_READ(ctl_reg); |
8c5f5f7c ED |
395 | } |
396 | ||
e43823ec JB |
397 | static bool hsw_infoframe_enabled(struct drm_encoder *encoder) |
398 | { | |
399 | struct drm_device *dev = encoder->dev; | |
400 | struct drm_i915_private *dev_priv = dev->dev_private; | |
401 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); | |
6e3c9717 | 402 | u32 ctl_reg = HSW_TVIDEO_DIP_CTL(intel_crtc->config->cpu_transcoder); |
e43823ec JB |
403 | u32 val = I915_READ(ctl_reg); |
404 | ||
ec1dc603 VS |
405 | return val & (VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_AVI_HSW | |
406 | VIDEO_DIP_ENABLE_GCP_HSW | VIDEO_DIP_ENABLE_VS_HSW | | |
407 | VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW); | |
e43823ec JB |
408 | } |
409 | ||
5adaea79 DL |
410 | /* |
411 | * The data we write to the DIP data buffer registers is 1 byte bigger than the | |
412 | * HDMI infoframe size because of an ECC/reserved byte at position 3 (starting | |
413 | * at 0). It's also a byte used by DisplayPort so the same DIP registers can be | |
414 | * used for both technologies. | |
415 | * | |
416 | * DW0: Reserved/ECC/DP | HB2 | HB1 | HB0 | |
417 | * DW1: DB3 | DB2 | DB1 | DB0 | |
418 | * DW2: DB7 | DB6 | DB5 | DB4 | |
419 | * DW3: ... | |
420 | * | |
421 | * (HB is Header Byte, DB is Data Byte) | |
422 | * | |
423 | * The hdmi pack() functions don't know about that hardware specific hole so we | |
424 | * trick them by giving an offset into the buffer and moving back the header | |
425 | * bytes by one. | |
426 | */ | |
9198ee5b DL |
427 | static void intel_write_infoframe(struct drm_encoder *encoder, |
428 | union hdmi_infoframe *frame) | |
45187ace JB |
429 | { |
430 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); | |
5adaea79 DL |
431 | uint8_t buffer[VIDEO_DIP_DATA_SIZE]; |
432 | ssize_t len; | |
45187ace | 433 | |
5adaea79 DL |
434 | /* see comment above for the reason for this offset */ |
435 | len = hdmi_infoframe_pack(frame, buffer + 1, sizeof(buffer) - 1); | |
436 | if (len < 0) | |
437 | return; | |
438 | ||
439 | /* Insert the 'hole' (see big comment above) at position 3 */ | |
440 | buffer[0] = buffer[1]; | |
441 | buffer[1] = buffer[2]; | |
442 | buffer[2] = buffer[3]; | |
443 | buffer[3] = 0; | |
444 | len++; | |
45187ace | 445 | |
5adaea79 | 446 | intel_hdmi->write_infoframe(encoder, frame->any.type, buffer, len); |
45187ace JB |
447 | } |
448 | ||
687f4d06 | 449 | static void intel_hdmi_set_avi_infoframe(struct drm_encoder *encoder, |
c846b619 | 450 | struct drm_display_mode *adjusted_mode) |
45187ace | 451 | { |
abedc077 | 452 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); |
50f3b016 | 453 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); |
5adaea79 DL |
454 | union hdmi_infoframe frame; |
455 | int ret; | |
45187ace | 456 | |
5adaea79 DL |
457 | ret = drm_hdmi_avi_infoframe_from_display_mode(&frame.avi, |
458 | adjusted_mode); | |
459 | if (ret < 0) { | |
460 | DRM_ERROR("couldn't fill AVI infoframe\n"); | |
461 | return; | |
462 | } | |
c846b619 | 463 | |
abedc077 | 464 | if (intel_hdmi->rgb_quant_range_selectable) { |
6e3c9717 | 465 | if (intel_crtc->config->limited_color_range) |
5adaea79 DL |
466 | frame.avi.quantization_range = |
467 | HDMI_QUANTIZATION_RANGE_LIMITED; | |
abedc077 | 468 | else |
5adaea79 DL |
469 | frame.avi.quantization_range = |
470 | HDMI_QUANTIZATION_RANGE_FULL; | |
abedc077 VS |
471 | } |
472 | ||
9198ee5b | 473 | intel_write_infoframe(encoder, &frame); |
b055c8f3 JB |
474 | } |
475 | ||
687f4d06 | 476 | static void intel_hdmi_set_spd_infoframe(struct drm_encoder *encoder) |
c0864cb3 | 477 | { |
5adaea79 DL |
478 | union hdmi_infoframe frame; |
479 | int ret; | |
480 | ||
481 | ret = hdmi_spd_infoframe_init(&frame.spd, "Intel", "Integrated gfx"); | |
482 | if (ret < 0) { | |
483 | DRM_ERROR("couldn't fill SPD infoframe\n"); | |
484 | return; | |
485 | } | |
c0864cb3 | 486 | |
5adaea79 | 487 | frame.spd.sdi = HDMI_SPD_SDI_PC; |
c0864cb3 | 488 | |
9198ee5b | 489 | intel_write_infoframe(encoder, &frame); |
c0864cb3 JB |
490 | } |
491 | ||
c8bb75af LD |
492 | static void |
493 | intel_hdmi_set_hdmi_infoframe(struct drm_encoder *encoder, | |
494 | struct drm_display_mode *adjusted_mode) | |
495 | { | |
496 | union hdmi_infoframe frame; | |
497 | int ret; | |
498 | ||
499 | ret = drm_hdmi_vendor_infoframe_from_display_mode(&frame.vendor.hdmi, | |
500 | adjusted_mode); | |
501 | if (ret < 0) | |
502 | return; | |
503 | ||
504 | intel_write_infoframe(encoder, &frame); | |
505 | } | |
506 | ||
687f4d06 | 507 | static void g4x_set_infoframes(struct drm_encoder *encoder, |
6897b4b5 | 508 | bool enable, |
687f4d06 PZ |
509 | struct drm_display_mode *adjusted_mode) |
510 | { | |
0c14c7f9 | 511 | struct drm_i915_private *dev_priv = encoder->dev->dev_private; |
69fde0a6 VS |
512 | struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); |
513 | struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi; | |
0c14c7f9 PZ |
514 | u32 reg = VIDEO_DIP_CTL; |
515 | u32 val = I915_READ(reg); | |
822cdc52 | 516 | u32 port = VIDEO_DIP_PORT(intel_dig_port->port); |
0c14c7f9 | 517 | |
afba0188 DV |
518 | assert_hdmi_port_disabled(intel_hdmi); |
519 | ||
0c14c7f9 PZ |
520 | /* If the registers were not initialized yet, they might be zeroes, |
521 | * which means we're selecting the AVI DIP and we're setting its | |
522 | * frequency to once. This seems to really confuse the HW and make | |
523 | * things stop working (the register spec says the AVI always needs to | |
524 | * be sent every VSync). So here we avoid writing to the register more | |
525 | * than we need and also explicitly select the AVI DIP and explicitly | |
526 | * set its frequency to every VSync. Avoiding to write it twice seems to | |
527 | * be enough to solve the problem, but being defensive shouldn't hurt us | |
528 | * either. */ | |
529 | val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; | |
530 | ||
6897b4b5 | 531 | if (!enable) { |
0c14c7f9 PZ |
532 | if (!(val & VIDEO_DIP_ENABLE)) |
533 | return; | |
0be6f0c8 VS |
534 | if (port != (val & VIDEO_DIP_PORT_MASK)) { |
535 | DRM_DEBUG_KMS("video DIP still enabled on port %c\n", | |
536 | (val & VIDEO_DIP_PORT_MASK) >> 29); | |
537 | return; | |
538 | } | |
539 | val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI | | |
540 | VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD); | |
0c14c7f9 | 541 | I915_WRITE(reg, val); |
9d9740f0 | 542 | POSTING_READ(reg); |
0c14c7f9 PZ |
543 | return; |
544 | } | |
545 | ||
72b78c9d PZ |
546 | if (port != (val & VIDEO_DIP_PORT_MASK)) { |
547 | if (val & VIDEO_DIP_ENABLE) { | |
0be6f0c8 VS |
548 | DRM_DEBUG_KMS("video DIP already enabled on port %c\n", |
549 | (val & VIDEO_DIP_PORT_MASK) >> 29); | |
550 | return; | |
72b78c9d PZ |
551 | } |
552 | val &= ~VIDEO_DIP_PORT_MASK; | |
553 | val |= port; | |
554 | } | |
555 | ||
822974ae | 556 | val |= VIDEO_DIP_ENABLE; |
0be6f0c8 VS |
557 | val &= ~(VIDEO_DIP_ENABLE_AVI | |
558 | VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD); | |
822974ae | 559 | |
f278d972 | 560 | I915_WRITE(reg, val); |
9d9740f0 | 561 | POSTING_READ(reg); |
f278d972 | 562 | |
687f4d06 PZ |
563 | intel_hdmi_set_avi_infoframe(encoder, adjusted_mode); |
564 | intel_hdmi_set_spd_infoframe(encoder); | |
c8bb75af | 565 | intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode); |
687f4d06 PZ |
566 | } |
567 | ||
6d67415f VS |
568 | static bool hdmi_sink_is_deep_color(struct drm_encoder *encoder) |
569 | { | |
570 | struct drm_device *dev = encoder->dev; | |
571 | struct drm_connector *connector; | |
572 | ||
573 | WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex)); | |
574 | ||
575 | /* | |
576 | * HDMI cloning is only supported on g4x which doesn't | |
577 | * support deep color or GCP infoframes anyway so no | |
578 | * need to worry about multiple HDMI sinks here. | |
579 | */ | |
580 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) | |
581 | if (connector->encoder == encoder) | |
582 | return connector->display_info.bpc > 8; | |
583 | ||
584 | return false; | |
585 | } | |
586 | ||
12aa3290 VS |
587 | /* |
588 | * Determine if default_phase=1 can be indicated in the GCP infoframe. | |
589 | * | |
590 | * From HDMI specification 1.4a: | |
591 | * - The first pixel of each Video Data Period shall always have a pixel packing phase of 0 | |
592 | * - The first pixel following each Video Data Period shall have a pixel packing phase of 0 | |
593 | * - The PP bits shall be constant for all GCPs and will be equal to the last packing phase | |
594 | * - The first pixel following every transition of HSYNC or VSYNC shall have a pixel packing | |
595 | * phase of 0 | |
596 | */ | |
597 | static bool gcp_default_phase_possible(int pipe_bpp, | |
598 | const struct drm_display_mode *mode) | |
599 | { | |
600 | unsigned int pixels_per_group; | |
601 | ||
602 | switch (pipe_bpp) { | |
603 | case 30: | |
604 | /* 4 pixels in 5 clocks */ | |
605 | pixels_per_group = 4; | |
606 | break; | |
607 | case 36: | |
608 | /* 2 pixels in 3 clocks */ | |
609 | pixels_per_group = 2; | |
610 | break; | |
611 | case 48: | |
612 | /* 1 pixel in 2 clocks */ | |
613 | pixels_per_group = 1; | |
614 | break; | |
615 | default: | |
616 | /* phase information not relevant for 8bpc */ | |
617 | return false; | |
618 | } | |
619 | ||
620 | return mode->crtc_hdisplay % pixels_per_group == 0 && | |
621 | mode->crtc_htotal % pixels_per_group == 0 && | |
622 | mode->crtc_hblank_start % pixels_per_group == 0 && | |
623 | mode->crtc_hblank_end % pixels_per_group == 0 && | |
624 | mode->crtc_hsync_start % pixels_per_group == 0 && | |
625 | mode->crtc_hsync_end % pixels_per_group == 0 && | |
626 | ((mode->flags & DRM_MODE_FLAG_INTERLACE) == 0 || | |
627 | mode->crtc_htotal/2 % pixels_per_group == 0); | |
628 | } | |
629 | ||
6d67415f VS |
630 | static bool intel_hdmi_set_gcp_infoframe(struct drm_encoder *encoder) |
631 | { | |
632 | struct drm_i915_private *dev_priv = encoder->dev->dev_private; | |
633 | struct intel_crtc *crtc = to_intel_crtc(encoder->crtc); | |
634 | u32 reg, val = 0; | |
635 | ||
636 | if (HAS_DDI(dev_priv)) | |
637 | reg = HSW_TVIDEO_DIP_GCP(crtc->config->cpu_transcoder); | |
638 | else if (IS_VALLEYVIEW(dev_priv)) | |
639 | reg = VLV_TVIDEO_DIP_GCP(crtc->pipe); | |
640 | else if (HAS_PCH_SPLIT(dev_priv->dev)) | |
641 | reg = TVIDEO_DIP_GCP(crtc->pipe); | |
642 | else | |
643 | return false; | |
644 | ||
645 | /* Indicate color depth whenever the sink supports deep color */ | |
646 | if (hdmi_sink_is_deep_color(encoder)) | |
647 | val |= GCP_COLOR_INDICATION; | |
648 | ||
12aa3290 VS |
649 | /* Enable default_phase whenever the display mode is suitably aligned */ |
650 | if (gcp_default_phase_possible(crtc->config->pipe_bpp, | |
651 | &crtc->config->base.adjusted_mode)) | |
652 | val |= GCP_DEFAULT_PHASE_ENABLE; | |
653 | ||
6d67415f VS |
654 | I915_WRITE(reg, val); |
655 | ||
656 | return val != 0; | |
657 | } | |
658 | ||
687f4d06 | 659 | static void ibx_set_infoframes(struct drm_encoder *encoder, |
6897b4b5 | 660 | bool enable, |
687f4d06 PZ |
661 | struct drm_display_mode *adjusted_mode) |
662 | { | |
0c14c7f9 PZ |
663 | struct drm_i915_private *dev_priv = encoder->dev->dev_private; |
664 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); | |
69fde0a6 VS |
665 | struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); |
666 | struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi; | |
0c14c7f9 PZ |
667 | u32 reg = TVIDEO_DIP_CTL(intel_crtc->pipe); |
668 | u32 val = I915_READ(reg); | |
822cdc52 | 669 | u32 port = VIDEO_DIP_PORT(intel_dig_port->port); |
0c14c7f9 | 670 | |
afba0188 DV |
671 | assert_hdmi_port_disabled(intel_hdmi); |
672 | ||
0c14c7f9 PZ |
673 | /* See the big comment in g4x_set_infoframes() */ |
674 | val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; | |
675 | ||
6897b4b5 | 676 | if (!enable) { |
0c14c7f9 PZ |
677 | if (!(val & VIDEO_DIP_ENABLE)) |
678 | return; | |
0be6f0c8 VS |
679 | val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI | |
680 | VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | | |
681 | VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); | |
0c14c7f9 | 682 | I915_WRITE(reg, val); |
9d9740f0 | 683 | POSTING_READ(reg); |
0c14c7f9 PZ |
684 | return; |
685 | } | |
686 | ||
72b78c9d | 687 | if (port != (val & VIDEO_DIP_PORT_MASK)) { |
0be6f0c8 VS |
688 | WARN(val & VIDEO_DIP_ENABLE, |
689 | "DIP already enabled on port %c\n", | |
690 | (val & VIDEO_DIP_PORT_MASK) >> 29); | |
72b78c9d PZ |
691 | val &= ~VIDEO_DIP_PORT_MASK; |
692 | val |= port; | |
693 | } | |
694 | ||
822974ae | 695 | val |= VIDEO_DIP_ENABLE; |
0be6f0c8 VS |
696 | val &= ~(VIDEO_DIP_ENABLE_AVI | |
697 | VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | | |
698 | VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); | |
822974ae | 699 | |
6d67415f VS |
700 | if (intel_hdmi_set_gcp_infoframe(encoder)) |
701 | val |= VIDEO_DIP_ENABLE_GCP; | |
702 | ||
f278d972 | 703 | I915_WRITE(reg, val); |
9d9740f0 | 704 | POSTING_READ(reg); |
f278d972 | 705 | |
687f4d06 PZ |
706 | intel_hdmi_set_avi_infoframe(encoder, adjusted_mode); |
707 | intel_hdmi_set_spd_infoframe(encoder); | |
c8bb75af | 708 | intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode); |
687f4d06 PZ |
709 | } |
710 | ||
711 | static void cpt_set_infoframes(struct drm_encoder *encoder, | |
6897b4b5 | 712 | bool enable, |
687f4d06 PZ |
713 | struct drm_display_mode *adjusted_mode) |
714 | { | |
0c14c7f9 PZ |
715 | struct drm_i915_private *dev_priv = encoder->dev->dev_private; |
716 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); | |
717 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); | |
718 | u32 reg = TVIDEO_DIP_CTL(intel_crtc->pipe); | |
719 | u32 val = I915_READ(reg); | |
720 | ||
afba0188 DV |
721 | assert_hdmi_port_disabled(intel_hdmi); |
722 | ||
0c14c7f9 PZ |
723 | /* See the big comment in g4x_set_infoframes() */ |
724 | val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; | |
725 | ||
6897b4b5 | 726 | if (!enable) { |
0c14c7f9 PZ |
727 | if (!(val & VIDEO_DIP_ENABLE)) |
728 | return; | |
0be6f0c8 VS |
729 | val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI | |
730 | VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | | |
731 | VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); | |
0c14c7f9 | 732 | I915_WRITE(reg, val); |
9d9740f0 | 733 | POSTING_READ(reg); |
0c14c7f9 PZ |
734 | return; |
735 | } | |
736 | ||
822974ae PZ |
737 | /* Set both together, unset both together: see the spec. */ |
738 | val |= VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI; | |
0dd87d20 | 739 | val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | |
0be6f0c8 | 740 | VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); |
822974ae | 741 | |
6d67415f VS |
742 | if (intel_hdmi_set_gcp_infoframe(encoder)) |
743 | val |= VIDEO_DIP_ENABLE_GCP; | |
744 | ||
822974ae | 745 | I915_WRITE(reg, val); |
9d9740f0 | 746 | POSTING_READ(reg); |
822974ae | 747 | |
687f4d06 PZ |
748 | intel_hdmi_set_avi_infoframe(encoder, adjusted_mode); |
749 | intel_hdmi_set_spd_infoframe(encoder); | |
c8bb75af | 750 | intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode); |
687f4d06 PZ |
751 | } |
752 | ||
753 | static void vlv_set_infoframes(struct drm_encoder *encoder, | |
6897b4b5 | 754 | bool enable, |
687f4d06 PZ |
755 | struct drm_display_mode *adjusted_mode) |
756 | { | |
0c14c7f9 | 757 | struct drm_i915_private *dev_priv = encoder->dev->dev_private; |
6a2b8021 | 758 | struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); |
0c14c7f9 PZ |
759 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); |
760 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); | |
761 | u32 reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe); | |
762 | u32 val = I915_READ(reg); | |
6a2b8021 | 763 | u32 port = VIDEO_DIP_PORT(intel_dig_port->port); |
0c14c7f9 | 764 | |
afba0188 DV |
765 | assert_hdmi_port_disabled(intel_hdmi); |
766 | ||
0c14c7f9 PZ |
767 | /* See the big comment in g4x_set_infoframes() */ |
768 | val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; | |
769 | ||
6897b4b5 | 770 | if (!enable) { |
0c14c7f9 PZ |
771 | if (!(val & VIDEO_DIP_ENABLE)) |
772 | return; | |
0be6f0c8 VS |
773 | val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI | |
774 | VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | | |
775 | VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); | |
0c14c7f9 | 776 | I915_WRITE(reg, val); |
9d9740f0 | 777 | POSTING_READ(reg); |
0c14c7f9 PZ |
778 | return; |
779 | } | |
780 | ||
6a2b8021 | 781 | if (port != (val & VIDEO_DIP_PORT_MASK)) { |
0be6f0c8 VS |
782 | WARN(val & VIDEO_DIP_ENABLE, |
783 | "DIP already enabled on port %c\n", | |
784 | (val & VIDEO_DIP_PORT_MASK) >> 29); | |
6a2b8021 JB |
785 | val &= ~VIDEO_DIP_PORT_MASK; |
786 | val |= port; | |
787 | } | |
788 | ||
822974ae | 789 | val |= VIDEO_DIP_ENABLE; |
0be6f0c8 VS |
790 | val &= ~(VIDEO_DIP_ENABLE_AVI | |
791 | VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | | |
792 | VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); | |
822974ae | 793 | |
6d67415f VS |
794 | if (intel_hdmi_set_gcp_infoframe(encoder)) |
795 | val |= VIDEO_DIP_ENABLE_GCP; | |
796 | ||
822974ae | 797 | I915_WRITE(reg, val); |
9d9740f0 | 798 | POSTING_READ(reg); |
822974ae | 799 | |
687f4d06 PZ |
800 | intel_hdmi_set_avi_infoframe(encoder, adjusted_mode); |
801 | intel_hdmi_set_spd_infoframe(encoder); | |
c8bb75af | 802 | intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode); |
687f4d06 PZ |
803 | } |
804 | ||
805 | static void hsw_set_infoframes(struct drm_encoder *encoder, | |
6897b4b5 | 806 | bool enable, |
687f4d06 PZ |
807 | struct drm_display_mode *adjusted_mode) |
808 | { | |
0c14c7f9 PZ |
809 | struct drm_i915_private *dev_priv = encoder->dev->dev_private; |
810 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); | |
811 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); | |
6e3c9717 | 812 | u32 reg = HSW_TVIDEO_DIP_CTL(intel_crtc->config->cpu_transcoder); |
0dd87d20 | 813 | u32 val = I915_READ(reg); |
0c14c7f9 | 814 | |
afba0188 DV |
815 | assert_hdmi_port_disabled(intel_hdmi); |
816 | ||
0be6f0c8 VS |
817 | val &= ~(VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_AVI_HSW | |
818 | VIDEO_DIP_ENABLE_GCP_HSW | VIDEO_DIP_ENABLE_VS_HSW | | |
819 | VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW); | |
820 | ||
6897b4b5 | 821 | if (!enable) { |
0be6f0c8 | 822 | I915_WRITE(reg, val); |
9d9740f0 | 823 | POSTING_READ(reg); |
0c14c7f9 PZ |
824 | return; |
825 | } | |
826 | ||
6d67415f VS |
827 | if (intel_hdmi_set_gcp_infoframe(encoder)) |
828 | val |= VIDEO_DIP_ENABLE_GCP_HSW; | |
829 | ||
0dd87d20 | 830 | I915_WRITE(reg, val); |
9d9740f0 | 831 | POSTING_READ(reg); |
0dd87d20 | 832 | |
687f4d06 PZ |
833 | intel_hdmi_set_avi_infoframe(encoder, adjusted_mode); |
834 | intel_hdmi_set_spd_infoframe(encoder); | |
c8bb75af | 835 | intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode); |
687f4d06 PZ |
836 | } |
837 | ||
4cde8a21 | 838 | static void intel_hdmi_prepare(struct intel_encoder *encoder) |
7d57382e | 839 | { |
c59423a3 | 840 | struct drm_device *dev = encoder->base.dev; |
7d57382e | 841 | struct drm_i915_private *dev_priv = dev->dev_private; |
c59423a3 DV |
842 | struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); |
843 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); | |
6e3c9717 | 844 | struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode; |
b242b7f7 | 845 | u32 hdmi_val; |
7d57382e | 846 | |
b242b7f7 | 847 | hdmi_val = SDVO_ENCODING_HDMI; |
0f2a2a75 VS |
848 | if (!HAS_PCH_SPLIT(dev) && crtc->config->limited_color_range) |
849 | hdmi_val |= HDMI_COLOR_RANGE_16_235; | |
b599c0bc | 850 | if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) |
b242b7f7 | 851 | hdmi_val |= SDVO_VSYNC_ACTIVE_HIGH; |
b599c0bc | 852 | if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) |
b242b7f7 | 853 | hdmi_val |= SDVO_HSYNC_ACTIVE_HIGH; |
7d57382e | 854 | |
6e3c9717 | 855 | if (crtc->config->pipe_bpp > 24) |
4f3a8bc7 | 856 | hdmi_val |= HDMI_COLOR_FORMAT_12bpc; |
020f6704 | 857 | else |
4f3a8bc7 | 858 | hdmi_val |= SDVO_COLOR_FORMAT_8bpc; |
020f6704 | 859 | |
6e3c9717 | 860 | if (crtc->config->has_hdmi_sink) |
dc0fa718 | 861 | hdmi_val |= HDMI_MODE_SELECT_HDMI; |
2e3d6006 | 862 | |
75770564 | 863 | if (HAS_PCH_CPT(dev)) |
c59423a3 | 864 | hdmi_val |= SDVO_PIPE_SEL_CPT(crtc->pipe); |
44f37d1f CML |
865 | else if (IS_CHERRYVIEW(dev)) |
866 | hdmi_val |= SDVO_PIPE_SEL_CHV(crtc->pipe); | |
dc0fa718 | 867 | else |
c59423a3 | 868 | hdmi_val |= SDVO_PIPE_SEL(crtc->pipe); |
7d57382e | 869 | |
b242b7f7 PZ |
870 | I915_WRITE(intel_hdmi->hdmi_reg, hdmi_val); |
871 | POSTING_READ(intel_hdmi->hdmi_reg); | |
7d57382e EA |
872 | } |
873 | ||
85234cdc DV |
874 | static bool intel_hdmi_get_hw_state(struct intel_encoder *encoder, |
875 | enum pipe *pipe) | |
7d57382e | 876 | { |
85234cdc | 877 | struct drm_device *dev = encoder->base.dev; |
7d57382e | 878 | struct drm_i915_private *dev_priv = dev->dev_private; |
85234cdc | 879 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); |
6d129bea | 880 | enum intel_display_power_domain power_domain; |
85234cdc DV |
881 | u32 tmp; |
882 | ||
6d129bea | 883 | power_domain = intel_display_port_power_domain(encoder); |
f458ebbc | 884 | if (!intel_display_power_is_enabled(dev_priv, power_domain)) |
6d129bea ID |
885 | return false; |
886 | ||
b242b7f7 | 887 | tmp = I915_READ(intel_hdmi->hdmi_reg); |
85234cdc DV |
888 | |
889 | if (!(tmp & SDVO_ENABLE)) | |
890 | return false; | |
891 | ||
892 | if (HAS_PCH_CPT(dev)) | |
893 | *pipe = PORT_TO_PIPE_CPT(tmp); | |
71485e0a VS |
894 | else if (IS_CHERRYVIEW(dev)) |
895 | *pipe = SDVO_PORT_TO_PIPE_CHV(tmp); | |
85234cdc DV |
896 | else |
897 | *pipe = PORT_TO_PIPE(tmp); | |
898 | ||
899 | return true; | |
900 | } | |
901 | ||
045ac3b5 | 902 | static void intel_hdmi_get_config(struct intel_encoder *encoder, |
5cec258b | 903 | struct intel_crtc_state *pipe_config) |
045ac3b5 JB |
904 | { |
905 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); | |
8c875fca VS |
906 | struct drm_device *dev = encoder->base.dev; |
907 | struct drm_i915_private *dev_priv = dev->dev_private; | |
045ac3b5 | 908 | u32 tmp, flags = 0; |
18442d08 | 909 | int dotclock; |
045ac3b5 JB |
910 | |
911 | tmp = I915_READ(intel_hdmi->hdmi_reg); | |
912 | ||
913 | if (tmp & SDVO_HSYNC_ACTIVE_HIGH) | |
914 | flags |= DRM_MODE_FLAG_PHSYNC; | |
915 | else | |
916 | flags |= DRM_MODE_FLAG_NHSYNC; | |
917 | ||
918 | if (tmp & SDVO_VSYNC_ACTIVE_HIGH) | |
919 | flags |= DRM_MODE_FLAG_PVSYNC; | |
920 | else | |
921 | flags |= DRM_MODE_FLAG_NVSYNC; | |
922 | ||
6897b4b5 DV |
923 | if (tmp & HDMI_MODE_SELECT_HDMI) |
924 | pipe_config->has_hdmi_sink = true; | |
925 | ||
e43823ec JB |
926 | if (intel_hdmi->infoframe_enabled(&encoder->base)) |
927 | pipe_config->has_infoframe = true; | |
928 | ||
c84db770 | 929 | if (tmp & SDVO_AUDIO_ENABLE) |
9ed109a7 DV |
930 | pipe_config->has_audio = true; |
931 | ||
8c875fca VS |
932 | if (!HAS_PCH_SPLIT(dev) && |
933 | tmp & HDMI_COLOR_RANGE_16_235) | |
934 | pipe_config->limited_color_range = true; | |
935 | ||
2d112de7 | 936 | pipe_config->base.adjusted_mode.flags |= flags; |
18442d08 VS |
937 | |
938 | if ((tmp & SDVO_COLOR_FORMAT_MASK) == HDMI_COLOR_FORMAT_12bpc) | |
939 | dotclock = pipe_config->port_clock * 2 / 3; | |
940 | else | |
941 | dotclock = pipe_config->port_clock; | |
942 | ||
be69a133 VS |
943 | if (pipe_config->pixel_multiplier) |
944 | dotclock /= pipe_config->pixel_multiplier; | |
945 | ||
18442d08 VS |
946 | if (HAS_PCH_SPLIT(dev_priv->dev)) |
947 | ironlake_check_encoder_dotclock(pipe_config, dotclock); | |
948 | ||
2d112de7 | 949 | pipe_config->base.adjusted_mode.crtc_clock = dotclock; |
045ac3b5 JB |
950 | } |
951 | ||
d1b1589c VS |
952 | static void intel_enable_hdmi_audio(struct intel_encoder *encoder) |
953 | { | |
954 | struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); | |
955 | ||
956 | WARN_ON(!crtc->config->has_hdmi_sink); | |
957 | DRM_DEBUG_DRIVER("Enabling HDMI audio on pipe %c\n", | |
958 | pipe_name(crtc->pipe)); | |
959 | intel_audio_codec_enable(encoder); | |
960 | } | |
961 | ||
bf868c7d | 962 | static void g4x_enable_hdmi(struct intel_encoder *encoder) |
7d57382e | 963 | { |
5ab432ef | 964 | struct drm_device *dev = encoder->base.dev; |
7d57382e | 965 | struct drm_i915_private *dev_priv = dev->dev_private; |
bf868c7d | 966 | struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); |
5ab432ef | 967 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); |
7d57382e EA |
968 | u32 temp; |
969 | ||
b242b7f7 | 970 | temp = I915_READ(intel_hdmi->hdmi_reg); |
d8a2d0e0 | 971 | |
bf868c7d VS |
972 | temp |= SDVO_ENABLE; |
973 | if (crtc->config->has_audio) | |
974 | temp |= SDVO_AUDIO_ENABLE; | |
7a87c289 | 975 | |
bf868c7d VS |
976 | I915_WRITE(intel_hdmi->hdmi_reg, temp); |
977 | POSTING_READ(intel_hdmi->hdmi_reg); | |
978 | ||
979 | if (crtc->config->has_audio) | |
980 | intel_enable_hdmi_audio(encoder); | |
981 | } | |
982 | ||
983 | static void ibx_enable_hdmi(struct intel_encoder *encoder) | |
984 | { | |
985 | struct drm_device *dev = encoder->base.dev; | |
986 | struct drm_i915_private *dev_priv = dev->dev_private; | |
987 | struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); | |
988 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); | |
989 | u32 temp; | |
990 | ||
991 | temp = I915_READ(intel_hdmi->hdmi_reg); | |
d8a2d0e0 | 992 | |
bf868c7d VS |
993 | temp |= SDVO_ENABLE; |
994 | if (crtc->config->has_audio) | |
995 | temp |= SDVO_AUDIO_ENABLE; | |
5ab432ef | 996 | |
bf868c7d VS |
997 | /* |
998 | * HW workaround, need to write this twice for issue | |
999 | * that may result in first write getting masked. | |
1000 | */ | |
1001 | I915_WRITE(intel_hdmi->hdmi_reg, temp); | |
1002 | POSTING_READ(intel_hdmi->hdmi_reg); | |
b242b7f7 PZ |
1003 | I915_WRITE(intel_hdmi->hdmi_reg, temp); |
1004 | POSTING_READ(intel_hdmi->hdmi_reg); | |
5ab432ef | 1005 | |
bf868c7d VS |
1006 | /* |
1007 | * HW workaround, need to toggle enable bit off and on | |
1008 | * for 12bpc with pixel repeat. | |
1009 | * | |
1010 | * FIXME: BSpec says this should be done at the end of | |
1011 | * of the modeset sequence, so not sure if this isn't too soon. | |
5ab432ef | 1012 | */ |
bf868c7d VS |
1013 | if (crtc->config->pipe_bpp > 24 && |
1014 | crtc->config->pixel_multiplier > 1) { | |
1015 | I915_WRITE(intel_hdmi->hdmi_reg, temp & ~SDVO_ENABLE); | |
1016 | POSTING_READ(intel_hdmi->hdmi_reg); | |
1017 | ||
1018 | /* | |
1019 | * HW workaround, need to write this twice for issue | |
1020 | * that may result in first write getting masked. | |
1021 | */ | |
1022 | I915_WRITE(intel_hdmi->hdmi_reg, temp); | |
1023 | POSTING_READ(intel_hdmi->hdmi_reg); | |
b242b7f7 PZ |
1024 | I915_WRITE(intel_hdmi->hdmi_reg, temp); |
1025 | POSTING_READ(intel_hdmi->hdmi_reg); | |
7d57382e | 1026 | } |
c1dec79a | 1027 | |
bf868c7d | 1028 | if (crtc->config->has_audio) |
d1b1589c VS |
1029 | intel_enable_hdmi_audio(encoder); |
1030 | } | |
1031 | ||
1032 | static void cpt_enable_hdmi(struct intel_encoder *encoder) | |
1033 | { | |
1034 | struct drm_device *dev = encoder->base.dev; | |
1035 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1036 | struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); | |
1037 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); | |
1038 | enum pipe pipe = crtc->pipe; | |
1039 | u32 temp; | |
1040 | ||
1041 | temp = I915_READ(intel_hdmi->hdmi_reg); | |
1042 | ||
1043 | temp |= SDVO_ENABLE; | |
1044 | if (crtc->config->has_audio) | |
1045 | temp |= SDVO_AUDIO_ENABLE; | |
1046 | ||
1047 | /* | |
1048 | * WaEnableHDMI8bpcBefore12bpc:snb,ivb | |
1049 | * | |
1050 | * The procedure for 12bpc is as follows: | |
1051 | * 1. disable HDMI clock gating | |
1052 | * 2. enable HDMI with 8bpc | |
1053 | * 3. enable HDMI with 12bpc | |
1054 | * 4. enable HDMI clock gating | |
1055 | */ | |
1056 | ||
1057 | if (crtc->config->pipe_bpp > 24) { | |
1058 | I915_WRITE(TRANS_CHICKEN1(pipe), | |
1059 | I915_READ(TRANS_CHICKEN1(pipe)) | | |
1060 | TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE); | |
1061 | ||
1062 | temp &= ~SDVO_COLOR_FORMAT_MASK; | |
1063 | temp |= SDVO_COLOR_FORMAT_8bpc; | |
c1dec79a | 1064 | } |
d1b1589c VS |
1065 | |
1066 | I915_WRITE(intel_hdmi->hdmi_reg, temp); | |
1067 | POSTING_READ(intel_hdmi->hdmi_reg); | |
1068 | ||
1069 | if (crtc->config->pipe_bpp > 24) { | |
1070 | temp &= ~SDVO_COLOR_FORMAT_MASK; | |
1071 | temp |= HDMI_COLOR_FORMAT_12bpc; | |
1072 | ||
1073 | I915_WRITE(intel_hdmi->hdmi_reg, temp); | |
1074 | POSTING_READ(intel_hdmi->hdmi_reg); | |
1075 | ||
1076 | I915_WRITE(TRANS_CHICKEN1(pipe), | |
1077 | I915_READ(TRANS_CHICKEN1(pipe)) & | |
1078 | ~TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE); | |
1079 | } | |
1080 | ||
1081 | if (crtc->config->has_audio) | |
1082 | intel_enable_hdmi_audio(encoder); | |
b76cf76b | 1083 | } |
89b667f8 | 1084 | |
b76cf76b JN |
1085 | static void vlv_enable_hdmi(struct intel_encoder *encoder) |
1086 | { | |
5ab432ef DV |
1087 | } |
1088 | ||
1089 | static void intel_disable_hdmi(struct intel_encoder *encoder) | |
1090 | { | |
1091 | struct drm_device *dev = encoder->base.dev; | |
1092 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1093 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); | |
495a5bb8 | 1094 | struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); |
5ab432ef | 1095 | u32 temp; |
5ab432ef | 1096 | |
b242b7f7 | 1097 | temp = I915_READ(intel_hdmi->hdmi_reg); |
5ab432ef | 1098 | |
1612c8bd | 1099 | temp &= ~(SDVO_ENABLE | SDVO_AUDIO_ENABLE); |
b242b7f7 PZ |
1100 | I915_WRITE(intel_hdmi->hdmi_reg, temp); |
1101 | POSTING_READ(intel_hdmi->hdmi_reg); | |
1612c8bd VS |
1102 | |
1103 | /* | |
1104 | * HW workaround for IBX, we need to move the port | |
1105 | * to transcoder A after disabling it to allow the | |
1106 | * matching DP port to be enabled on transcoder A. | |
1107 | */ | |
1108 | if (HAS_PCH_IBX(dev) && crtc->pipe == PIPE_B) { | |
1109 | temp &= ~SDVO_PIPE_B_SELECT; | |
1110 | temp |= SDVO_ENABLE; | |
1111 | /* | |
1112 | * HW workaround, need to write this twice for issue | |
1113 | * that may result in first write getting masked. | |
1114 | */ | |
1115 | I915_WRITE(intel_hdmi->hdmi_reg, temp); | |
1116 | POSTING_READ(intel_hdmi->hdmi_reg); | |
1117 | I915_WRITE(intel_hdmi->hdmi_reg, temp); | |
1118 | POSTING_READ(intel_hdmi->hdmi_reg); | |
1119 | ||
1120 | temp &= ~SDVO_ENABLE; | |
1121 | I915_WRITE(intel_hdmi->hdmi_reg, temp); | |
1122 | POSTING_READ(intel_hdmi->hdmi_reg); | |
1123 | } | |
6d67415f | 1124 | |
0be6f0c8 | 1125 | intel_hdmi->set_infoframes(&encoder->base, false, NULL); |
7d57382e EA |
1126 | } |
1127 | ||
a4790cec VS |
1128 | static void g4x_disable_hdmi(struct intel_encoder *encoder) |
1129 | { | |
1130 | struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); | |
1131 | ||
1132 | if (crtc->config->has_audio) | |
1133 | intel_audio_codec_disable(encoder); | |
1134 | ||
1135 | intel_disable_hdmi(encoder); | |
1136 | } | |
1137 | ||
1138 | static void pch_disable_hdmi(struct intel_encoder *encoder) | |
1139 | { | |
1140 | struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); | |
1141 | ||
1142 | if (crtc->config->has_audio) | |
1143 | intel_audio_codec_disable(encoder); | |
1144 | } | |
1145 | ||
1146 | static void pch_post_disable_hdmi(struct intel_encoder *encoder) | |
1147 | { | |
1148 | intel_disable_hdmi(encoder); | |
1149 | } | |
1150 | ||
e64e739e | 1151 | static int hdmi_port_clock_limit(struct intel_hdmi *hdmi, bool respect_dvi_limit) |
7d148ef5 DV |
1152 | { |
1153 | struct drm_device *dev = intel_hdmi_to_dev(hdmi); | |
1154 | ||
40478455 | 1155 | if ((respect_dvi_limit && !hdmi->has_hdmi_sink) || IS_G4X(dev)) |
7d148ef5 | 1156 | return 165000; |
e3c33578 | 1157 | else if (IS_HASWELL(dev) || INTEL_INFO(dev)->gen >= 8) |
7d148ef5 DV |
1158 | return 300000; |
1159 | else | |
1160 | return 225000; | |
1161 | } | |
1162 | ||
e64e739e VS |
1163 | static enum drm_mode_status |
1164 | hdmi_port_clock_valid(struct intel_hdmi *hdmi, | |
1165 | int clock, bool respect_dvi_limit) | |
1166 | { | |
1167 | struct drm_device *dev = intel_hdmi_to_dev(hdmi); | |
1168 | ||
1169 | if (clock < 25000) | |
1170 | return MODE_CLOCK_LOW; | |
1171 | if (clock > hdmi_port_clock_limit(hdmi, respect_dvi_limit)) | |
1172 | return MODE_CLOCK_HIGH; | |
1173 | ||
5e6ccc0b VS |
1174 | /* BXT DPLL can't generate 223-240 MHz */ |
1175 | if (IS_BROXTON(dev) && clock > 223333 && clock < 240000) | |
1176 | return MODE_CLOCK_RANGE; | |
1177 | ||
1178 | /* CHV DPLL can't generate 216-240 MHz */ | |
1179 | if (IS_CHERRYVIEW(dev) && clock > 216000 && clock < 240000) | |
e64e739e VS |
1180 | return MODE_CLOCK_RANGE; |
1181 | ||
1182 | return MODE_OK; | |
1183 | } | |
1184 | ||
c19de8eb DL |
1185 | static enum drm_mode_status |
1186 | intel_hdmi_mode_valid(struct drm_connector *connector, | |
1187 | struct drm_display_mode *mode) | |
7d57382e | 1188 | { |
e64e739e VS |
1189 | struct intel_hdmi *hdmi = intel_attached_hdmi(connector); |
1190 | struct drm_device *dev = intel_hdmi_to_dev(hdmi); | |
1191 | enum drm_mode_status status; | |
1192 | int clock; | |
1193 | ||
1194 | if (mode->flags & DRM_MODE_FLAG_DBLSCAN) | |
1195 | return MODE_NO_DBLESCAN; | |
697c4078 | 1196 | |
e64e739e | 1197 | clock = mode->clock; |
697c4078 CT |
1198 | if (mode->flags & DRM_MODE_FLAG_DBLCLK) |
1199 | clock *= 2; | |
1200 | ||
e64e739e VS |
1201 | /* check if we can do 8bpc */ |
1202 | status = hdmi_port_clock_valid(hdmi, clock, true); | |
7d57382e | 1203 | |
e64e739e VS |
1204 | /* if we can't do 8bpc we may still be able to do 12bpc */ |
1205 | if (!HAS_GMCH_DISPLAY(dev) && status != MODE_OK) | |
1206 | status = hdmi_port_clock_valid(hdmi, clock * 3 / 2, true); | |
7d57382e | 1207 | |
e64e739e | 1208 | return status; |
7d57382e EA |
1209 | } |
1210 | ||
77f06c86 | 1211 | static bool hdmi_12bpc_possible(struct intel_crtc_state *crtc_state) |
71800632 | 1212 | { |
77f06c86 ACO |
1213 | struct drm_device *dev = crtc_state->base.crtc->dev; |
1214 | struct drm_atomic_state *state; | |
71800632 | 1215 | struct intel_encoder *encoder; |
da3ced29 | 1216 | struct drm_connector *connector; |
77f06c86 | 1217 | struct drm_connector_state *connector_state; |
71800632 | 1218 | int count = 0, count_hdmi = 0; |
77f06c86 | 1219 | int i; |
71800632 | 1220 | |
f227ae9e | 1221 | if (HAS_GMCH_DISPLAY(dev)) |
71800632 VS |
1222 | return false; |
1223 | ||
77f06c86 ACO |
1224 | state = crtc_state->base.state; |
1225 | ||
da3ced29 | 1226 | for_each_connector_in_state(state, connector, connector_state, i) { |
77f06c86 ACO |
1227 | if (connector_state->crtc != crtc_state->base.crtc) |
1228 | continue; | |
1229 | ||
1230 | encoder = to_intel_encoder(connector_state->best_encoder); | |
1231 | ||
71800632 VS |
1232 | count_hdmi += encoder->type == INTEL_OUTPUT_HDMI; |
1233 | count++; | |
1234 | } | |
1235 | ||
1236 | /* | |
1237 | * HDMI 12bpc affects the clocks, so it's only possible | |
1238 | * when not cloning with other encoder types. | |
1239 | */ | |
1240 | return count_hdmi > 0 && count_hdmi == count; | |
1241 | } | |
1242 | ||
5bfe2ac0 | 1243 | bool intel_hdmi_compute_config(struct intel_encoder *encoder, |
5cec258b | 1244 | struct intel_crtc_state *pipe_config) |
7d57382e | 1245 | { |
5bfe2ac0 DV |
1246 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); |
1247 | struct drm_device *dev = encoder->base.dev; | |
2d112de7 | 1248 | struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; |
e64e739e VS |
1249 | int clock_8bpc = pipe_config->base.adjusted_mode.crtc_clock; |
1250 | int clock_12bpc = clock_8bpc * 3 / 2; | |
e29c22c0 | 1251 | int desired_bpp; |
3685a8f3 | 1252 | |
6897b4b5 DV |
1253 | pipe_config->has_hdmi_sink = intel_hdmi->has_hdmi_sink; |
1254 | ||
e43823ec JB |
1255 | if (pipe_config->has_hdmi_sink) |
1256 | pipe_config->has_infoframe = true; | |
1257 | ||
55bc60db VS |
1258 | if (intel_hdmi->color_range_auto) { |
1259 | /* See CEA-861-E - 5.1 Default Encoding Parameters */ | |
0f2a2a75 VS |
1260 | pipe_config->limited_color_range = |
1261 | pipe_config->has_hdmi_sink && | |
1262 | drm_match_cea_mode(adjusted_mode) > 1; | |
1263 | } else { | |
1264 | pipe_config->limited_color_range = | |
1265 | intel_hdmi->limited_color_range; | |
55bc60db VS |
1266 | } |
1267 | ||
697c4078 CT |
1268 | if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK) { |
1269 | pipe_config->pixel_multiplier = 2; | |
e64e739e | 1270 | clock_8bpc *= 2; |
3320e37f | 1271 | clock_12bpc *= 2; |
697c4078 CT |
1272 | } |
1273 | ||
5bfe2ac0 DV |
1274 | if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev)) |
1275 | pipe_config->has_pch_encoder = true; | |
1276 | ||
9ed109a7 DV |
1277 | if (pipe_config->has_hdmi_sink && intel_hdmi->has_audio) |
1278 | pipe_config->has_audio = true; | |
1279 | ||
4e53c2e0 DV |
1280 | /* |
1281 | * HDMI is either 12 or 8, so if the display lets 10bpc sneak | |
1282 | * through, clamp it down. Note that g4x/vlv don't support 12bpc hdmi | |
325b9d04 DV |
1283 | * outputs. We also need to check that the higher clock still fits |
1284 | * within limits. | |
4e53c2e0 | 1285 | */ |
6897b4b5 | 1286 | if (pipe_config->pipe_bpp > 8*3 && pipe_config->has_hdmi_sink && |
e64e739e | 1287 | hdmi_port_clock_valid(intel_hdmi, clock_12bpc, false) == MODE_OK && |
7a0baa62 | 1288 | hdmi_12bpc_possible(pipe_config)) { |
e29c22c0 DV |
1289 | DRM_DEBUG_KMS("picking bpc to 12 for HDMI output\n"); |
1290 | desired_bpp = 12*3; | |
325b9d04 DV |
1291 | |
1292 | /* Need to adjust the port link by 1.5x for 12bpc. */ | |
ff9a6750 | 1293 | pipe_config->port_clock = clock_12bpc; |
4e53c2e0 | 1294 | } else { |
e29c22c0 DV |
1295 | DRM_DEBUG_KMS("picking bpc to 8 for HDMI output\n"); |
1296 | desired_bpp = 8*3; | |
e64e739e VS |
1297 | |
1298 | pipe_config->port_clock = clock_8bpc; | |
e29c22c0 DV |
1299 | } |
1300 | ||
1301 | if (!pipe_config->bw_constrained) { | |
1302 | DRM_DEBUG_KMS("forcing pipe bpc to %i for HDMI\n", desired_bpp); | |
1303 | pipe_config->pipe_bpp = desired_bpp; | |
4e53c2e0 DV |
1304 | } |
1305 | ||
e64e739e VS |
1306 | if (hdmi_port_clock_valid(intel_hdmi, pipe_config->port_clock, |
1307 | false) != MODE_OK) { | |
1308 | DRM_DEBUG_KMS("unsupported HDMI clock, rejecting mode\n"); | |
325b9d04 DV |
1309 | return false; |
1310 | } | |
1311 | ||
28b468a0 VS |
1312 | /* Set user selected PAR to incoming mode's member */ |
1313 | adjusted_mode->picture_aspect_ratio = intel_hdmi->aspect_ratio; | |
1314 | ||
7d57382e EA |
1315 | return true; |
1316 | } | |
1317 | ||
953ece69 CW |
1318 | static void |
1319 | intel_hdmi_unset_edid(struct drm_connector *connector) | |
9dff6af8 | 1320 | { |
df0e9248 | 1321 | struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); |
9dff6af8 | 1322 | |
953ece69 CW |
1323 | intel_hdmi->has_hdmi_sink = false; |
1324 | intel_hdmi->has_audio = false; | |
1325 | intel_hdmi->rgb_quant_range_selectable = false; | |
1326 | ||
1327 | kfree(to_intel_connector(connector)->detect_edid); | |
1328 | to_intel_connector(connector)->detect_edid = NULL; | |
1329 | } | |
1330 | ||
1331 | static bool | |
237ed86c | 1332 | intel_hdmi_set_edid(struct drm_connector *connector, bool force) |
953ece69 CW |
1333 | { |
1334 | struct drm_i915_private *dev_priv = to_i915(connector->dev); | |
1335 | struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); | |
1336 | struct intel_encoder *intel_encoder = | |
1337 | &hdmi_to_dig_port(intel_hdmi)->base; | |
1338 | enum intel_display_power_domain power_domain; | |
237ed86c | 1339 | struct edid *edid = NULL; |
953ece69 | 1340 | bool connected = false; |
164c8598 | 1341 | |
671dedd2 ID |
1342 | power_domain = intel_display_port_power_domain(intel_encoder); |
1343 | intel_display_power_get(dev_priv, power_domain); | |
1344 | ||
237ed86c SJ |
1345 | if (force) |
1346 | edid = drm_get_edid(connector, | |
1347 | intel_gmbus_get_adapter(dev_priv, | |
1348 | intel_hdmi->ddc_bus)); | |
2ded9e27 | 1349 | |
953ece69 | 1350 | intel_display_power_put(dev_priv, power_domain); |
30ad48b7 | 1351 | |
953ece69 CW |
1352 | to_intel_connector(connector)->detect_edid = edid; |
1353 | if (edid && edid->input & DRM_EDID_INPUT_DIGITAL) { | |
1354 | intel_hdmi->rgb_quant_range_selectable = | |
1355 | drm_rgb_quant_range_selectable(edid); | |
1356 | ||
1357 | intel_hdmi->has_audio = drm_detect_monitor_audio(edid); | |
b1d7e4b4 WF |
1358 | if (intel_hdmi->force_audio != HDMI_AUDIO_AUTO) |
1359 | intel_hdmi->has_audio = | |
953ece69 CW |
1360 | intel_hdmi->force_audio == HDMI_AUDIO_ON; |
1361 | ||
1362 | if (intel_hdmi->force_audio != HDMI_AUDIO_OFF_DVI) | |
1363 | intel_hdmi->has_hdmi_sink = | |
1364 | drm_detect_hdmi_monitor(edid); | |
1365 | ||
1366 | connected = true; | |
55b7d6e8 CW |
1367 | } |
1368 | ||
953ece69 CW |
1369 | return connected; |
1370 | } | |
1371 | ||
1372 | static enum drm_connector_status | |
1373 | intel_hdmi_detect(struct drm_connector *connector, bool force) | |
1374 | { | |
1375 | enum drm_connector_status status; | |
237ed86c SJ |
1376 | struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); |
1377 | struct drm_i915_private *dev_priv = to_i915(connector->dev); | |
1378 | bool live_status = false; | |
1379 | unsigned int retry = 3; | |
953ece69 CW |
1380 | |
1381 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", | |
1382 | connector->base.id, connector->name); | |
1383 | ||
237ed86c SJ |
1384 | while (!live_status && --retry) { |
1385 | live_status = intel_digital_port_connected(dev_priv, | |
1386 | hdmi_to_dig_port(intel_hdmi)); | |
1387 | mdelay(10); | |
1388 | } | |
1389 | ||
1390 | if (!live_status) | |
1391 | DRM_DEBUG_KMS("Live status not up!"); | |
1392 | ||
953ece69 CW |
1393 | intel_hdmi_unset_edid(connector); |
1394 | ||
237ed86c | 1395 | if (intel_hdmi_set_edid(connector, live_status)) { |
953ece69 CW |
1396 | struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); |
1397 | ||
1398 | hdmi_to_dig_port(intel_hdmi)->base.type = INTEL_OUTPUT_HDMI; | |
1399 | status = connector_status_connected; | |
1400 | } else | |
1401 | status = connector_status_disconnected; | |
671dedd2 | 1402 | |
2ded9e27 | 1403 | return status; |
7d57382e EA |
1404 | } |
1405 | ||
953ece69 CW |
1406 | static void |
1407 | intel_hdmi_force(struct drm_connector *connector) | |
7d57382e | 1408 | { |
953ece69 | 1409 | struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); |
7d57382e | 1410 | |
953ece69 CW |
1411 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", |
1412 | connector->base.id, connector->name); | |
7d57382e | 1413 | |
953ece69 | 1414 | intel_hdmi_unset_edid(connector); |
671dedd2 | 1415 | |
953ece69 CW |
1416 | if (connector->status != connector_status_connected) |
1417 | return; | |
671dedd2 | 1418 | |
237ed86c | 1419 | intel_hdmi_set_edid(connector, true); |
953ece69 CW |
1420 | hdmi_to_dig_port(intel_hdmi)->base.type = INTEL_OUTPUT_HDMI; |
1421 | } | |
671dedd2 | 1422 | |
953ece69 CW |
1423 | static int intel_hdmi_get_modes(struct drm_connector *connector) |
1424 | { | |
1425 | struct edid *edid; | |
1426 | ||
1427 | edid = to_intel_connector(connector)->detect_edid; | |
1428 | if (edid == NULL) | |
1429 | return 0; | |
671dedd2 | 1430 | |
953ece69 | 1431 | return intel_connector_update_modes(connector, edid); |
7d57382e EA |
1432 | } |
1433 | ||
1aad7ac0 CW |
1434 | static bool |
1435 | intel_hdmi_detect_audio(struct drm_connector *connector) | |
1436 | { | |
1aad7ac0 | 1437 | bool has_audio = false; |
953ece69 | 1438 | struct edid *edid; |
1aad7ac0 | 1439 | |
953ece69 CW |
1440 | edid = to_intel_connector(connector)->detect_edid; |
1441 | if (edid && edid->input & DRM_EDID_INPUT_DIGITAL) | |
1442 | has_audio = drm_detect_monitor_audio(edid); | |
671dedd2 | 1443 | |
1aad7ac0 CW |
1444 | return has_audio; |
1445 | } | |
1446 | ||
55b7d6e8 CW |
1447 | static int |
1448 | intel_hdmi_set_property(struct drm_connector *connector, | |
ed517fbb PZ |
1449 | struct drm_property *property, |
1450 | uint64_t val) | |
55b7d6e8 CW |
1451 | { |
1452 | struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); | |
da63a9f2 PZ |
1453 | struct intel_digital_port *intel_dig_port = |
1454 | hdmi_to_dig_port(intel_hdmi); | |
e953fd7b | 1455 | struct drm_i915_private *dev_priv = connector->dev->dev_private; |
55b7d6e8 CW |
1456 | int ret; |
1457 | ||
662595df | 1458 | ret = drm_object_property_set_value(&connector->base, property, val); |
55b7d6e8 CW |
1459 | if (ret) |
1460 | return ret; | |
1461 | ||
3f43c48d | 1462 | if (property == dev_priv->force_audio_property) { |
b1d7e4b4 | 1463 | enum hdmi_force_audio i = val; |
1aad7ac0 CW |
1464 | bool has_audio; |
1465 | ||
1466 | if (i == intel_hdmi->force_audio) | |
55b7d6e8 CW |
1467 | return 0; |
1468 | ||
1aad7ac0 | 1469 | intel_hdmi->force_audio = i; |
55b7d6e8 | 1470 | |
b1d7e4b4 | 1471 | if (i == HDMI_AUDIO_AUTO) |
1aad7ac0 CW |
1472 | has_audio = intel_hdmi_detect_audio(connector); |
1473 | else | |
b1d7e4b4 | 1474 | has_audio = (i == HDMI_AUDIO_ON); |
1aad7ac0 | 1475 | |
b1d7e4b4 WF |
1476 | if (i == HDMI_AUDIO_OFF_DVI) |
1477 | intel_hdmi->has_hdmi_sink = 0; | |
55b7d6e8 | 1478 | |
1aad7ac0 | 1479 | intel_hdmi->has_audio = has_audio; |
55b7d6e8 CW |
1480 | goto done; |
1481 | } | |
1482 | ||
e953fd7b | 1483 | if (property == dev_priv->broadcast_rgb_property) { |
ae4edb80 | 1484 | bool old_auto = intel_hdmi->color_range_auto; |
0f2a2a75 | 1485 | bool old_range = intel_hdmi->limited_color_range; |
ae4edb80 | 1486 | |
55bc60db VS |
1487 | switch (val) { |
1488 | case INTEL_BROADCAST_RGB_AUTO: | |
1489 | intel_hdmi->color_range_auto = true; | |
1490 | break; | |
1491 | case INTEL_BROADCAST_RGB_FULL: | |
1492 | intel_hdmi->color_range_auto = false; | |
0f2a2a75 | 1493 | intel_hdmi->limited_color_range = false; |
55bc60db VS |
1494 | break; |
1495 | case INTEL_BROADCAST_RGB_LIMITED: | |
1496 | intel_hdmi->color_range_auto = false; | |
0f2a2a75 | 1497 | intel_hdmi->limited_color_range = true; |
55bc60db VS |
1498 | break; |
1499 | default: | |
1500 | return -EINVAL; | |
1501 | } | |
ae4edb80 DV |
1502 | |
1503 | if (old_auto == intel_hdmi->color_range_auto && | |
0f2a2a75 | 1504 | old_range == intel_hdmi->limited_color_range) |
ae4edb80 DV |
1505 | return 0; |
1506 | ||
e953fd7b CW |
1507 | goto done; |
1508 | } | |
1509 | ||
94a11ddc VK |
1510 | if (property == connector->dev->mode_config.aspect_ratio_property) { |
1511 | switch (val) { | |
1512 | case DRM_MODE_PICTURE_ASPECT_NONE: | |
1513 | intel_hdmi->aspect_ratio = HDMI_PICTURE_ASPECT_NONE; | |
1514 | break; | |
1515 | case DRM_MODE_PICTURE_ASPECT_4_3: | |
1516 | intel_hdmi->aspect_ratio = HDMI_PICTURE_ASPECT_4_3; | |
1517 | break; | |
1518 | case DRM_MODE_PICTURE_ASPECT_16_9: | |
1519 | intel_hdmi->aspect_ratio = HDMI_PICTURE_ASPECT_16_9; | |
1520 | break; | |
1521 | default: | |
1522 | return -EINVAL; | |
1523 | } | |
1524 | goto done; | |
1525 | } | |
1526 | ||
55b7d6e8 CW |
1527 | return -EINVAL; |
1528 | ||
1529 | done: | |
c0c36b94 CW |
1530 | if (intel_dig_port->base.base.crtc) |
1531 | intel_crtc_restore_mode(intel_dig_port->base.base.crtc); | |
55b7d6e8 CW |
1532 | |
1533 | return 0; | |
1534 | } | |
1535 | ||
13732ba7 JB |
1536 | static void intel_hdmi_pre_enable(struct intel_encoder *encoder) |
1537 | { | |
1538 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); | |
1539 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); | |
124abe07 | 1540 | struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode; |
13732ba7 | 1541 | |
4cde8a21 DV |
1542 | intel_hdmi_prepare(encoder); |
1543 | ||
6897b4b5 | 1544 | intel_hdmi->set_infoframes(&encoder->base, |
6e3c9717 | 1545 | intel_crtc->config->has_hdmi_sink, |
6897b4b5 | 1546 | adjusted_mode); |
13732ba7 JB |
1547 | } |
1548 | ||
9514ac6e | 1549 | static void vlv_hdmi_pre_enable(struct intel_encoder *encoder) |
89b667f8 JB |
1550 | { |
1551 | struct intel_digital_port *dport = enc_to_dig_port(&encoder->base); | |
13732ba7 | 1552 | struct intel_hdmi *intel_hdmi = &dport->hdmi; |
89b667f8 JB |
1553 | struct drm_device *dev = encoder->base.dev; |
1554 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1555 | struct intel_crtc *intel_crtc = | |
1556 | to_intel_crtc(encoder->base.crtc); | |
124abe07 | 1557 | struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode; |
e4607fcf | 1558 | enum dpio_channel port = vlv_dport_to_channel(dport); |
89b667f8 JB |
1559 | int pipe = intel_crtc->pipe; |
1560 | u32 val; | |
1561 | ||
89b667f8 | 1562 | /* Enable clock channels for this port */ |
a580516d | 1563 | mutex_lock(&dev_priv->sb_lock); |
ab3c759a | 1564 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port)); |
89b667f8 JB |
1565 | val = 0; |
1566 | if (pipe) | |
1567 | val |= (1<<21); | |
1568 | else | |
1569 | val &= ~(1<<21); | |
1570 | val |= 0x001000c4; | |
ab3c759a | 1571 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val); |
89b667f8 JB |
1572 | |
1573 | /* HDMI 1.0V-2dB */ | |
ab3c759a CML |
1574 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0); |
1575 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), 0x2b245f5f); | |
1576 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port), 0x5578b83a); | |
1577 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0c782040); | |
1578 | vlv_dpio_write(dev_priv, pipe, VLV_TX3_DW4(port), 0x2b247878); | |
1579 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000); | |
1580 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), 0x00002000); | |
1581 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), DPIO_TX_OCALINIT_EN); | |
89b667f8 JB |
1582 | |
1583 | /* Program lane clock */ | |
ab3c759a CML |
1584 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018); |
1585 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888); | |
a580516d | 1586 | mutex_unlock(&dev_priv->sb_lock); |
b76cf76b | 1587 | |
6897b4b5 | 1588 | intel_hdmi->set_infoframes(&encoder->base, |
6e3c9717 | 1589 | intel_crtc->config->has_hdmi_sink, |
6897b4b5 | 1590 | adjusted_mode); |
13732ba7 | 1591 | |
bf868c7d | 1592 | g4x_enable_hdmi(encoder); |
b76cf76b | 1593 | |
9b6de0a1 | 1594 | vlv_wait_port_ready(dev_priv, dport, 0x0); |
89b667f8 JB |
1595 | } |
1596 | ||
9514ac6e | 1597 | static void vlv_hdmi_pre_pll_enable(struct intel_encoder *encoder) |
89b667f8 JB |
1598 | { |
1599 | struct intel_digital_port *dport = enc_to_dig_port(&encoder->base); | |
1600 | struct drm_device *dev = encoder->base.dev; | |
1601 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5e69f97f CML |
1602 | struct intel_crtc *intel_crtc = |
1603 | to_intel_crtc(encoder->base.crtc); | |
e4607fcf | 1604 | enum dpio_channel port = vlv_dport_to_channel(dport); |
5e69f97f | 1605 | int pipe = intel_crtc->pipe; |
89b667f8 | 1606 | |
4cde8a21 DV |
1607 | intel_hdmi_prepare(encoder); |
1608 | ||
89b667f8 | 1609 | /* Program Tx lane resets to default */ |
a580516d | 1610 | mutex_lock(&dev_priv->sb_lock); |
ab3c759a | 1611 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port), |
89b667f8 JB |
1612 | DPIO_PCS_TX_LANE2_RESET | |
1613 | DPIO_PCS_TX_LANE1_RESET); | |
ab3c759a | 1614 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port), |
89b667f8 JB |
1615 | DPIO_PCS_CLK_CRI_RXEB_EIOS_EN | |
1616 | DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN | | |
1617 | (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) | | |
1618 | DPIO_PCS_CLK_SOFT_RESET); | |
1619 | ||
1620 | /* Fix up inter-pair skew failure */ | |
ab3c759a CML |
1621 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW12(port), 0x00750f00); |
1622 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW11(port), 0x00001500); | |
1623 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000); | |
1624 | ||
1625 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), 0x00002000); | |
1626 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), DPIO_TX_OCALINIT_EN); | |
a580516d | 1627 | mutex_unlock(&dev_priv->sb_lock); |
89b667f8 JB |
1628 | } |
1629 | ||
a8f327fb VS |
1630 | static void chv_data_lane_soft_reset(struct intel_encoder *encoder, |
1631 | bool reset) | |
1632 | { | |
1633 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); | |
1634 | enum dpio_channel ch = vlv_dport_to_channel(enc_to_dig_port(&encoder->base)); | |
1635 | struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); | |
1636 | enum pipe pipe = crtc->pipe; | |
1637 | uint32_t val; | |
1638 | ||
1639 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch)); | |
1640 | if (reset) | |
1641 | val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET); | |
1642 | else | |
1643 | val |= DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET; | |
1644 | vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val); | |
1645 | ||
1646 | if (crtc->config->lane_count > 2) { | |
1647 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch)); | |
1648 | if (reset) | |
1649 | val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET); | |
1650 | else | |
1651 | val |= DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET; | |
1652 | vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val); | |
1653 | } | |
1654 | ||
1655 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch)); | |
1656 | val |= CHV_PCS_REQ_SOFTRESET_EN; | |
1657 | if (reset) | |
1658 | val &= ~DPIO_PCS_CLK_SOFT_RESET; | |
1659 | else | |
1660 | val |= DPIO_PCS_CLK_SOFT_RESET; | |
1661 | vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val); | |
1662 | ||
1663 | if (crtc->config->lane_count > 2) { | |
1664 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch)); | |
1665 | val |= CHV_PCS_REQ_SOFTRESET_EN; | |
1666 | if (reset) | |
1667 | val &= ~DPIO_PCS_CLK_SOFT_RESET; | |
1668 | else | |
1669 | val |= DPIO_PCS_CLK_SOFT_RESET; | |
1670 | vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val); | |
1671 | } | |
1672 | } | |
1673 | ||
9197c88b VS |
1674 | static void chv_hdmi_pre_pll_enable(struct intel_encoder *encoder) |
1675 | { | |
1676 | struct intel_digital_port *dport = enc_to_dig_port(&encoder->base); | |
1677 | struct drm_device *dev = encoder->base.dev; | |
1678 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1679 | struct intel_crtc *intel_crtc = | |
1680 | to_intel_crtc(encoder->base.crtc); | |
1681 | enum dpio_channel ch = vlv_dport_to_channel(dport); | |
1682 | enum pipe pipe = intel_crtc->pipe; | |
1683 | u32 val; | |
1684 | ||
625695f8 VS |
1685 | intel_hdmi_prepare(encoder); |
1686 | ||
b0b33846 VS |
1687 | /* |
1688 | * Must trick the second common lane into life. | |
1689 | * Otherwise we can't even access the PLL. | |
1690 | */ | |
1691 | if (ch == DPIO_CH0 && pipe == PIPE_B) | |
1692 | dport->release_cl2_override = | |
1693 | !chv_phy_powergate_ch(dev_priv, DPIO_PHY0, DPIO_CH1, true); | |
1694 | ||
e0fce78f VS |
1695 | chv_phy_powergate_lanes(encoder, true, 0x0); |
1696 | ||
a580516d | 1697 | mutex_lock(&dev_priv->sb_lock); |
9197c88b | 1698 | |
a8f327fb VS |
1699 | /* Assert data lane reset */ |
1700 | chv_data_lane_soft_reset(encoder, true); | |
1701 | ||
b9e5ac3c VS |
1702 | /* program left/right clock distribution */ |
1703 | if (pipe != PIPE_B) { | |
1704 | val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0); | |
1705 | val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK); | |
1706 | if (ch == DPIO_CH0) | |
1707 | val |= CHV_BUFLEFTENA1_FORCE; | |
1708 | if (ch == DPIO_CH1) | |
1709 | val |= CHV_BUFRIGHTENA1_FORCE; | |
1710 | vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val); | |
1711 | } else { | |
1712 | val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1); | |
1713 | val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK); | |
1714 | if (ch == DPIO_CH0) | |
1715 | val |= CHV_BUFLEFTENA2_FORCE; | |
1716 | if (ch == DPIO_CH1) | |
1717 | val |= CHV_BUFRIGHTENA2_FORCE; | |
1718 | vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val); | |
1719 | } | |
1720 | ||
9197c88b VS |
1721 | /* program clock channel usage */ |
1722 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(ch)); | |
1723 | val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE; | |
1724 | if (pipe != PIPE_B) | |
1725 | val &= ~CHV_PCS_USEDCLKCHANNEL; | |
1726 | else | |
1727 | val |= CHV_PCS_USEDCLKCHANNEL; | |
1728 | vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW8(ch), val); | |
1729 | ||
1730 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW8(ch)); | |
1731 | val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE; | |
1732 | if (pipe != PIPE_B) | |
1733 | val &= ~CHV_PCS_USEDCLKCHANNEL; | |
1734 | else | |
1735 | val |= CHV_PCS_USEDCLKCHANNEL; | |
1736 | vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW8(ch), val); | |
1737 | ||
1738 | /* | |
1739 | * This a a bit weird since generally CL | |
1740 | * matches the pipe, but here we need to | |
1741 | * pick the CL based on the port. | |
1742 | */ | |
1743 | val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW19(ch)); | |
1744 | if (pipe != PIPE_B) | |
1745 | val &= ~CHV_CMN_USEDCLKCHANNEL; | |
1746 | else | |
1747 | val |= CHV_CMN_USEDCLKCHANNEL; | |
1748 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW19(ch), val); | |
1749 | ||
a580516d | 1750 | mutex_unlock(&dev_priv->sb_lock); |
9197c88b VS |
1751 | } |
1752 | ||
d6db995f VS |
1753 | static void chv_hdmi_post_pll_disable(struct intel_encoder *encoder) |
1754 | { | |
1755 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); | |
1756 | enum pipe pipe = to_intel_crtc(encoder->base.crtc)->pipe; | |
1757 | u32 val; | |
1758 | ||
1759 | mutex_lock(&dev_priv->sb_lock); | |
1760 | ||
1761 | /* disable left/right clock distribution */ | |
1762 | if (pipe != PIPE_B) { | |
1763 | val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0); | |
1764 | val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK); | |
1765 | vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val); | |
1766 | } else { | |
1767 | val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1); | |
1768 | val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK); | |
1769 | vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val); | |
1770 | } | |
1771 | ||
1772 | mutex_unlock(&dev_priv->sb_lock); | |
e0fce78f | 1773 | |
b0b33846 VS |
1774 | /* |
1775 | * Leave the power down bit cleared for at least one | |
1776 | * lane so that chv_powergate_phy_ch() will power | |
1777 | * on something when the channel is otherwise unused. | |
1778 | * When the port is off and the override is removed | |
1779 | * the lanes power down anyway, so otherwise it doesn't | |
1780 | * really matter what the state of power down bits is | |
1781 | * after this. | |
1782 | */ | |
e0fce78f | 1783 | chv_phy_powergate_lanes(encoder, false, 0x0); |
d6db995f VS |
1784 | } |
1785 | ||
9514ac6e | 1786 | static void vlv_hdmi_post_disable(struct intel_encoder *encoder) |
89b667f8 JB |
1787 | { |
1788 | struct intel_digital_port *dport = enc_to_dig_port(&encoder->base); | |
1789 | struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; | |
5e69f97f CML |
1790 | struct intel_crtc *intel_crtc = |
1791 | to_intel_crtc(encoder->base.crtc); | |
e4607fcf | 1792 | enum dpio_channel port = vlv_dport_to_channel(dport); |
5e69f97f | 1793 | int pipe = intel_crtc->pipe; |
89b667f8 JB |
1794 | |
1795 | /* Reset lanes to avoid HDMI flicker (VLV w/a) */ | |
a580516d | 1796 | mutex_lock(&dev_priv->sb_lock); |
ab3c759a CML |
1797 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port), 0x00000000); |
1798 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port), 0x00e00060); | |
a580516d | 1799 | mutex_unlock(&dev_priv->sb_lock); |
89b667f8 JB |
1800 | } |
1801 | ||
580d3811 VS |
1802 | static void chv_hdmi_post_disable(struct intel_encoder *encoder) |
1803 | { | |
580d3811 VS |
1804 | struct drm_device *dev = encoder->base.dev; |
1805 | struct drm_i915_private *dev_priv = dev->dev_private; | |
580d3811 | 1806 | |
a580516d | 1807 | mutex_lock(&dev_priv->sb_lock); |
580d3811 | 1808 | |
a8f327fb VS |
1809 | /* Assert data lane reset */ |
1810 | chv_data_lane_soft_reset(encoder, true); | |
580d3811 | 1811 | |
a580516d | 1812 | mutex_unlock(&dev_priv->sb_lock); |
580d3811 VS |
1813 | } |
1814 | ||
e4a1d846 CML |
1815 | static void chv_hdmi_pre_enable(struct intel_encoder *encoder) |
1816 | { | |
1817 | struct intel_digital_port *dport = enc_to_dig_port(&encoder->base); | |
b4eb1564 | 1818 | struct intel_hdmi *intel_hdmi = &dport->hdmi; |
e4a1d846 CML |
1819 | struct drm_device *dev = encoder->base.dev; |
1820 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1821 | struct intel_crtc *intel_crtc = | |
1822 | to_intel_crtc(encoder->base.crtc); | |
124abe07 | 1823 | struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode; |
e4a1d846 CML |
1824 | enum dpio_channel ch = vlv_dport_to_channel(dport); |
1825 | int pipe = intel_crtc->pipe; | |
2e523e98 | 1826 | int data, i, stagger; |
e4a1d846 CML |
1827 | u32 val; |
1828 | ||
a580516d | 1829 | mutex_lock(&dev_priv->sb_lock); |
949c1d43 | 1830 | |
570e2a74 VS |
1831 | /* allow hardware to manage TX FIFO reset source */ |
1832 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch)); | |
1833 | val &= ~DPIO_LANEDESKEW_STRAP_OVRD; | |
1834 | vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val); | |
1835 | ||
1836 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch)); | |
1837 | val &= ~DPIO_LANEDESKEW_STRAP_OVRD; | |
1838 | vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val); | |
1839 | ||
949c1d43 | 1840 | /* Program Tx latency optimal setting */ |
e4a1d846 | 1841 | for (i = 0; i < 4; i++) { |
e4a1d846 CML |
1842 | /* Set the upar bit */ |
1843 | data = (i == 1) ? 0x0 : 0x1; | |
1844 | vlv_dpio_write(dev_priv, pipe, CHV_TX_DW14(ch, i), | |
1845 | data << DPIO_UPAR_SHIFT); | |
1846 | } | |
1847 | ||
1848 | /* Data lane stagger programming */ | |
2e523e98 VS |
1849 | if (intel_crtc->config->port_clock > 270000) |
1850 | stagger = 0x18; | |
1851 | else if (intel_crtc->config->port_clock > 135000) | |
1852 | stagger = 0xd; | |
1853 | else if (intel_crtc->config->port_clock > 67500) | |
1854 | stagger = 0x7; | |
1855 | else if (intel_crtc->config->port_clock > 33750) | |
1856 | stagger = 0x4; | |
1857 | else | |
1858 | stagger = 0x2; | |
1859 | ||
1860 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch)); | |
1861 | val |= DPIO_TX2_STAGGER_MASK(0x1f); | |
1862 | vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val); | |
1863 | ||
1864 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch)); | |
1865 | val |= DPIO_TX2_STAGGER_MASK(0x1f); | |
1866 | vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val); | |
1867 | ||
1868 | vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW12(ch), | |
1869 | DPIO_LANESTAGGER_STRAP(stagger) | | |
1870 | DPIO_LANESTAGGER_STRAP_OVRD | | |
1871 | DPIO_TX1_STAGGER_MASK(0x1f) | | |
1872 | DPIO_TX1_STAGGER_MULT(6) | | |
1873 | DPIO_TX2_STAGGER_MULT(0)); | |
1874 | ||
1875 | vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW12(ch), | |
1876 | DPIO_LANESTAGGER_STRAP(stagger) | | |
1877 | DPIO_LANESTAGGER_STRAP_OVRD | | |
1878 | DPIO_TX1_STAGGER_MASK(0x1f) | | |
1879 | DPIO_TX1_STAGGER_MULT(7) | | |
1880 | DPIO_TX2_STAGGER_MULT(5)); | |
e4a1d846 | 1881 | |
a8f327fb VS |
1882 | /* Deassert data lane reset */ |
1883 | chv_data_lane_soft_reset(encoder, false); | |
1884 | ||
e4a1d846 | 1885 | /* Clear calc init */ |
1966e59e VS |
1886 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch)); |
1887 | val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3); | |
a02ef3c7 VS |
1888 | val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK); |
1889 | val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5; | |
1966e59e VS |
1890 | vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val); |
1891 | ||
1892 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch)); | |
1893 | val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3); | |
a02ef3c7 VS |
1894 | val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK); |
1895 | val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5; | |
1966e59e | 1896 | vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val); |
e4a1d846 | 1897 | |
a02ef3c7 VS |
1898 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW9(ch)); |
1899 | val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK); | |
1900 | val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000; | |
1901 | vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW9(ch), val); | |
1902 | ||
1903 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW9(ch)); | |
1904 | val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK); | |
1905 | val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000; | |
1906 | vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW9(ch), val); | |
1907 | ||
e4a1d846 CML |
1908 | /* FIXME: Program the support xxx V-dB */ |
1909 | /* Use 800mV-0dB */ | |
f72df8db VS |
1910 | for (i = 0; i < 4; i++) { |
1911 | val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW4(ch, i)); | |
1912 | val &= ~DPIO_SWING_DEEMPH9P5_MASK; | |
1913 | val |= 128 << DPIO_SWING_DEEMPH9P5_SHIFT; | |
1914 | vlv_dpio_write(dev_priv, pipe, CHV_TX_DW4(ch, i), val); | |
1915 | } | |
e4a1d846 | 1916 | |
f72df8db VS |
1917 | for (i = 0; i < 4; i++) { |
1918 | val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i)); | |
67fa24b4 | 1919 | |
1fb44505 VS |
1920 | val &= ~DPIO_SWING_MARGIN000_MASK; |
1921 | val |= 102 << DPIO_SWING_MARGIN000_SHIFT; | |
67fa24b4 VS |
1922 | |
1923 | /* | |
1924 | * Supposedly this value shouldn't matter when unique transition | |
1925 | * scale is disabled, but in fact it does matter. Let's just | |
1926 | * always program the same value and hope it's OK. | |
1927 | */ | |
1928 | val &= ~(0xff << DPIO_UNIQ_TRANS_SCALE_SHIFT); | |
1929 | val |= 0x9a << DPIO_UNIQ_TRANS_SCALE_SHIFT; | |
1930 | ||
f72df8db VS |
1931 | vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val); |
1932 | } | |
e4a1d846 | 1933 | |
67fa24b4 VS |
1934 | /* |
1935 | * The document said it needs to set bit 27 for ch0 and bit 26 | |
1936 | * for ch1. Might be a typo in the doc. | |
1937 | * For now, for this unique transition scale selection, set bit | |
1938 | * 27 for ch0 and ch1. | |
1939 | */ | |
f72df8db VS |
1940 | for (i = 0; i < 4; i++) { |
1941 | val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i)); | |
1942 | val &= ~DPIO_TX_UNIQ_TRANS_SCALE_EN; | |
1943 | vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val); | |
1944 | } | |
e4a1d846 | 1945 | |
e4a1d846 | 1946 | /* Start swing calculation */ |
1966e59e VS |
1947 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch)); |
1948 | val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3; | |
1949 | vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val); | |
1950 | ||
1951 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch)); | |
1952 | val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3; | |
1953 | vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val); | |
e4a1d846 CML |
1954 | |
1955 | /* LRC Bypass */ | |
1956 | val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW30); | |
1957 | val |= DPIO_LRC_BYPASS; | |
1958 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW30, val); | |
1959 | ||
a580516d | 1960 | mutex_unlock(&dev_priv->sb_lock); |
e4a1d846 | 1961 | |
b4eb1564 | 1962 | intel_hdmi->set_infoframes(&encoder->base, |
6e3c9717 | 1963 | intel_crtc->config->has_hdmi_sink, |
b4eb1564 CT |
1964 | adjusted_mode); |
1965 | ||
bf868c7d | 1966 | g4x_enable_hdmi(encoder); |
e4a1d846 | 1967 | |
9b6de0a1 | 1968 | vlv_wait_port_ready(dev_priv, dport, 0x0); |
b0b33846 VS |
1969 | |
1970 | /* Second common lane will stay alive on its own now */ | |
1971 | if (dport->release_cl2_override) { | |
1972 | chv_phy_powergate_ch(dev_priv, DPIO_PHY0, DPIO_CH1, false); | |
1973 | dport->release_cl2_override = false; | |
1974 | } | |
e4a1d846 CML |
1975 | } |
1976 | ||
7d57382e EA |
1977 | static void intel_hdmi_destroy(struct drm_connector *connector) |
1978 | { | |
10e972d3 | 1979 | kfree(to_intel_connector(connector)->detect_edid); |
7d57382e | 1980 | drm_connector_cleanup(connector); |
674e2d08 | 1981 | kfree(connector); |
7d57382e EA |
1982 | } |
1983 | ||
7d57382e | 1984 | static const struct drm_connector_funcs intel_hdmi_connector_funcs = { |
4d688a2a | 1985 | .dpms = drm_atomic_helper_connector_dpms, |
7d57382e | 1986 | .detect = intel_hdmi_detect, |
953ece69 | 1987 | .force = intel_hdmi_force, |
7d57382e | 1988 | .fill_modes = drm_helper_probe_single_connector_modes, |
55b7d6e8 | 1989 | .set_property = intel_hdmi_set_property, |
2545e4a6 | 1990 | .atomic_get_property = intel_connector_atomic_get_property, |
7d57382e | 1991 | .destroy = intel_hdmi_destroy, |
c6f95f27 | 1992 | .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, |
98969725 | 1993 | .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, |
7d57382e EA |
1994 | }; |
1995 | ||
1996 | static const struct drm_connector_helper_funcs intel_hdmi_connector_helper_funcs = { | |
1997 | .get_modes = intel_hdmi_get_modes, | |
1998 | .mode_valid = intel_hdmi_mode_valid, | |
df0e9248 | 1999 | .best_encoder = intel_best_encoder, |
7d57382e EA |
2000 | }; |
2001 | ||
7d57382e | 2002 | static const struct drm_encoder_funcs intel_hdmi_enc_funcs = { |
ea5b213a | 2003 | .destroy = intel_encoder_destroy, |
7d57382e EA |
2004 | }; |
2005 | ||
94a11ddc VK |
2006 | static void |
2007 | intel_attach_aspect_ratio_property(struct drm_connector *connector) | |
2008 | { | |
2009 | if (!drm_mode_create_aspect_ratio_property(connector->dev)) | |
2010 | drm_object_attach_property(&connector->base, | |
2011 | connector->dev->mode_config.aspect_ratio_property, | |
2012 | DRM_MODE_PICTURE_ASPECT_NONE); | |
2013 | } | |
2014 | ||
55b7d6e8 CW |
2015 | static void |
2016 | intel_hdmi_add_properties(struct intel_hdmi *intel_hdmi, struct drm_connector *connector) | |
2017 | { | |
3f43c48d | 2018 | intel_attach_force_audio_property(connector); |
e953fd7b | 2019 | intel_attach_broadcast_rgb_property(connector); |
55bc60db | 2020 | intel_hdmi->color_range_auto = true; |
94a11ddc VK |
2021 | intel_attach_aspect_ratio_property(connector); |
2022 | intel_hdmi->aspect_ratio = HDMI_PICTURE_ASPECT_NONE; | |
55b7d6e8 CW |
2023 | } |
2024 | ||
00c09d70 PZ |
2025 | void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port, |
2026 | struct intel_connector *intel_connector) | |
7d57382e | 2027 | { |
b9cb234c PZ |
2028 | struct drm_connector *connector = &intel_connector->base; |
2029 | struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi; | |
2030 | struct intel_encoder *intel_encoder = &intel_dig_port->base; | |
2031 | struct drm_device *dev = intel_encoder->base.dev; | |
7d57382e | 2032 | struct drm_i915_private *dev_priv = dev->dev_private; |
174edf1f | 2033 | enum port port = intel_dig_port->port; |
11c1b657 | 2034 | uint8_t alternate_ddc_pin; |
373a3cf7 | 2035 | |
7d57382e | 2036 | drm_connector_init(dev, connector, &intel_hdmi_connector_funcs, |
8d91104a | 2037 | DRM_MODE_CONNECTOR_HDMIA); |
7d57382e EA |
2038 | drm_connector_helper_add(connector, &intel_hdmi_connector_helper_funcs); |
2039 | ||
c3febcc4 | 2040 | connector->interlace_allowed = 1; |
7d57382e | 2041 | connector->doublescan_allowed = 0; |
573e74ad | 2042 | connector->stereo_allowed = 1; |
66a9278e | 2043 | |
08d644ad DV |
2044 | switch (port) { |
2045 | case PORT_B: | |
4c272834 JN |
2046 | if (IS_BROXTON(dev_priv)) |
2047 | intel_hdmi->ddc_bus = GMBUS_PIN_1_BXT; | |
2048 | else | |
2049 | intel_hdmi->ddc_bus = GMBUS_PIN_DPB; | |
cf1d5883 SJ |
2050 | /* |
2051 | * On BXT A0/A1, sw needs to activate DDIA HPD logic and | |
2052 | * interrupts to check the external panel connection. | |
2053 | */ | |
2054 | if (IS_BROXTON(dev_priv) && (INTEL_REVID(dev) < BXT_REVID_B0)) | |
2055 | intel_encoder->hpd_pin = HPD_PORT_A; | |
2056 | else | |
2057 | intel_encoder->hpd_pin = HPD_PORT_B; | |
08d644ad DV |
2058 | break; |
2059 | case PORT_C: | |
4c272834 JN |
2060 | if (IS_BROXTON(dev_priv)) |
2061 | intel_hdmi->ddc_bus = GMBUS_PIN_2_BXT; | |
2062 | else | |
2063 | intel_hdmi->ddc_bus = GMBUS_PIN_DPC; | |
1d843f9d | 2064 | intel_encoder->hpd_pin = HPD_PORT_C; |
08d644ad DV |
2065 | break; |
2066 | case PORT_D: | |
4c272834 JN |
2067 | if (WARN_ON(IS_BROXTON(dev_priv))) |
2068 | intel_hdmi->ddc_bus = GMBUS_PIN_DISABLED; | |
2069 | else if (IS_CHERRYVIEW(dev_priv)) | |
988c7015 | 2070 | intel_hdmi->ddc_bus = GMBUS_PIN_DPD_CHV; |
c0c35329 | 2071 | else |
988c7015 | 2072 | intel_hdmi->ddc_bus = GMBUS_PIN_DPD; |
1d843f9d | 2073 | intel_encoder->hpd_pin = HPD_PORT_D; |
08d644ad | 2074 | break; |
11c1b657 XZ |
2075 | case PORT_E: |
2076 | /* On SKL PORT E doesn't have seperate GMBUS pin | |
2077 | * We rely on VBT to set a proper alternate GMBUS pin. */ | |
2078 | alternate_ddc_pin = | |
2079 | dev_priv->vbt.ddi_port_info[PORT_E].alternate_ddc_pin; | |
2080 | switch (alternate_ddc_pin) { | |
2081 | case DDC_PIN_B: | |
2082 | intel_hdmi->ddc_bus = GMBUS_PIN_DPB; | |
2083 | break; | |
2084 | case DDC_PIN_C: | |
2085 | intel_hdmi->ddc_bus = GMBUS_PIN_DPC; | |
2086 | break; | |
2087 | case DDC_PIN_D: | |
2088 | intel_hdmi->ddc_bus = GMBUS_PIN_DPD; | |
2089 | break; | |
2090 | default: | |
2091 | MISSING_CASE(alternate_ddc_pin); | |
2092 | } | |
2093 | intel_encoder->hpd_pin = HPD_PORT_E; | |
2094 | break; | |
08d644ad | 2095 | case PORT_A: |
1d843f9d | 2096 | intel_encoder->hpd_pin = HPD_PORT_A; |
08d644ad DV |
2097 | /* Internal port only for eDP. */ |
2098 | default: | |
6e4c1677 | 2099 | BUG(); |
f8aed700 | 2100 | } |
7d57382e | 2101 | |
7637bfdb | 2102 | if (IS_VALLEYVIEW(dev)) { |
90b107c8 | 2103 | intel_hdmi->write_infoframe = vlv_write_infoframe; |
687f4d06 | 2104 | intel_hdmi->set_infoframes = vlv_set_infoframes; |
e43823ec | 2105 | intel_hdmi->infoframe_enabled = vlv_infoframe_enabled; |
b98856a8 | 2106 | } else if (IS_G4X(dev)) { |
7637bfdb JB |
2107 | intel_hdmi->write_infoframe = g4x_write_infoframe; |
2108 | intel_hdmi->set_infoframes = g4x_set_infoframes; | |
e43823ec | 2109 | intel_hdmi->infoframe_enabled = g4x_infoframe_enabled; |
22b8bf17 | 2110 | } else if (HAS_DDI(dev)) { |
8c5f5f7c | 2111 | intel_hdmi->write_infoframe = hsw_write_infoframe; |
687f4d06 | 2112 | intel_hdmi->set_infoframes = hsw_set_infoframes; |
e43823ec | 2113 | intel_hdmi->infoframe_enabled = hsw_infoframe_enabled; |
fdf1250a PZ |
2114 | } else if (HAS_PCH_IBX(dev)) { |
2115 | intel_hdmi->write_infoframe = ibx_write_infoframe; | |
687f4d06 | 2116 | intel_hdmi->set_infoframes = ibx_set_infoframes; |
e43823ec | 2117 | intel_hdmi->infoframe_enabled = ibx_infoframe_enabled; |
fdf1250a PZ |
2118 | } else { |
2119 | intel_hdmi->write_infoframe = cpt_write_infoframe; | |
687f4d06 | 2120 | intel_hdmi->set_infoframes = cpt_set_infoframes; |
e43823ec | 2121 | intel_hdmi->infoframe_enabled = cpt_infoframe_enabled; |
64a8fc01 | 2122 | } |
45187ace | 2123 | |
affa9354 | 2124 | if (HAS_DDI(dev)) |
bcbc889b PZ |
2125 | intel_connector->get_hw_state = intel_ddi_connector_get_hw_state; |
2126 | else | |
2127 | intel_connector->get_hw_state = intel_connector_get_hw_state; | |
4932e2c3 | 2128 | intel_connector->unregister = intel_connector_unregister; |
b9cb234c PZ |
2129 | |
2130 | intel_hdmi_add_properties(intel_hdmi, connector); | |
2131 | ||
2132 | intel_connector_attach_encoder(intel_connector, intel_encoder); | |
34ea3d38 | 2133 | drm_connector_register(connector); |
d8b4c43a | 2134 | intel_hdmi->attached_connector = intel_connector; |
b9cb234c PZ |
2135 | |
2136 | /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written | |
2137 | * 0xd. Failure to do so will result in spurious interrupts being | |
2138 | * generated on the port when a cable is not attached. | |
2139 | */ | |
2140 | if (IS_G4X(dev) && !IS_GM45(dev)) { | |
2141 | u32 temp = I915_READ(PEG_BAND_GAP_DATA); | |
2142 | I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd); | |
2143 | } | |
2144 | } | |
2145 | ||
b242b7f7 | 2146 | void intel_hdmi_init(struct drm_device *dev, int hdmi_reg, enum port port) |
b9cb234c PZ |
2147 | { |
2148 | struct intel_digital_port *intel_dig_port; | |
2149 | struct intel_encoder *intel_encoder; | |
b9cb234c PZ |
2150 | struct intel_connector *intel_connector; |
2151 | ||
b14c5679 | 2152 | intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL); |
b9cb234c PZ |
2153 | if (!intel_dig_port) |
2154 | return; | |
2155 | ||
08d9bc92 | 2156 | intel_connector = intel_connector_alloc(); |
b9cb234c PZ |
2157 | if (!intel_connector) { |
2158 | kfree(intel_dig_port); | |
2159 | return; | |
2160 | } | |
2161 | ||
2162 | intel_encoder = &intel_dig_port->base; | |
b9cb234c PZ |
2163 | |
2164 | drm_encoder_init(dev, &intel_encoder->base, &intel_hdmi_enc_funcs, | |
2165 | DRM_MODE_ENCODER_TMDS); | |
00c09d70 | 2166 | |
5bfe2ac0 | 2167 | intel_encoder->compute_config = intel_hdmi_compute_config; |
a4790cec VS |
2168 | if (HAS_PCH_SPLIT(dev)) { |
2169 | intel_encoder->disable = pch_disable_hdmi; | |
2170 | intel_encoder->post_disable = pch_post_disable_hdmi; | |
2171 | } else { | |
2172 | intel_encoder->disable = g4x_disable_hdmi; | |
2173 | } | |
00c09d70 | 2174 | intel_encoder->get_hw_state = intel_hdmi_get_hw_state; |
045ac3b5 | 2175 | intel_encoder->get_config = intel_hdmi_get_config; |
e4a1d846 | 2176 | if (IS_CHERRYVIEW(dev)) { |
9197c88b | 2177 | intel_encoder->pre_pll_enable = chv_hdmi_pre_pll_enable; |
e4a1d846 CML |
2178 | intel_encoder->pre_enable = chv_hdmi_pre_enable; |
2179 | intel_encoder->enable = vlv_enable_hdmi; | |
580d3811 | 2180 | intel_encoder->post_disable = chv_hdmi_post_disable; |
d6db995f | 2181 | intel_encoder->post_pll_disable = chv_hdmi_post_pll_disable; |
e4a1d846 | 2182 | } else if (IS_VALLEYVIEW(dev)) { |
9514ac6e CML |
2183 | intel_encoder->pre_pll_enable = vlv_hdmi_pre_pll_enable; |
2184 | intel_encoder->pre_enable = vlv_hdmi_pre_enable; | |
b76cf76b | 2185 | intel_encoder->enable = vlv_enable_hdmi; |
9514ac6e | 2186 | intel_encoder->post_disable = vlv_hdmi_post_disable; |
b76cf76b | 2187 | } else { |
13732ba7 | 2188 | intel_encoder->pre_enable = intel_hdmi_pre_enable; |
d1b1589c VS |
2189 | if (HAS_PCH_CPT(dev)) |
2190 | intel_encoder->enable = cpt_enable_hdmi; | |
bf868c7d VS |
2191 | else if (HAS_PCH_IBX(dev)) |
2192 | intel_encoder->enable = ibx_enable_hdmi; | |
d1b1589c | 2193 | else |
bf868c7d | 2194 | intel_encoder->enable = g4x_enable_hdmi; |
89b667f8 | 2195 | } |
5ab432ef | 2196 | |
b9cb234c | 2197 | intel_encoder->type = INTEL_OUTPUT_HDMI; |
882ec384 VS |
2198 | if (IS_CHERRYVIEW(dev)) { |
2199 | if (port == PORT_D) | |
2200 | intel_encoder->crtc_mask = 1 << 2; | |
2201 | else | |
2202 | intel_encoder->crtc_mask = (1 << 0) | (1 << 1); | |
2203 | } else { | |
2204 | intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2); | |
2205 | } | |
301ea74a | 2206 | intel_encoder->cloneable = 1 << INTEL_OUTPUT_ANALOG; |
c6f1495d VS |
2207 | /* |
2208 | * BSpec is unclear about HDMI+HDMI cloning on g4x, but it seems | |
2209 | * to work on real hardware. And since g4x can send infoframes to | |
2210 | * only one port anyway, nothing is lost by allowing it. | |
2211 | */ | |
2212 | if (IS_G4X(dev)) | |
2213 | intel_encoder->cloneable |= 1 << INTEL_OUTPUT_HDMI; | |
7d57382e | 2214 | |
174edf1f | 2215 | intel_dig_port->port = port; |
b242b7f7 | 2216 | intel_dig_port->hdmi.hdmi_reg = hdmi_reg; |
b9cb234c | 2217 | intel_dig_port->dp.output_reg = 0; |
55b7d6e8 | 2218 | |
b9cb234c | 2219 | intel_hdmi_init_connector(intel_dig_port, intel_connector); |
7d57382e | 2220 | } |