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7d57382e EA |
1 | /* |
2 | * Copyright 2006 Dave Airlie <airlied@linux.ie> | |
3 | * Copyright © 2006-2009 Intel Corporation | |
4 | * | |
5 | * Permission is hereby granted, free of charge, to any person obtaining a | |
6 | * copy of this software and associated documentation files (the "Software"), | |
7 | * to deal in the Software without restriction, including without limitation | |
8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
9 | * and/or sell copies of the Software, and to permit persons to whom the | |
10 | * Software is furnished to do so, subject to the following conditions: | |
11 | * | |
12 | * The above copyright notice and this permission notice (including the next | |
13 | * paragraph) shall be included in all copies or substantial portions of the | |
14 | * Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
21 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
22 | * DEALINGS IN THE SOFTWARE. | |
23 | * | |
24 | * Authors: | |
25 | * Eric Anholt <eric@anholt.net> | |
26 | * Jesse Barnes <jesse.barnes@intel.com> | |
27 | */ | |
28 | ||
29 | #include <linux/i2c.h> | |
5a0e3ad6 | 30 | #include <linux/slab.h> |
7d57382e | 31 | #include <linux/delay.h> |
760285e7 DH |
32 | #include <drm/drmP.h> |
33 | #include <drm/drm_crtc.h> | |
34 | #include <drm/drm_edid.h> | |
7d57382e | 35 | #include "intel_drv.h" |
760285e7 | 36 | #include <drm/i915_drm.h> |
7d57382e EA |
37 | #include "i915_drv.h" |
38 | ||
30add22d PZ |
39 | static struct drm_device *intel_hdmi_to_dev(struct intel_hdmi *intel_hdmi) |
40 | { | |
41 | return intel_hdmi->base.base.dev; | |
42 | } | |
43 | ||
afba0188 DV |
44 | static void |
45 | assert_hdmi_port_disabled(struct intel_hdmi *intel_hdmi) | |
46 | { | |
30add22d | 47 | struct drm_device *dev = intel_hdmi_to_dev(intel_hdmi); |
afba0188 DV |
48 | struct drm_i915_private *dev_priv = dev->dev_private; |
49 | uint32_t enabled_bits; | |
50 | ||
51 | enabled_bits = IS_HASWELL(dev) ? DDI_BUF_CTL_ENABLE : SDVO_ENABLE; | |
52 | ||
53 | WARN(I915_READ(intel_hdmi->sdvox_reg) & enabled_bits, | |
54 | "HDMI port enabled, expecting disabled\n"); | |
55 | } | |
56 | ||
f5bbfca3 | 57 | struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder) |
ea5b213a | 58 | { |
4ef69c7a | 59 | return container_of(encoder, struct intel_hdmi, base.base); |
ea5b213a CW |
60 | } |
61 | ||
df0e9248 CW |
62 | static struct intel_hdmi *intel_attached_hdmi(struct drm_connector *connector) |
63 | { | |
64 | return container_of(intel_attached_encoder(connector), | |
65 | struct intel_hdmi, base); | |
66 | } | |
67 | ||
45187ace | 68 | void intel_dip_infoframe_csum(struct dip_infoframe *frame) |
3c17fe4b | 69 | { |
45187ace | 70 | uint8_t *data = (uint8_t *)frame; |
3c17fe4b DH |
71 | uint8_t sum = 0; |
72 | unsigned i; | |
73 | ||
45187ace JB |
74 | frame->checksum = 0; |
75 | frame->ecc = 0; | |
3c17fe4b | 76 | |
64a8fc01 | 77 | for (i = 0; i < frame->len + DIP_HEADER_SIZE; i++) |
3c17fe4b DH |
78 | sum += data[i]; |
79 | ||
45187ace | 80 | frame->checksum = 0x100 - sum; |
3c17fe4b DH |
81 | } |
82 | ||
bc2481f3 | 83 | static u32 g4x_infoframe_index(struct dip_infoframe *frame) |
3c17fe4b | 84 | { |
45187ace JB |
85 | switch (frame->type) { |
86 | case DIP_TYPE_AVI: | |
ed517fbb | 87 | return VIDEO_DIP_SELECT_AVI; |
45187ace | 88 | case DIP_TYPE_SPD: |
ed517fbb | 89 | return VIDEO_DIP_SELECT_SPD; |
45187ace JB |
90 | default: |
91 | DRM_DEBUG_DRIVER("unknown info frame type %d\n", frame->type); | |
ed517fbb | 92 | return 0; |
45187ace | 93 | } |
45187ace JB |
94 | } |
95 | ||
bc2481f3 | 96 | static u32 g4x_infoframe_enable(struct dip_infoframe *frame) |
45187ace | 97 | { |
45187ace JB |
98 | switch (frame->type) { |
99 | case DIP_TYPE_AVI: | |
ed517fbb | 100 | return VIDEO_DIP_ENABLE_AVI; |
45187ace | 101 | case DIP_TYPE_SPD: |
ed517fbb | 102 | return VIDEO_DIP_ENABLE_SPD; |
fa193ff7 PZ |
103 | default: |
104 | DRM_DEBUG_DRIVER("unknown info frame type %d\n", frame->type); | |
ed517fbb | 105 | return 0; |
fa193ff7 | 106 | } |
fa193ff7 PZ |
107 | } |
108 | ||
2da8af54 PZ |
109 | static u32 hsw_infoframe_enable(struct dip_infoframe *frame) |
110 | { | |
111 | switch (frame->type) { | |
112 | case DIP_TYPE_AVI: | |
113 | return VIDEO_DIP_ENABLE_AVI_HSW; | |
114 | case DIP_TYPE_SPD: | |
115 | return VIDEO_DIP_ENABLE_SPD_HSW; | |
116 | default: | |
117 | DRM_DEBUG_DRIVER("unknown info frame type %d\n", frame->type); | |
118 | return 0; | |
119 | } | |
120 | } | |
121 | ||
122 | static u32 hsw_infoframe_data_reg(struct dip_infoframe *frame, enum pipe pipe) | |
123 | { | |
124 | switch (frame->type) { | |
125 | case DIP_TYPE_AVI: | |
126 | return HSW_TVIDEO_DIP_AVI_DATA(pipe); | |
127 | case DIP_TYPE_SPD: | |
128 | return HSW_TVIDEO_DIP_SPD_DATA(pipe); | |
129 | default: | |
130 | DRM_DEBUG_DRIVER("unknown info frame type %d\n", frame->type); | |
131 | return 0; | |
132 | } | |
133 | } | |
134 | ||
a3da1df7 DV |
135 | static void g4x_write_infoframe(struct drm_encoder *encoder, |
136 | struct dip_infoframe *frame) | |
45187ace JB |
137 | { |
138 | uint32_t *data = (uint32_t *)frame; | |
3c17fe4b DH |
139 | struct drm_device *dev = encoder->dev; |
140 | struct drm_i915_private *dev_priv = dev->dev_private; | |
22509ec8 | 141 | u32 val = I915_READ(VIDEO_DIP_CTL); |
45187ace | 142 | unsigned i, len = DIP_HEADER_SIZE + frame->len; |
3c17fe4b | 143 | |
822974ae PZ |
144 | WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n"); |
145 | ||
1d4f85ac | 146 | val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ |
bc2481f3 | 147 | val |= g4x_infoframe_index(frame); |
22509ec8 | 148 | |
bc2481f3 | 149 | val &= ~g4x_infoframe_enable(frame); |
45187ace | 150 | |
22509ec8 | 151 | I915_WRITE(VIDEO_DIP_CTL, val); |
3c17fe4b | 152 | |
9d9740f0 | 153 | mmiowb(); |
45187ace | 154 | for (i = 0; i < len; i += 4) { |
3c17fe4b DH |
155 | I915_WRITE(VIDEO_DIP_DATA, *data); |
156 | data++; | |
157 | } | |
adf00b26 PZ |
158 | /* Write every possible data byte to force correct ECC calculation. */ |
159 | for (; i < VIDEO_DIP_DATA_SIZE; i += 4) | |
160 | I915_WRITE(VIDEO_DIP_DATA, 0); | |
9d9740f0 | 161 | mmiowb(); |
3c17fe4b | 162 | |
bc2481f3 | 163 | val |= g4x_infoframe_enable(frame); |
60c5ea2d | 164 | val &= ~VIDEO_DIP_FREQ_MASK; |
4b24c933 | 165 | val |= VIDEO_DIP_FREQ_VSYNC; |
45187ace | 166 | |
22509ec8 | 167 | I915_WRITE(VIDEO_DIP_CTL, val); |
9d9740f0 | 168 | POSTING_READ(VIDEO_DIP_CTL); |
3c17fe4b DH |
169 | } |
170 | ||
fdf1250a PZ |
171 | static void ibx_write_infoframe(struct drm_encoder *encoder, |
172 | struct dip_infoframe *frame) | |
173 | { | |
174 | uint32_t *data = (uint32_t *)frame; | |
175 | struct drm_device *dev = encoder->dev; | |
176 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ed517fbb | 177 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); |
fdf1250a PZ |
178 | int reg = TVIDEO_DIP_CTL(intel_crtc->pipe); |
179 | unsigned i, len = DIP_HEADER_SIZE + frame->len; | |
180 | u32 val = I915_READ(reg); | |
181 | ||
822974ae PZ |
182 | WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n"); |
183 | ||
fdf1250a | 184 | val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ |
bc2481f3 | 185 | val |= g4x_infoframe_index(frame); |
fdf1250a | 186 | |
bc2481f3 | 187 | val &= ~g4x_infoframe_enable(frame); |
fdf1250a PZ |
188 | |
189 | I915_WRITE(reg, val); | |
190 | ||
9d9740f0 | 191 | mmiowb(); |
fdf1250a PZ |
192 | for (i = 0; i < len; i += 4) { |
193 | I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data); | |
194 | data++; | |
195 | } | |
adf00b26 PZ |
196 | /* Write every possible data byte to force correct ECC calculation. */ |
197 | for (; i < VIDEO_DIP_DATA_SIZE; i += 4) | |
198 | I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0); | |
9d9740f0 | 199 | mmiowb(); |
fdf1250a | 200 | |
bc2481f3 | 201 | val |= g4x_infoframe_enable(frame); |
fdf1250a | 202 | val &= ~VIDEO_DIP_FREQ_MASK; |
4b24c933 | 203 | val |= VIDEO_DIP_FREQ_VSYNC; |
fdf1250a PZ |
204 | |
205 | I915_WRITE(reg, val); | |
9d9740f0 | 206 | POSTING_READ(reg); |
fdf1250a PZ |
207 | } |
208 | ||
209 | static void cpt_write_infoframe(struct drm_encoder *encoder, | |
210 | struct dip_infoframe *frame) | |
b055c8f3 | 211 | { |
45187ace | 212 | uint32_t *data = (uint32_t *)frame; |
b055c8f3 JB |
213 | struct drm_device *dev = encoder->dev; |
214 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ed517fbb | 215 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); |
b055c8f3 | 216 | int reg = TVIDEO_DIP_CTL(intel_crtc->pipe); |
45187ace | 217 | unsigned i, len = DIP_HEADER_SIZE + frame->len; |
22509ec8 | 218 | u32 val = I915_READ(reg); |
b055c8f3 | 219 | |
822974ae PZ |
220 | WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n"); |
221 | ||
64a8fc01 | 222 | val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ |
bc2481f3 | 223 | val |= g4x_infoframe_index(frame); |
45187ace | 224 | |
ecb97851 PZ |
225 | /* The DIP control register spec says that we need to update the AVI |
226 | * infoframe without clearing its enable bit */ | |
822974ae | 227 | if (frame->type != DIP_TYPE_AVI) |
bc2481f3 | 228 | val &= ~g4x_infoframe_enable(frame); |
ecb97851 | 229 | |
22509ec8 | 230 | I915_WRITE(reg, val); |
45187ace | 231 | |
9d9740f0 | 232 | mmiowb(); |
45187ace | 233 | for (i = 0; i < len; i += 4) { |
b055c8f3 JB |
234 | I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data); |
235 | data++; | |
236 | } | |
adf00b26 PZ |
237 | /* Write every possible data byte to force correct ECC calculation. */ |
238 | for (; i < VIDEO_DIP_DATA_SIZE; i += 4) | |
239 | I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0); | |
9d9740f0 | 240 | mmiowb(); |
b055c8f3 | 241 | |
bc2481f3 | 242 | val |= g4x_infoframe_enable(frame); |
60c5ea2d | 243 | val &= ~VIDEO_DIP_FREQ_MASK; |
4b24c933 | 244 | val |= VIDEO_DIP_FREQ_VSYNC; |
45187ace | 245 | |
22509ec8 | 246 | I915_WRITE(reg, val); |
9d9740f0 | 247 | POSTING_READ(reg); |
45187ace | 248 | } |
90b107c8 SK |
249 | |
250 | static void vlv_write_infoframe(struct drm_encoder *encoder, | |
251 | struct dip_infoframe *frame) | |
252 | { | |
253 | uint32_t *data = (uint32_t *)frame; | |
254 | struct drm_device *dev = encoder->dev; | |
255 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ed517fbb | 256 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); |
90b107c8 SK |
257 | int reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe); |
258 | unsigned i, len = DIP_HEADER_SIZE + frame->len; | |
22509ec8 | 259 | u32 val = I915_READ(reg); |
90b107c8 | 260 | |
822974ae PZ |
261 | WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n"); |
262 | ||
90b107c8 | 263 | val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ |
bc2481f3 | 264 | val |= g4x_infoframe_index(frame); |
22509ec8 | 265 | |
bc2481f3 | 266 | val &= ~g4x_infoframe_enable(frame); |
90b107c8 | 267 | |
22509ec8 | 268 | I915_WRITE(reg, val); |
90b107c8 | 269 | |
9d9740f0 | 270 | mmiowb(); |
90b107c8 SK |
271 | for (i = 0; i < len; i += 4) { |
272 | I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), *data); | |
273 | data++; | |
274 | } | |
adf00b26 PZ |
275 | /* Write every possible data byte to force correct ECC calculation. */ |
276 | for (; i < VIDEO_DIP_DATA_SIZE; i += 4) | |
277 | I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), 0); | |
9d9740f0 | 278 | mmiowb(); |
90b107c8 | 279 | |
bc2481f3 | 280 | val |= g4x_infoframe_enable(frame); |
60c5ea2d | 281 | val &= ~VIDEO_DIP_FREQ_MASK; |
4b24c933 | 282 | val |= VIDEO_DIP_FREQ_VSYNC; |
90b107c8 | 283 | |
22509ec8 | 284 | I915_WRITE(reg, val); |
9d9740f0 | 285 | POSTING_READ(reg); |
90b107c8 SK |
286 | } |
287 | ||
8c5f5f7c | 288 | static void hsw_write_infoframe(struct drm_encoder *encoder, |
ed517fbb | 289 | struct dip_infoframe *frame) |
8c5f5f7c | 290 | { |
2da8af54 PZ |
291 | uint32_t *data = (uint32_t *)frame; |
292 | struct drm_device *dev = encoder->dev; | |
293 | struct drm_i915_private *dev_priv = dev->dev_private; | |
294 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); | |
295 | u32 ctl_reg = HSW_TVIDEO_DIP_CTL(intel_crtc->pipe); | |
296 | u32 data_reg = hsw_infoframe_data_reg(frame, intel_crtc->pipe); | |
297 | unsigned int i, len = DIP_HEADER_SIZE + frame->len; | |
298 | u32 val = I915_READ(ctl_reg); | |
8c5f5f7c | 299 | |
2da8af54 PZ |
300 | if (data_reg == 0) |
301 | return; | |
302 | ||
2da8af54 PZ |
303 | val &= ~hsw_infoframe_enable(frame); |
304 | I915_WRITE(ctl_reg, val); | |
305 | ||
9d9740f0 | 306 | mmiowb(); |
2da8af54 PZ |
307 | for (i = 0; i < len; i += 4) { |
308 | I915_WRITE(data_reg + i, *data); | |
309 | data++; | |
310 | } | |
adf00b26 PZ |
311 | /* Write every possible data byte to force correct ECC calculation. */ |
312 | for (; i < VIDEO_DIP_DATA_SIZE; i += 4) | |
313 | I915_WRITE(data_reg + i, 0); | |
9d9740f0 | 314 | mmiowb(); |
8c5f5f7c | 315 | |
2da8af54 PZ |
316 | val |= hsw_infoframe_enable(frame); |
317 | I915_WRITE(ctl_reg, val); | |
9d9740f0 | 318 | POSTING_READ(ctl_reg); |
8c5f5f7c ED |
319 | } |
320 | ||
45187ace JB |
321 | static void intel_set_infoframe(struct drm_encoder *encoder, |
322 | struct dip_infoframe *frame) | |
323 | { | |
324 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); | |
325 | ||
45187ace JB |
326 | intel_dip_infoframe_csum(frame); |
327 | intel_hdmi->write_infoframe(encoder, frame); | |
328 | } | |
329 | ||
687f4d06 | 330 | static void intel_hdmi_set_avi_infoframe(struct drm_encoder *encoder, |
c846b619 | 331 | struct drm_display_mode *adjusted_mode) |
45187ace JB |
332 | { |
333 | struct dip_infoframe avi_if = { | |
334 | .type = DIP_TYPE_AVI, | |
335 | .ver = DIP_VERSION_AVI, | |
336 | .len = DIP_LEN_AVI, | |
337 | }; | |
338 | ||
c846b619 PZ |
339 | if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK) |
340 | avi_if.body.avi.YQ_CN_PR |= DIP_AVI_PR_2; | |
341 | ||
45187ace | 342 | intel_set_infoframe(encoder, &avi_if); |
b055c8f3 JB |
343 | } |
344 | ||
687f4d06 | 345 | static void intel_hdmi_set_spd_infoframe(struct drm_encoder *encoder) |
c0864cb3 JB |
346 | { |
347 | struct dip_infoframe spd_if; | |
348 | ||
349 | memset(&spd_if, 0, sizeof(spd_if)); | |
350 | spd_if.type = DIP_TYPE_SPD; | |
351 | spd_if.ver = DIP_VERSION_SPD; | |
352 | spd_if.len = DIP_LEN_SPD; | |
353 | strcpy(spd_if.body.spd.vn, "Intel"); | |
354 | strcpy(spd_if.body.spd.pd, "Integrated gfx"); | |
355 | spd_if.body.spd.sdi = DIP_SPD_PC; | |
356 | ||
357 | intel_set_infoframe(encoder, &spd_if); | |
358 | } | |
359 | ||
687f4d06 PZ |
360 | static void g4x_set_infoframes(struct drm_encoder *encoder, |
361 | struct drm_display_mode *adjusted_mode) | |
362 | { | |
0c14c7f9 PZ |
363 | struct drm_i915_private *dev_priv = encoder->dev->dev_private; |
364 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); | |
365 | u32 reg = VIDEO_DIP_CTL; | |
366 | u32 val = I915_READ(reg); | |
72b78c9d | 367 | u32 port; |
0c14c7f9 | 368 | |
afba0188 DV |
369 | assert_hdmi_port_disabled(intel_hdmi); |
370 | ||
0c14c7f9 PZ |
371 | /* If the registers were not initialized yet, they might be zeroes, |
372 | * which means we're selecting the AVI DIP and we're setting its | |
373 | * frequency to once. This seems to really confuse the HW and make | |
374 | * things stop working (the register spec says the AVI always needs to | |
375 | * be sent every VSync). So here we avoid writing to the register more | |
376 | * than we need and also explicitly select the AVI DIP and explicitly | |
377 | * set its frequency to every VSync. Avoiding to write it twice seems to | |
378 | * be enough to solve the problem, but being defensive shouldn't hurt us | |
379 | * either. */ | |
380 | val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; | |
381 | ||
382 | if (!intel_hdmi->has_hdmi_sink) { | |
383 | if (!(val & VIDEO_DIP_ENABLE)) | |
384 | return; | |
385 | val &= ~VIDEO_DIP_ENABLE; | |
386 | I915_WRITE(reg, val); | |
9d9740f0 | 387 | POSTING_READ(reg); |
0c14c7f9 PZ |
388 | return; |
389 | } | |
390 | ||
f278d972 PZ |
391 | switch (intel_hdmi->sdvox_reg) { |
392 | case SDVOB: | |
72b78c9d | 393 | port = VIDEO_DIP_PORT_B; |
f278d972 PZ |
394 | break; |
395 | case SDVOC: | |
72b78c9d | 396 | port = VIDEO_DIP_PORT_C; |
f278d972 PZ |
397 | break; |
398 | default: | |
57df2ae9 | 399 | BUG(); |
f278d972 PZ |
400 | return; |
401 | } | |
402 | ||
72b78c9d PZ |
403 | if (port != (val & VIDEO_DIP_PORT_MASK)) { |
404 | if (val & VIDEO_DIP_ENABLE) { | |
405 | val &= ~VIDEO_DIP_ENABLE; | |
406 | I915_WRITE(reg, val); | |
9d9740f0 | 407 | POSTING_READ(reg); |
72b78c9d PZ |
408 | } |
409 | val &= ~VIDEO_DIP_PORT_MASK; | |
410 | val |= port; | |
411 | } | |
412 | ||
822974ae | 413 | val |= VIDEO_DIP_ENABLE; |
0dd87d20 | 414 | val &= ~VIDEO_DIP_ENABLE_VENDOR; |
822974ae | 415 | |
f278d972 | 416 | I915_WRITE(reg, val); |
9d9740f0 | 417 | POSTING_READ(reg); |
f278d972 | 418 | |
687f4d06 PZ |
419 | intel_hdmi_set_avi_infoframe(encoder, adjusted_mode); |
420 | intel_hdmi_set_spd_infoframe(encoder); | |
421 | } | |
422 | ||
423 | static void ibx_set_infoframes(struct drm_encoder *encoder, | |
424 | struct drm_display_mode *adjusted_mode) | |
425 | { | |
0c14c7f9 PZ |
426 | struct drm_i915_private *dev_priv = encoder->dev->dev_private; |
427 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); | |
428 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); | |
429 | u32 reg = TVIDEO_DIP_CTL(intel_crtc->pipe); | |
430 | u32 val = I915_READ(reg); | |
72b78c9d | 431 | u32 port; |
0c14c7f9 | 432 | |
afba0188 DV |
433 | assert_hdmi_port_disabled(intel_hdmi); |
434 | ||
0c14c7f9 PZ |
435 | /* See the big comment in g4x_set_infoframes() */ |
436 | val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; | |
437 | ||
438 | if (!intel_hdmi->has_hdmi_sink) { | |
439 | if (!(val & VIDEO_DIP_ENABLE)) | |
440 | return; | |
441 | val &= ~VIDEO_DIP_ENABLE; | |
442 | I915_WRITE(reg, val); | |
9d9740f0 | 443 | POSTING_READ(reg); |
0c14c7f9 PZ |
444 | return; |
445 | } | |
446 | ||
f278d972 PZ |
447 | switch (intel_hdmi->sdvox_reg) { |
448 | case HDMIB: | |
72b78c9d | 449 | port = VIDEO_DIP_PORT_B; |
f278d972 PZ |
450 | break; |
451 | case HDMIC: | |
72b78c9d | 452 | port = VIDEO_DIP_PORT_C; |
f278d972 PZ |
453 | break; |
454 | case HDMID: | |
72b78c9d | 455 | port = VIDEO_DIP_PORT_D; |
f278d972 PZ |
456 | break; |
457 | default: | |
57df2ae9 | 458 | BUG(); |
f278d972 PZ |
459 | return; |
460 | } | |
461 | ||
72b78c9d PZ |
462 | if (port != (val & VIDEO_DIP_PORT_MASK)) { |
463 | if (val & VIDEO_DIP_ENABLE) { | |
464 | val &= ~VIDEO_DIP_ENABLE; | |
465 | I915_WRITE(reg, val); | |
9d9740f0 | 466 | POSTING_READ(reg); |
72b78c9d PZ |
467 | } |
468 | val &= ~VIDEO_DIP_PORT_MASK; | |
469 | val |= port; | |
470 | } | |
471 | ||
822974ae | 472 | val |= VIDEO_DIP_ENABLE; |
0dd87d20 PZ |
473 | val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | |
474 | VIDEO_DIP_ENABLE_GCP); | |
822974ae | 475 | |
f278d972 | 476 | I915_WRITE(reg, val); |
9d9740f0 | 477 | POSTING_READ(reg); |
f278d972 | 478 | |
687f4d06 PZ |
479 | intel_hdmi_set_avi_infoframe(encoder, adjusted_mode); |
480 | intel_hdmi_set_spd_infoframe(encoder); | |
481 | } | |
482 | ||
483 | static void cpt_set_infoframes(struct drm_encoder *encoder, | |
484 | struct drm_display_mode *adjusted_mode) | |
485 | { | |
0c14c7f9 PZ |
486 | struct drm_i915_private *dev_priv = encoder->dev->dev_private; |
487 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); | |
488 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); | |
489 | u32 reg = TVIDEO_DIP_CTL(intel_crtc->pipe); | |
490 | u32 val = I915_READ(reg); | |
491 | ||
afba0188 DV |
492 | assert_hdmi_port_disabled(intel_hdmi); |
493 | ||
0c14c7f9 PZ |
494 | /* See the big comment in g4x_set_infoframes() */ |
495 | val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; | |
496 | ||
497 | if (!intel_hdmi->has_hdmi_sink) { | |
498 | if (!(val & VIDEO_DIP_ENABLE)) | |
499 | return; | |
500 | val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI); | |
501 | I915_WRITE(reg, val); | |
9d9740f0 | 502 | POSTING_READ(reg); |
0c14c7f9 PZ |
503 | return; |
504 | } | |
505 | ||
822974ae PZ |
506 | /* Set both together, unset both together: see the spec. */ |
507 | val |= VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI; | |
0dd87d20 PZ |
508 | val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | |
509 | VIDEO_DIP_ENABLE_GCP); | |
822974ae PZ |
510 | |
511 | I915_WRITE(reg, val); | |
9d9740f0 | 512 | POSTING_READ(reg); |
822974ae | 513 | |
687f4d06 PZ |
514 | intel_hdmi_set_avi_infoframe(encoder, adjusted_mode); |
515 | intel_hdmi_set_spd_infoframe(encoder); | |
516 | } | |
517 | ||
518 | static void vlv_set_infoframes(struct drm_encoder *encoder, | |
519 | struct drm_display_mode *adjusted_mode) | |
520 | { | |
0c14c7f9 PZ |
521 | struct drm_i915_private *dev_priv = encoder->dev->dev_private; |
522 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); | |
523 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); | |
524 | u32 reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe); | |
525 | u32 val = I915_READ(reg); | |
526 | ||
afba0188 DV |
527 | assert_hdmi_port_disabled(intel_hdmi); |
528 | ||
0c14c7f9 PZ |
529 | /* See the big comment in g4x_set_infoframes() */ |
530 | val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; | |
531 | ||
532 | if (!intel_hdmi->has_hdmi_sink) { | |
533 | if (!(val & VIDEO_DIP_ENABLE)) | |
534 | return; | |
535 | val &= ~VIDEO_DIP_ENABLE; | |
536 | I915_WRITE(reg, val); | |
9d9740f0 | 537 | POSTING_READ(reg); |
0c14c7f9 PZ |
538 | return; |
539 | } | |
540 | ||
822974ae | 541 | val |= VIDEO_DIP_ENABLE; |
0dd87d20 PZ |
542 | val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | |
543 | VIDEO_DIP_ENABLE_GCP); | |
822974ae PZ |
544 | |
545 | I915_WRITE(reg, val); | |
9d9740f0 | 546 | POSTING_READ(reg); |
822974ae | 547 | |
687f4d06 PZ |
548 | intel_hdmi_set_avi_infoframe(encoder, adjusted_mode); |
549 | intel_hdmi_set_spd_infoframe(encoder); | |
550 | } | |
551 | ||
552 | static void hsw_set_infoframes(struct drm_encoder *encoder, | |
553 | struct drm_display_mode *adjusted_mode) | |
554 | { | |
0c14c7f9 PZ |
555 | struct drm_i915_private *dev_priv = encoder->dev->dev_private; |
556 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); | |
557 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); | |
558 | u32 reg = HSW_TVIDEO_DIP_CTL(intel_crtc->pipe); | |
0dd87d20 | 559 | u32 val = I915_READ(reg); |
0c14c7f9 | 560 | |
afba0188 DV |
561 | assert_hdmi_port_disabled(intel_hdmi); |
562 | ||
0c14c7f9 PZ |
563 | if (!intel_hdmi->has_hdmi_sink) { |
564 | I915_WRITE(reg, 0); | |
9d9740f0 | 565 | POSTING_READ(reg); |
0c14c7f9 PZ |
566 | return; |
567 | } | |
568 | ||
0dd87d20 PZ |
569 | val &= ~(VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_GCP_HSW | |
570 | VIDEO_DIP_ENABLE_VS_HSW | VIDEO_DIP_ENABLE_GMP_HSW); | |
571 | ||
572 | I915_WRITE(reg, val); | |
9d9740f0 | 573 | POSTING_READ(reg); |
0dd87d20 | 574 | |
687f4d06 PZ |
575 | intel_hdmi_set_avi_infoframe(encoder, adjusted_mode); |
576 | intel_hdmi_set_spd_infoframe(encoder); | |
577 | } | |
578 | ||
7d57382e EA |
579 | static void intel_hdmi_mode_set(struct drm_encoder *encoder, |
580 | struct drm_display_mode *mode, | |
581 | struct drm_display_mode *adjusted_mode) | |
582 | { | |
583 | struct drm_device *dev = encoder->dev; | |
584 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ed517fbb | 585 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); |
ea5b213a | 586 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); |
7d57382e EA |
587 | u32 sdvox; |
588 | ||
b659c3db | 589 | sdvox = SDVO_ENCODING_HDMI; |
5d4fac97 JB |
590 | if (!HAS_PCH_SPLIT(dev)) |
591 | sdvox |= intel_hdmi->color_range; | |
b599c0bc AJ |
592 | if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) |
593 | sdvox |= SDVO_VSYNC_ACTIVE_HIGH; | |
594 | if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) | |
595 | sdvox |= SDVO_HSYNC_ACTIVE_HIGH; | |
7d57382e | 596 | |
020f6704 JB |
597 | if (intel_crtc->bpp > 24) |
598 | sdvox |= COLOR_FORMAT_12bpc; | |
599 | else | |
600 | sdvox |= COLOR_FORMAT_8bpc; | |
601 | ||
2e3d6006 ZW |
602 | /* Required on CPT */ |
603 | if (intel_hdmi->has_hdmi_sink && HAS_PCH_CPT(dev)) | |
604 | sdvox |= HDMI_MODE_SELECT; | |
605 | ||
3c17fe4b | 606 | if (intel_hdmi->has_audio) { |
e0dac65e WF |
607 | DRM_DEBUG_DRIVER("Enabling HDMI audio on pipe %c\n", |
608 | pipe_name(intel_crtc->pipe)); | |
7d57382e | 609 | sdvox |= SDVO_AUDIO_ENABLE; |
3c17fe4b | 610 | sdvox |= SDVO_NULL_PACKETS_DURING_VSYNC; |
e0dac65e | 611 | intel_write_eld(encoder, adjusted_mode); |
3c17fe4b | 612 | } |
7d57382e | 613 | |
75770564 JB |
614 | if (HAS_PCH_CPT(dev)) |
615 | sdvox |= PORT_TRANS_SEL_CPT(intel_crtc->pipe); | |
7a87c289 | 616 | else if (intel_crtc->pipe == PIPE_B) |
75770564 | 617 | sdvox |= SDVO_PIPE_B_SELECT; |
7d57382e | 618 | |
ea5b213a CW |
619 | I915_WRITE(intel_hdmi->sdvox_reg, sdvox); |
620 | POSTING_READ(intel_hdmi->sdvox_reg); | |
3c17fe4b | 621 | |
687f4d06 | 622 | intel_hdmi->set_infoframes(encoder, adjusted_mode); |
7d57382e EA |
623 | } |
624 | ||
85234cdc DV |
625 | static bool intel_hdmi_get_hw_state(struct intel_encoder *encoder, |
626 | enum pipe *pipe) | |
7d57382e | 627 | { |
85234cdc | 628 | struct drm_device *dev = encoder->base.dev; |
7d57382e | 629 | struct drm_i915_private *dev_priv = dev->dev_private; |
85234cdc DV |
630 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); |
631 | u32 tmp; | |
632 | ||
633 | tmp = I915_READ(intel_hdmi->sdvox_reg); | |
634 | ||
635 | if (!(tmp & SDVO_ENABLE)) | |
636 | return false; | |
637 | ||
638 | if (HAS_PCH_CPT(dev)) | |
639 | *pipe = PORT_TO_PIPE_CPT(tmp); | |
640 | else | |
641 | *pipe = PORT_TO_PIPE(tmp); | |
642 | ||
643 | return true; | |
644 | } | |
645 | ||
5ab432ef | 646 | static void intel_enable_hdmi(struct intel_encoder *encoder) |
7d57382e | 647 | { |
5ab432ef | 648 | struct drm_device *dev = encoder->base.dev; |
7d57382e | 649 | struct drm_i915_private *dev_priv = dev->dev_private; |
5ab432ef | 650 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); |
7d57382e | 651 | u32 temp; |
2deed761 WF |
652 | u32 enable_bits = SDVO_ENABLE; |
653 | ||
654 | if (intel_hdmi->has_audio) | |
655 | enable_bits |= SDVO_AUDIO_ENABLE; | |
7d57382e | 656 | |
ea5b213a | 657 | temp = I915_READ(intel_hdmi->sdvox_reg); |
d8a2d0e0 | 658 | |
7a87c289 DV |
659 | /* HW workaround for IBX, we need to move the port to transcoder A |
660 | * before disabling it. */ | |
661 | if (HAS_PCH_IBX(dev)) { | |
5ab432ef | 662 | struct drm_crtc *crtc = encoder->base.crtc; |
7a87c289 DV |
663 | int pipe = crtc ? to_intel_crtc(crtc)->pipe : -1; |
664 | ||
5ab432ef DV |
665 | /* Restore the transcoder select bit. */ |
666 | if (pipe == PIPE_B) | |
667 | enable_bits |= SDVO_PIPE_B_SELECT; | |
7a87c289 DV |
668 | } |
669 | ||
d8a2d0e0 ZW |
670 | /* HW workaround, need to toggle enable bit off and on for 12bpc, but |
671 | * we do this anyway which shows more stable in testing. | |
672 | */ | |
c619eed4 | 673 | if (HAS_PCH_SPLIT(dev)) { |
ea5b213a CW |
674 | I915_WRITE(intel_hdmi->sdvox_reg, temp & ~SDVO_ENABLE); |
675 | POSTING_READ(intel_hdmi->sdvox_reg); | |
d8a2d0e0 ZW |
676 | } |
677 | ||
5ab432ef DV |
678 | temp |= enable_bits; |
679 | ||
680 | I915_WRITE(intel_hdmi->sdvox_reg, temp); | |
681 | POSTING_READ(intel_hdmi->sdvox_reg); | |
682 | ||
683 | /* HW workaround, need to write this twice for issue that may result | |
684 | * in first write getting masked. | |
685 | */ | |
686 | if (HAS_PCH_SPLIT(dev)) { | |
687 | I915_WRITE(intel_hdmi->sdvox_reg, temp); | |
688 | POSTING_READ(intel_hdmi->sdvox_reg); | |
7d57382e | 689 | } |
5ab432ef DV |
690 | } |
691 | ||
692 | static void intel_disable_hdmi(struct intel_encoder *encoder) | |
693 | { | |
694 | struct drm_device *dev = encoder->base.dev; | |
695 | struct drm_i915_private *dev_priv = dev->dev_private; | |
696 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); | |
697 | u32 temp; | |
3cce574f | 698 | u32 enable_bits = SDVO_ENABLE | SDVO_AUDIO_ENABLE; |
5ab432ef DV |
699 | |
700 | temp = I915_READ(intel_hdmi->sdvox_reg); | |
701 | ||
702 | /* HW workaround for IBX, we need to move the port to transcoder A | |
703 | * before disabling it. */ | |
704 | if (HAS_PCH_IBX(dev)) { | |
705 | struct drm_crtc *crtc = encoder->base.crtc; | |
706 | int pipe = crtc ? to_intel_crtc(crtc)->pipe : -1; | |
707 | ||
708 | if (temp & SDVO_PIPE_B_SELECT) { | |
709 | temp &= ~SDVO_PIPE_B_SELECT; | |
710 | I915_WRITE(intel_hdmi->sdvox_reg, temp); | |
711 | POSTING_READ(intel_hdmi->sdvox_reg); | |
712 | ||
713 | /* Again we need to write this twice. */ | |
714 | I915_WRITE(intel_hdmi->sdvox_reg, temp); | |
715 | POSTING_READ(intel_hdmi->sdvox_reg); | |
716 | ||
717 | /* Transcoder selection bits only update | |
718 | * effectively on vblank. */ | |
719 | if (crtc) | |
720 | intel_wait_for_vblank(dev, pipe); | |
721 | else | |
722 | msleep(50); | |
723 | } | |
7d57382e | 724 | } |
d8a2d0e0 | 725 | |
5ab432ef DV |
726 | /* HW workaround, need to toggle enable bit off and on for 12bpc, but |
727 | * we do this anyway which shows more stable in testing. | |
728 | */ | |
729 | if (HAS_PCH_SPLIT(dev)) { | |
730 | I915_WRITE(intel_hdmi->sdvox_reg, temp & ~SDVO_ENABLE); | |
731 | POSTING_READ(intel_hdmi->sdvox_reg); | |
732 | } | |
733 | ||
734 | temp &= ~enable_bits; | |
d8a2d0e0 | 735 | |
ea5b213a CW |
736 | I915_WRITE(intel_hdmi->sdvox_reg, temp); |
737 | POSTING_READ(intel_hdmi->sdvox_reg); | |
d8a2d0e0 ZW |
738 | |
739 | /* HW workaround, need to write this twice for issue that may result | |
740 | * in first write getting masked. | |
741 | */ | |
c619eed4 | 742 | if (HAS_PCH_SPLIT(dev)) { |
ea5b213a CW |
743 | I915_WRITE(intel_hdmi->sdvox_reg, temp); |
744 | POSTING_READ(intel_hdmi->sdvox_reg); | |
d8a2d0e0 | 745 | } |
7d57382e EA |
746 | } |
747 | ||
7d57382e EA |
748 | static int intel_hdmi_mode_valid(struct drm_connector *connector, |
749 | struct drm_display_mode *mode) | |
750 | { | |
751 | if (mode->clock > 165000) | |
752 | return MODE_CLOCK_HIGH; | |
753 | if (mode->clock < 20000) | |
5cbba41d | 754 | return MODE_CLOCK_LOW; |
7d57382e EA |
755 | |
756 | if (mode->flags & DRM_MODE_FLAG_DBLSCAN) | |
757 | return MODE_NO_DBLESCAN; | |
758 | ||
759 | return MODE_OK; | |
760 | } | |
761 | ||
762 | static bool intel_hdmi_mode_fixup(struct drm_encoder *encoder, | |
e811f5ae | 763 | const struct drm_display_mode *mode, |
7d57382e EA |
764 | struct drm_display_mode *adjusted_mode) |
765 | { | |
766 | return true; | |
767 | } | |
768 | ||
8ec22b21 CW |
769 | static bool g4x_hdmi_connected(struct intel_hdmi *intel_hdmi) |
770 | { | |
30add22d | 771 | struct drm_device *dev = intel_hdmi_to_dev(intel_hdmi); |
8ec22b21 CW |
772 | struct drm_i915_private *dev_priv = dev->dev_private; |
773 | uint32_t bit; | |
774 | ||
775 | switch (intel_hdmi->sdvox_reg) { | |
eeafaaca | 776 | case SDVOB: |
8ec22b21 CW |
777 | bit = HDMIB_HOTPLUG_LIVE_STATUS; |
778 | break; | |
eeafaaca | 779 | case SDVOC: |
8ec22b21 CW |
780 | bit = HDMIC_HOTPLUG_LIVE_STATUS; |
781 | break; | |
8ec22b21 CW |
782 | default: |
783 | bit = 0; | |
784 | break; | |
785 | } | |
786 | ||
787 | return I915_READ(PORT_HOTPLUG_STAT) & bit; | |
788 | } | |
789 | ||
aa93d632 | 790 | static enum drm_connector_status |
930a9e28 | 791 | intel_hdmi_detect(struct drm_connector *connector, bool force) |
9dff6af8 | 792 | { |
df0e9248 | 793 | struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); |
f899fc64 CW |
794 | struct drm_i915_private *dev_priv = connector->dev->dev_private; |
795 | struct edid *edid; | |
aa93d632 | 796 | enum drm_connector_status status = connector_status_disconnected; |
9dff6af8 | 797 | |
8ec22b21 CW |
798 | if (IS_G4X(connector->dev) && !g4x_hdmi_connected(intel_hdmi)) |
799 | return status; | |
800 | ||
ea5b213a | 801 | intel_hdmi->has_hdmi_sink = false; |
2e3d6006 | 802 | intel_hdmi->has_audio = false; |
f899fc64 | 803 | edid = drm_get_edid(connector, |
3bd7d909 DK |
804 | intel_gmbus_get_adapter(dev_priv, |
805 | intel_hdmi->ddc_bus)); | |
2ded9e27 | 806 | |
aa93d632 | 807 | if (edid) { |
be9f1c4f | 808 | if (edid->input & DRM_EDID_INPUT_DIGITAL) { |
aa93d632 | 809 | status = connector_status_connected; |
b1d7e4b4 WF |
810 | if (intel_hdmi->force_audio != HDMI_AUDIO_OFF_DVI) |
811 | intel_hdmi->has_hdmi_sink = | |
812 | drm_detect_hdmi_monitor(edid); | |
2e3d6006 | 813 | intel_hdmi->has_audio = drm_detect_monitor_audio(edid); |
aa93d632 | 814 | } |
aa93d632 | 815 | kfree(edid); |
9dff6af8 | 816 | } |
30ad48b7 | 817 | |
55b7d6e8 | 818 | if (status == connector_status_connected) { |
b1d7e4b4 WF |
819 | if (intel_hdmi->force_audio != HDMI_AUDIO_AUTO) |
820 | intel_hdmi->has_audio = | |
821 | (intel_hdmi->force_audio == HDMI_AUDIO_ON); | |
55b7d6e8 CW |
822 | } |
823 | ||
2ded9e27 | 824 | return status; |
7d57382e EA |
825 | } |
826 | ||
827 | static int intel_hdmi_get_modes(struct drm_connector *connector) | |
828 | { | |
df0e9248 | 829 | struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); |
f899fc64 | 830 | struct drm_i915_private *dev_priv = connector->dev->dev_private; |
7d57382e EA |
831 | |
832 | /* We should parse the EDID data and find out if it's an HDMI sink so | |
833 | * we can send audio to it. | |
834 | */ | |
835 | ||
f899fc64 | 836 | return intel_ddc_get_modes(connector, |
3bd7d909 DK |
837 | intel_gmbus_get_adapter(dev_priv, |
838 | intel_hdmi->ddc_bus)); | |
7d57382e EA |
839 | } |
840 | ||
1aad7ac0 CW |
841 | static bool |
842 | intel_hdmi_detect_audio(struct drm_connector *connector) | |
843 | { | |
844 | struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); | |
845 | struct drm_i915_private *dev_priv = connector->dev->dev_private; | |
846 | struct edid *edid; | |
847 | bool has_audio = false; | |
848 | ||
849 | edid = drm_get_edid(connector, | |
3bd7d909 DK |
850 | intel_gmbus_get_adapter(dev_priv, |
851 | intel_hdmi->ddc_bus)); | |
1aad7ac0 CW |
852 | if (edid) { |
853 | if (edid->input & DRM_EDID_INPUT_DIGITAL) | |
854 | has_audio = drm_detect_monitor_audio(edid); | |
1aad7ac0 CW |
855 | kfree(edid); |
856 | } | |
857 | ||
858 | return has_audio; | |
859 | } | |
860 | ||
55b7d6e8 CW |
861 | static int |
862 | intel_hdmi_set_property(struct drm_connector *connector, | |
ed517fbb PZ |
863 | struct drm_property *property, |
864 | uint64_t val) | |
55b7d6e8 CW |
865 | { |
866 | struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); | |
e953fd7b | 867 | struct drm_i915_private *dev_priv = connector->dev->dev_private; |
55b7d6e8 CW |
868 | int ret; |
869 | ||
870 | ret = drm_connector_property_set_value(connector, property, val); | |
871 | if (ret) | |
872 | return ret; | |
873 | ||
3f43c48d | 874 | if (property == dev_priv->force_audio_property) { |
b1d7e4b4 | 875 | enum hdmi_force_audio i = val; |
1aad7ac0 CW |
876 | bool has_audio; |
877 | ||
878 | if (i == intel_hdmi->force_audio) | |
55b7d6e8 CW |
879 | return 0; |
880 | ||
1aad7ac0 | 881 | intel_hdmi->force_audio = i; |
55b7d6e8 | 882 | |
b1d7e4b4 | 883 | if (i == HDMI_AUDIO_AUTO) |
1aad7ac0 CW |
884 | has_audio = intel_hdmi_detect_audio(connector); |
885 | else | |
b1d7e4b4 | 886 | has_audio = (i == HDMI_AUDIO_ON); |
1aad7ac0 | 887 | |
b1d7e4b4 WF |
888 | if (i == HDMI_AUDIO_OFF_DVI) |
889 | intel_hdmi->has_hdmi_sink = 0; | |
55b7d6e8 | 890 | |
1aad7ac0 | 891 | intel_hdmi->has_audio = has_audio; |
55b7d6e8 CW |
892 | goto done; |
893 | } | |
894 | ||
e953fd7b CW |
895 | if (property == dev_priv->broadcast_rgb_property) { |
896 | if (val == !!intel_hdmi->color_range) | |
897 | return 0; | |
898 | ||
899 | intel_hdmi->color_range = val ? SDVO_COLOR_RANGE_16_235 : 0; | |
900 | goto done; | |
901 | } | |
902 | ||
55b7d6e8 CW |
903 | return -EINVAL; |
904 | ||
905 | done: | |
906 | if (intel_hdmi->base.base.crtc) { | |
907 | struct drm_crtc *crtc = intel_hdmi->base.base.crtc; | |
a6778b3c DV |
908 | intel_set_mode(crtc, &crtc->mode, |
909 | crtc->x, crtc->y, crtc->fb); | |
55b7d6e8 CW |
910 | } |
911 | ||
912 | return 0; | |
913 | } | |
914 | ||
7d57382e EA |
915 | static void intel_hdmi_destroy(struct drm_connector *connector) |
916 | { | |
7d57382e EA |
917 | drm_sysfs_connector_remove(connector); |
918 | drm_connector_cleanup(connector); | |
674e2d08 | 919 | kfree(connector); |
7d57382e EA |
920 | } |
921 | ||
72662e10 | 922 | static const struct drm_encoder_helper_funcs intel_hdmi_helper_funcs_hsw = { |
72662e10 | 923 | .mode_fixup = intel_hdmi_mode_fixup, |
72662e10 | 924 | .mode_set = intel_ddi_mode_set, |
1f703855 | 925 | .disable = intel_encoder_noop, |
72662e10 ED |
926 | }; |
927 | ||
7d57382e | 928 | static const struct drm_encoder_helper_funcs intel_hdmi_helper_funcs = { |
7d57382e | 929 | .mode_fixup = intel_hdmi_mode_fixup, |
7d57382e | 930 | .mode_set = intel_hdmi_mode_set, |
1f703855 | 931 | .disable = intel_encoder_noop, |
7d57382e EA |
932 | }; |
933 | ||
934 | static const struct drm_connector_funcs intel_hdmi_connector_funcs = { | |
5ab432ef | 935 | .dpms = intel_connector_dpms, |
7d57382e EA |
936 | .detect = intel_hdmi_detect, |
937 | .fill_modes = drm_helper_probe_single_connector_modes, | |
55b7d6e8 | 938 | .set_property = intel_hdmi_set_property, |
7d57382e EA |
939 | .destroy = intel_hdmi_destroy, |
940 | }; | |
941 | ||
942 | static const struct drm_connector_helper_funcs intel_hdmi_connector_helper_funcs = { | |
943 | .get_modes = intel_hdmi_get_modes, | |
944 | .mode_valid = intel_hdmi_mode_valid, | |
df0e9248 | 945 | .best_encoder = intel_best_encoder, |
7d57382e EA |
946 | }; |
947 | ||
7d57382e | 948 | static const struct drm_encoder_funcs intel_hdmi_enc_funcs = { |
ea5b213a | 949 | .destroy = intel_encoder_destroy, |
7d57382e EA |
950 | }; |
951 | ||
55b7d6e8 CW |
952 | static void |
953 | intel_hdmi_add_properties(struct intel_hdmi *intel_hdmi, struct drm_connector *connector) | |
954 | { | |
3f43c48d | 955 | intel_attach_force_audio_property(connector); |
e953fd7b | 956 | intel_attach_broadcast_rgb_property(connector); |
55b7d6e8 CW |
957 | } |
958 | ||
08d644ad | 959 | void intel_hdmi_init(struct drm_device *dev, int sdvox_reg, enum port port) |
7d57382e EA |
960 | { |
961 | struct drm_i915_private *dev_priv = dev->dev_private; | |
962 | struct drm_connector *connector; | |
21d40d37 | 963 | struct intel_encoder *intel_encoder; |
674e2d08 | 964 | struct intel_connector *intel_connector; |
ea5b213a | 965 | struct intel_hdmi *intel_hdmi; |
7d57382e | 966 | |
ea5b213a CW |
967 | intel_hdmi = kzalloc(sizeof(struct intel_hdmi), GFP_KERNEL); |
968 | if (!intel_hdmi) | |
7d57382e | 969 | return; |
674e2d08 ZW |
970 | |
971 | intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL); | |
972 | if (!intel_connector) { | |
ea5b213a | 973 | kfree(intel_hdmi); |
674e2d08 ZW |
974 | return; |
975 | } | |
976 | ||
ea5b213a | 977 | intel_encoder = &intel_hdmi->base; |
373a3cf7 CW |
978 | drm_encoder_init(dev, &intel_encoder->base, &intel_hdmi_enc_funcs, |
979 | DRM_MODE_ENCODER_TMDS); | |
980 | ||
674e2d08 | 981 | connector = &intel_connector->base; |
7d57382e | 982 | drm_connector_init(dev, connector, &intel_hdmi_connector_funcs, |
8d91104a | 983 | DRM_MODE_CONNECTOR_HDMIA); |
7d57382e EA |
984 | drm_connector_helper_add(connector, &intel_hdmi_connector_helper_funcs); |
985 | ||
21d40d37 | 986 | intel_encoder->type = INTEL_OUTPUT_HDMI; |
7d57382e | 987 | |
eb1f8e4f | 988 | connector->polled = DRM_CONNECTOR_POLL_HPD; |
c3febcc4 | 989 | connector->interlace_allowed = 1; |
7d57382e | 990 | connector->doublescan_allowed = 0; |
27f8227b | 991 | intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2); |
7d57382e | 992 | |
66a9278e DV |
993 | intel_encoder->cloneable = false; |
994 | ||
08d644ad DV |
995 | intel_hdmi->ddi_port = port; |
996 | switch (port) { | |
997 | case PORT_B: | |
f899fc64 | 998 | intel_hdmi->ddc_bus = GMBUS_PORT_DPB; |
b01f2c3a | 999 | dev_priv->hotplug_supported_mask |= HDMIB_HOTPLUG_INT_STATUS; |
08d644ad DV |
1000 | break; |
1001 | case PORT_C: | |
7ceae0a5 | 1002 | intel_hdmi->ddc_bus = GMBUS_PORT_DPC; |
7ceae0a5 | 1003 | dev_priv->hotplug_supported_mask |= HDMIC_HOTPLUG_INT_STATUS; |
08d644ad DV |
1004 | break; |
1005 | case PORT_D: | |
7ceae0a5 | 1006 | intel_hdmi->ddc_bus = GMBUS_PORT_DPD; |
7ceae0a5 | 1007 | dev_priv->hotplug_supported_mask |= HDMID_HOTPLUG_INT_STATUS; |
08d644ad DV |
1008 | break; |
1009 | case PORT_A: | |
1010 | /* Internal port only for eDP. */ | |
1011 | default: | |
6e4c1677 | 1012 | BUG(); |
f8aed700 | 1013 | } |
7d57382e | 1014 | |
ea5b213a | 1015 | intel_hdmi->sdvox_reg = sdvox_reg; |
7d57382e | 1016 | |
64a8fc01 | 1017 | if (!HAS_PCH_SPLIT(dev)) { |
a3da1df7 | 1018 | intel_hdmi->write_infoframe = g4x_write_infoframe; |
687f4d06 | 1019 | intel_hdmi->set_infoframes = g4x_set_infoframes; |
90b107c8 SK |
1020 | } else if (IS_VALLEYVIEW(dev)) { |
1021 | intel_hdmi->write_infoframe = vlv_write_infoframe; | |
687f4d06 | 1022 | intel_hdmi->set_infoframes = vlv_set_infoframes; |
8c5f5f7c | 1023 | } else if (IS_HASWELL(dev)) { |
8c5f5f7c | 1024 | intel_hdmi->write_infoframe = hsw_write_infoframe; |
687f4d06 | 1025 | intel_hdmi->set_infoframes = hsw_set_infoframes; |
fdf1250a PZ |
1026 | } else if (HAS_PCH_IBX(dev)) { |
1027 | intel_hdmi->write_infoframe = ibx_write_infoframe; | |
687f4d06 | 1028 | intel_hdmi->set_infoframes = ibx_set_infoframes; |
fdf1250a PZ |
1029 | } else { |
1030 | intel_hdmi->write_infoframe = cpt_write_infoframe; | |
687f4d06 | 1031 | intel_hdmi->set_infoframes = cpt_set_infoframes; |
64a8fc01 | 1032 | } |
45187ace | 1033 | |
5ab432ef | 1034 | if (IS_HASWELL(dev)) { |
6441ab5f | 1035 | intel_encoder->pre_enable = intel_ddi_pre_enable; |
5ab432ef DV |
1036 | intel_encoder->enable = intel_enable_ddi; |
1037 | intel_encoder->disable = intel_disable_ddi; | |
6441ab5f | 1038 | intel_encoder->post_disable = intel_ddi_post_disable; |
85234cdc | 1039 | intel_encoder->get_hw_state = intel_ddi_get_hw_state; |
5ab432ef DV |
1040 | drm_encoder_helper_add(&intel_encoder->base, |
1041 | &intel_hdmi_helper_funcs_hsw); | |
1042 | } else { | |
1043 | intel_encoder->enable = intel_enable_hdmi; | |
1044 | intel_encoder->disable = intel_disable_hdmi; | |
85234cdc | 1045 | intel_encoder->get_hw_state = intel_hdmi_get_hw_state; |
5ab432ef DV |
1046 | drm_encoder_helper_add(&intel_encoder->base, |
1047 | &intel_hdmi_helper_funcs); | |
1048 | } | |
85234cdc | 1049 | intel_connector->get_hw_state = intel_connector_get_hw_state; |
5ab432ef | 1050 | |
7d57382e | 1051 | |
55b7d6e8 CW |
1052 | intel_hdmi_add_properties(intel_hdmi, connector); |
1053 | ||
df0e9248 | 1054 | intel_connector_attach_encoder(intel_connector, intel_encoder); |
7d57382e EA |
1055 | drm_sysfs_connector_add(connector); |
1056 | ||
1057 | /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written | |
1058 | * 0xd. Failure to do so will result in spurious interrupts being | |
1059 | * generated on the port when a cable is not attached. | |
1060 | */ | |
1061 | if (IS_G4X(dev) && !IS_GM45(dev)) { | |
1062 | u32 temp = I915_READ(PEG_BAND_GAP_DATA); | |
1063 | I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd); | |
1064 | } | |
7d57382e | 1065 | } |