]>
Commit | Line | Data |
---|---|---|
7d57382e EA |
1 | /* |
2 | * Copyright 2006 Dave Airlie <airlied@linux.ie> | |
3 | * Copyright © 2006-2009 Intel Corporation | |
4 | * | |
5 | * Permission is hereby granted, free of charge, to any person obtaining a | |
6 | * copy of this software and associated documentation files (the "Software"), | |
7 | * to deal in the Software without restriction, including without limitation | |
8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
9 | * and/or sell copies of the Software, and to permit persons to whom the | |
10 | * Software is furnished to do so, subject to the following conditions: | |
11 | * | |
12 | * The above copyright notice and this permission notice (including the next | |
13 | * paragraph) shall be included in all copies or substantial portions of the | |
14 | * Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
21 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
22 | * DEALINGS IN THE SOFTWARE. | |
23 | * | |
24 | * Authors: | |
25 | * Eric Anholt <eric@anholt.net> | |
26 | * Jesse Barnes <jesse.barnes@intel.com> | |
27 | */ | |
28 | ||
29 | #include <linux/i2c.h> | |
5a0e3ad6 | 30 | #include <linux/slab.h> |
7d57382e EA |
31 | #include <linux/delay.h> |
32 | #include "drmP.h" | |
33 | #include "drm.h" | |
34 | #include "drm_crtc.h" | |
aa93d632 | 35 | #include "drm_edid.h" |
7d57382e EA |
36 | #include "intel_drv.h" |
37 | #include "i915_drm.h" | |
38 | #include "i915_drv.h" | |
39 | ||
ea5b213a CW |
40 | struct intel_hdmi { |
41 | struct intel_encoder base; | |
7d57382e | 42 | u32 sdvox_reg; |
f899fc64 | 43 | int ddc_bus; |
e953fd7b | 44 | uint32_t color_range; |
9dff6af8 | 45 | bool has_hdmi_sink; |
2e3d6006 | 46 | bool has_audio; |
b1d7e4b4 | 47 | enum hdmi_force_audio force_audio; |
45187ace JB |
48 | void (*write_infoframe)(struct drm_encoder *encoder, |
49 | struct dip_infoframe *frame); | |
7d57382e EA |
50 | }; |
51 | ||
ea5b213a CW |
52 | static struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder) |
53 | { | |
4ef69c7a | 54 | return container_of(encoder, struct intel_hdmi, base.base); |
ea5b213a CW |
55 | } |
56 | ||
df0e9248 CW |
57 | static struct intel_hdmi *intel_attached_hdmi(struct drm_connector *connector) |
58 | { | |
59 | return container_of(intel_attached_encoder(connector), | |
60 | struct intel_hdmi, base); | |
61 | } | |
62 | ||
45187ace | 63 | void intel_dip_infoframe_csum(struct dip_infoframe *frame) |
3c17fe4b | 64 | { |
45187ace | 65 | uint8_t *data = (uint8_t *)frame; |
3c17fe4b DH |
66 | uint8_t sum = 0; |
67 | unsigned i; | |
68 | ||
45187ace JB |
69 | frame->checksum = 0; |
70 | frame->ecc = 0; | |
3c17fe4b | 71 | |
64a8fc01 | 72 | for (i = 0; i < frame->len + DIP_HEADER_SIZE; i++) |
3c17fe4b DH |
73 | sum += data[i]; |
74 | ||
45187ace | 75 | frame->checksum = 0x100 - sum; |
3c17fe4b DH |
76 | } |
77 | ||
45187ace | 78 | static u32 intel_infoframe_index(struct dip_infoframe *frame) |
3c17fe4b | 79 | { |
45187ace JB |
80 | u32 flags = 0; |
81 | ||
82 | switch (frame->type) { | |
83 | case DIP_TYPE_AVI: | |
84 | flags |= VIDEO_DIP_SELECT_AVI; | |
85 | break; | |
86 | case DIP_TYPE_SPD: | |
87 | flags |= VIDEO_DIP_SELECT_SPD; | |
88 | break; | |
89 | default: | |
90 | DRM_DEBUG_DRIVER("unknown info frame type %d\n", frame->type); | |
91 | break; | |
92 | } | |
93 | ||
94 | return flags; | |
95 | } | |
96 | ||
97 | static u32 intel_infoframe_flags(struct dip_infoframe *frame) | |
98 | { | |
99 | u32 flags = 0; | |
100 | ||
101 | switch (frame->type) { | |
102 | case DIP_TYPE_AVI: | |
103 | flags |= VIDEO_DIP_ENABLE_AVI | VIDEO_DIP_FREQ_VSYNC; | |
104 | break; | |
105 | case DIP_TYPE_SPD: | |
64a8fc01 | 106 | flags |= VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_FREQ_VSYNC; |
45187ace JB |
107 | break; |
108 | default: | |
109 | DRM_DEBUG_DRIVER("unknown info frame type %d\n", frame->type); | |
110 | break; | |
111 | } | |
112 | ||
113 | return flags; | |
114 | } | |
115 | ||
116 | static void i9xx_write_infoframe(struct drm_encoder *encoder, | |
117 | struct dip_infoframe *frame) | |
118 | { | |
119 | uint32_t *data = (uint32_t *)frame; | |
3c17fe4b DH |
120 | struct drm_device *dev = encoder->dev; |
121 | struct drm_i915_private *dev_priv = dev->dev_private; | |
122 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); | |
22509ec8 | 123 | u32 val = I915_READ(VIDEO_DIP_CTL); |
45187ace | 124 | unsigned i, len = DIP_HEADER_SIZE + frame->len; |
3c17fe4b | 125 | |
3c17fe4b DH |
126 | |
127 | /* XXX first guess at handling video port, is this corrent? */ | |
3e6e6395 | 128 | val &= ~VIDEO_DIP_PORT_MASK; |
3c17fe4b | 129 | if (intel_hdmi->sdvox_reg == SDVOB) |
22509ec8 | 130 | val |= VIDEO_DIP_PORT_B; |
3c17fe4b | 131 | else if (intel_hdmi->sdvox_reg == SDVOC) |
22509ec8 | 132 | val |= VIDEO_DIP_PORT_C; |
3c17fe4b DH |
133 | else |
134 | return; | |
135 | ||
1d4f85ac | 136 | val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ |
22509ec8 PZ |
137 | val |= intel_infoframe_index(frame); |
138 | ||
139 | val |= VIDEO_DIP_ENABLE; | |
45187ace | 140 | |
22509ec8 | 141 | I915_WRITE(VIDEO_DIP_CTL, val); |
3c17fe4b | 142 | |
45187ace | 143 | for (i = 0; i < len; i += 4) { |
3c17fe4b DH |
144 | I915_WRITE(VIDEO_DIP_DATA, *data); |
145 | data++; | |
146 | } | |
147 | ||
22509ec8 | 148 | val |= intel_infoframe_flags(frame); |
45187ace | 149 | |
22509ec8 | 150 | I915_WRITE(VIDEO_DIP_CTL, val); |
3c17fe4b DH |
151 | } |
152 | ||
45187ace JB |
153 | static void ironlake_write_infoframe(struct drm_encoder *encoder, |
154 | struct dip_infoframe *frame) | |
b055c8f3 | 155 | { |
45187ace | 156 | uint32_t *data = (uint32_t *)frame; |
b055c8f3 JB |
157 | struct drm_device *dev = encoder->dev; |
158 | struct drm_i915_private *dev_priv = dev->dev_private; | |
b055c8f3 JB |
159 | struct drm_crtc *crtc = encoder->crtc; |
160 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
161 | int reg = TVIDEO_DIP_CTL(intel_crtc->pipe); | |
45187ace | 162 | unsigned i, len = DIP_HEADER_SIZE + frame->len; |
22509ec8 | 163 | u32 val = I915_READ(reg); |
b055c8f3 JB |
164 | |
165 | intel_wait_for_vblank(dev, intel_crtc->pipe); | |
166 | ||
64a8fc01 | 167 | val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ |
22509ec8 | 168 | val |= intel_infoframe_index(frame); |
45187ace | 169 | |
22509ec8 PZ |
170 | val |= VIDEO_DIP_ENABLE; |
171 | ||
172 | I915_WRITE(reg, val); | |
45187ace JB |
173 | |
174 | for (i = 0; i < len; i += 4) { | |
b055c8f3 JB |
175 | I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data); |
176 | data++; | |
177 | } | |
178 | ||
22509ec8 | 179 | val |= intel_infoframe_flags(frame); |
45187ace | 180 | |
22509ec8 | 181 | I915_WRITE(reg, val); |
45187ace | 182 | } |
90b107c8 SK |
183 | |
184 | static void vlv_write_infoframe(struct drm_encoder *encoder, | |
185 | struct dip_infoframe *frame) | |
186 | { | |
187 | uint32_t *data = (uint32_t *)frame; | |
188 | struct drm_device *dev = encoder->dev; | |
189 | struct drm_i915_private *dev_priv = dev->dev_private; | |
190 | struct drm_crtc *crtc = encoder->crtc; | |
191 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
192 | int reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe); | |
193 | unsigned i, len = DIP_HEADER_SIZE + frame->len; | |
22509ec8 | 194 | u32 val = I915_READ(reg); |
90b107c8 SK |
195 | |
196 | intel_wait_for_vblank(dev, intel_crtc->pipe); | |
197 | ||
90b107c8 | 198 | val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ |
22509ec8 PZ |
199 | val |= intel_infoframe_index(frame); |
200 | ||
201 | val |= VIDEO_DIP_ENABLE; | |
90b107c8 | 202 | |
22509ec8 | 203 | I915_WRITE(reg, val); |
90b107c8 SK |
204 | |
205 | for (i = 0; i < len; i += 4) { | |
206 | I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), *data); | |
207 | data++; | |
208 | } | |
209 | ||
22509ec8 | 210 | val |= intel_infoframe_flags(frame); |
90b107c8 | 211 | |
22509ec8 | 212 | I915_WRITE(reg, val); |
90b107c8 SK |
213 | } |
214 | ||
45187ace JB |
215 | static void intel_set_infoframe(struct drm_encoder *encoder, |
216 | struct dip_infoframe *frame) | |
217 | { | |
218 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); | |
219 | ||
220 | if (!intel_hdmi->has_hdmi_sink) | |
221 | return; | |
222 | ||
223 | intel_dip_infoframe_csum(frame); | |
224 | intel_hdmi->write_infoframe(encoder, frame); | |
225 | } | |
226 | ||
c846b619 PZ |
227 | static void intel_hdmi_set_avi_infoframe(struct drm_encoder *encoder, |
228 | struct drm_display_mode *adjusted_mode) | |
45187ace JB |
229 | { |
230 | struct dip_infoframe avi_if = { | |
231 | .type = DIP_TYPE_AVI, | |
232 | .ver = DIP_VERSION_AVI, | |
233 | .len = DIP_LEN_AVI, | |
234 | }; | |
235 | ||
c846b619 PZ |
236 | if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK) |
237 | avi_if.body.avi.YQ_CN_PR |= DIP_AVI_PR_2; | |
238 | ||
45187ace | 239 | intel_set_infoframe(encoder, &avi_if); |
b055c8f3 JB |
240 | } |
241 | ||
c0864cb3 JB |
242 | static void intel_hdmi_set_spd_infoframe(struct drm_encoder *encoder) |
243 | { | |
244 | struct dip_infoframe spd_if; | |
245 | ||
246 | memset(&spd_if, 0, sizeof(spd_if)); | |
247 | spd_if.type = DIP_TYPE_SPD; | |
248 | spd_if.ver = DIP_VERSION_SPD; | |
249 | spd_if.len = DIP_LEN_SPD; | |
250 | strcpy(spd_if.body.spd.vn, "Intel"); | |
251 | strcpy(spd_if.body.spd.pd, "Integrated gfx"); | |
252 | spd_if.body.spd.sdi = DIP_SPD_PC; | |
253 | ||
254 | intel_set_infoframe(encoder, &spd_if); | |
255 | } | |
256 | ||
7d57382e EA |
257 | static void intel_hdmi_mode_set(struct drm_encoder *encoder, |
258 | struct drm_display_mode *mode, | |
259 | struct drm_display_mode *adjusted_mode) | |
260 | { | |
261 | struct drm_device *dev = encoder->dev; | |
262 | struct drm_i915_private *dev_priv = dev->dev_private; | |
263 | struct drm_crtc *crtc = encoder->crtc; | |
264 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
ea5b213a | 265 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); |
7d57382e EA |
266 | u32 sdvox; |
267 | ||
b599c0bc | 268 | sdvox = SDVO_ENCODING_HDMI | SDVO_BORDER_ENABLE; |
5d4fac97 JB |
269 | if (!HAS_PCH_SPLIT(dev)) |
270 | sdvox |= intel_hdmi->color_range; | |
b599c0bc AJ |
271 | if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) |
272 | sdvox |= SDVO_VSYNC_ACTIVE_HIGH; | |
273 | if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) | |
274 | sdvox |= SDVO_HSYNC_ACTIVE_HIGH; | |
7d57382e | 275 | |
020f6704 JB |
276 | if (intel_crtc->bpp > 24) |
277 | sdvox |= COLOR_FORMAT_12bpc; | |
278 | else | |
279 | sdvox |= COLOR_FORMAT_8bpc; | |
280 | ||
2e3d6006 ZW |
281 | /* Required on CPT */ |
282 | if (intel_hdmi->has_hdmi_sink && HAS_PCH_CPT(dev)) | |
283 | sdvox |= HDMI_MODE_SELECT; | |
284 | ||
3c17fe4b | 285 | if (intel_hdmi->has_audio) { |
e0dac65e WF |
286 | DRM_DEBUG_DRIVER("Enabling HDMI audio on pipe %c\n", |
287 | pipe_name(intel_crtc->pipe)); | |
7d57382e | 288 | sdvox |= SDVO_AUDIO_ENABLE; |
3c17fe4b | 289 | sdvox |= SDVO_NULL_PACKETS_DURING_VSYNC; |
e0dac65e | 290 | intel_write_eld(encoder, adjusted_mode); |
3c17fe4b | 291 | } |
7d57382e | 292 | |
75770564 JB |
293 | if (HAS_PCH_CPT(dev)) |
294 | sdvox |= PORT_TRANS_SEL_CPT(intel_crtc->pipe); | |
295 | else if (intel_crtc->pipe == 1) | |
296 | sdvox |= SDVO_PIPE_B_SELECT; | |
7d57382e | 297 | |
ea5b213a CW |
298 | I915_WRITE(intel_hdmi->sdvox_reg, sdvox); |
299 | POSTING_READ(intel_hdmi->sdvox_reg); | |
3c17fe4b | 300 | |
c846b619 | 301 | intel_hdmi_set_avi_infoframe(encoder, adjusted_mode); |
c0864cb3 | 302 | intel_hdmi_set_spd_infoframe(encoder); |
7d57382e EA |
303 | } |
304 | ||
305 | static void intel_hdmi_dpms(struct drm_encoder *encoder, int mode) | |
306 | { | |
307 | struct drm_device *dev = encoder->dev; | |
308 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ea5b213a | 309 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); |
7d57382e | 310 | u32 temp; |
2deed761 WF |
311 | u32 enable_bits = SDVO_ENABLE; |
312 | ||
313 | if (intel_hdmi->has_audio) | |
314 | enable_bits |= SDVO_AUDIO_ENABLE; | |
7d57382e | 315 | |
ea5b213a | 316 | temp = I915_READ(intel_hdmi->sdvox_reg); |
d8a2d0e0 ZW |
317 | |
318 | /* HW workaround, need to toggle enable bit off and on for 12bpc, but | |
319 | * we do this anyway which shows more stable in testing. | |
320 | */ | |
c619eed4 | 321 | if (HAS_PCH_SPLIT(dev)) { |
ea5b213a CW |
322 | I915_WRITE(intel_hdmi->sdvox_reg, temp & ~SDVO_ENABLE); |
323 | POSTING_READ(intel_hdmi->sdvox_reg); | |
d8a2d0e0 ZW |
324 | } |
325 | ||
326 | if (mode != DRM_MODE_DPMS_ON) { | |
2deed761 | 327 | temp &= ~enable_bits; |
7d57382e | 328 | } else { |
2deed761 | 329 | temp |= enable_bits; |
7d57382e | 330 | } |
d8a2d0e0 | 331 | |
ea5b213a CW |
332 | I915_WRITE(intel_hdmi->sdvox_reg, temp); |
333 | POSTING_READ(intel_hdmi->sdvox_reg); | |
d8a2d0e0 ZW |
334 | |
335 | /* HW workaround, need to write this twice for issue that may result | |
336 | * in first write getting masked. | |
337 | */ | |
c619eed4 | 338 | if (HAS_PCH_SPLIT(dev)) { |
ea5b213a CW |
339 | I915_WRITE(intel_hdmi->sdvox_reg, temp); |
340 | POSTING_READ(intel_hdmi->sdvox_reg); | |
d8a2d0e0 | 341 | } |
7d57382e EA |
342 | } |
343 | ||
7d57382e EA |
344 | static int intel_hdmi_mode_valid(struct drm_connector *connector, |
345 | struct drm_display_mode *mode) | |
346 | { | |
347 | if (mode->clock > 165000) | |
348 | return MODE_CLOCK_HIGH; | |
349 | if (mode->clock < 20000) | |
5cbba41d | 350 | return MODE_CLOCK_LOW; |
7d57382e EA |
351 | |
352 | if (mode->flags & DRM_MODE_FLAG_DBLSCAN) | |
353 | return MODE_NO_DBLESCAN; | |
354 | ||
355 | return MODE_OK; | |
356 | } | |
357 | ||
358 | static bool intel_hdmi_mode_fixup(struct drm_encoder *encoder, | |
359 | struct drm_display_mode *mode, | |
360 | struct drm_display_mode *adjusted_mode) | |
361 | { | |
362 | return true; | |
363 | } | |
364 | ||
aa93d632 | 365 | static enum drm_connector_status |
930a9e28 | 366 | intel_hdmi_detect(struct drm_connector *connector, bool force) |
9dff6af8 | 367 | { |
df0e9248 | 368 | struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); |
f899fc64 CW |
369 | struct drm_i915_private *dev_priv = connector->dev->dev_private; |
370 | struct edid *edid; | |
aa93d632 | 371 | enum drm_connector_status status = connector_status_disconnected; |
9dff6af8 | 372 | |
ea5b213a | 373 | intel_hdmi->has_hdmi_sink = false; |
2e3d6006 | 374 | intel_hdmi->has_audio = false; |
f899fc64 | 375 | edid = drm_get_edid(connector, |
3bd7d909 DK |
376 | intel_gmbus_get_adapter(dev_priv, |
377 | intel_hdmi->ddc_bus)); | |
2ded9e27 | 378 | |
aa93d632 | 379 | if (edid) { |
be9f1c4f | 380 | if (edid->input & DRM_EDID_INPUT_DIGITAL) { |
aa93d632 | 381 | status = connector_status_connected; |
b1d7e4b4 WF |
382 | if (intel_hdmi->force_audio != HDMI_AUDIO_OFF_DVI) |
383 | intel_hdmi->has_hdmi_sink = | |
384 | drm_detect_hdmi_monitor(edid); | |
2e3d6006 | 385 | intel_hdmi->has_audio = drm_detect_monitor_audio(edid); |
aa93d632 | 386 | } |
674e2d08 | 387 | connector->display_info.raw_edid = NULL; |
aa93d632 | 388 | kfree(edid); |
9dff6af8 | 389 | } |
30ad48b7 | 390 | |
55b7d6e8 | 391 | if (status == connector_status_connected) { |
b1d7e4b4 WF |
392 | if (intel_hdmi->force_audio != HDMI_AUDIO_AUTO) |
393 | intel_hdmi->has_audio = | |
394 | (intel_hdmi->force_audio == HDMI_AUDIO_ON); | |
55b7d6e8 CW |
395 | } |
396 | ||
2ded9e27 | 397 | return status; |
7d57382e EA |
398 | } |
399 | ||
400 | static int intel_hdmi_get_modes(struct drm_connector *connector) | |
401 | { | |
df0e9248 | 402 | struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); |
f899fc64 | 403 | struct drm_i915_private *dev_priv = connector->dev->dev_private; |
7d57382e EA |
404 | |
405 | /* We should parse the EDID data and find out if it's an HDMI sink so | |
406 | * we can send audio to it. | |
407 | */ | |
408 | ||
f899fc64 | 409 | return intel_ddc_get_modes(connector, |
3bd7d909 DK |
410 | intel_gmbus_get_adapter(dev_priv, |
411 | intel_hdmi->ddc_bus)); | |
7d57382e EA |
412 | } |
413 | ||
1aad7ac0 CW |
414 | static bool |
415 | intel_hdmi_detect_audio(struct drm_connector *connector) | |
416 | { | |
417 | struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); | |
418 | struct drm_i915_private *dev_priv = connector->dev->dev_private; | |
419 | struct edid *edid; | |
420 | bool has_audio = false; | |
421 | ||
422 | edid = drm_get_edid(connector, | |
3bd7d909 DK |
423 | intel_gmbus_get_adapter(dev_priv, |
424 | intel_hdmi->ddc_bus)); | |
1aad7ac0 CW |
425 | if (edid) { |
426 | if (edid->input & DRM_EDID_INPUT_DIGITAL) | |
427 | has_audio = drm_detect_monitor_audio(edid); | |
428 | ||
429 | connector->display_info.raw_edid = NULL; | |
430 | kfree(edid); | |
431 | } | |
432 | ||
433 | return has_audio; | |
434 | } | |
435 | ||
55b7d6e8 CW |
436 | static int |
437 | intel_hdmi_set_property(struct drm_connector *connector, | |
438 | struct drm_property *property, | |
439 | uint64_t val) | |
440 | { | |
441 | struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); | |
e953fd7b | 442 | struct drm_i915_private *dev_priv = connector->dev->dev_private; |
55b7d6e8 CW |
443 | int ret; |
444 | ||
445 | ret = drm_connector_property_set_value(connector, property, val); | |
446 | if (ret) | |
447 | return ret; | |
448 | ||
3f43c48d | 449 | if (property == dev_priv->force_audio_property) { |
b1d7e4b4 | 450 | enum hdmi_force_audio i = val; |
1aad7ac0 CW |
451 | bool has_audio; |
452 | ||
453 | if (i == intel_hdmi->force_audio) | |
55b7d6e8 CW |
454 | return 0; |
455 | ||
1aad7ac0 | 456 | intel_hdmi->force_audio = i; |
55b7d6e8 | 457 | |
b1d7e4b4 | 458 | if (i == HDMI_AUDIO_AUTO) |
1aad7ac0 CW |
459 | has_audio = intel_hdmi_detect_audio(connector); |
460 | else | |
b1d7e4b4 | 461 | has_audio = (i == HDMI_AUDIO_ON); |
1aad7ac0 | 462 | |
b1d7e4b4 WF |
463 | if (i == HDMI_AUDIO_OFF_DVI) |
464 | intel_hdmi->has_hdmi_sink = 0; | |
55b7d6e8 | 465 | |
1aad7ac0 | 466 | intel_hdmi->has_audio = has_audio; |
55b7d6e8 CW |
467 | goto done; |
468 | } | |
469 | ||
e953fd7b CW |
470 | if (property == dev_priv->broadcast_rgb_property) { |
471 | if (val == !!intel_hdmi->color_range) | |
472 | return 0; | |
473 | ||
474 | intel_hdmi->color_range = val ? SDVO_COLOR_RANGE_16_235 : 0; | |
475 | goto done; | |
476 | } | |
477 | ||
55b7d6e8 CW |
478 | return -EINVAL; |
479 | ||
480 | done: | |
481 | if (intel_hdmi->base.base.crtc) { | |
482 | struct drm_crtc *crtc = intel_hdmi->base.base.crtc; | |
483 | drm_crtc_helper_set_mode(crtc, &crtc->mode, | |
484 | crtc->x, crtc->y, | |
485 | crtc->fb); | |
486 | } | |
487 | ||
488 | return 0; | |
489 | } | |
490 | ||
7d57382e EA |
491 | static void intel_hdmi_destroy(struct drm_connector *connector) |
492 | { | |
7d57382e EA |
493 | drm_sysfs_connector_remove(connector); |
494 | drm_connector_cleanup(connector); | |
674e2d08 | 495 | kfree(connector); |
7d57382e EA |
496 | } |
497 | ||
498 | static const struct drm_encoder_helper_funcs intel_hdmi_helper_funcs = { | |
499 | .dpms = intel_hdmi_dpms, | |
500 | .mode_fixup = intel_hdmi_mode_fixup, | |
501 | .prepare = intel_encoder_prepare, | |
502 | .mode_set = intel_hdmi_mode_set, | |
503 | .commit = intel_encoder_commit, | |
504 | }; | |
505 | ||
506 | static const struct drm_connector_funcs intel_hdmi_connector_funcs = { | |
c9fb15f6 | 507 | .dpms = drm_helper_connector_dpms, |
7d57382e EA |
508 | .detect = intel_hdmi_detect, |
509 | .fill_modes = drm_helper_probe_single_connector_modes, | |
55b7d6e8 | 510 | .set_property = intel_hdmi_set_property, |
7d57382e EA |
511 | .destroy = intel_hdmi_destroy, |
512 | }; | |
513 | ||
514 | static const struct drm_connector_helper_funcs intel_hdmi_connector_helper_funcs = { | |
515 | .get_modes = intel_hdmi_get_modes, | |
516 | .mode_valid = intel_hdmi_mode_valid, | |
df0e9248 | 517 | .best_encoder = intel_best_encoder, |
7d57382e EA |
518 | }; |
519 | ||
7d57382e | 520 | static const struct drm_encoder_funcs intel_hdmi_enc_funcs = { |
ea5b213a | 521 | .destroy = intel_encoder_destroy, |
7d57382e EA |
522 | }; |
523 | ||
55b7d6e8 CW |
524 | static void |
525 | intel_hdmi_add_properties(struct intel_hdmi *intel_hdmi, struct drm_connector *connector) | |
526 | { | |
3f43c48d | 527 | intel_attach_force_audio_property(connector); |
e953fd7b | 528 | intel_attach_broadcast_rgb_property(connector); |
55b7d6e8 CW |
529 | } |
530 | ||
7d57382e EA |
531 | void intel_hdmi_init(struct drm_device *dev, int sdvox_reg) |
532 | { | |
533 | struct drm_i915_private *dev_priv = dev->dev_private; | |
534 | struct drm_connector *connector; | |
21d40d37 | 535 | struct intel_encoder *intel_encoder; |
674e2d08 | 536 | struct intel_connector *intel_connector; |
ea5b213a | 537 | struct intel_hdmi *intel_hdmi; |
64a8fc01 | 538 | int i; |
7d57382e | 539 | |
ea5b213a CW |
540 | intel_hdmi = kzalloc(sizeof(struct intel_hdmi), GFP_KERNEL); |
541 | if (!intel_hdmi) | |
7d57382e | 542 | return; |
674e2d08 ZW |
543 | |
544 | intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL); | |
545 | if (!intel_connector) { | |
ea5b213a | 546 | kfree(intel_hdmi); |
674e2d08 ZW |
547 | return; |
548 | } | |
549 | ||
ea5b213a | 550 | intel_encoder = &intel_hdmi->base; |
373a3cf7 CW |
551 | drm_encoder_init(dev, &intel_encoder->base, &intel_hdmi_enc_funcs, |
552 | DRM_MODE_ENCODER_TMDS); | |
553 | ||
674e2d08 | 554 | connector = &intel_connector->base; |
7d57382e | 555 | drm_connector_init(dev, connector, &intel_hdmi_connector_funcs, |
8d91104a | 556 | DRM_MODE_CONNECTOR_HDMIA); |
7d57382e EA |
557 | drm_connector_helper_add(connector, &intel_hdmi_connector_helper_funcs); |
558 | ||
21d40d37 | 559 | intel_encoder->type = INTEL_OUTPUT_HDMI; |
7d57382e | 560 | |
eb1f8e4f | 561 | connector->polled = DRM_CONNECTOR_POLL_HPD; |
c3febcc4 | 562 | connector->interlace_allowed = 1; |
7d57382e | 563 | connector->doublescan_allowed = 0; |
27f8227b | 564 | intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2); |
7d57382e EA |
565 | |
566 | /* Set up the DDC bus. */ | |
f8aed700 | 567 | if (sdvox_reg == SDVOB) { |
21d40d37 | 568 | intel_encoder->clone_mask = (1 << INTEL_HDMIB_CLONE_BIT); |
f899fc64 | 569 | intel_hdmi->ddc_bus = GMBUS_PORT_DPB; |
b01f2c3a | 570 | dev_priv->hotplug_supported_mask |= HDMIB_HOTPLUG_INT_STATUS; |
f8aed700 | 571 | } else if (sdvox_reg == SDVOC) { |
21d40d37 | 572 | intel_encoder->clone_mask = (1 << INTEL_HDMIC_CLONE_BIT); |
f899fc64 | 573 | intel_hdmi->ddc_bus = GMBUS_PORT_DPC; |
b01f2c3a | 574 | dev_priv->hotplug_supported_mask |= HDMIC_HOTPLUG_INT_STATUS; |
f8aed700 | 575 | } else if (sdvox_reg == HDMIB) { |
21d40d37 | 576 | intel_encoder->clone_mask = (1 << INTEL_HDMID_CLONE_BIT); |
f899fc64 | 577 | intel_hdmi->ddc_bus = GMBUS_PORT_DPB; |
b01f2c3a | 578 | dev_priv->hotplug_supported_mask |= HDMIB_HOTPLUG_INT_STATUS; |
f8aed700 | 579 | } else if (sdvox_reg == HDMIC) { |
21d40d37 | 580 | intel_encoder->clone_mask = (1 << INTEL_HDMIE_CLONE_BIT); |
f899fc64 | 581 | intel_hdmi->ddc_bus = GMBUS_PORT_DPC; |
b01f2c3a | 582 | dev_priv->hotplug_supported_mask |= HDMIC_HOTPLUG_INT_STATUS; |
f8aed700 | 583 | } else if (sdvox_reg == HDMID) { |
21d40d37 | 584 | intel_encoder->clone_mask = (1 << INTEL_HDMIF_CLONE_BIT); |
f899fc64 | 585 | intel_hdmi->ddc_bus = GMBUS_PORT_DPD; |
b01f2c3a | 586 | dev_priv->hotplug_supported_mask |= HDMID_HOTPLUG_INT_STATUS; |
f8aed700 | 587 | } |
7d57382e | 588 | |
ea5b213a | 589 | intel_hdmi->sdvox_reg = sdvox_reg; |
7d57382e | 590 | |
64a8fc01 | 591 | if (!HAS_PCH_SPLIT(dev)) { |
45187ace | 592 | intel_hdmi->write_infoframe = i9xx_write_infoframe; |
64a8fc01 | 593 | I915_WRITE(VIDEO_DIP_CTL, 0); |
90b107c8 SK |
594 | } else if (IS_VALLEYVIEW(dev)) { |
595 | intel_hdmi->write_infoframe = vlv_write_infoframe; | |
596 | for_each_pipe(i) | |
597 | I915_WRITE(VLV_TVIDEO_DIP_CTL(i), 0); | |
598 | } else { | |
45187ace | 599 | intel_hdmi->write_infoframe = ironlake_write_infoframe; |
64a8fc01 JB |
600 | for_each_pipe(i) |
601 | I915_WRITE(TVIDEO_DIP_CTL(i), 0); | |
602 | } | |
45187ace | 603 | |
4ef69c7a | 604 | drm_encoder_helper_add(&intel_encoder->base, &intel_hdmi_helper_funcs); |
7d57382e | 605 | |
55b7d6e8 CW |
606 | intel_hdmi_add_properties(intel_hdmi, connector); |
607 | ||
df0e9248 | 608 | intel_connector_attach_encoder(intel_connector, intel_encoder); |
7d57382e EA |
609 | drm_sysfs_connector_add(connector); |
610 | ||
611 | /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written | |
612 | * 0xd. Failure to do so will result in spurious interrupts being | |
613 | * generated on the port when a cable is not attached. | |
614 | */ | |
615 | if (IS_G4X(dev) && !IS_GM45(dev)) { | |
616 | u32 temp = I915_READ(PEG_BAND_GAP_DATA); | |
617 | I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd); | |
618 | } | |
7d57382e | 619 | } |