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7d57382e EA |
1 | /* |
2 | * Copyright 2006 Dave Airlie <airlied@linux.ie> | |
3 | * Copyright © 2006-2009 Intel Corporation | |
4 | * | |
5 | * Permission is hereby granted, free of charge, to any person obtaining a | |
6 | * copy of this software and associated documentation files (the "Software"), | |
7 | * to deal in the Software without restriction, including without limitation | |
8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
9 | * and/or sell copies of the Software, and to permit persons to whom the | |
10 | * Software is furnished to do so, subject to the following conditions: | |
11 | * | |
12 | * The above copyright notice and this permission notice (including the next | |
13 | * paragraph) shall be included in all copies or substantial portions of the | |
14 | * Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
21 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
22 | * DEALINGS IN THE SOFTWARE. | |
23 | * | |
24 | * Authors: | |
25 | * Eric Anholt <eric@anholt.net> | |
26 | * Jesse Barnes <jesse.barnes@intel.com> | |
27 | */ | |
28 | ||
29 | #include <linux/i2c.h> | |
5a0e3ad6 | 30 | #include <linux/slab.h> |
7d57382e EA |
31 | #include <linux/delay.h> |
32 | #include "drmP.h" | |
7d57382e | 33 | #include "drm_crtc.h" |
aa93d632 | 34 | #include "drm_edid.h" |
7d57382e EA |
35 | #include "intel_drv.h" |
36 | #include "i915_drm.h" | |
37 | #include "i915_drv.h" | |
38 | ||
afba0188 DV |
39 | static void |
40 | assert_hdmi_port_disabled(struct intel_hdmi *intel_hdmi) | |
41 | { | |
42 | struct drm_device *dev = intel_hdmi->base.base.dev; | |
43 | struct drm_i915_private *dev_priv = dev->dev_private; | |
44 | uint32_t enabled_bits; | |
45 | ||
46 | enabled_bits = IS_HASWELL(dev) ? DDI_BUF_CTL_ENABLE : SDVO_ENABLE; | |
47 | ||
48 | WARN(I915_READ(intel_hdmi->sdvox_reg) & enabled_bits, | |
49 | "HDMI port enabled, expecting disabled\n"); | |
50 | } | |
51 | ||
f5bbfca3 | 52 | struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder) |
ea5b213a | 53 | { |
4ef69c7a | 54 | return container_of(encoder, struct intel_hdmi, base.base); |
ea5b213a CW |
55 | } |
56 | ||
df0e9248 CW |
57 | static struct intel_hdmi *intel_attached_hdmi(struct drm_connector *connector) |
58 | { | |
59 | return container_of(intel_attached_encoder(connector), | |
60 | struct intel_hdmi, base); | |
61 | } | |
62 | ||
45187ace | 63 | void intel_dip_infoframe_csum(struct dip_infoframe *frame) |
3c17fe4b | 64 | { |
45187ace | 65 | uint8_t *data = (uint8_t *)frame; |
3c17fe4b DH |
66 | uint8_t sum = 0; |
67 | unsigned i; | |
68 | ||
45187ace JB |
69 | frame->checksum = 0; |
70 | frame->ecc = 0; | |
3c17fe4b | 71 | |
64a8fc01 | 72 | for (i = 0; i < frame->len + DIP_HEADER_SIZE; i++) |
3c17fe4b DH |
73 | sum += data[i]; |
74 | ||
45187ace | 75 | frame->checksum = 0x100 - sum; |
3c17fe4b DH |
76 | } |
77 | ||
bc2481f3 | 78 | static u32 g4x_infoframe_index(struct dip_infoframe *frame) |
3c17fe4b | 79 | { |
45187ace JB |
80 | switch (frame->type) { |
81 | case DIP_TYPE_AVI: | |
ed517fbb | 82 | return VIDEO_DIP_SELECT_AVI; |
45187ace | 83 | case DIP_TYPE_SPD: |
ed517fbb | 84 | return VIDEO_DIP_SELECT_SPD; |
45187ace JB |
85 | default: |
86 | DRM_DEBUG_DRIVER("unknown info frame type %d\n", frame->type); | |
ed517fbb | 87 | return 0; |
45187ace | 88 | } |
45187ace JB |
89 | } |
90 | ||
bc2481f3 | 91 | static u32 g4x_infoframe_enable(struct dip_infoframe *frame) |
45187ace | 92 | { |
45187ace JB |
93 | switch (frame->type) { |
94 | case DIP_TYPE_AVI: | |
ed517fbb | 95 | return VIDEO_DIP_ENABLE_AVI; |
45187ace | 96 | case DIP_TYPE_SPD: |
ed517fbb | 97 | return VIDEO_DIP_ENABLE_SPD; |
fa193ff7 PZ |
98 | default: |
99 | DRM_DEBUG_DRIVER("unknown info frame type %d\n", frame->type); | |
ed517fbb | 100 | return 0; |
fa193ff7 | 101 | } |
fa193ff7 PZ |
102 | } |
103 | ||
2da8af54 PZ |
104 | static u32 hsw_infoframe_enable(struct dip_infoframe *frame) |
105 | { | |
106 | switch (frame->type) { | |
107 | case DIP_TYPE_AVI: | |
108 | return VIDEO_DIP_ENABLE_AVI_HSW; | |
109 | case DIP_TYPE_SPD: | |
110 | return VIDEO_DIP_ENABLE_SPD_HSW; | |
111 | default: | |
112 | DRM_DEBUG_DRIVER("unknown info frame type %d\n", frame->type); | |
113 | return 0; | |
114 | } | |
115 | } | |
116 | ||
117 | static u32 hsw_infoframe_data_reg(struct dip_infoframe *frame, enum pipe pipe) | |
118 | { | |
119 | switch (frame->type) { | |
120 | case DIP_TYPE_AVI: | |
121 | return HSW_TVIDEO_DIP_AVI_DATA(pipe); | |
122 | case DIP_TYPE_SPD: | |
123 | return HSW_TVIDEO_DIP_SPD_DATA(pipe); | |
124 | default: | |
125 | DRM_DEBUG_DRIVER("unknown info frame type %d\n", frame->type); | |
126 | return 0; | |
127 | } | |
128 | } | |
129 | ||
a3da1df7 DV |
130 | static void g4x_write_infoframe(struct drm_encoder *encoder, |
131 | struct dip_infoframe *frame) | |
45187ace JB |
132 | { |
133 | uint32_t *data = (uint32_t *)frame; | |
3c17fe4b DH |
134 | struct drm_device *dev = encoder->dev; |
135 | struct drm_i915_private *dev_priv = dev->dev_private; | |
22509ec8 | 136 | u32 val = I915_READ(VIDEO_DIP_CTL); |
45187ace | 137 | unsigned i, len = DIP_HEADER_SIZE + frame->len; |
3c17fe4b | 138 | |
822974ae PZ |
139 | WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n"); |
140 | ||
1d4f85ac | 141 | val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ |
bc2481f3 | 142 | val |= g4x_infoframe_index(frame); |
22509ec8 | 143 | |
bc2481f3 | 144 | val &= ~g4x_infoframe_enable(frame); |
45187ace | 145 | |
22509ec8 | 146 | I915_WRITE(VIDEO_DIP_CTL, val); |
3c17fe4b | 147 | |
9d9740f0 | 148 | mmiowb(); |
45187ace | 149 | for (i = 0; i < len; i += 4) { |
3c17fe4b DH |
150 | I915_WRITE(VIDEO_DIP_DATA, *data); |
151 | data++; | |
152 | } | |
9d9740f0 | 153 | mmiowb(); |
3c17fe4b | 154 | |
bc2481f3 | 155 | val |= g4x_infoframe_enable(frame); |
60c5ea2d | 156 | val &= ~VIDEO_DIP_FREQ_MASK; |
4b24c933 | 157 | val |= VIDEO_DIP_FREQ_VSYNC; |
45187ace | 158 | |
22509ec8 | 159 | I915_WRITE(VIDEO_DIP_CTL, val); |
9d9740f0 | 160 | POSTING_READ(VIDEO_DIP_CTL); |
3c17fe4b DH |
161 | } |
162 | ||
fdf1250a PZ |
163 | static void ibx_write_infoframe(struct drm_encoder *encoder, |
164 | struct dip_infoframe *frame) | |
165 | { | |
166 | uint32_t *data = (uint32_t *)frame; | |
167 | struct drm_device *dev = encoder->dev; | |
168 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ed517fbb | 169 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); |
fdf1250a PZ |
170 | int reg = TVIDEO_DIP_CTL(intel_crtc->pipe); |
171 | unsigned i, len = DIP_HEADER_SIZE + frame->len; | |
172 | u32 val = I915_READ(reg); | |
173 | ||
822974ae PZ |
174 | WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n"); |
175 | ||
fdf1250a | 176 | val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ |
bc2481f3 | 177 | val |= g4x_infoframe_index(frame); |
fdf1250a | 178 | |
bc2481f3 | 179 | val &= ~g4x_infoframe_enable(frame); |
fdf1250a PZ |
180 | |
181 | I915_WRITE(reg, val); | |
182 | ||
9d9740f0 | 183 | mmiowb(); |
fdf1250a PZ |
184 | for (i = 0; i < len; i += 4) { |
185 | I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data); | |
186 | data++; | |
187 | } | |
9d9740f0 | 188 | mmiowb(); |
fdf1250a | 189 | |
bc2481f3 | 190 | val |= g4x_infoframe_enable(frame); |
fdf1250a | 191 | val &= ~VIDEO_DIP_FREQ_MASK; |
4b24c933 | 192 | val |= VIDEO_DIP_FREQ_VSYNC; |
fdf1250a PZ |
193 | |
194 | I915_WRITE(reg, val); | |
9d9740f0 | 195 | POSTING_READ(reg); |
fdf1250a PZ |
196 | } |
197 | ||
198 | static void cpt_write_infoframe(struct drm_encoder *encoder, | |
199 | struct dip_infoframe *frame) | |
b055c8f3 | 200 | { |
45187ace | 201 | uint32_t *data = (uint32_t *)frame; |
b055c8f3 JB |
202 | struct drm_device *dev = encoder->dev; |
203 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ed517fbb | 204 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); |
b055c8f3 | 205 | int reg = TVIDEO_DIP_CTL(intel_crtc->pipe); |
45187ace | 206 | unsigned i, len = DIP_HEADER_SIZE + frame->len; |
22509ec8 | 207 | u32 val = I915_READ(reg); |
b055c8f3 | 208 | |
822974ae PZ |
209 | WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n"); |
210 | ||
64a8fc01 | 211 | val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ |
bc2481f3 | 212 | val |= g4x_infoframe_index(frame); |
45187ace | 213 | |
ecb97851 PZ |
214 | /* The DIP control register spec says that we need to update the AVI |
215 | * infoframe without clearing its enable bit */ | |
822974ae | 216 | if (frame->type != DIP_TYPE_AVI) |
bc2481f3 | 217 | val &= ~g4x_infoframe_enable(frame); |
ecb97851 | 218 | |
22509ec8 | 219 | I915_WRITE(reg, val); |
45187ace | 220 | |
9d9740f0 | 221 | mmiowb(); |
45187ace | 222 | for (i = 0; i < len; i += 4) { |
b055c8f3 JB |
223 | I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data); |
224 | data++; | |
225 | } | |
9d9740f0 | 226 | mmiowb(); |
b055c8f3 | 227 | |
bc2481f3 | 228 | val |= g4x_infoframe_enable(frame); |
60c5ea2d | 229 | val &= ~VIDEO_DIP_FREQ_MASK; |
4b24c933 | 230 | val |= VIDEO_DIP_FREQ_VSYNC; |
45187ace | 231 | |
22509ec8 | 232 | I915_WRITE(reg, val); |
9d9740f0 | 233 | POSTING_READ(reg); |
45187ace | 234 | } |
90b107c8 SK |
235 | |
236 | static void vlv_write_infoframe(struct drm_encoder *encoder, | |
237 | struct dip_infoframe *frame) | |
238 | { | |
239 | uint32_t *data = (uint32_t *)frame; | |
240 | struct drm_device *dev = encoder->dev; | |
241 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ed517fbb | 242 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); |
90b107c8 SK |
243 | int reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe); |
244 | unsigned i, len = DIP_HEADER_SIZE + frame->len; | |
22509ec8 | 245 | u32 val = I915_READ(reg); |
90b107c8 | 246 | |
822974ae PZ |
247 | WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n"); |
248 | ||
90b107c8 | 249 | val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ |
bc2481f3 | 250 | val |= g4x_infoframe_index(frame); |
22509ec8 | 251 | |
bc2481f3 | 252 | val &= ~g4x_infoframe_enable(frame); |
90b107c8 | 253 | |
22509ec8 | 254 | I915_WRITE(reg, val); |
90b107c8 | 255 | |
9d9740f0 | 256 | mmiowb(); |
90b107c8 SK |
257 | for (i = 0; i < len; i += 4) { |
258 | I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), *data); | |
259 | data++; | |
260 | } | |
9d9740f0 | 261 | mmiowb(); |
90b107c8 | 262 | |
bc2481f3 | 263 | val |= g4x_infoframe_enable(frame); |
60c5ea2d | 264 | val &= ~VIDEO_DIP_FREQ_MASK; |
4b24c933 | 265 | val |= VIDEO_DIP_FREQ_VSYNC; |
90b107c8 | 266 | |
22509ec8 | 267 | I915_WRITE(reg, val); |
9d9740f0 | 268 | POSTING_READ(reg); |
90b107c8 SK |
269 | } |
270 | ||
8c5f5f7c | 271 | static void hsw_write_infoframe(struct drm_encoder *encoder, |
ed517fbb | 272 | struct dip_infoframe *frame) |
8c5f5f7c | 273 | { |
2da8af54 PZ |
274 | uint32_t *data = (uint32_t *)frame; |
275 | struct drm_device *dev = encoder->dev; | |
276 | struct drm_i915_private *dev_priv = dev->dev_private; | |
277 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); | |
278 | u32 ctl_reg = HSW_TVIDEO_DIP_CTL(intel_crtc->pipe); | |
279 | u32 data_reg = hsw_infoframe_data_reg(frame, intel_crtc->pipe); | |
280 | unsigned int i, len = DIP_HEADER_SIZE + frame->len; | |
281 | u32 val = I915_READ(ctl_reg); | |
8c5f5f7c | 282 | |
2da8af54 PZ |
283 | if (data_reg == 0) |
284 | return; | |
285 | ||
2da8af54 PZ |
286 | val &= ~hsw_infoframe_enable(frame); |
287 | I915_WRITE(ctl_reg, val); | |
288 | ||
9d9740f0 | 289 | mmiowb(); |
2da8af54 PZ |
290 | for (i = 0; i < len; i += 4) { |
291 | I915_WRITE(data_reg + i, *data); | |
292 | data++; | |
293 | } | |
9d9740f0 | 294 | mmiowb(); |
8c5f5f7c | 295 | |
2da8af54 PZ |
296 | val |= hsw_infoframe_enable(frame); |
297 | I915_WRITE(ctl_reg, val); | |
9d9740f0 | 298 | POSTING_READ(ctl_reg); |
8c5f5f7c ED |
299 | } |
300 | ||
45187ace JB |
301 | static void intel_set_infoframe(struct drm_encoder *encoder, |
302 | struct dip_infoframe *frame) | |
303 | { | |
304 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); | |
305 | ||
45187ace JB |
306 | intel_dip_infoframe_csum(frame); |
307 | intel_hdmi->write_infoframe(encoder, frame); | |
308 | } | |
309 | ||
687f4d06 | 310 | static void intel_hdmi_set_avi_infoframe(struct drm_encoder *encoder, |
c846b619 | 311 | struct drm_display_mode *adjusted_mode) |
45187ace JB |
312 | { |
313 | struct dip_infoframe avi_if = { | |
314 | .type = DIP_TYPE_AVI, | |
315 | .ver = DIP_VERSION_AVI, | |
316 | .len = DIP_LEN_AVI, | |
317 | }; | |
318 | ||
c846b619 PZ |
319 | if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK) |
320 | avi_if.body.avi.YQ_CN_PR |= DIP_AVI_PR_2; | |
321 | ||
45187ace | 322 | intel_set_infoframe(encoder, &avi_if); |
b055c8f3 JB |
323 | } |
324 | ||
687f4d06 | 325 | static void intel_hdmi_set_spd_infoframe(struct drm_encoder *encoder) |
c0864cb3 JB |
326 | { |
327 | struct dip_infoframe spd_if; | |
328 | ||
329 | memset(&spd_if, 0, sizeof(spd_if)); | |
330 | spd_if.type = DIP_TYPE_SPD; | |
331 | spd_if.ver = DIP_VERSION_SPD; | |
332 | spd_if.len = DIP_LEN_SPD; | |
333 | strcpy(spd_if.body.spd.vn, "Intel"); | |
334 | strcpy(spd_if.body.spd.pd, "Integrated gfx"); | |
335 | spd_if.body.spd.sdi = DIP_SPD_PC; | |
336 | ||
337 | intel_set_infoframe(encoder, &spd_if); | |
338 | } | |
339 | ||
687f4d06 PZ |
340 | static void g4x_set_infoframes(struct drm_encoder *encoder, |
341 | struct drm_display_mode *adjusted_mode) | |
342 | { | |
0c14c7f9 PZ |
343 | struct drm_i915_private *dev_priv = encoder->dev->dev_private; |
344 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); | |
345 | u32 reg = VIDEO_DIP_CTL; | |
346 | u32 val = I915_READ(reg); | |
72b78c9d | 347 | u32 port; |
0c14c7f9 | 348 | |
afba0188 DV |
349 | assert_hdmi_port_disabled(intel_hdmi); |
350 | ||
0c14c7f9 PZ |
351 | /* If the registers were not initialized yet, they might be zeroes, |
352 | * which means we're selecting the AVI DIP and we're setting its | |
353 | * frequency to once. This seems to really confuse the HW and make | |
354 | * things stop working (the register spec says the AVI always needs to | |
355 | * be sent every VSync). So here we avoid writing to the register more | |
356 | * than we need and also explicitly select the AVI DIP and explicitly | |
357 | * set its frequency to every VSync. Avoiding to write it twice seems to | |
358 | * be enough to solve the problem, but being defensive shouldn't hurt us | |
359 | * either. */ | |
360 | val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; | |
361 | ||
362 | if (!intel_hdmi->has_hdmi_sink) { | |
363 | if (!(val & VIDEO_DIP_ENABLE)) | |
364 | return; | |
365 | val &= ~VIDEO_DIP_ENABLE; | |
366 | I915_WRITE(reg, val); | |
9d9740f0 | 367 | POSTING_READ(reg); |
0c14c7f9 PZ |
368 | return; |
369 | } | |
370 | ||
f278d972 PZ |
371 | switch (intel_hdmi->sdvox_reg) { |
372 | case SDVOB: | |
72b78c9d | 373 | port = VIDEO_DIP_PORT_B; |
f278d972 PZ |
374 | break; |
375 | case SDVOC: | |
72b78c9d | 376 | port = VIDEO_DIP_PORT_C; |
f278d972 PZ |
377 | break; |
378 | default: | |
379 | return; | |
380 | } | |
381 | ||
72b78c9d PZ |
382 | if (port != (val & VIDEO_DIP_PORT_MASK)) { |
383 | if (val & VIDEO_DIP_ENABLE) { | |
384 | val &= ~VIDEO_DIP_ENABLE; | |
385 | I915_WRITE(reg, val); | |
9d9740f0 | 386 | POSTING_READ(reg); |
72b78c9d PZ |
387 | } |
388 | val &= ~VIDEO_DIP_PORT_MASK; | |
389 | val |= port; | |
390 | } | |
391 | ||
822974ae | 392 | val |= VIDEO_DIP_ENABLE; |
0dd87d20 | 393 | val &= ~VIDEO_DIP_ENABLE_VENDOR; |
822974ae | 394 | |
f278d972 | 395 | I915_WRITE(reg, val); |
9d9740f0 | 396 | POSTING_READ(reg); |
f278d972 | 397 | |
687f4d06 PZ |
398 | intel_hdmi_set_avi_infoframe(encoder, adjusted_mode); |
399 | intel_hdmi_set_spd_infoframe(encoder); | |
400 | } | |
401 | ||
402 | static void ibx_set_infoframes(struct drm_encoder *encoder, | |
403 | struct drm_display_mode *adjusted_mode) | |
404 | { | |
0c14c7f9 PZ |
405 | struct drm_i915_private *dev_priv = encoder->dev->dev_private; |
406 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); | |
407 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); | |
408 | u32 reg = TVIDEO_DIP_CTL(intel_crtc->pipe); | |
409 | u32 val = I915_READ(reg); | |
72b78c9d | 410 | u32 port; |
0c14c7f9 | 411 | |
afba0188 DV |
412 | assert_hdmi_port_disabled(intel_hdmi); |
413 | ||
0c14c7f9 PZ |
414 | /* See the big comment in g4x_set_infoframes() */ |
415 | val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; | |
416 | ||
417 | if (!intel_hdmi->has_hdmi_sink) { | |
418 | if (!(val & VIDEO_DIP_ENABLE)) | |
419 | return; | |
420 | val &= ~VIDEO_DIP_ENABLE; | |
421 | I915_WRITE(reg, val); | |
9d9740f0 | 422 | POSTING_READ(reg); |
0c14c7f9 PZ |
423 | return; |
424 | } | |
425 | ||
f278d972 PZ |
426 | switch (intel_hdmi->sdvox_reg) { |
427 | case HDMIB: | |
72b78c9d | 428 | port = VIDEO_DIP_PORT_B; |
f278d972 PZ |
429 | break; |
430 | case HDMIC: | |
72b78c9d | 431 | port = VIDEO_DIP_PORT_C; |
f278d972 PZ |
432 | break; |
433 | case HDMID: | |
72b78c9d | 434 | port = VIDEO_DIP_PORT_D; |
f278d972 PZ |
435 | break; |
436 | default: | |
437 | return; | |
438 | } | |
439 | ||
72b78c9d PZ |
440 | if (port != (val & VIDEO_DIP_PORT_MASK)) { |
441 | if (val & VIDEO_DIP_ENABLE) { | |
442 | val &= ~VIDEO_DIP_ENABLE; | |
443 | I915_WRITE(reg, val); | |
9d9740f0 | 444 | POSTING_READ(reg); |
72b78c9d PZ |
445 | } |
446 | val &= ~VIDEO_DIP_PORT_MASK; | |
447 | val |= port; | |
448 | } | |
449 | ||
822974ae | 450 | val |= VIDEO_DIP_ENABLE; |
0dd87d20 PZ |
451 | val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | |
452 | VIDEO_DIP_ENABLE_GCP); | |
822974ae | 453 | |
f278d972 | 454 | I915_WRITE(reg, val); |
9d9740f0 | 455 | POSTING_READ(reg); |
f278d972 | 456 | |
687f4d06 PZ |
457 | intel_hdmi_set_avi_infoframe(encoder, adjusted_mode); |
458 | intel_hdmi_set_spd_infoframe(encoder); | |
459 | } | |
460 | ||
461 | static void cpt_set_infoframes(struct drm_encoder *encoder, | |
462 | struct drm_display_mode *adjusted_mode) | |
463 | { | |
0c14c7f9 PZ |
464 | struct drm_i915_private *dev_priv = encoder->dev->dev_private; |
465 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); | |
466 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); | |
467 | u32 reg = TVIDEO_DIP_CTL(intel_crtc->pipe); | |
468 | u32 val = I915_READ(reg); | |
469 | ||
afba0188 DV |
470 | assert_hdmi_port_disabled(intel_hdmi); |
471 | ||
0c14c7f9 PZ |
472 | /* See the big comment in g4x_set_infoframes() */ |
473 | val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; | |
474 | ||
475 | if (!intel_hdmi->has_hdmi_sink) { | |
476 | if (!(val & VIDEO_DIP_ENABLE)) | |
477 | return; | |
478 | val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI); | |
479 | I915_WRITE(reg, val); | |
9d9740f0 | 480 | POSTING_READ(reg); |
0c14c7f9 PZ |
481 | return; |
482 | } | |
483 | ||
822974ae PZ |
484 | /* Set both together, unset both together: see the spec. */ |
485 | val |= VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI; | |
0dd87d20 PZ |
486 | val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | |
487 | VIDEO_DIP_ENABLE_GCP); | |
822974ae PZ |
488 | |
489 | I915_WRITE(reg, val); | |
9d9740f0 | 490 | POSTING_READ(reg); |
822974ae | 491 | |
687f4d06 PZ |
492 | intel_hdmi_set_avi_infoframe(encoder, adjusted_mode); |
493 | intel_hdmi_set_spd_infoframe(encoder); | |
494 | } | |
495 | ||
496 | static void vlv_set_infoframes(struct drm_encoder *encoder, | |
497 | struct drm_display_mode *adjusted_mode) | |
498 | { | |
0c14c7f9 PZ |
499 | struct drm_i915_private *dev_priv = encoder->dev->dev_private; |
500 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); | |
501 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); | |
502 | u32 reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe); | |
503 | u32 val = I915_READ(reg); | |
504 | ||
afba0188 DV |
505 | assert_hdmi_port_disabled(intel_hdmi); |
506 | ||
0c14c7f9 PZ |
507 | /* See the big comment in g4x_set_infoframes() */ |
508 | val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; | |
509 | ||
510 | if (!intel_hdmi->has_hdmi_sink) { | |
511 | if (!(val & VIDEO_DIP_ENABLE)) | |
512 | return; | |
513 | val &= ~VIDEO_DIP_ENABLE; | |
514 | I915_WRITE(reg, val); | |
9d9740f0 | 515 | POSTING_READ(reg); |
0c14c7f9 PZ |
516 | return; |
517 | } | |
518 | ||
822974ae | 519 | val |= VIDEO_DIP_ENABLE; |
0dd87d20 PZ |
520 | val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | |
521 | VIDEO_DIP_ENABLE_GCP); | |
822974ae PZ |
522 | |
523 | I915_WRITE(reg, val); | |
9d9740f0 | 524 | POSTING_READ(reg); |
822974ae | 525 | |
687f4d06 PZ |
526 | intel_hdmi_set_avi_infoframe(encoder, adjusted_mode); |
527 | intel_hdmi_set_spd_infoframe(encoder); | |
528 | } | |
529 | ||
530 | static void hsw_set_infoframes(struct drm_encoder *encoder, | |
531 | struct drm_display_mode *adjusted_mode) | |
532 | { | |
0c14c7f9 PZ |
533 | struct drm_i915_private *dev_priv = encoder->dev->dev_private; |
534 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); | |
535 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); | |
536 | u32 reg = HSW_TVIDEO_DIP_CTL(intel_crtc->pipe); | |
0dd87d20 | 537 | u32 val = I915_READ(reg); |
0c14c7f9 | 538 | |
afba0188 DV |
539 | assert_hdmi_port_disabled(intel_hdmi); |
540 | ||
0c14c7f9 PZ |
541 | if (!intel_hdmi->has_hdmi_sink) { |
542 | I915_WRITE(reg, 0); | |
9d9740f0 | 543 | POSTING_READ(reg); |
0c14c7f9 PZ |
544 | return; |
545 | } | |
546 | ||
0dd87d20 PZ |
547 | val &= ~(VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_GCP_HSW | |
548 | VIDEO_DIP_ENABLE_VS_HSW | VIDEO_DIP_ENABLE_GMP_HSW); | |
549 | ||
550 | I915_WRITE(reg, val); | |
9d9740f0 | 551 | POSTING_READ(reg); |
0dd87d20 | 552 | |
687f4d06 PZ |
553 | intel_hdmi_set_avi_infoframe(encoder, adjusted_mode); |
554 | intel_hdmi_set_spd_infoframe(encoder); | |
555 | } | |
556 | ||
7d57382e EA |
557 | static void intel_hdmi_mode_set(struct drm_encoder *encoder, |
558 | struct drm_display_mode *mode, | |
559 | struct drm_display_mode *adjusted_mode) | |
560 | { | |
561 | struct drm_device *dev = encoder->dev; | |
562 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ed517fbb | 563 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); |
ea5b213a | 564 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); |
7d57382e EA |
565 | u32 sdvox; |
566 | ||
b659c3db | 567 | sdvox = SDVO_ENCODING_HDMI; |
5d4fac97 JB |
568 | if (!HAS_PCH_SPLIT(dev)) |
569 | sdvox |= intel_hdmi->color_range; | |
b599c0bc AJ |
570 | if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) |
571 | sdvox |= SDVO_VSYNC_ACTIVE_HIGH; | |
572 | if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) | |
573 | sdvox |= SDVO_HSYNC_ACTIVE_HIGH; | |
7d57382e | 574 | |
020f6704 JB |
575 | if (intel_crtc->bpp > 24) |
576 | sdvox |= COLOR_FORMAT_12bpc; | |
577 | else | |
578 | sdvox |= COLOR_FORMAT_8bpc; | |
579 | ||
2e3d6006 ZW |
580 | /* Required on CPT */ |
581 | if (intel_hdmi->has_hdmi_sink && HAS_PCH_CPT(dev)) | |
582 | sdvox |= HDMI_MODE_SELECT; | |
583 | ||
3c17fe4b | 584 | if (intel_hdmi->has_audio) { |
e0dac65e WF |
585 | DRM_DEBUG_DRIVER("Enabling HDMI audio on pipe %c\n", |
586 | pipe_name(intel_crtc->pipe)); | |
7d57382e | 587 | sdvox |= SDVO_AUDIO_ENABLE; |
3c17fe4b | 588 | sdvox |= SDVO_NULL_PACKETS_DURING_VSYNC; |
e0dac65e | 589 | intel_write_eld(encoder, adjusted_mode); |
3c17fe4b | 590 | } |
7d57382e | 591 | |
75770564 JB |
592 | if (HAS_PCH_CPT(dev)) |
593 | sdvox |= PORT_TRANS_SEL_CPT(intel_crtc->pipe); | |
7a87c289 | 594 | else if (intel_crtc->pipe == PIPE_B) |
75770564 | 595 | sdvox |= SDVO_PIPE_B_SELECT; |
7d57382e | 596 | |
ea5b213a CW |
597 | I915_WRITE(intel_hdmi->sdvox_reg, sdvox); |
598 | POSTING_READ(intel_hdmi->sdvox_reg); | |
3c17fe4b | 599 | |
687f4d06 | 600 | intel_hdmi->set_infoframes(encoder, adjusted_mode); |
7d57382e EA |
601 | } |
602 | ||
603 | static void intel_hdmi_dpms(struct drm_encoder *encoder, int mode) | |
604 | { | |
605 | struct drm_device *dev = encoder->dev; | |
606 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ea5b213a | 607 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); |
7d57382e | 608 | u32 temp; |
2deed761 WF |
609 | u32 enable_bits = SDVO_ENABLE; |
610 | ||
b98b6016 | 611 | if (intel_hdmi->has_audio || mode != DRM_MODE_DPMS_ON) |
2deed761 | 612 | enable_bits |= SDVO_AUDIO_ENABLE; |
7d57382e | 613 | |
ea5b213a | 614 | temp = I915_READ(intel_hdmi->sdvox_reg); |
d8a2d0e0 | 615 | |
7a87c289 DV |
616 | /* HW workaround for IBX, we need to move the port to transcoder A |
617 | * before disabling it. */ | |
618 | if (HAS_PCH_IBX(dev)) { | |
619 | struct drm_crtc *crtc = encoder->crtc; | |
620 | int pipe = crtc ? to_intel_crtc(crtc)->pipe : -1; | |
621 | ||
622 | if (mode != DRM_MODE_DPMS_ON) { | |
623 | if (temp & SDVO_PIPE_B_SELECT) { | |
624 | temp &= ~SDVO_PIPE_B_SELECT; | |
625 | I915_WRITE(intel_hdmi->sdvox_reg, temp); | |
626 | POSTING_READ(intel_hdmi->sdvox_reg); | |
627 | ||
628 | /* Again we need to write this twice. */ | |
629 | I915_WRITE(intel_hdmi->sdvox_reg, temp); | |
630 | POSTING_READ(intel_hdmi->sdvox_reg); | |
631 | ||
632 | /* Transcoder selection bits only update | |
633 | * effectively on vblank. */ | |
634 | if (crtc) | |
635 | intel_wait_for_vblank(dev, pipe); | |
636 | else | |
637 | msleep(50); | |
638 | } | |
639 | } else { | |
640 | /* Restore the transcoder select bit. */ | |
641 | if (pipe == PIPE_B) | |
642 | enable_bits |= SDVO_PIPE_B_SELECT; | |
643 | } | |
644 | } | |
645 | ||
d8a2d0e0 ZW |
646 | /* HW workaround, need to toggle enable bit off and on for 12bpc, but |
647 | * we do this anyway which shows more stable in testing. | |
648 | */ | |
c619eed4 | 649 | if (HAS_PCH_SPLIT(dev)) { |
ea5b213a CW |
650 | I915_WRITE(intel_hdmi->sdvox_reg, temp & ~SDVO_ENABLE); |
651 | POSTING_READ(intel_hdmi->sdvox_reg); | |
d8a2d0e0 ZW |
652 | } |
653 | ||
654 | if (mode != DRM_MODE_DPMS_ON) { | |
2deed761 | 655 | temp &= ~enable_bits; |
7d57382e | 656 | } else { |
2deed761 | 657 | temp |= enable_bits; |
7d57382e | 658 | } |
d8a2d0e0 | 659 | |
ea5b213a CW |
660 | I915_WRITE(intel_hdmi->sdvox_reg, temp); |
661 | POSTING_READ(intel_hdmi->sdvox_reg); | |
d8a2d0e0 ZW |
662 | |
663 | /* HW workaround, need to write this twice for issue that may result | |
664 | * in first write getting masked. | |
665 | */ | |
c619eed4 | 666 | if (HAS_PCH_SPLIT(dev)) { |
ea5b213a CW |
667 | I915_WRITE(intel_hdmi->sdvox_reg, temp); |
668 | POSTING_READ(intel_hdmi->sdvox_reg); | |
d8a2d0e0 | 669 | } |
7d57382e EA |
670 | } |
671 | ||
7d57382e EA |
672 | static int intel_hdmi_mode_valid(struct drm_connector *connector, |
673 | struct drm_display_mode *mode) | |
674 | { | |
675 | if (mode->clock > 165000) | |
676 | return MODE_CLOCK_HIGH; | |
677 | if (mode->clock < 20000) | |
5cbba41d | 678 | return MODE_CLOCK_LOW; |
7d57382e EA |
679 | |
680 | if (mode->flags & DRM_MODE_FLAG_DBLSCAN) | |
681 | return MODE_NO_DBLESCAN; | |
682 | ||
683 | return MODE_OK; | |
684 | } | |
685 | ||
686 | static bool intel_hdmi_mode_fixup(struct drm_encoder *encoder, | |
e811f5ae | 687 | const struct drm_display_mode *mode, |
7d57382e EA |
688 | struct drm_display_mode *adjusted_mode) |
689 | { | |
690 | return true; | |
691 | } | |
692 | ||
8ec22b21 CW |
693 | static bool g4x_hdmi_connected(struct intel_hdmi *intel_hdmi) |
694 | { | |
695 | struct drm_device *dev = intel_hdmi->base.base.dev; | |
696 | struct drm_i915_private *dev_priv = dev->dev_private; | |
697 | uint32_t bit; | |
698 | ||
699 | switch (intel_hdmi->sdvox_reg) { | |
eeafaaca | 700 | case SDVOB: |
8ec22b21 CW |
701 | bit = HDMIB_HOTPLUG_LIVE_STATUS; |
702 | break; | |
eeafaaca | 703 | case SDVOC: |
8ec22b21 CW |
704 | bit = HDMIC_HOTPLUG_LIVE_STATUS; |
705 | break; | |
8ec22b21 CW |
706 | default: |
707 | bit = 0; | |
708 | break; | |
709 | } | |
710 | ||
711 | return I915_READ(PORT_HOTPLUG_STAT) & bit; | |
712 | } | |
713 | ||
aa93d632 | 714 | static enum drm_connector_status |
930a9e28 | 715 | intel_hdmi_detect(struct drm_connector *connector, bool force) |
9dff6af8 | 716 | { |
df0e9248 | 717 | struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); |
f899fc64 CW |
718 | struct drm_i915_private *dev_priv = connector->dev->dev_private; |
719 | struct edid *edid; | |
aa93d632 | 720 | enum drm_connector_status status = connector_status_disconnected; |
9dff6af8 | 721 | |
8ec22b21 CW |
722 | if (IS_G4X(connector->dev) && !g4x_hdmi_connected(intel_hdmi)) |
723 | return status; | |
724 | ||
ea5b213a | 725 | intel_hdmi->has_hdmi_sink = false; |
2e3d6006 | 726 | intel_hdmi->has_audio = false; |
f899fc64 | 727 | edid = drm_get_edid(connector, |
3bd7d909 DK |
728 | intel_gmbus_get_adapter(dev_priv, |
729 | intel_hdmi->ddc_bus)); | |
2ded9e27 | 730 | |
aa93d632 | 731 | if (edid) { |
be9f1c4f | 732 | if (edid->input & DRM_EDID_INPUT_DIGITAL) { |
aa93d632 | 733 | status = connector_status_connected; |
b1d7e4b4 WF |
734 | if (intel_hdmi->force_audio != HDMI_AUDIO_OFF_DVI) |
735 | intel_hdmi->has_hdmi_sink = | |
736 | drm_detect_hdmi_monitor(edid); | |
2e3d6006 | 737 | intel_hdmi->has_audio = drm_detect_monitor_audio(edid); |
aa93d632 | 738 | } |
674e2d08 | 739 | connector->display_info.raw_edid = NULL; |
aa93d632 | 740 | kfree(edid); |
9dff6af8 | 741 | } |
30ad48b7 | 742 | |
55b7d6e8 | 743 | if (status == connector_status_connected) { |
b1d7e4b4 WF |
744 | if (intel_hdmi->force_audio != HDMI_AUDIO_AUTO) |
745 | intel_hdmi->has_audio = | |
746 | (intel_hdmi->force_audio == HDMI_AUDIO_ON); | |
55b7d6e8 CW |
747 | } |
748 | ||
2ded9e27 | 749 | return status; |
7d57382e EA |
750 | } |
751 | ||
752 | static int intel_hdmi_get_modes(struct drm_connector *connector) | |
753 | { | |
df0e9248 | 754 | struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); |
f899fc64 | 755 | struct drm_i915_private *dev_priv = connector->dev->dev_private; |
7d57382e EA |
756 | |
757 | /* We should parse the EDID data and find out if it's an HDMI sink so | |
758 | * we can send audio to it. | |
759 | */ | |
760 | ||
f899fc64 | 761 | return intel_ddc_get_modes(connector, |
3bd7d909 DK |
762 | intel_gmbus_get_adapter(dev_priv, |
763 | intel_hdmi->ddc_bus)); | |
7d57382e EA |
764 | } |
765 | ||
1aad7ac0 CW |
766 | static bool |
767 | intel_hdmi_detect_audio(struct drm_connector *connector) | |
768 | { | |
769 | struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); | |
770 | struct drm_i915_private *dev_priv = connector->dev->dev_private; | |
771 | struct edid *edid; | |
772 | bool has_audio = false; | |
773 | ||
774 | edid = drm_get_edid(connector, | |
3bd7d909 DK |
775 | intel_gmbus_get_adapter(dev_priv, |
776 | intel_hdmi->ddc_bus)); | |
1aad7ac0 CW |
777 | if (edid) { |
778 | if (edid->input & DRM_EDID_INPUT_DIGITAL) | |
779 | has_audio = drm_detect_monitor_audio(edid); | |
780 | ||
781 | connector->display_info.raw_edid = NULL; | |
782 | kfree(edid); | |
783 | } | |
784 | ||
785 | return has_audio; | |
786 | } | |
787 | ||
55b7d6e8 CW |
788 | static int |
789 | intel_hdmi_set_property(struct drm_connector *connector, | |
ed517fbb PZ |
790 | struct drm_property *property, |
791 | uint64_t val) | |
55b7d6e8 CW |
792 | { |
793 | struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); | |
e953fd7b | 794 | struct drm_i915_private *dev_priv = connector->dev->dev_private; |
55b7d6e8 CW |
795 | int ret; |
796 | ||
797 | ret = drm_connector_property_set_value(connector, property, val); | |
798 | if (ret) | |
799 | return ret; | |
800 | ||
3f43c48d | 801 | if (property == dev_priv->force_audio_property) { |
b1d7e4b4 | 802 | enum hdmi_force_audio i = val; |
1aad7ac0 CW |
803 | bool has_audio; |
804 | ||
805 | if (i == intel_hdmi->force_audio) | |
55b7d6e8 CW |
806 | return 0; |
807 | ||
1aad7ac0 | 808 | intel_hdmi->force_audio = i; |
55b7d6e8 | 809 | |
b1d7e4b4 | 810 | if (i == HDMI_AUDIO_AUTO) |
1aad7ac0 CW |
811 | has_audio = intel_hdmi_detect_audio(connector); |
812 | else | |
b1d7e4b4 | 813 | has_audio = (i == HDMI_AUDIO_ON); |
1aad7ac0 | 814 | |
b1d7e4b4 WF |
815 | if (i == HDMI_AUDIO_OFF_DVI) |
816 | intel_hdmi->has_hdmi_sink = 0; | |
55b7d6e8 | 817 | |
1aad7ac0 | 818 | intel_hdmi->has_audio = has_audio; |
55b7d6e8 CW |
819 | goto done; |
820 | } | |
821 | ||
e953fd7b CW |
822 | if (property == dev_priv->broadcast_rgb_property) { |
823 | if (val == !!intel_hdmi->color_range) | |
824 | return 0; | |
825 | ||
826 | intel_hdmi->color_range = val ? SDVO_COLOR_RANGE_16_235 : 0; | |
827 | goto done; | |
828 | } | |
829 | ||
55b7d6e8 CW |
830 | return -EINVAL; |
831 | ||
832 | done: | |
833 | if (intel_hdmi->base.base.crtc) { | |
834 | struct drm_crtc *crtc = intel_hdmi->base.base.crtc; | |
835 | drm_crtc_helper_set_mode(crtc, &crtc->mode, | |
836 | crtc->x, crtc->y, | |
837 | crtc->fb); | |
838 | } | |
839 | ||
840 | return 0; | |
841 | } | |
842 | ||
7d57382e EA |
843 | static void intel_hdmi_destroy(struct drm_connector *connector) |
844 | { | |
7d57382e EA |
845 | drm_sysfs_connector_remove(connector); |
846 | drm_connector_cleanup(connector); | |
674e2d08 | 847 | kfree(connector); |
7d57382e EA |
848 | } |
849 | ||
72662e10 ED |
850 | static const struct drm_encoder_helper_funcs intel_hdmi_helper_funcs_hsw = { |
851 | .dpms = intel_ddi_dpms, | |
852 | .mode_fixup = intel_hdmi_mode_fixup, | |
853 | .prepare = intel_encoder_prepare, | |
854 | .mode_set = intel_ddi_mode_set, | |
855 | .commit = intel_encoder_commit, | |
856 | }; | |
857 | ||
7d57382e EA |
858 | static const struct drm_encoder_helper_funcs intel_hdmi_helper_funcs = { |
859 | .dpms = intel_hdmi_dpms, | |
860 | .mode_fixup = intel_hdmi_mode_fixup, | |
861 | .prepare = intel_encoder_prepare, | |
862 | .mode_set = intel_hdmi_mode_set, | |
863 | .commit = intel_encoder_commit, | |
864 | }; | |
865 | ||
866 | static const struct drm_connector_funcs intel_hdmi_connector_funcs = { | |
c9fb15f6 | 867 | .dpms = drm_helper_connector_dpms, |
7d57382e EA |
868 | .detect = intel_hdmi_detect, |
869 | .fill_modes = drm_helper_probe_single_connector_modes, | |
55b7d6e8 | 870 | .set_property = intel_hdmi_set_property, |
7d57382e EA |
871 | .destroy = intel_hdmi_destroy, |
872 | }; | |
873 | ||
874 | static const struct drm_connector_helper_funcs intel_hdmi_connector_helper_funcs = { | |
875 | .get_modes = intel_hdmi_get_modes, | |
876 | .mode_valid = intel_hdmi_mode_valid, | |
df0e9248 | 877 | .best_encoder = intel_best_encoder, |
7d57382e EA |
878 | }; |
879 | ||
7d57382e | 880 | static const struct drm_encoder_funcs intel_hdmi_enc_funcs = { |
ea5b213a | 881 | .destroy = intel_encoder_destroy, |
7d57382e EA |
882 | }; |
883 | ||
55b7d6e8 CW |
884 | static void |
885 | intel_hdmi_add_properties(struct intel_hdmi *intel_hdmi, struct drm_connector *connector) | |
886 | { | |
3f43c48d | 887 | intel_attach_force_audio_property(connector); |
e953fd7b | 888 | intel_attach_broadcast_rgb_property(connector); |
55b7d6e8 CW |
889 | } |
890 | ||
7d57382e EA |
891 | void intel_hdmi_init(struct drm_device *dev, int sdvox_reg) |
892 | { | |
893 | struct drm_i915_private *dev_priv = dev->dev_private; | |
894 | struct drm_connector *connector; | |
21d40d37 | 895 | struct intel_encoder *intel_encoder; |
674e2d08 | 896 | struct intel_connector *intel_connector; |
ea5b213a | 897 | struct intel_hdmi *intel_hdmi; |
7d57382e | 898 | |
ea5b213a CW |
899 | intel_hdmi = kzalloc(sizeof(struct intel_hdmi), GFP_KERNEL); |
900 | if (!intel_hdmi) | |
7d57382e | 901 | return; |
674e2d08 ZW |
902 | |
903 | intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL); | |
904 | if (!intel_connector) { | |
ea5b213a | 905 | kfree(intel_hdmi); |
674e2d08 ZW |
906 | return; |
907 | } | |
908 | ||
ea5b213a | 909 | intel_encoder = &intel_hdmi->base; |
373a3cf7 CW |
910 | drm_encoder_init(dev, &intel_encoder->base, &intel_hdmi_enc_funcs, |
911 | DRM_MODE_ENCODER_TMDS); | |
912 | ||
674e2d08 | 913 | connector = &intel_connector->base; |
7d57382e | 914 | drm_connector_init(dev, connector, &intel_hdmi_connector_funcs, |
8d91104a | 915 | DRM_MODE_CONNECTOR_HDMIA); |
7d57382e EA |
916 | drm_connector_helper_add(connector, &intel_hdmi_connector_helper_funcs); |
917 | ||
21d40d37 | 918 | intel_encoder->type = INTEL_OUTPUT_HDMI; |
7d57382e | 919 | |
eb1f8e4f | 920 | connector->polled = DRM_CONNECTOR_POLL_HPD; |
c3febcc4 | 921 | connector->interlace_allowed = 1; |
7d57382e | 922 | connector->doublescan_allowed = 0; |
27f8227b | 923 | intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2); |
7d57382e EA |
924 | |
925 | /* Set up the DDC bus. */ | |
f8aed700 | 926 | if (sdvox_reg == SDVOB) { |
21d40d37 | 927 | intel_encoder->clone_mask = (1 << INTEL_HDMIB_CLONE_BIT); |
f899fc64 | 928 | intel_hdmi->ddc_bus = GMBUS_PORT_DPB; |
b01f2c3a | 929 | dev_priv->hotplug_supported_mask |= HDMIB_HOTPLUG_INT_STATUS; |
f8aed700 | 930 | } else if (sdvox_reg == SDVOC) { |
21d40d37 | 931 | intel_encoder->clone_mask = (1 << INTEL_HDMIC_CLONE_BIT); |
f899fc64 | 932 | intel_hdmi->ddc_bus = GMBUS_PORT_DPC; |
b01f2c3a | 933 | dev_priv->hotplug_supported_mask |= HDMIC_HOTPLUG_INT_STATUS; |
f8aed700 | 934 | } else if (sdvox_reg == HDMIB) { |
21d40d37 | 935 | intel_encoder->clone_mask = (1 << INTEL_HDMID_CLONE_BIT); |
f899fc64 | 936 | intel_hdmi->ddc_bus = GMBUS_PORT_DPB; |
b01f2c3a | 937 | dev_priv->hotplug_supported_mask |= HDMIB_HOTPLUG_INT_STATUS; |
f8aed700 | 938 | } else if (sdvox_reg == HDMIC) { |
21d40d37 | 939 | intel_encoder->clone_mask = (1 << INTEL_HDMIE_CLONE_BIT); |
f899fc64 | 940 | intel_hdmi->ddc_bus = GMBUS_PORT_DPC; |
b01f2c3a | 941 | dev_priv->hotplug_supported_mask |= HDMIC_HOTPLUG_INT_STATUS; |
f8aed700 | 942 | } else if (sdvox_reg == HDMID) { |
21d40d37 | 943 | intel_encoder->clone_mask = (1 << INTEL_HDMIF_CLONE_BIT); |
f899fc64 | 944 | intel_hdmi->ddc_bus = GMBUS_PORT_DPD; |
b01f2c3a | 945 | dev_priv->hotplug_supported_mask |= HDMID_HOTPLUG_INT_STATUS; |
7ceae0a5 ED |
946 | } else if (sdvox_reg == DDI_BUF_CTL(PORT_B)) { |
947 | DRM_DEBUG_DRIVER("LPT: detected output on DDI B\n"); | |
948 | intel_encoder->clone_mask = (1 << INTEL_HDMIB_CLONE_BIT); | |
949 | intel_hdmi->ddc_bus = GMBUS_PORT_DPB; | |
950 | intel_hdmi->ddi_port = PORT_B; | |
951 | dev_priv->hotplug_supported_mask |= HDMIB_HOTPLUG_INT_STATUS; | |
952 | } else if (sdvox_reg == DDI_BUF_CTL(PORT_C)) { | |
953 | DRM_DEBUG_DRIVER("LPT: detected output on DDI C\n"); | |
954 | intel_encoder->clone_mask = (1 << INTEL_HDMIC_CLONE_BIT); | |
955 | intel_hdmi->ddc_bus = GMBUS_PORT_DPC; | |
956 | intel_hdmi->ddi_port = PORT_C; | |
957 | dev_priv->hotplug_supported_mask |= HDMIC_HOTPLUG_INT_STATUS; | |
958 | } else if (sdvox_reg == DDI_BUF_CTL(PORT_D)) { | |
959 | DRM_DEBUG_DRIVER("LPT: detected output on DDI D\n"); | |
960 | intel_encoder->clone_mask = (1 << INTEL_HDMID_CLONE_BIT); | |
961 | intel_hdmi->ddc_bus = GMBUS_PORT_DPD; | |
962 | intel_hdmi->ddi_port = PORT_D; | |
963 | dev_priv->hotplug_supported_mask |= HDMID_HOTPLUG_INT_STATUS; | |
6e4c1677 ED |
964 | } else { |
965 | /* If we got an unknown sdvox_reg, things are pretty much broken | |
966 | * in a way that we should let the kernel know about it */ | |
967 | BUG(); | |
f8aed700 | 968 | } |
7d57382e | 969 | |
ea5b213a | 970 | intel_hdmi->sdvox_reg = sdvox_reg; |
7d57382e | 971 | |
64a8fc01 | 972 | if (!HAS_PCH_SPLIT(dev)) { |
a3da1df7 | 973 | intel_hdmi->write_infoframe = g4x_write_infoframe; |
687f4d06 | 974 | intel_hdmi->set_infoframes = g4x_set_infoframes; |
90b107c8 SK |
975 | } else if (IS_VALLEYVIEW(dev)) { |
976 | intel_hdmi->write_infoframe = vlv_write_infoframe; | |
687f4d06 | 977 | intel_hdmi->set_infoframes = vlv_set_infoframes; |
8c5f5f7c | 978 | } else if (IS_HASWELL(dev)) { |
8c5f5f7c | 979 | intel_hdmi->write_infoframe = hsw_write_infoframe; |
687f4d06 | 980 | intel_hdmi->set_infoframes = hsw_set_infoframes; |
fdf1250a PZ |
981 | } else if (HAS_PCH_IBX(dev)) { |
982 | intel_hdmi->write_infoframe = ibx_write_infoframe; | |
687f4d06 | 983 | intel_hdmi->set_infoframes = ibx_set_infoframes; |
fdf1250a PZ |
984 | } else { |
985 | intel_hdmi->write_infoframe = cpt_write_infoframe; | |
687f4d06 | 986 | intel_hdmi->set_infoframes = cpt_set_infoframes; |
64a8fc01 | 987 | } |
45187ace | 988 | |
72662e10 ED |
989 | if (IS_HASWELL(dev)) |
990 | drm_encoder_helper_add(&intel_encoder->base, &intel_hdmi_helper_funcs_hsw); | |
991 | else | |
992 | drm_encoder_helper_add(&intel_encoder->base, &intel_hdmi_helper_funcs); | |
7d57382e | 993 | |
55b7d6e8 CW |
994 | intel_hdmi_add_properties(intel_hdmi, connector); |
995 | ||
df0e9248 | 996 | intel_connector_attach_encoder(intel_connector, intel_encoder); |
7d57382e EA |
997 | drm_sysfs_connector_add(connector); |
998 | ||
999 | /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written | |
1000 | * 0xd. Failure to do so will result in spurious interrupts being | |
1001 | * generated on the port when a cable is not attached. | |
1002 | */ | |
1003 | if (IS_G4X(dev) && !IS_GM45(dev)) { | |
1004 | u32 temp = I915_READ(PEG_BAND_GAP_DATA); | |
1005 | I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd); | |
1006 | } | |
7d57382e | 1007 | } |