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7d57382e EA |
1 | /* |
2 | * Copyright 2006 Dave Airlie <airlied@linux.ie> | |
3 | * Copyright © 2006-2009 Intel Corporation | |
4 | * | |
5 | * Permission is hereby granted, free of charge, to any person obtaining a | |
6 | * copy of this software and associated documentation files (the "Software"), | |
7 | * to deal in the Software without restriction, including without limitation | |
8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
9 | * and/or sell copies of the Software, and to permit persons to whom the | |
10 | * Software is furnished to do so, subject to the following conditions: | |
11 | * | |
12 | * The above copyright notice and this permission notice (including the next | |
13 | * paragraph) shall be included in all copies or substantial portions of the | |
14 | * Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
21 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
22 | * DEALINGS IN THE SOFTWARE. | |
23 | * | |
24 | * Authors: | |
25 | * Eric Anholt <eric@anholt.net> | |
26 | * Jesse Barnes <jesse.barnes@intel.com> | |
27 | */ | |
28 | ||
29 | #include <linux/i2c.h> | |
5a0e3ad6 | 30 | #include <linux/slab.h> |
7d57382e | 31 | #include <linux/delay.h> |
760285e7 DH |
32 | #include <drm/drmP.h> |
33 | #include <drm/drm_crtc.h> | |
34 | #include <drm/drm_edid.h> | |
7d57382e | 35 | #include "intel_drv.h" |
760285e7 | 36 | #include <drm/i915_drm.h> |
7d57382e EA |
37 | #include "i915_drv.h" |
38 | ||
30add22d PZ |
39 | static struct drm_device *intel_hdmi_to_dev(struct intel_hdmi *intel_hdmi) |
40 | { | |
da63a9f2 | 41 | return hdmi_to_dig_port(intel_hdmi)->base.base.dev; |
30add22d PZ |
42 | } |
43 | ||
afba0188 DV |
44 | static void |
45 | assert_hdmi_port_disabled(struct intel_hdmi *intel_hdmi) | |
46 | { | |
30add22d | 47 | struct drm_device *dev = intel_hdmi_to_dev(intel_hdmi); |
afba0188 DV |
48 | struct drm_i915_private *dev_priv = dev->dev_private; |
49 | uint32_t enabled_bits; | |
50 | ||
51 | enabled_bits = IS_HASWELL(dev) ? DDI_BUF_CTL_ENABLE : SDVO_ENABLE; | |
52 | ||
53 | WARN(I915_READ(intel_hdmi->sdvox_reg) & enabled_bits, | |
54 | "HDMI port enabled, expecting disabled\n"); | |
55 | } | |
56 | ||
f5bbfca3 | 57 | struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder) |
ea5b213a | 58 | { |
da63a9f2 PZ |
59 | struct intel_digital_port *intel_dig_port = |
60 | container_of(encoder, struct intel_digital_port, base.base); | |
61 | return &intel_dig_port->hdmi; | |
ea5b213a CW |
62 | } |
63 | ||
df0e9248 CW |
64 | static struct intel_hdmi *intel_attached_hdmi(struct drm_connector *connector) |
65 | { | |
da63a9f2 | 66 | return enc_to_intel_hdmi(&intel_attached_encoder(connector)->base); |
df0e9248 CW |
67 | } |
68 | ||
45187ace | 69 | void intel_dip_infoframe_csum(struct dip_infoframe *frame) |
3c17fe4b | 70 | { |
45187ace | 71 | uint8_t *data = (uint8_t *)frame; |
3c17fe4b DH |
72 | uint8_t sum = 0; |
73 | unsigned i; | |
74 | ||
45187ace JB |
75 | frame->checksum = 0; |
76 | frame->ecc = 0; | |
3c17fe4b | 77 | |
64a8fc01 | 78 | for (i = 0; i < frame->len + DIP_HEADER_SIZE; i++) |
3c17fe4b DH |
79 | sum += data[i]; |
80 | ||
45187ace | 81 | frame->checksum = 0x100 - sum; |
3c17fe4b DH |
82 | } |
83 | ||
bc2481f3 | 84 | static u32 g4x_infoframe_index(struct dip_infoframe *frame) |
3c17fe4b | 85 | { |
45187ace JB |
86 | switch (frame->type) { |
87 | case DIP_TYPE_AVI: | |
ed517fbb | 88 | return VIDEO_DIP_SELECT_AVI; |
45187ace | 89 | case DIP_TYPE_SPD: |
ed517fbb | 90 | return VIDEO_DIP_SELECT_SPD; |
45187ace JB |
91 | default: |
92 | DRM_DEBUG_DRIVER("unknown info frame type %d\n", frame->type); | |
ed517fbb | 93 | return 0; |
45187ace | 94 | } |
45187ace JB |
95 | } |
96 | ||
bc2481f3 | 97 | static u32 g4x_infoframe_enable(struct dip_infoframe *frame) |
45187ace | 98 | { |
45187ace JB |
99 | switch (frame->type) { |
100 | case DIP_TYPE_AVI: | |
ed517fbb | 101 | return VIDEO_DIP_ENABLE_AVI; |
45187ace | 102 | case DIP_TYPE_SPD: |
ed517fbb | 103 | return VIDEO_DIP_ENABLE_SPD; |
fa193ff7 PZ |
104 | default: |
105 | DRM_DEBUG_DRIVER("unknown info frame type %d\n", frame->type); | |
ed517fbb | 106 | return 0; |
fa193ff7 | 107 | } |
fa193ff7 PZ |
108 | } |
109 | ||
2da8af54 PZ |
110 | static u32 hsw_infoframe_enable(struct dip_infoframe *frame) |
111 | { | |
112 | switch (frame->type) { | |
113 | case DIP_TYPE_AVI: | |
114 | return VIDEO_DIP_ENABLE_AVI_HSW; | |
115 | case DIP_TYPE_SPD: | |
116 | return VIDEO_DIP_ENABLE_SPD_HSW; | |
117 | default: | |
118 | DRM_DEBUG_DRIVER("unknown info frame type %d\n", frame->type); | |
119 | return 0; | |
120 | } | |
121 | } | |
122 | ||
123 | static u32 hsw_infoframe_data_reg(struct dip_infoframe *frame, enum pipe pipe) | |
124 | { | |
125 | switch (frame->type) { | |
126 | case DIP_TYPE_AVI: | |
127 | return HSW_TVIDEO_DIP_AVI_DATA(pipe); | |
128 | case DIP_TYPE_SPD: | |
129 | return HSW_TVIDEO_DIP_SPD_DATA(pipe); | |
130 | default: | |
131 | DRM_DEBUG_DRIVER("unknown info frame type %d\n", frame->type); | |
132 | return 0; | |
133 | } | |
134 | } | |
135 | ||
a3da1df7 DV |
136 | static void g4x_write_infoframe(struct drm_encoder *encoder, |
137 | struct dip_infoframe *frame) | |
45187ace JB |
138 | { |
139 | uint32_t *data = (uint32_t *)frame; | |
3c17fe4b DH |
140 | struct drm_device *dev = encoder->dev; |
141 | struct drm_i915_private *dev_priv = dev->dev_private; | |
22509ec8 | 142 | u32 val = I915_READ(VIDEO_DIP_CTL); |
45187ace | 143 | unsigned i, len = DIP_HEADER_SIZE + frame->len; |
3c17fe4b | 144 | |
822974ae PZ |
145 | WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n"); |
146 | ||
1d4f85ac | 147 | val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ |
bc2481f3 | 148 | val |= g4x_infoframe_index(frame); |
22509ec8 | 149 | |
bc2481f3 | 150 | val &= ~g4x_infoframe_enable(frame); |
45187ace | 151 | |
22509ec8 | 152 | I915_WRITE(VIDEO_DIP_CTL, val); |
3c17fe4b | 153 | |
9d9740f0 | 154 | mmiowb(); |
45187ace | 155 | for (i = 0; i < len; i += 4) { |
3c17fe4b DH |
156 | I915_WRITE(VIDEO_DIP_DATA, *data); |
157 | data++; | |
158 | } | |
adf00b26 PZ |
159 | /* Write every possible data byte to force correct ECC calculation. */ |
160 | for (; i < VIDEO_DIP_DATA_SIZE; i += 4) | |
161 | I915_WRITE(VIDEO_DIP_DATA, 0); | |
9d9740f0 | 162 | mmiowb(); |
3c17fe4b | 163 | |
bc2481f3 | 164 | val |= g4x_infoframe_enable(frame); |
60c5ea2d | 165 | val &= ~VIDEO_DIP_FREQ_MASK; |
4b24c933 | 166 | val |= VIDEO_DIP_FREQ_VSYNC; |
45187ace | 167 | |
22509ec8 | 168 | I915_WRITE(VIDEO_DIP_CTL, val); |
9d9740f0 | 169 | POSTING_READ(VIDEO_DIP_CTL); |
3c17fe4b DH |
170 | } |
171 | ||
fdf1250a PZ |
172 | static void ibx_write_infoframe(struct drm_encoder *encoder, |
173 | struct dip_infoframe *frame) | |
174 | { | |
175 | uint32_t *data = (uint32_t *)frame; | |
176 | struct drm_device *dev = encoder->dev; | |
177 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ed517fbb | 178 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); |
fdf1250a PZ |
179 | int reg = TVIDEO_DIP_CTL(intel_crtc->pipe); |
180 | unsigned i, len = DIP_HEADER_SIZE + frame->len; | |
181 | u32 val = I915_READ(reg); | |
182 | ||
822974ae PZ |
183 | WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n"); |
184 | ||
fdf1250a | 185 | val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ |
bc2481f3 | 186 | val |= g4x_infoframe_index(frame); |
fdf1250a | 187 | |
bc2481f3 | 188 | val &= ~g4x_infoframe_enable(frame); |
fdf1250a PZ |
189 | |
190 | I915_WRITE(reg, val); | |
191 | ||
9d9740f0 | 192 | mmiowb(); |
fdf1250a PZ |
193 | for (i = 0; i < len; i += 4) { |
194 | I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data); | |
195 | data++; | |
196 | } | |
adf00b26 PZ |
197 | /* Write every possible data byte to force correct ECC calculation. */ |
198 | for (; i < VIDEO_DIP_DATA_SIZE; i += 4) | |
199 | I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0); | |
9d9740f0 | 200 | mmiowb(); |
fdf1250a | 201 | |
bc2481f3 | 202 | val |= g4x_infoframe_enable(frame); |
fdf1250a | 203 | val &= ~VIDEO_DIP_FREQ_MASK; |
4b24c933 | 204 | val |= VIDEO_DIP_FREQ_VSYNC; |
fdf1250a PZ |
205 | |
206 | I915_WRITE(reg, val); | |
9d9740f0 | 207 | POSTING_READ(reg); |
fdf1250a PZ |
208 | } |
209 | ||
210 | static void cpt_write_infoframe(struct drm_encoder *encoder, | |
211 | struct dip_infoframe *frame) | |
b055c8f3 | 212 | { |
45187ace | 213 | uint32_t *data = (uint32_t *)frame; |
b055c8f3 JB |
214 | struct drm_device *dev = encoder->dev; |
215 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ed517fbb | 216 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); |
b055c8f3 | 217 | int reg = TVIDEO_DIP_CTL(intel_crtc->pipe); |
45187ace | 218 | unsigned i, len = DIP_HEADER_SIZE + frame->len; |
22509ec8 | 219 | u32 val = I915_READ(reg); |
b055c8f3 | 220 | |
822974ae PZ |
221 | WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n"); |
222 | ||
64a8fc01 | 223 | val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ |
bc2481f3 | 224 | val |= g4x_infoframe_index(frame); |
45187ace | 225 | |
ecb97851 PZ |
226 | /* The DIP control register spec says that we need to update the AVI |
227 | * infoframe without clearing its enable bit */ | |
822974ae | 228 | if (frame->type != DIP_TYPE_AVI) |
bc2481f3 | 229 | val &= ~g4x_infoframe_enable(frame); |
ecb97851 | 230 | |
22509ec8 | 231 | I915_WRITE(reg, val); |
45187ace | 232 | |
9d9740f0 | 233 | mmiowb(); |
45187ace | 234 | for (i = 0; i < len; i += 4) { |
b055c8f3 JB |
235 | I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data); |
236 | data++; | |
237 | } | |
adf00b26 PZ |
238 | /* Write every possible data byte to force correct ECC calculation. */ |
239 | for (; i < VIDEO_DIP_DATA_SIZE; i += 4) | |
240 | I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0); | |
9d9740f0 | 241 | mmiowb(); |
b055c8f3 | 242 | |
bc2481f3 | 243 | val |= g4x_infoframe_enable(frame); |
60c5ea2d | 244 | val &= ~VIDEO_DIP_FREQ_MASK; |
4b24c933 | 245 | val |= VIDEO_DIP_FREQ_VSYNC; |
45187ace | 246 | |
22509ec8 | 247 | I915_WRITE(reg, val); |
9d9740f0 | 248 | POSTING_READ(reg); |
45187ace | 249 | } |
90b107c8 SK |
250 | |
251 | static void vlv_write_infoframe(struct drm_encoder *encoder, | |
252 | struct dip_infoframe *frame) | |
253 | { | |
254 | uint32_t *data = (uint32_t *)frame; | |
255 | struct drm_device *dev = encoder->dev; | |
256 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ed517fbb | 257 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); |
90b107c8 SK |
258 | int reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe); |
259 | unsigned i, len = DIP_HEADER_SIZE + frame->len; | |
22509ec8 | 260 | u32 val = I915_READ(reg); |
90b107c8 | 261 | |
822974ae PZ |
262 | WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n"); |
263 | ||
90b107c8 | 264 | val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ |
bc2481f3 | 265 | val |= g4x_infoframe_index(frame); |
22509ec8 | 266 | |
bc2481f3 | 267 | val &= ~g4x_infoframe_enable(frame); |
90b107c8 | 268 | |
22509ec8 | 269 | I915_WRITE(reg, val); |
90b107c8 | 270 | |
9d9740f0 | 271 | mmiowb(); |
90b107c8 SK |
272 | for (i = 0; i < len; i += 4) { |
273 | I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), *data); | |
274 | data++; | |
275 | } | |
adf00b26 PZ |
276 | /* Write every possible data byte to force correct ECC calculation. */ |
277 | for (; i < VIDEO_DIP_DATA_SIZE; i += 4) | |
278 | I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), 0); | |
9d9740f0 | 279 | mmiowb(); |
90b107c8 | 280 | |
bc2481f3 | 281 | val |= g4x_infoframe_enable(frame); |
60c5ea2d | 282 | val &= ~VIDEO_DIP_FREQ_MASK; |
4b24c933 | 283 | val |= VIDEO_DIP_FREQ_VSYNC; |
90b107c8 | 284 | |
22509ec8 | 285 | I915_WRITE(reg, val); |
9d9740f0 | 286 | POSTING_READ(reg); |
90b107c8 SK |
287 | } |
288 | ||
8c5f5f7c | 289 | static void hsw_write_infoframe(struct drm_encoder *encoder, |
ed517fbb | 290 | struct dip_infoframe *frame) |
8c5f5f7c | 291 | { |
2da8af54 PZ |
292 | uint32_t *data = (uint32_t *)frame; |
293 | struct drm_device *dev = encoder->dev; | |
294 | struct drm_i915_private *dev_priv = dev->dev_private; | |
295 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); | |
296 | u32 ctl_reg = HSW_TVIDEO_DIP_CTL(intel_crtc->pipe); | |
297 | u32 data_reg = hsw_infoframe_data_reg(frame, intel_crtc->pipe); | |
298 | unsigned int i, len = DIP_HEADER_SIZE + frame->len; | |
299 | u32 val = I915_READ(ctl_reg); | |
8c5f5f7c | 300 | |
2da8af54 PZ |
301 | if (data_reg == 0) |
302 | return; | |
303 | ||
2da8af54 PZ |
304 | val &= ~hsw_infoframe_enable(frame); |
305 | I915_WRITE(ctl_reg, val); | |
306 | ||
9d9740f0 | 307 | mmiowb(); |
2da8af54 PZ |
308 | for (i = 0; i < len; i += 4) { |
309 | I915_WRITE(data_reg + i, *data); | |
310 | data++; | |
311 | } | |
adf00b26 PZ |
312 | /* Write every possible data byte to force correct ECC calculation. */ |
313 | for (; i < VIDEO_DIP_DATA_SIZE; i += 4) | |
314 | I915_WRITE(data_reg + i, 0); | |
9d9740f0 | 315 | mmiowb(); |
8c5f5f7c | 316 | |
2da8af54 PZ |
317 | val |= hsw_infoframe_enable(frame); |
318 | I915_WRITE(ctl_reg, val); | |
9d9740f0 | 319 | POSTING_READ(ctl_reg); |
8c5f5f7c ED |
320 | } |
321 | ||
45187ace JB |
322 | static void intel_set_infoframe(struct drm_encoder *encoder, |
323 | struct dip_infoframe *frame) | |
324 | { | |
325 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); | |
326 | ||
45187ace JB |
327 | intel_dip_infoframe_csum(frame); |
328 | intel_hdmi->write_infoframe(encoder, frame); | |
329 | } | |
330 | ||
687f4d06 | 331 | static void intel_hdmi_set_avi_infoframe(struct drm_encoder *encoder, |
c846b619 | 332 | struct drm_display_mode *adjusted_mode) |
45187ace JB |
333 | { |
334 | struct dip_infoframe avi_if = { | |
335 | .type = DIP_TYPE_AVI, | |
336 | .ver = DIP_VERSION_AVI, | |
337 | .len = DIP_LEN_AVI, | |
338 | }; | |
339 | ||
c846b619 PZ |
340 | if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK) |
341 | avi_if.body.avi.YQ_CN_PR |= DIP_AVI_PR_2; | |
342 | ||
45187ace | 343 | intel_set_infoframe(encoder, &avi_if); |
b055c8f3 JB |
344 | } |
345 | ||
687f4d06 | 346 | static void intel_hdmi_set_spd_infoframe(struct drm_encoder *encoder) |
c0864cb3 JB |
347 | { |
348 | struct dip_infoframe spd_if; | |
349 | ||
350 | memset(&spd_if, 0, sizeof(spd_if)); | |
351 | spd_if.type = DIP_TYPE_SPD; | |
352 | spd_if.ver = DIP_VERSION_SPD; | |
353 | spd_if.len = DIP_LEN_SPD; | |
354 | strcpy(spd_if.body.spd.vn, "Intel"); | |
355 | strcpy(spd_if.body.spd.pd, "Integrated gfx"); | |
356 | spd_if.body.spd.sdi = DIP_SPD_PC; | |
357 | ||
358 | intel_set_infoframe(encoder, &spd_if); | |
359 | } | |
360 | ||
687f4d06 PZ |
361 | static void g4x_set_infoframes(struct drm_encoder *encoder, |
362 | struct drm_display_mode *adjusted_mode) | |
363 | { | |
0c14c7f9 PZ |
364 | struct drm_i915_private *dev_priv = encoder->dev->dev_private; |
365 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); | |
366 | u32 reg = VIDEO_DIP_CTL; | |
367 | u32 val = I915_READ(reg); | |
72b78c9d | 368 | u32 port; |
0c14c7f9 | 369 | |
afba0188 DV |
370 | assert_hdmi_port_disabled(intel_hdmi); |
371 | ||
0c14c7f9 PZ |
372 | /* If the registers were not initialized yet, they might be zeroes, |
373 | * which means we're selecting the AVI DIP and we're setting its | |
374 | * frequency to once. This seems to really confuse the HW and make | |
375 | * things stop working (the register spec says the AVI always needs to | |
376 | * be sent every VSync). So here we avoid writing to the register more | |
377 | * than we need and also explicitly select the AVI DIP and explicitly | |
378 | * set its frequency to every VSync. Avoiding to write it twice seems to | |
379 | * be enough to solve the problem, but being defensive shouldn't hurt us | |
380 | * either. */ | |
381 | val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; | |
382 | ||
383 | if (!intel_hdmi->has_hdmi_sink) { | |
384 | if (!(val & VIDEO_DIP_ENABLE)) | |
385 | return; | |
386 | val &= ~VIDEO_DIP_ENABLE; | |
387 | I915_WRITE(reg, val); | |
9d9740f0 | 388 | POSTING_READ(reg); |
0c14c7f9 PZ |
389 | return; |
390 | } | |
391 | ||
f278d972 PZ |
392 | switch (intel_hdmi->sdvox_reg) { |
393 | case SDVOB: | |
72b78c9d | 394 | port = VIDEO_DIP_PORT_B; |
f278d972 PZ |
395 | break; |
396 | case SDVOC: | |
72b78c9d | 397 | port = VIDEO_DIP_PORT_C; |
f278d972 PZ |
398 | break; |
399 | default: | |
57df2ae9 | 400 | BUG(); |
f278d972 PZ |
401 | return; |
402 | } | |
403 | ||
72b78c9d PZ |
404 | if (port != (val & VIDEO_DIP_PORT_MASK)) { |
405 | if (val & VIDEO_DIP_ENABLE) { | |
406 | val &= ~VIDEO_DIP_ENABLE; | |
407 | I915_WRITE(reg, val); | |
9d9740f0 | 408 | POSTING_READ(reg); |
72b78c9d PZ |
409 | } |
410 | val &= ~VIDEO_DIP_PORT_MASK; | |
411 | val |= port; | |
412 | } | |
413 | ||
822974ae | 414 | val |= VIDEO_DIP_ENABLE; |
0dd87d20 | 415 | val &= ~VIDEO_DIP_ENABLE_VENDOR; |
822974ae | 416 | |
f278d972 | 417 | I915_WRITE(reg, val); |
9d9740f0 | 418 | POSTING_READ(reg); |
f278d972 | 419 | |
687f4d06 PZ |
420 | intel_hdmi_set_avi_infoframe(encoder, adjusted_mode); |
421 | intel_hdmi_set_spd_infoframe(encoder); | |
422 | } | |
423 | ||
424 | static void ibx_set_infoframes(struct drm_encoder *encoder, | |
425 | struct drm_display_mode *adjusted_mode) | |
426 | { | |
0c14c7f9 PZ |
427 | struct drm_i915_private *dev_priv = encoder->dev->dev_private; |
428 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); | |
429 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); | |
430 | u32 reg = TVIDEO_DIP_CTL(intel_crtc->pipe); | |
431 | u32 val = I915_READ(reg); | |
72b78c9d | 432 | u32 port; |
0c14c7f9 | 433 | |
afba0188 DV |
434 | assert_hdmi_port_disabled(intel_hdmi); |
435 | ||
0c14c7f9 PZ |
436 | /* See the big comment in g4x_set_infoframes() */ |
437 | val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; | |
438 | ||
439 | if (!intel_hdmi->has_hdmi_sink) { | |
440 | if (!(val & VIDEO_DIP_ENABLE)) | |
441 | return; | |
442 | val &= ~VIDEO_DIP_ENABLE; | |
443 | I915_WRITE(reg, val); | |
9d9740f0 | 444 | POSTING_READ(reg); |
0c14c7f9 PZ |
445 | return; |
446 | } | |
447 | ||
f278d972 PZ |
448 | switch (intel_hdmi->sdvox_reg) { |
449 | case HDMIB: | |
72b78c9d | 450 | port = VIDEO_DIP_PORT_B; |
f278d972 PZ |
451 | break; |
452 | case HDMIC: | |
72b78c9d | 453 | port = VIDEO_DIP_PORT_C; |
f278d972 PZ |
454 | break; |
455 | case HDMID: | |
72b78c9d | 456 | port = VIDEO_DIP_PORT_D; |
f278d972 PZ |
457 | break; |
458 | default: | |
57df2ae9 | 459 | BUG(); |
f278d972 PZ |
460 | return; |
461 | } | |
462 | ||
72b78c9d PZ |
463 | if (port != (val & VIDEO_DIP_PORT_MASK)) { |
464 | if (val & VIDEO_DIP_ENABLE) { | |
465 | val &= ~VIDEO_DIP_ENABLE; | |
466 | I915_WRITE(reg, val); | |
9d9740f0 | 467 | POSTING_READ(reg); |
72b78c9d PZ |
468 | } |
469 | val &= ~VIDEO_DIP_PORT_MASK; | |
470 | val |= port; | |
471 | } | |
472 | ||
822974ae | 473 | val |= VIDEO_DIP_ENABLE; |
0dd87d20 PZ |
474 | val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | |
475 | VIDEO_DIP_ENABLE_GCP); | |
822974ae | 476 | |
f278d972 | 477 | I915_WRITE(reg, val); |
9d9740f0 | 478 | POSTING_READ(reg); |
f278d972 | 479 | |
687f4d06 PZ |
480 | intel_hdmi_set_avi_infoframe(encoder, adjusted_mode); |
481 | intel_hdmi_set_spd_infoframe(encoder); | |
482 | } | |
483 | ||
484 | static void cpt_set_infoframes(struct drm_encoder *encoder, | |
485 | struct drm_display_mode *adjusted_mode) | |
486 | { | |
0c14c7f9 PZ |
487 | struct drm_i915_private *dev_priv = encoder->dev->dev_private; |
488 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); | |
489 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); | |
490 | u32 reg = TVIDEO_DIP_CTL(intel_crtc->pipe); | |
491 | u32 val = I915_READ(reg); | |
492 | ||
afba0188 DV |
493 | assert_hdmi_port_disabled(intel_hdmi); |
494 | ||
0c14c7f9 PZ |
495 | /* See the big comment in g4x_set_infoframes() */ |
496 | val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; | |
497 | ||
498 | if (!intel_hdmi->has_hdmi_sink) { | |
499 | if (!(val & VIDEO_DIP_ENABLE)) | |
500 | return; | |
501 | val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI); | |
502 | I915_WRITE(reg, val); | |
9d9740f0 | 503 | POSTING_READ(reg); |
0c14c7f9 PZ |
504 | return; |
505 | } | |
506 | ||
822974ae PZ |
507 | /* Set both together, unset both together: see the spec. */ |
508 | val |= VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI; | |
0dd87d20 PZ |
509 | val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | |
510 | VIDEO_DIP_ENABLE_GCP); | |
822974ae PZ |
511 | |
512 | I915_WRITE(reg, val); | |
9d9740f0 | 513 | POSTING_READ(reg); |
822974ae | 514 | |
687f4d06 PZ |
515 | intel_hdmi_set_avi_infoframe(encoder, adjusted_mode); |
516 | intel_hdmi_set_spd_infoframe(encoder); | |
517 | } | |
518 | ||
519 | static void vlv_set_infoframes(struct drm_encoder *encoder, | |
520 | struct drm_display_mode *adjusted_mode) | |
521 | { | |
0c14c7f9 PZ |
522 | struct drm_i915_private *dev_priv = encoder->dev->dev_private; |
523 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); | |
524 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); | |
525 | u32 reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe); | |
526 | u32 val = I915_READ(reg); | |
527 | ||
afba0188 DV |
528 | assert_hdmi_port_disabled(intel_hdmi); |
529 | ||
0c14c7f9 PZ |
530 | /* See the big comment in g4x_set_infoframes() */ |
531 | val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; | |
532 | ||
533 | if (!intel_hdmi->has_hdmi_sink) { | |
534 | if (!(val & VIDEO_DIP_ENABLE)) | |
535 | return; | |
536 | val &= ~VIDEO_DIP_ENABLE; | |
537 | I915_WRITE(reg, val); | |
9d9740f0 | 538 | POSTING_READ(reg); |
0c14c7f9 PZ |
539 | return; |
540 | } | |
541 | ||
822974ae | 542 | val |= VIDEO_DIP_ENABLE; |
0dd87d20 PZ |
543 | val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | |
544 | VIDEO_DIP_ENABLE_GCP); | |
822974ae PZ |
545 | |
546 | I915_WRITE(reg, val); | |
9d9740f0 | 547 | POSTING_READ(reg); |
822974ae | 548 | |
687f4d06 PZ |
549 | intel_hdmi_set_avi_infoframe(encoder, adjusted_mode); |
550 | intel_hdmi_set_spd_infoframe(encoder); | |
551 | } | |
552 | ||
553 | static void hsw_set_infoframes(struct drm_encoder *encoder, | |
554 | struct drm_display_mode *adjusted_mode) | |
555 | { | |
0c14c7f9 PZ |
556 | struct drm_i915_private *dev_priv = encoder->dev->dev_private; |
557 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); | |
558 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); | |
559 | u32 reg = HSW_TVIDEO_DIP_CTL(intel_crtc->pipe); | |
0dd87d20 | 560 | u32 val = I915_READ(reg); |
0c14c7f9 | 561 | |
afba0188 DV |
562 | assert_hdmi_port_disabled(intel_hdmi); |
563 | ||
0c14c7f9 PZ |
564 | if (!intel_hdmi->has_hdmi_sink) { |
565 | I915_WRITE(reg, 0); | |
9d9740f0 | 566 | POSTING_READ(reg); |
0c14c7f9 PZ |
567 | return; |
568 | } | |
569 | ||
0dd87d20 PZ |
570 | val &= ~(VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_GCP_HSW | |
571 | VIDEO_DIP_ENABLE_VS_HSW | VIDEO_DIP_ENABLE_GMP_HSW); | |
572 | ||
573 | I915_WRITE(reg, val); | |
9d9740f0 | 574 | POSTING_READ(reg); |
0dd87d20 | 575 | |
687f4d06 PZ |
576 | intel_hdmi_set_avi_infoframe(encoder, adjusted_mode); |
577 | intel_hdmi_set_spd_infoframe(encoder); | |
578 | } | |
579 | ||
7d57382e EA |
580 | static void intel_hdmi_mode_set(struct drm_encoder *encoder, |
581 | struct drm_display_mode *mode, | |
582 | struct drm_display_mode *adjusted_mode) | |
583 | { | |
584 | struct drm_device *dev = encoder->dev; | |
585 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ed517fbb | 586 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); |
ea5b213a | 587 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); |
7d57382e EA |
588 | u32 sdvox; |
589 | ||
b659c3db | 590 | sdvox = SDVO_ENCODING_HDMI; |
5d4fac97 JB |
591 | if (!HAS_PCH_SPLIT(dev)) |
592 | sdvox |= intel_hdmi->color_range; | |
b599c0bc AJ |
593 | if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) |
594 | sdvox |= SDVO_VSYNC_ACTIVE_HIGH; | |
595 | if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) | |
596 | sdvox |= SDVO_HSYNC_ACTIVE_HIGH; | |
7d57382e | 597 | |
020f6704 JB |
598 | if (intel_crtc->bpp > 24) |
599 | sdvox |= COLOR_FORMAT_12bpc; | |
600 | else | |
601 | sdvox |= COLOR_FORMAT_8bpc; | |
602 | ||
2e3d6006 ZW |
603 | /* Required on CPT */ |
604 | if (intel_hdmi->has_hdmi_sink && HAS_PCH_CPT(dev)) | |
605 | sdvox |= HDMI_MODE_SELECT; | |
606 | ||
3c17fe4b | 607 | if (intel_hdmi->has_audio) { |
e0dac65e WF |
608 | DRM_DEBUG_DRIVER("Enabling HDMI audio on pipe %c\n", |
609 | pipe_name(intel_crtc->pipe)); | |
7d57382e | 610 | sdvox |= SDVO_AUDIO_ENABLE; |
3c17fe4b | 611 | sdvox |= SDVO_NULL_PACKETS_DURING_VSYNC; |
e0dac65e | 612 | intel_write_eld(encoder, adjusted_mode); |
3c17fe4b | 613 | } |
7d57382e | 614 | |
75770564 JB |
615 | if (HAS_PCH_CPT(dev)) |
616 | sdvox |= PORT_TRANS_SEL_CPT(intel_crtc->pipe); | |
7a87c289 | 617 | else if (intel_crtc->pipe == PIPE_B) |
75770564 | 618 | sdvox |= SDVO_PIPE_B_SELECT; |
7d57382e | 619 | |
ea5b213a CW |
620 | I915_WRITE(intel_hdmi->sdvox_reg, sdvox); |
621 | POSTING_READ(intel_hdmi->sdvox_reg); | |
3c17fe4b | 622 | |
687f4d06 | 623 | intel_hdmi->set_infoframes(encoder, adjusted_mode); |
7d57382e EA |
624 | } |
625 | ||
85234cdc DV |
626 | static bool intel_hdmi_get_hw_state(struct intel_encoder *encoder, |
627 | enum pipe *pipe) | |
7d57382e | 628 | { |
85234cdc | 629 | struct drm_device *dev = encoder->base.dev; |
7d57382e | 630 | struct drm_i915_private *dev_priv = dev->dev_private; |
85234cdc DV |
631 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); |
632 | u32 tmp; | |
633 | ||
634 | tmp = I915_READ(intel_hdmi->sdvox_reg); | |
635 | ||
636 | if (!(tmp & SDVO_ENABLE)) | |
637 | return false; | |
638 | ||
639 | if (HAS_PCH_CPT(dev)) | |
640 | *pipe = PORT_TO_PIPE_CPT(tmp); | |
641 | else | |
642 | *pipe = PORT_TO_PIPE(tmp); | |
643 | ||
644 | return true; | |
645 | } | |
646 | ||
5ab432ef | 647 | static void intel_enable_hdmi(struct intel_encoder *encoder) |
7d57382e | 648 | { |
5ab432ef | 649 | struct drm_device *dev = encoder->base.dev; |
7d57382e | 650 | struct drm_i915_private *dev_priv = dev->dev_private; |
5ab432ef | 651 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); |
7d57382e | 652 | u32 temp; |
2deed761 WF |
653 | u32 enable_bits = SDVO_ENABLE; |
654 | ||
655 | if (intel_hdmi->has_audio) | |
656 | enable_bits |= SDVO_AUDIO_ENABLE; | |
7d57382e | 657 | |
ea5b213a | 658 | temp = I915_READ(intel_hdmi->sdvox_reg); |
d8a2d0e0 | 659 | |
7a87c289 DV |
660 | /* HW workaround for IBX, we need to move the port to transcoder A |
661 | * before disabling it. */ | |
662 | if (HAS_PCH_IBX(dev)) { | |
5ab432ef | 663 | struct drm_crtc *crtc = encoder->base.crtc; |
7a87c289 DV |
664 | int pipe = crtc ? to_intel_crtc(crtc)->pipe : -1; |
665 | ||
5ab432ef DV |
666 | /* Restore the transcoder select bit. */ |
667 | if (pipe == PIPE_B) | |
668 | enable_bits |= SDVO_PIPE_B_SELECT; | |
7a87c289 DV |
669 | } |
670 | ||
d8a2d0e0 ZW |
671 | /* HW workaround, need to toggle enable bit off and on for 12bpc, but |
672 | * we do this anyway which shows more stable in testing. | |
673 | */ | |
c619eed4 | 674 | if (HAS_PCH_SPLIT(dev)) { |
ea5b213a CW |
675 | I915_WRITE(intel_hdmi->sdvox_reg, temp & ~SDVO_ENABLE); |
676 | POSTING_READ(intel_hdmi->sdvox_reg); | |
d8a2d0e0 ZW |
677 | } |
678 | ||
5ab432ef DV |
679 | temp |= enable_bits; |
680 | ||
681 | I915_WRITE(intel_hdmi->sdvox_reg, temp); | |
682 | POSTING_READ(intel_hdmi->sdvox_reg); | |
683 | ||
684 | /* HW workaround, need to write this twice for issue that may result | |
685 | * in first write getting masked. | |
686 | */ | |
687 | if (HAS_PCH_SPLIT(dev)) { | |
688 | I915_WRITE(intel_hdmi->sdvox_reg, temp); | |
689 | POSTING_READ(intel_hdmi->sdvox_reg); | |
7d57382e | 690 | } |
5ab432ef DV |
691 | } |
692 | ||
693 | static void intel_disable_hdmi(struct intel_encoder *encoder) | |
694 | { | |
695 | struct drm_device *dev = encoder->base.dev; | |
696 | struct drm_i915_private *dev_priv = dev->dev_private; | |
697 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); | |
698 | u32 temp; | |
3cce574f | 699 | u32 enable_bits = SDVO_ENABLE | SDVO_AUDIO_ENABLE; |
5ab432ef DV |
700 | |
701 | temp = I915_READ(intel_hdmi->sdvox_reg); | |
702 | ||
703 | /* HW workaround for IBX, we need to move the port to transcoder A | |
704 | * before disabling it. */ | |
705 | if (HAS_PCH_IBX(dev)) { | |
706 | struct drm_crtc *crtc = encoder->base.crtc; | |
707 | int pipe = crtc ? to_intel_crtc(crtc)->pipe : -1; | |
708 | ||
709 | if (temp & SDVO_PIPE_B_SELECT) { | |
710 | temp &= ~SDVO_PIPE_B_SELECT; | |
711 | I915_WRITE(intel_hdmi->sdvox_reg, temp); | |
712 | POSTING_READ(intel_hdmi->sdvox_reg); | |
713 | ||
714 | /* Again we need to write this twice. */ | |
715 | I915_WRITE(intel_hdmi->sdvox_reg, temp); | |
716 | POSTING_READ(intel_hdmi->sdvox_reg); | |
717 | ||
718 | /* Transcoder selection bits only update | |
719 | * effectively on vblank. */ | |
720 | if (crtc) | |
721 | intel_wait_for_vblank(dev, pipe); | |
722 | else | |
723 | msleep(50); | |
724 | } | |
7d57382e | 725 | } |
d8a2d0e0 | 726 | |
5ab432ef DV |
727 | /* HW workaround, need to toggle enable bit off and on for 12bpc, but |
728 | * we do this anyway which shows more stable in testing. | |
729 | */ | |
730 | if (HAS_PCH_SPLIT(dev)) { | |
731 | I915_WRITE(intel_hdmi->sdvox_reg, temp & ~SDVO_ENABLE); | |
732 | POSTING_READ(intel_hdmi->sdvox_reg); | |
733 | } | |
734 | ||
735 | temp &= ~enable_bits; | |
d8a2d0e0 | 736 | |
ea5b213a CW |
737 | I915_WRITE(intel_hdmi->sdvox_reg, temp); |
738 | POSTING_READ(intel_hdmi->sdvox_reg); | |
d8a2d0e0 ZW |
739 | |
740 | /* HW workaround, need to write this twice for issue that may result | |
741 | * in first write getting masked. | |
742 | */ | |
c619eed4 | 743 | if (HAS_PCH_SPLIT(dev)) { |
ea5b213a CW |
744 | I915_WRITE(intel_hdmi->sdvox_reg, temp); |
745 | POSTING_READ(intel_hdmi->sdvox_reg); | |
d8a2d0e0 | 746 | } |
7d57382e EA |
747 | } |
748 | ||
7d57382e EA |
749 | static int intel_hdmi_mode_valid(struct drm_connector *connector, |
750 | struct drm_display_mode *mode) | |
751 | { | |
752 | if (mode->clock > 165000) | |
753 | return MODE_CLOCK_HIGH; | |
754 | if (mode->clock < 20000) | |
5cbba41d | 755 | return MODE_CLOCK_LOW; |
7d57382e EA |
756 | |
757 | if (mode->flags & DRM_MODE_FLAG_DBLSCAN) | |
758 | return MODE_NO_DBLESCAN; | |
759 | ||
760 | return MODE_OK; | |
761 | } | |
762 | ||
00c09d70 PZ |
763 | bool intel_hdmi_mode_fixup(struct drm_encoder *encoder, |
764 | const struct drm_display_mode *mode, | |
765 | struct drm_display_mode *adjusted_mode) | |
7d57382e EA |
766 | { |
767 | return true; | |
768 | } | |
769 | ||
8ec22b21 CW |
770 | static bool g4x_hdmi_connected(struct intel_hdmi *intel_hdmi) |
771 | { | |
30add22d | 772 | struct drm_device *dev = intel_hdmi_to_dev(intel_hdmi); |
8ec22b21 CW |
773 | struct drm_i915_private *dev_priv = dev->dev_private; |
774 | uint32_t bit; | |
775 | ||
776 | switch (intel_hdmi->sdvox_reg) { | |
eeafaaca | 777 | case SDVOB: |
8ec22b21 CW |
778 | bit = HDMIB_HOTPLUG_LIVE_STATUS; |
779 | break; | |
eeafaaca | 780 | case SDVOC: |
8ec22b21 CW |
781 | bit = HDMIC_HOTPLUG_LIVE_STATUS; |
782 | break; | |
8ec22b21 CW |
783 | default: |
784 | bit = 0; | |
785 | break; | |
786 | } | |
787 | ||
788 | return I915_READ(PORT_HOTPLUG_STAT) & bit; | |
789 | } | |
790 | ||
aa93d632 | 791 | static enum drm_connector_status |
930a9e28 | 792 | intel_hdmi_detect(struct drm_connector *connector, bool force) |
9dff6af8 | 793 | { |
df0e9248 | 794 | struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); |
d63885da PZ |
795 | struct intel_digital_port *intel_dig_port = |
796 | hdmi_to_dig_port(intel_hdmi); | |
797 | struct intel_encoder *intel_encoder = &intel_dig_port->base; | |
f899fc64 CW |
798 | struct drm_i915_private *dev_priv = connector->dev->dev_private; |
799 | struct edid *edid; | |
aa93d632 | 800 | enum drm_connector_status status = connector_status_disconnected; |
9dff6af8 | 801 | |
8ec22b21 CW |
802 | if (IS_G4X(connector->dev) && !g4x_hdmi_connected(intel_hdmi)) |
803 | return status; | |
804 | ||
ea5b213a | 805 | intel_hdmi->has_hdmi_sink = false; |
2e3d6006 | 806 | intel_hdmi->has_audio = false; |
f899fc64 | 807 | edid = drm_get_edid(connector, |
3bd7d909 DK |
808 | intel_gmbus_get_adapter(dev_priv, |
809 | intel_hdmi->ddc_bus)); | |
2ded9e27 | 810 | |
aa93d632 | 811 | if (edid) { |
be9f1c4f | 812 | if (edid->input & DRM_EDID_INPUT_DIGITAL) { |
aa93d632 | 813 | status = connector_status_connected; |
b1d7e4b4 WF |
814 | if (intel_hdmi->force_audio != HDMI_AUDIO_OFF_DVI) |
815 | intel_hdmi->has_hdmi_sink = | |
816 | drm_detect_hdmi_monitor(edid); | |
2e3d6006 | 817 | intel_hdmi->has_audio = drm_detect_monitor_audio(edid); |
aa93d632 | 818 | } |
aa93d632 | 819 | kfree(edid); |
9dff6af8 | 820 | } |
30ad48b7 | 821 | |
55b7d6e8 | 822 | if (status == connector_status_connected) { |
b1d7e4b4 WF |
823 | if (intel_hdmi->force_audio != HDMI_AUDIO_AUTO) |
824 | intel_hdmi->has_audio = | |
825 | (intel_hdmi->force_audio == HDMI_AUDIO_ON); | |
d63885da | 826 | intel_encoder->type = INTEL_OUTPUT_HDMI; |
55b7d6e8 CW |
827 | } |
828 | ||
2ded9e27 | 829 | return status; |
7d57382e EA |
830 | } |
831 | ||
832 | static int intel_hdmi_get_modes(struct drm_connector *connector) | |
833 | { | |
df0e9248 | 834 | struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); |
f899fc64 | 835 | struct drm_i915_private *dev_priv = connector->dev->dev_private; |
7d57382e EA |
836 | |
837 | /* We should parse the EDID data and find out if it's an HDMI sink so | |
838 | * we can send audio to it. | |
839 | */ | |
840 | ||
f899fc64 | 841 | return intel_ddc_get_modes(connector, |
3bd7d909 DK |
842 | intel_gmbus_get_adapter(dev_priv, |
843 | intel_hdmi->ddc_bus)); | |
7d57382e EA |
844 | } |
845 | ||
1aad7ac0 CW |
846 | static bool |
847 | intel_hdmi_detect_audio(struct drm_connector *connector) | |
848 | { | |
849 | struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); | |
850 | struct drm_i915_private *dev_priv = connector->dev->dev_private; | |
851 | struct edid *edid; | |
852 | bool has_audio = false; | |
853 | ||
854 | edid = drm_get_edid(connector, | |
3bd7d909 DK |
855 | intel_gmbus_get_adapter(dev_priv, |
856 | intel_hdmi->ddc_bus)); | |
1aad7ac0 CW |
857 | if (edid) { |
858 | if (edid->input & DRM_EDID_INPUT_DIGITAL) | |
859 | has_audio = drm_detect_monitor_audio(edid); | |
1aad7ac0 CW |
860 | kfree(edid); |
861 | } | |
862 | ||
863 | return has_audio; | |
864 | } | |
865 | ||
55b7d6e8 CW |
866 | static int |
867 | intel_hdmi_set_property(struct drm_connector *connector, | |
ed517fbb PZ |
868 | struct drm_property *property, |
869 | uint64_t val) | |
55b7d6e8 CW |
870 | { |
871 | struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); | |
da63a9f2 PZ |
872 | struct intel_digital_port *intel_dig_port = |
873 | hdmi_to_dig_port(intel_hdmi); | |
e953fd7b | 874 | struct drm_i915_private *dev_priv = connector->dev->dev_private; |
55b7d6e8 CW |
875 | int ret; |
876 | ||
877 | ret = drm_connector_property_set_value(connector, property, val); | |
878 | if (ret) | |
879 | return ret; | |
880 | ||
3f43c48d | 881 | if (property == dev_priv->force_audio_property) { |
b1d7e4b4 | 882 | enum hdmi_force_audio i = val; |
1aad7ac0 CW |
883 | bool has_audio; |
884 | ||
885 | if (i == intel_hdmi->force_audio) | |
55b7d6e8 CW |
886 | return 0; |
887 | ||
1aad7ac0 | 888 | intel_hdmi->force_audio = i; |
55b7d6e8 | 889 | |
b1d7e4b4 | 890 | if (i == HDMI_AUDIO_AUTO) |
1aad7ac0 CW |
891 | has_audio = intel_hdmi_detect_audio(connector); |
892 | else | |
b1d7e4b4 | 893 | has_audio = (i == HDMI_AUDIO_ON); |
1aad7ac0 | 894 | |
b1d7e4b4 WF |
895 | if (i == HDMI_AUDIO_OFF_DVI) |
896 | intel_hdmi->has_hdmi_sink = 0; | |
55b7d6e8 | 897 | |
1aad7ac0 | 898 | intel_hdmi->has_audio = has_audio; |
55b7d6e8 CW |
899 | goto done; |
900 | } | |
901 | ||
e953fd7b CW |
902 | if (property == dev_priv->broadcast_rgb_property) { |
903 | if (val == !!intel_hdmi->color_range) | |
904 | return 0; | |
905 | ||
906 | intel_hdmi->color_range = val ? SDVO_COLOR_RANGE_16_235 : 0; | |
907 | goto done; | |
908 | } | |
909 | ||
55b7d6e8 CW |
910 | return -EINVAL; |
911 | ||
912 | done: | |
da63a9f2 PZ |
913 | if (intel_dig_port->base.base.crtc) { |
914 | struct drm_crtc *crtc = intel_dig_port->base.base.crtc; | |
a6778b3c DV |
915 | intel_set_mode(crtc, &crtc->mode, |
916 | crtc->x, crtc->y, crtc->fb); | |
55b7d6e8 CW |
917 | } |
918 | ||
919 | return 0; | |
920 | } | |
921 | ||
7d57382e EA |
922 | static void intel_hdmi_destroy(struct drm_connector *connector) |
923 | { | |
7d57382e EA |
924 | drm_sysfs_connector_remove(connector); |
925 | drm_connector_cleanup(connector); | |
674e2d08 | 926 | kfree(connector); |
7d57382e EA |
927 | } |
928 | ||
929 | static const struct drm_encoder_helper_funcs intel_hdmi_helper_funcs = { | |
7d57382e | 930 | .mode_fixup = intel_hdmi_mode_fixup, |
7d57382e | 931 | .mode_set = intel_hdmi_mode_set, |
1f703855 | 932 | .disable = intel_encoder_noop, |
7d57382e EA |
933 | }; |
934 | ||
935 | static const struct drm_connector_funcs intel_hdmi_connector_funcs = { | |
5ab432ef | 936 | .dpms = intel_connector_dpms, |
7d57382e EA |
937 | .detect = intel_hdmi_detect, |
938 | .fill_modes = drm_helper_probe_single_connector_modes, | |
55b7d6e8 | 939 | .set_property = intel_hdmi_set_property, |
7d57382e EA |
940 | .destroy = intel_hdmi_destroy, |
941 | }; | |
942 | ||
943 | static const struct drm_connector_helper_funcs intel_hdmi_connector_helper_funcs = { | |
944 | .get_modes = intel_hdmi_get_modes, | |
945 | .mode_valid = intel_hdmi_mode_valid, | |
df0e9248 | 946 | .best_encoder = intel_best_encoder, |
7d57382e EA |
947 | }; |
948 | ||
7d57382e | 949 | static const struct drm_encoder_funcs intel_hdmi_enc_funcs = { |
ea5b213a | 950 | .destroy = intel_encoder_destroy, |
7d57382e EA |
951 | }; |
952 | ||
55b7d6e8 CW |
953 | static void |
954 | intel_hdmi_add_properties(struct intel_hdmi *intel_hdmi, struct drm_connector *connector) | |
955 | { | |
3f43c48d | 956 | intel_attach_force_audio_property(connector); |
e953fd7b | 957 | intel_attach_broadcast_rgb_property(connector); |
55b7d6e8 CW |
958 | } |
959 | ||
00c09d70 PZ |
960 | void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port, |
961 | struct intel_connector *intel_connector) | |
7d57382e | 962 | { |
b9cb234c PZ |
963 | struct drm_connector *connector = &intel_connector->base; |
964 | struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi; | |
965 | struct intel_encoder *intel_encoder = &intel_dig_port->base; | |
966 | struct drm_device *dev = intel_encoder->base.dev; | |
7d57382e | 967 | struct drm_i915_private *dev_priv = dev->dev_private; |
174edf1f | 968 | enum port port = intel_dig_port->port; |
373a3cf7 | 969 | |
7d57382e | 970 | drm_connector_init(dev, connector, &intel_hdmi_connector_funcs, |
8d91104a | 971 | DRM_MODE_CONNECTOR_HDMIA); |
7d57382e EA |
972 | drm_connector_helper_add(connector, &intel_hdmi_connector_helper_funcs); |
973 | ||
eb1f8e4f | 974 | connector->polled = DRM_CONNECTOR_POLL_HPD; |
c3febcc4 | 975 | connector->interlace_allowed = 1; |
7d57382e | 976 | connector->doublescan_allowed = 0; |
66a9278e | 977 | |
08d644ad DV |
978 | switch (port) { |
979 | case PORT_B: | |
f899fc64 | 980 | intel_hdmi->ddc_bus = GMBUS_PORT_DPB; |
b01f2c3a | 981 | dev_priv->hotplug_supported_mask |= HDMIB_HOTPLUG_INT_STATUS; |
08d644ad DV |
982 | break; |
983 | case PORT_C: | |
7ceae0a5 | 984 | intel_hdmi->ddc_bus = GMBUS_PORT_DPC; |
7ceae0a5 | 985 | dev_priv->hotplug_supported_mask |= HDMIC_HOTPLUG_INT_STATUS; |
08d644ad DV |
986 | break; |
987 | case PORT_D: | |
7ceae0a5 | 988 | intel_hdmi->ddc_bus = GMBUS_PORT_DPD; |
7ceae0a5 | 989 | dev_priv->hotplug_supported_mask |= HDMID_HOTPLUG_INT_STATUS; |
08d644ad DV |
990 | break; |
991 | case PORT_A: | |
992 | /* Internal port only for eDP. */ | |
993 | default: | |
6e4c1677 | 994 | BUG(); |
f8aed700 | 995 | } |
7d57382e | 996 | |
64a8fc01 | 997 | if (!HAS_PCH_SPLIT(dev)) { |
a3da1df7 | 998 | intel_hdmi->write_infoframe = g4x_write_infoframe; |
687f4d06 | 999 | intel_hdmi->set_infoframes = g4x_set_infoframes; |
90b107c8 SK |
1000 | } else if (IS_VALLEYVIEW(dev)) { |
1001 | intel_hdmi->write_infoframe = vlv_write_infoframe; | |
687f4d06 | 1002 | intel_hdmi->set_infoframes = vlv_set_infoframes; |
8c5f5f7c | 1003 | } else if (IS_HASWELL(dev)) { |
8c5f5f7c | 1004 | intel_hdmi->write_infoframe = hsw_write_infoframe; |
687f4d06 | 1005 | intel_hdmi->set_infoframes = hsw_set_infoframes; |
fdf1250a PZ |
1006 | } else if (HAS_PCH_IBX(dev)) { |
1007 | intel_hdmi->write_infoframe = ibx_write_infoframe; | |
687f4d06 | 1008 | intel_hdmi->set_infoframes = ibx_set_infoframes; |
fdf1250a PZ |
1009 | } else { |
1010 | intel_hdmi->write_infoframe = cpt_write_infoframe; | |
687f4d06 | 1011 | intel_hdmi->set_infoframes = cpt_set_infoframes; |
64a8fc01 | 1012 | } |
45187ace | 1013 | |
bcbc889b PZ |
1014 | if (IS_HASWELL(dev)) |
1015 | intel_connector->get_hw_state = intel_ddi_connector_get_hw_state; | |
1016 | else | |
1017 | intel_connector->get_hw_state = intel_connector_get_hw_state; | |
b9cb234c PZ |
1018 | |
1019 | intel_hdmi_add_properties(intel_hdmi, connector); | |
1020 | ||
1021 | intel_connector_attach_encoder(intel_connector, intel_encoder); | |
1022 | drm_sysfs_connector_add(connector); | |
1023 | ||
1024 | /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written | |
1025 | * 0xd. Failure to do so will result in spurious interrupts being | |
1026 | * generated on the port when a cable is not attached. | |
1027 | */ | |
1028 | if (IS_G4X(dev) && !IS_GM45(dev)) { | |
1029 | u32 temp = I915_READ(PEG_BAND_GAP_DATA); | |
1030 | I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd); | |
1031 | } | |
1032 | } | |
1033 | ||
1034 | void intel_hdmi_init(struct drm_device *dev, int sdvox_reg, enum port port) | |
1035 | { | |
1036 | struct intel_digital_port *intel_dig_port; | |
1037 | struct intel_encoder *intel_encoder; | |
1038 | struct drm_encoder *encoder; | |
1039 | struct intel_connector *intel_connector; | |
1040 | ||
1041 | intel_dig_port = kzalloc(sizeof(struct intel_digital_port), GFP_KERNEL); | |
1042 | if (!intel_dig_port) | |
1043 | return; | |
1044 | ||
1045 | intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL); | |
1046 | if (!intel_connector) { | |
1047 | kfree(intel_dig_port); | |
1048 | return; | |
1049 | } | |
1050 | ||
1051 | intel_encoder = &intel_dig_port->base; | |
1052 | encoder = &intel_encoder->base; | |
1053 | ||
1054 | drm_encoder_init(dev, &intel_encoder->base, &intel_hdmi_enc_funcs, | |
1055 | DRM_MODE_ENCODER_TMDS); | |
00c09d70 PZ |
1056 | drm_encoder_helper_add(&intel_encoder->base, &intel_hdmi_helper_funcs); |
1057 | ||
1058 | intel_encoder->enable = intel_enable_hdmi; | |
1059 | intel_encoder->disable = intel_disable_hdmi; | |
1060 | intel_encoder->get_hw_state = intel_hdmi_get_hw_state; | |
5ab432ef | 1061 | |
b9cb234c PZ |
1062 | intel_encoder->type = INTEL_OUTPUT_HDMI; |
1063 | intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2); | |
1064 | intel_encoder->cloneable = false; | |
7d57382e | 1065 | |
174edf1f | 1066 | intel_dig_port->port = port; |
b9cb234c PZ |
1067 | intel_dig_port->hdmi.sdvox_reg = sdvox_reg; |
1068 | intel_dig_port->dp.output_reg = 0; | |
55b7d6e8 | 1069 | |
b9cb234c | 1070 | intel_hdmi_init_connector(intel_dig_port, intel_connector); |
7d57382e | 1071 | } |