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7d57382e EA |
1 | /* |
2 | * Copyright 2006 Dave Airlie <airlied@linux.ie> | |
3 | * Copyright © 2006-2009 Intel Corporation | |
4 | * | |
5 | * Permission is hereby granted, free of charge, to any person obtaining a | |
6 | * copy of this software and associated documentation files (the "Software"), | |
7 | * to deal in the Software without restriction, including without limitation | |
8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
9 | * and/or sell copies of the Software, and to permit persons to whom the | |
10 | * Software is furnished to do so, subject to the following conditions: | |
11 | * | |
12 | * The above copyright notice and this permission notice (including the next | |
13 | * paragraph) shall be included in all copies or substantial portions of the | |
14 | * Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
21 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
22 | * DEALINGS IN THE SOFTWARE. | |
23 | * | |
24 | * Authors: | |
25 | * Eric Anholt <eric@anholt.net> | |
26 | * Jesse Barnes <jesse.barnes@intel.com> | |
27 | */ | |
28 | ||
29 | #include <linux/i2c.h> | |
5a0e3ad6 | 30 | #include <linux/slab.h> |
7d57382e | 31 | #include <linux/delay.h> |
178f736a | 32 | #include <linux/hdmi.h> |
760285e7 | 33 | #include <drm/drmP.h> |
c6f95f27 | 34 | #include <drm/drm_atomic_helper.h> |
760285e7 DH |
35 | #include <drm/drm_crtc.h> |
36 | #include <drm/drm_edid.h> | |
7d57382e | 37 | #include "intel_drv.h" |
760285e7 | 38 | #include <drm/i915_drm.h> |
7d57382e EA |
39 | #include "i915_drv.h" |
40 | ||
30add22d PZ |
41 | static struct drm_device *intel_hdmi_to_dev(struct intel_hdmi *intel_hdmi) |
42 | { | |
da63a9f2 | 43 | return hdmi_to_dig_port(intel_hdmi)->base.base.dev; |
30add22d PZ |
44 | } |
45 | ||
afba0188 DV |
46 | static void |
47 | assert_hdmi_port_disabled(struct intel_hdmi *intel_hdmi) | |
48 | { | |
30add22d | 49 | struct drm_device *dev = intel_hdmi_to_dev(intel_hdmi); |
afba0188 DV |
50 | struct drm_i915_private *dev_priv = dev->dev_private; |
51 | uint32_t enabled_bits; | |
52 | ||
affa9354 | 53 | enabled_bits = HAS_DDI(dev) ? DDI_BUF_CTL_ENABLE : SDVO_ENABLE; |
afba0188 | 54 | |
b242b7f7 | 55 | WARN(I915_READ(intel_hdmi->hdmi_reg) & enabled_bits, |
afba0188 DV |
56 | "HDMI port enabled, expecting disabled\n"); |
57 | } | |
58 | ||
f5bbfca3 | 59 | struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder) |
ea5b213a | 60 | { |
da63a9f2 PZ |
61 | struct intel_digital_port *intel_dig_port = |
62 | container_of(encoder, struct intel_digital_port, base.base); | |
63 | return &intel_dig_port->hdmi; | |
ea5b213a CW |
64 | } |
65 | ||
df0e9248 CW |
66 | static struct intel_hdmi *intel_attached_hdmi(struct drm_connector *connector) |
67 | { | |
da63a9f2 | 68 | return enc_to_intel_hdmi(&intel_attached_encoder(connector)->base); |
df0e9248 CW |
69 | } |
70 | ||
178f736a | 71 | static u32 g4x_infoframe_index(enum hdmi_infoframe_type type) |
3c17fe4b | 72 | { |
178f736a DL |
73 | switch (type) { |
74 | case HDMI_INFOFRAME_TYPE_AVI: | |
ed517fbb | 75 | return VIDEO_DIP_SELECT_AVI; |
178f736a | 76 | case HDMI_INFOFRAME_TYPE_SPD: |
ed517fbb | 77 | return VIDEO_DIP_SELECT_SPD; |
c8bb75af LD |
78 | case HDMI_INFOFRAME_TYPE_VENDOR: |
79 | return VIDEO_DIP_SELECT_VENDOR; | |
45187ace | 80 | default: |
178f736a | 81 | DRM_DEBUG_DRIVER("unknown info frame type %d\n", type); |
ed517fbb | 82 | return 0; |
45187ace | 83 | } |
45187ace JB |
84 | } |
85 | ||
178f736a | 86 | static u32 g4x_infoframe_enable(enum hdmi_infoframe_type type) |
45187ace | 87 | { |
178f736a DL |
88 | switch (type) { |
89 | case HDMI_INFOFRAME_TYPE_AVI: | |
ed517fbb | 90 | return VIDEO_DIP_ENABLE_AVI; |
178f736a | 91 | case HDMI_INFOFRAME_TYPE_SPD: |
ed517fbb | 92 | return VIDEO_DIP_ENABLE_SPD; |
c8bb75af LD |
93 | case HDMI_INFOFRAME_TYPE_VENDOR: |
94 | return VIDEO_DIP_ENABLE_VENDOR; | |
fa193ff7 | 95 | default: |
178f736a | 96 | DRM_DEBUG_DRIVER("unknown info frame type %d\n", type); |
ed517fbb | 97 | return 0; |
fa193ff7 | 98 | } |
fa193ff7 PZ |
99 | } |
100 | ||
178f736a | 101 | static u32 hsw_infoframe_enable(enum hdmi_infoframe_type type) |
2da8af54 | 102 | { |
178f736a DL |
103 | switch (type) { |
104 | case HDMI_INFOFRAME_TYPE_AVI: | |
2da8af54 | 105 | return VIDEO_DIP_ENABLE_AVI_HSW; |
178f736a | 106 | case HDMI_INFOFRAME_TYPE_SPD: |
2da8af54 | 107 | return VIDEO_DIP_ENABLE_SPD_HSW; |
c8bb75af LD |
108 | case HDMI_INFOFRAME_TYPE_VENDOR: |
109 | return VIDEO_DIP_ENABLE_VS_HSW; | |
2da8af54 | 110 | default: |
178f736a | 111 | DRM_DEBUG_DRIVER("unknown info frame type %d\n", type); |
2da8af54 PZ |
112 | return 0; |
113 | } | |
114 | } | |
115 | ||
178f736a | 116 | static u32 hsw_infoframe_data_reg(enum hdmi_infoframe_type type, |
a57c774a AK |
117 | enum transcoder cpu_transcoder, |
118 | struct drm_i915_private *dev_priv) | |
2da8af54 | 119 | { |
178f736a DL |
120 | switch (type) { |
121 | case HDMI_INFOFRAME_TYPE_AVI: | |
7d9bcebe | 122 | return HSW_TVIDEO_DIP_AVI_DATA(cpu_transcoder); |
178f736a | 123 | case HDMI_INFOFRAME_TYPE_SPD: |
7d9bcebe | 124 | return HSW_TVIDEO_DIP_SPD_DATA(cpu_transcoder); |
c8bb75af LD |
125 | case HDMI_INFOFRAME_TYPE_VENDOR: |
126 | return HSW_TVIDEO_DIP_VS_DATA(cpu_transcoder); | |
2da8af54 | 127 | default: |
178f736a | 128 | DRM_DEBUG_DRIVER("unknown info frame type %d\n", type); |
2da8af54 PZ |
129 | return 0; |
130 | } | |
131 | } | |
132 | ||
a3da1df7 | 133 | static void g4x_write_infoframe(struct drm_encoder *encoder, |
178f736a | 134 | enum hdmi_infoframe_type type, |
fff63867 | 135 | const void *frame, ssize_t len) |
45187ace | 136 | { |
fff63867 | 137 | const uint32_t *data = frame; |
3c17fe4b DH |
138 | struct drm_device *dev = encoder->dev; |
139 | struct drm_i915_private *dev_priv = dev->dev_private; | |
22509ec8 | 140 | u32 val = I915_READ(VIDEO_DIP_CTL); |
178f736a | 141 | int i; |
3c17fe4b | 142 | |
822974ae PZ |
143 | WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n"); |
144 | ||
1d4f85ac | 145 | val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ |
178f736a | 146 | val |= g4x_infoframe_index(type); |
22509ec8 | 147 | |
178f736a | 148 | val &= ~g4x_infoframe_enable(type); |
45187ace | 149 | |
22509ec8 | 150 | I915_WRITE(VIDEO_DIP_CTL, val); |
3c17fe4b | 151 | |
9d9740f0 | 152 | mmiowb(); |
45187ace | 153 | for (i = 0; i < len; i += 4) { |
3c17fe4b DH |
154 | I915_WRITE(VIDEO_DIP_DATA, *data); |
155 | data++; | |
156 | } | |
adf00b26 PZ |
157 | /* Write every possible data byte to force correct ECC calculation. */ |
158 | for (; i < VIDEO_DIP_DATA_SIZE; i += 4) | |
159 | I915_WRITE(VIDEO_DIP_DATA, 0); | |
9d9740f0 | 160 | mmiowb(); |
3c17fe4b | 161 | |
178f736a | 162 | val |= g4x_infoframe_enable(type); |
60c5ea2d | 163 | val &= ~VIDEO_DIP_FREQ_MASK; |
4b24c933 | 164 | val |= VIDEO_DIP_FREQ_VSYNC; |
45187ace | 165 | |
22509ec8 | 166 | I915_WRITE(VIDEO_DIP_CTL, val); |
9d9740f0 | 167 | POSTING_READ(VIDEO_DIP_CTL); |
3c17fe4b DH |
168 | } |
169 | ||
e43823ec JB |
170 | static bool g4x_infoframe_enabled(struct drm_encoder *encoder) |
171 | { | |
172 | struct drm_device *dev = encoder->dev; | |
173 | struct drm_i915_private *dev_priv = dev->dev_private; | |
89a35ecd | 174 | struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); |
e43823ec JB |
175 | u32 val = I915_READ(VIDEO_DIP_CTL); |
176 | ||
ec1dc603 VS |
177 | if ((val & VIDEO_DIP_ENABLE) == 0) |
178 | return false; | |
89a35ecd | 179 | |
ec1dc603 VS |
180 | if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(intel_dig_port->port)) |
181 | return false; | |
182 | ||
183 | return val & (VIDEO_DIP_ENABLE_AVI | | |
184 | VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD); | |
e43823ec JB |
185 | } |
186 | ||
fdf1250a | 187 | static void ibx_write_infoframe(struct drm_encoder *encoder, |
178f736a | 188 | enum hdmi_infoframe_type type, |
fff63867 | 189 | const void *frame, ssize_t len) |
fdf1250a | 190 | { |
fff63867 | 191 | const uint32_t *data = frame; |
fdf1250a PZ |
192 | struct drm_device *dev = encoder->dev; |
193 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ed517fbb | 194 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); |
178f736a | 195 | int i, reg = TVIDEO_DIP_CTL(intel_crtc->pipe); |
fdf1250a PZ |
196 | u32 val = I915_READ(reg); |
197 | ||
822974ae PZ |
198 | WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n"); |
199 | ||
fdf1250a | 200 | val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ |
178f736a | 201 | val |= g4x_infoframe_index(type); |
fdf1250a | 202 | |
178f736a | 203 | val &= ~g4x_infoframe_enable(type); |
fdf1250a PZ |
204 | |
205 | I915_WRITE(reg, val); | |
206 | ||
9d9740f0 | 207 | mmiowb(); |
fdf1250a PZ |
208 | for (i = 0; i < len; i += 4) { |
209 | I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data); | |
210 | data++; | |
211 | } | |
adf00b26 PZ |
212 | /* Write every possible data byte to force correct ECC calculation. */ |
213 | for (; i < VIDEO_DIP_DATA_SIZE; i += 4) | |
214 | I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0); | |
9d9740f0 | 215 | mmiowb(); |
fdf1250a | 216 | |
178f736a | 217 | val |= g4x_infoframe_enable(type); |
fdf1250a | 218 | val &= ~VIDEO_DIP_FREQ_MASK; |
4b24c933 | 219 | val |= VIDEO_DIP_FREQ_VSYNC; |
fdf1250a PZ |
220 | |
221 | I915_WRITE(reg, val); | |
9d9740f0 | 222 | POSTING_READ(reg); |
fdf1250a PZ |
223 | } |
224 | ||
e43823ec JB |
225 | static bool ibx_infoframe_enabled(struct drm_encoder *encoder) |
226 | { | |
227 | struct drm_device *dev = encoder->dev; | |
228 | struct drm_i915_private *dev_priv = dev->dev_private; | |
229 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); | |
052f62f7 | 230 | struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); |
e43823ec JB |
231 | int reg = TVIDEO_DIP_CTL(intel_crtc->pipe); |
232 | u32 val = I915_READ(reg); | |
233 | ||
ec1dc603 VS |
234 | if ((val & VIDEO_DIP_ENABLE) == 0) |
235 | return false; | |
236 | ||
237 | if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(intel_dig_port->port)) | |
238 | return false; | |
052f62f7 | 239 | |
ec1dc603 VS |
240 | return val & (VIDEO_DIP_ENABLE_AVI | |
241 | VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | | |
242 | VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); | |
e43823ec JB |
243 | } |
244 | ||
fdf1250a | 245 | static void cpt_write_infoframe(struct drm_encoder *encoder, |
178f736a | 246 | enum hdmi_infoframe_type type, |
fff63867 | 247 | const void *frame, ssize_t len) |
b055c8f3 | 248 | { |
fff63867 | 249 | const uint32_t *data = frame; |
b055c8f3 JB |
250 | struct drm_device *dev = encoder->dev; |
251 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ed517fbb | 252 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); |
178f736a | 253 | int i, reg = TVIDEO_DIP_CTL(intel_crtc->pipe); |
22509ec8 | 254 | u32 val = I915_READ(reg); |
b055c8f3 | 255 | |
822974ae PZ |
256 | WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n"); |
257 | ||
64a8fc01 | 258 | val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ |
178f736a | 259 | val |= g4x_infoframe_index(type); |
45187ace | 260 | |
ecb97851 PZ |
261 | /* The DIP control register spec says that we need to update the AVI |
262 | * infoframe without clearing its enable bit */ | |
178f736a DL |
263 | if (type != HDMI_INFOFRAME_TYPE_AVI) |
264 | val &= ~g4x_infoframe_enable(type); | |
ecb97851 | 265 | |
22509ec8 | 266 | I915_WRITE(reg, val); |
45187ace | 267 | |
9d9740f0 | 268 | mmiowb(); |
45187ace | 269 | for (i = 0; i < len; i += 4) { |
b055c8f3 JB |
270 | I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data); |
271 | data++; | |
272 | } | |
adf00b26 PZ |
273 | /* Write every possible data byte to force correct ECC calculation. */ |
274 | for (; i < VIDEO_DIP_DATA_SIZE; i += 4) | |
275 | I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0); | |
9d9740f0 | 276 | mmiowb(); |
b055c8f3 | 277 | |
178f736a | 278 | val |= g4x_infoframe_enable(type); |
60c5ea2d | 279 | val &= ~VIDEO_DIP_FREQ_MASK; |
4b24c933 | 280 | val |= VIDEO_DIP_FREQ_VSYNC; |
45187ace | 281 | |
22509ec8 | 282 | I915_WRITE(reg, val); |
9d9740f0 | 283 | POSTING_READ(reg); |
45187ace | 284 | } |
90b107c8 | 285 | |
e43823ec JB |
286 | static bool cpt_infoframe_enabled(struct drm_encoder *encoder) |
287 | { | |
288 | struct drm_device *dev = encoder->dev; | |
289 | struct drm_i915_private *dev_priv = dev->dev_private; | |
290 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); | |
291 | int reg = TVIDEO_DIP_CTL(intel_crtc->pipe); | |
292 | u32 val = I915_READ(reg); | |
293 | ||
ec1dc603 VS |
294 | if ((val & VIDEO_DIP_ENABLE) == 0) |
295 | return false; | |
296 | ||
297 | return val & (VIDEO_DIP_ENABLE_AVI | | |
298 | VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | | |
299 | VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); | |
e43823ec JB |
300 | } |
301 | ||
90b107c8 | 302 | static void vlv_write_infoframe(struct drm_encoder *encoder, |
178f736a | 303 | enum hdmi_infoframe_type type, |
fff63867 | 304 | const void *frame, ssize_t len) |
90b107c8 | 305 | { |
fff63867 | 306 | const uint32_t *data = frame; |
90b107c8 SK |
307 | struct drm_device *dev = encoder->dev; |
308 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ed517fbb | 309 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); |
178f736a | 310 | int i, reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe); |
22509ec8 | 311 | u32 val = I915_READ(reg); |
90b107c8 | 312 | |
822974ae PZ |
313 | WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n"); |
314 | ||
90b107c8 | 315 | val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ |
178f736a | 316 | val |= g4x_infoframe_index(type); |
22509ec8 | 317 | |
178f736a | 318 | val &= ~g4x_infoframe_enable(type); |
90b107c8 | 319 | |
22509ec8 | 320 | I915_WRITE(reg, val); |
90b107c8 | 321 | |
9d9740f0 | 322 | mmiowb(); |
90b107c8 SK |
323 | for (i = 0; i < len; i += 4) { |
324 | I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), *data); | |
325 | data++; | |
326 | } | |
adf00b26 PZ |
327 | /* Write every possible data byte to force correct ECC calculation. */ |
328 | for (; i < VIDEO_DIP_DATA_SIZE; i += 4) | |
329 | I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), 0); | |
9d9740f0 | 330 | mmiowb(); |
90b107c8 | 331 | |
178f736a | 332 | val |= g4x_infoframe_enable(type); |
60c5ea2d | 333 | val &= ~VIDEO_DIP_FREQ_MASK; |
4b24c933 | 334 | val |= VIDEO_DIP_FREQ_VSYNC; |
90b107c8 | 335 | |
22509ec8 | 336 | I915_WRITE(reg, val); |
9d9740f0 | 337 | POSTING_READ(reg); |
90b107c8 SK |
338 | } |
339 | ||
e43823ec JB |
340 | static bool vlv_infoframe_enabled(struct drm_encoder *encoder) |
341 | { | |
342 | struct drm_device *dev = encoder->dev; | |
343 | struct drm_i915_private *dev_priv = dev->dev_private; | |
344 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); | |
535afa2e | 345 | struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); |
e43823ec JB |
346 | int reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe); |
347 | u32 val = I915_READ(reg); | |
348 | ||
ec1dc603 VS |
349 | if ((val & VIDEO_DIP_ENABLE) == 0) |
350 | return false; | |
351 | ||
352 | if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(intel_dig_port->port)) | |
353 | return false; | |
535afa2e | 354 | |
ec1dc603 VS |
355 | return val & (VIDEO_DIP_ENABLE_AVI | |
356 | VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | | |
357 | VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); | |
e43823ec JB |
358 | } |
359 | ||
8c5f5f7c | 360 | static void hsw_write_infoframe(struct drm_encoder *encoder, |
178f736a | 361 | enum hdmi_infoframe_type type, |
fff63867 | 362 | const void *frame, ssize_t len) |
8c5f5f7c | 363 | { |
fff63867 | 364 | const uint32_t *data = frame; |
2da8af54 PZ |
365 | struct drm_device *dev = encoder->dev; |
366 | struct drm_i915_private *dev_priv = dev->dev_private; | |
367 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); | |
6e3c9717 | 368 | u32 ctl_reg = HSW_TVIDEO_DIP_CTL(intel_crtc->config->cpu_transcoder); |
178f736a DL |
369 | u32 data_reg; |
370 | int i; | |
2da8af54 | 371 | u32 val = I915_READ(ctl_reg); |
8c5f5f7c | 372 | |
178f736a | 373 | data_reg = hsw_infoframe_data_reg(type, |
6e3c9717 | 374 | intel_crtc->config->cpu_transcoder, |
a57c774a | 375 | dev_priv); |
2da8af54 PZ |
376 | if (data_reg == 0) |
377 | return; | |
378 | ||
178f736a | 379 | val &= ~hsw_infoframe_enable(type); |
2da8af54 PZ |
380 | I915_WRITE(ctl_reg, val); |
381 | ||
9d9740f0 | 382 | mmiowb(); |
2da8af54 PZ |
383 | for (i = 0; i < len; i += 4) { |
384 | I915_WRITE(data_reg + i, *data); | |
385 | data++; | |
386 | } | |
adf00b26 PZ |
387 | /* Write every possible data byte to force correct ECC calculation. */ |
388 | for (; i < VIDEO_DIP_DATA_SIZE; i += 4) | |
389 | I915_WRITE(data_reg + i, 0); | |
9d9740f0 | 390 | mmiowb(); |
8c5f5f7c | 391 | |
178f736a | 392 | val |= hsw_infoframe_enable(type); |
2da8af54 | 393 | I915_WRITE(ctl_reg, val); |
9d9740f0 | 394 | POSTING_READ(ctl_reg); |
8c5f5f7c ED |
395 | } |
396 | ||
e43823ec JB |
397 | static bool hsw_infoframe_enabled(struct drm_encoder *encoder) |
398 | { | |
399 | struct drm_device *dev = encoder->dev; | |
400 | struct drm_i915_private *dev_priv = dev->dev_private; | |
401 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); | |
6e3c9717 | 402 | u32 ctl_reg = HSW_TVIDEO_DIP_CTL(intel_crtc->config->cpu_transcoder); |
e43823ec JB |
403 | u32 val = I915_READ(ctl_reg); |
404 | ||
ec1dc603 VS |
405 | return val & (VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_AVI_HSW | |
406 | VIDEO_DIP_ENABLE_GCP_HSW | VIDEO_DIP_ENABLE_VS_HSW | | |
407 | VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW); | |
e43823ec JB |
408 | } |
409 | ||
5adaea79 DL |
410 | /* |
411 | * The data we write to the DIP data buffer registers is 1 byte bigger than the | |
412 | * HDMI infoframe size because of an ECC/reserved byte at position 3 (starting | |
413 | * at 0). It's also a byte used by DisplayPort so the same DIP registers can be | |
414 | * used for both technologies. | |
415 | * | |
416 | * DW0: Reserved/ECC/DP | HB2 | HB1 | HB0 | |
417 | * DW1: DB3 | DB2 | DB1 | DB0 | |
418 | * DW2: DB7 | DB6 | DB5 | DB4 | |
419 | * DW3: ... | |
420 | * | |
421 | * (HB is Header Byte, DB is Data Byte) | |
422 | * | |
423 | * The hdmi pack() functions don't know about that hardware specific hole so we | |
424 | * trick them by giving an offset into the buffer and moving back the header | |
425 | * bytes by one. | |
426 | */ | |
9198ee5b DL |
427 | static void intel_write_infoframe(struct drm_encoder *encoder, |
428 | union hdmi_infoframe *frame) | |
45187ace JB |
429 | { |
430 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); | |
5adaea79 DL |
431 | uint8_t buffer[VIDEO_DIP_DATA_SIZE]; |
432 | ssize_t len; | |
45187ace | 433 | |
5adaea79 DL |
434 | /* see comment above for the reason for this offset */ |
435 | len = hdmi_infoframe_pack(frame, buffer + 1, sizeof(buffer) - 1); | |
436 | if (len < 0) | |
437 | return; | |
438 | ||
439 | /* Insert the 'hole' (see big comment above) at position 3 */ | |
440 | buffer[0] = buffer[1]; | |
441 | buffer[1] = buffer[2]; | |
442 | buffer[2] = buffer[3]; | |
443 | buffer[3] = 0; | |
444 | len++; | |
45187ace | 445 | |
5adaea79 | 446 | intel_hdmi->write_infoframe(encoder, frame->any.type, buffer, len); |
45187ace JB |
447 | } |
448 | ||
687f4d06 | 449 | static void intel_hdmi_set_avi_infoframe(struct drm_encoder *encoder, |
c846b619 | 450 | struct drm_display_mode *adjusted_mode) |
45187ace | 451 | { |
abedc077 | 452 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); |
50f3b016 | 453 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); |
5adaea79 DL |
454 | union hdmi_infoframe frame; |
455 | int ret; | |
45187ace | 456 | |
94a11ddc VK |
457 | /* Set user selected PAR to incoming mode's member */ |
458 | adjusted_mode->picture_aspect_ratio = intel_hdmi->aspect_ratio; | |
459 | ||
5adaea79 DL |
460 | ret = drm_hdmi_avi_infoframe_from_display_mode(&frame.avi, |
461 | adjusted_mode); | |
462 | if (ret < 0) { | |
463 | DRM_ERROR("couldn't fill AVI infoframe\n"); | |
464 | return; | |
465 | } | |
c846b619 | 466 | |
abedc077 | 467 | if (intel_hdmi->rgb_quant_range_selectable) { |
6e3c9717 | 468 | if (intel_crtc->config->limited_color_range) |
5adaea79 DL |
469 | frame.avi.quantization_range = |
470 | HDMI_QUANTIZATION_RANGE_LIMITED; | |
abedc077 | 471 | else |
5adaea79 DL |
472 | frame.avi.quantization_range = |
473 | HDMI_QUANTIZATION_RANGE_FULL; | |
abedc077 VS |
474 | } |
475 | ||
9198ee5b | 476 | intel_write_infoframe(encoder, &frame); |
b055c8f3 JB |
477 | } |
478 | ||
687f4d06 | 479 | static void intel_hdmi_set_spd_infoframe(struct drm_encoder *encoder) |
c0864cb3 | 480 | { |
5adaea79 DL |
481 | union hdmi_infoframe frame; |
482 | int ret; | |
483 | ||
484 | ret = hdmi_spd_infoframe_init(&frame.spd, "Intel", "Integrated gfx"); | |
485 | if (ret < 0) { | |
486 | DRM_ERROR("couldn't fill SPD infoframe\n"); | |
487 | return; | |
488 | } | |
c0864cb3 | 489 | |
5adaea79 | 490 | frame.spd.sdi = HDMI_SPD_SDI_PC; |
c0864cb3 | 491 | |
9198ee5b | 492 | intel_write_infoframe(encoder, &frame); |
c0864cb3 JB |
493 | } |
494 | ||
c8bb75af LD |
495 | static void |
496 | intel_hdmi_set_hdmi_infoframe(struct drm_encoder *encoder, | |
497 | struct drm_display_mode *adjusted_mode) | |
498 | { | |
499 | union hdmi_infoframe frame; | |
500 | int ret; | |
501 | ||
502 | ret = drm_hdmi_vendor_infoframe_from_display_mode(&frame.vendor.hdmi, | |
503 | adjusted_mode); | |
504 | if (ret < 0) | |
505 | return; | |
506 | ||
507 | intel_write_infoframe(encoder, &frame); | |
508 | } | |
509 | ||
687f4d06 | 510 | static void g4x_set_infoframes(struct drm_encoder *encoder, |
6897b4b5 | 511 | bool enable, |
687f4d06 PZ |
512 | struct drm_display_mode *adjusted_mode) |
513 | { | |
0c14c7f9 | 514 | struct drm_i915_private *dev_priv = encoder->dev->dev_private; |
69fde0a6 VS |
515 | struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); |
516 | struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi; | |
0c14c7f9 PZ |
517 | u32 reg = VIDEO_DIP_CTL; |
518 | u32 val = I915_READ(reg); | |
822cdc52 | 519 | u32 port = VIDEO_DIP_PORT(intel_dig_port->port); |
0c14c7f9 | 520 | |
afba0188 DV |
521 | assert_hdmi_port_disabled(intel_hdmi); |
522 | ||
0c14c7f9 PZ |
523 | /* If the registers were not initialized yet, they might be zeroes, |
524 | * which means we're selecting the AVI DIP and we're setting its | |
525 | * frequency to once. This seems to really confuse the HW and make | |
526 | * things stop working (the register spec says the AVI always needs to | |
527 | * be sent every VSync). So here we avoid writing to the register more | |
528 | * than we need and also explicitly select the AVI DIP and explicitly | |
529 | * set its frequency to every VSync. Avoiding to write it twice seems to | |
530 | * be enough to solve the problem, but being defensive shouldn't hurt us | |
531 | * either. */ | |
532 | val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; | |
533 | ||
6897b4b5 | 534 | if (!enable) { |
0c14c7f9 PZ |
535 | if (!(val & VIDEO_DIP_ENABLE)) |
536 | return; | |
0be6f0c8 VS |
537 | if (port != (val & VIDEO_DIP_PORT_MASK)) { |
538 | DRM_DEBUG_KMS("video DIP still enabled on port %c\n", | |
539 | (val & VIDEO_DIP_PORT_MASK) >> 29); | |
540 | return; | |
541 | } | |
542 | val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI | | |
543 | VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD); | |
0c14c7f9 | 544 | I915_WRITE(reg, val); |
9d9740f0 | 545 | POSTING_READ(reg); |
0c14c7f9 PZ |
546 | return; |
547 | } | |
548 | ||
72b78c9d PZ |
549 | if (port != (val & VIDEO_DIP_PORT_MASK)) { |
550 | if (val & VIDEO_DIP_ENABLE) { | |
0be6f0c8 VS |
551 | DRM_DEBUG_KMS("video DIP already enabled on port %c\n", |
552 | (val & VIDEO_DIP_PORT_MASK) >> 29); | |
553 | return; | |
72b78c9d PZ |
554 | } |
555 | val &= ~VIDEO_DIP_PORT_MASK; | |
556 | val |= port; | |
557 | } | |
558 | ||
822974ae | 559 | val |= VIDEO_DIP_ENABLE; |
0be6f0c8 VS |
560 | val &= ~(VIDEO_DIP_ENABLE_AVI | |
561 | VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD); | |
822974ae | 562 | |
f278d972 | 563 | I915_WRITE(reg, val); |
9d9740f0 | 564 | POSTING_READ(reg); |
f278d972 | 565 | |
687f4d06 PZ |
566 | intel_hdmi_set_avi_infoframe(encoder, adjusted_mode); |
567 | intel_hdmi_set_spd_infoframe(encoder); | |
c8bb75af | 568 | intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode); |
687f4d06 PZ |
569 | } |
570 | ||
6d67415f VS |
571 | static bool hdmi_sink_is_deep_color(struct drm_encoder *encoder) |
572 | { | |
573 | struct drm_device *dev = encoder->dev; | |
574 | struct drm_connector *connector; | |
575 | ||
576 | WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex)); | |
577 | ||
578 | /* | |
579 | * HDMI cloning is only supported on g4x which doesn't | |
580 | * support deep color or GCP infoframes anyway so no | |
581 | * need to worry about multiple HDMI sinks here. | |
582 | */ | |
583 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) | |
584 | if (connector->encoder == encoder) | |
585 | return connector->display_info.bpc > 8; | |
586 | ||
587 | return false; | |
588 | } | |
589 | ||
12aa3290 VS |
590 | /* |
591 | * Determine if default_phase=1 can be indicated in the GCP infoframe. | |
592 | * | |
593 | * From HDMI specification 1.4a: | |
594 | * - The first pixel of each Video Data Period shall always have a pixel packing phase of 0 | |
595 | * - The first pixel following each Video Data Period shall have a pixel packing phase of 0 | |
596 | * - The PP bits shall be constant for all GCPs and will be equal to the last packing phase | |
597 | * - The first pixel following every transition of HSYNC or VSYNC shall have a pixel packing | |
598 | * phase of 0 | |
599 | */ | |
600 | static bool gcp_default_phase_possible(int pipe_bpp, | |
601 | const struct drm_display_mode *mode) | |
602 | { | |
603 | unsigned int pixels_per_group; | |
604 | ||
605 | switch (pipe_bpp) { | |
606 | case 30: | |
607 | /* 4 pixels in 5 clocks */ | |
608 | pixels_per_group = 4; | |
609 | break; | |
610 | case 36: | |
611 | /* 2 pixels in 3 clocks */ | |
612 | pixels_per_group = 2; | |
613 | break; | |
614 | case 48: | |
615 | /* 1 pixel in 2 clocks */ | |
616 | pixels_per_group = 1; | |
617 | break; | |
618 | default: | |
619 | /* phase information not relevant for 8bpc */ | |
620 | return false; | |
621 | } | |
622 | ||
623 | return mode->crtc_hdisplay % pixels_per_group == 0 && | |
624 | mode->crtc_htotal % pixels_per_group == 0 && | |
625 | mode->crtc_hblank_start % pixels_per_group == 0 && | |
626 | mode->crtc_hblank_end % pixels_per_group == 0 && | |
627 | mode->crtc_hsync_start % pixels_per_group == 0 && | |
628 | mode->crtc_hsync_end % pixels_per_group == 0 && | |
629 | ((mode->flags & DRM_MODE_FLAG_INTERLACE) == 0 || | |
630 | mode->crtc_htotal/2 % pixels_per_group == 0); | |
631 | } | |
632 | ||
6d67415f VS |
633 | static bool intel_hdmi_set_gcp_infoframe(struct drm_encoder *encoder) |
634 | { | |
635 | struct drm_i915_private *dev_priv = encoder->dev->dev_private; | |
636 | struct intel_crtc *crtc = to_intel_crtc(encoder->crtc); | |
637 | u32 reg, val = 0; | |
638 | ||
639 | if (HAS_DDI(dev_priv)) | |
640 | reg = HSW_TVIDEO_DIP_GCP(crtc->config->cpu_transcoder); | |
641 | else if (IS_VALLEYVIEW(dev_priv)) | |
642 | reg = VLV_TVIDEO_DIP_GCP(crtc->pipe); | |
643 | else if (HAS_PCH_SPLIT(dev_priv->dev)) | |
644 | reg = TVIDEO_DIP_GCP(crtc->pipe); | |
645 | else | |
646 | return false; | |
647 | ||
648 | /* Indicate color depth whenever the sink supports deep color */ | |
649 | if (hdmi_sink_is_deep_color(encoder)) | |
650 | val |= GCP_COLOR_INDICATION; | |
651 | ||
12aa3290 VS |
652 | /* Enable default_phase whenever the display mode is suitably aligned */ |
653 | if (gcp_default_phase_possible(crtc->config->pipe_bpp, | |
654 | &crtc->config->base.adjusted_mode)) | |
655 | val |= GCP_DEFAULT_PHASE_ENABLE; | |
656 | ||
6d67415f VS |
657 | I915_WRITE(reg, val); |
658 | ||
659 | return val != 0; | |
660 | } | |
661 | ||
687f4d06 | 662 | static void ibx_set_infoframes(struct drm_encoder *encoder, |
6897b4b5 | 663 | bool enable, |
687f4d06 PZ |
664 | struct drm_display_mode *adjusted_mode) |
665 | { | |
0c14c7f9 PZ |
666 | struct drm_i915_private *dev_priv = encoder->dev->dev_private; |
667 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); | |
69fde0a6 VS |
668 | struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); |
669 | struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi; | |
0c14c7f9 PZ |
670 | u32 reg = TVIDEO_DIP_CTL(intel_crtc->pipe); |
671 | u32 val = I915_READ(reg); | |
822cdc52 | 672 | u32 port = VIDEO_DIP_PORT(intel_dig_port->port); |
0c14c7f9 | 673 | |
afba0188 DV |
674 | assert_hdmi_port_disabled(intel_hdmi); |
675 | ||
0c14c7f9 PZ |
676 | /* See the big comment in g4x_set_infoframes() */ |
677 | val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; | |
678 | ||
6897b4b5 | 679 | if (!enable) { |
0c14c7f9 PZ |
680 | if (!(val & VIDEO_DIP_ENABLE)) |
681 | return; | |
0be6f0c8 VS |
682 | val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI | |
683 | VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | | |
684 | VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); | |
0c14c7f9 | 685 | I915_WRITE(reg, val); |
9d9740f0 | 686 | POSTING_READ(reg); |
0c14c7f9 PZ |
687 | return; |
688 | } | |
689 | ||
72b78c9d | 690 | if (port != (val & VIDEO_DIP_PORT_MASK)) { |
0be6f0c8 VS |
691 | WARN(val & VIDEO_DIP_ENABLE, |
692 | "DIP already enabled on port %c\n", | |
693 | (val & VIDEO_DIP_PORT_MASK) >> 29); | |
72b78c9d PZ |
694 | val &= ~VIDEO_DIP_PORT_MASK; |
695 | val |= port; | |
696 | } | |
697 | ||
822974ae | 698 | val |= VIDEO_DIP_ENABLE; |
0be6f0c8 VS |
699 | val &= ~(VIDEO_DIP_ENABLE_AVI | |
700 | VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | | |
701 | VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); | |
822974ae | 702 | |
6d67415f VS |
703 | if (intel_hdmi_set_gcp_infoframe(encoder)) |
704 | val |= VIDEO_DIP_ENABLE_GCP; | |
705 | ||
f278d972 | 706 | I915_WRITE(reg, val); |
9d9740f0 | 707 | POSTING_READ(reg); |
f278d972 | 708 | |
687f4d06 PZ |
709 | intel_hdmi_set_avi_infoframe(encoder, adjusted_mode); |
710 | intel_hdmi_set_spd_infoframe(encoder); | |
c8bb75af | 711 | intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode); |
687f4d06 PZ |
712 | } |
713 | ||
714 | static void cpt_set_infoframes(struct drm_encoder *encoder, | |
6897b4b5 | 715 | bool enable, |
687f4d06 PZ |
716 | struct drm_display_mode *adjusted_mode) |
717 | { | |
0c14c7f9 PZ |
718 | struct drm_i915_private *dev_priv = encoder->dev->dev_private; |
719 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); | |
720 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); | |
721 | u32 reg = TVIDEO_DIP_CTL(intel_crtc->pipe); | |
722 | u32 val = I915_READ(reg); | |
723 | ||
afba0188 DV |
724 | assert_hdmi_port_disabled(intel_hdmi); |
725 | ||
0c14c7f9 PZ |
726 | /* See the big comment in g4x_set_infoframes() */ |
727 | val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; | |
728 | ||
6897b4b5 | 729 | if (!enable) { |
0c14c7f9 PZ |
730 | if (!(val & VIDEO_DIP_ENABLE)) |
731 | return; | |
0be6f0c8 VS |
732 | val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI | |
733 | VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | | |
734 | VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); | |
0c14c7f9 | 735 | I915_WRITE(reg, val); |
9d9740f0 | 736 | POSTING_READ(reg); |
0c14c7f9 PZ |
737 | return; |
738 | } | |
739 | ||
822974ae PZ |
740 | /* Set both together, unset both together: see the spec. */ |
741 | val |= VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI; | |
0dd87d20 | 742 | val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | |
0be6f0c8 | 743 | VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); |
822974ae | 744 | |
6d67415f VS |
745 | if (intel_hdmi_set_gcp_infoframe(encoder)) |
746 | val |= VIDEO_DIP_ENABLE_GCP; | |
747 | ||
822974ae | 748 | I915_WRITE(reg, val); |
9d9740f0 | 749 | POSTING_READ(reg); |
822974ae | 750 | |
687f4d06 PZ |
751 | intel_hdmi_set_avi_infoframe(encoder, adjusted_mode); |
752 | intel_hdmi_set_spd_infoframe(encoder); | |
c8bb75af | 753 | intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode); |
687f4d06 PZ |
754 | } |
755 | ||
756 | static void vlv_set_infoframes(struct drm_encoder *encoder, | |
6897b4b5 | 757 | bool enable, |
687f4d06 PZ |
758 | struct drm_display_mode *adjusted_mode) |
759 | { | |
0c14c7f9 | 760 | struct drm_i915_private *dev_priv = encoder->dev->dev_private; |
6a2b8021 | 761 | struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); |
0c14c7f9 PZ |
762 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); |
763 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); | |
764 | u32 reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe); | |
765 | u32 val = I915_READ(reg); | |
6a2b8021 | 766 | u32 port = VIDEO_DIP_PORT(intel_dig_port->port); |
0c14c7f9 | 767 | |
afba0188 DV |
768 | assert_hdmi_port_disabled(intel_hdmi); |
769 | ||
0c14c7f9 PZ |
770 | /* See the big comment in g4x_set_infoframes() */ |
771 | val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; | |
772 | ||
6897b4b5 | 773 | if (!enable) { |
0c14c7f9 PZ |
774 | if (!(val & VIDEO_DIP_ENABLE)) |
775 | return; | |
0be6f0c8 VS |
776 | val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI | |
777 | VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | | |
778 | VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); | |
0c14c7f9 | 779 | I915_WRITE(reg, val); |
9d9740f0 | 780 | POSTING_READ(reg); |
0c14c7f9 PZ |
781 | return; |
782 | } | |
783 | ||
6a2b8021 | 784 | if (port != (val & VIDEO_DIP_PORT_MASK)) { |
0be6f0c8 VS |
785 | WARN(val & VIDEO_DIP_ENABLE, |
786 | "DIP already enabled on port %c\n", | |
787 | (val & VIDEO_DIP_PORT_MASK) >> 29); | |
6a2b8021 JB |
788 | val &= ~VIDEO_DIP_PORT_MASK; |
789 | val |= port; | |
790 | } | |
791 | ||
822974ae | 792 | val |= VIDEO_DIP_ENABLE; |
0be6f0c8 VS |
793 | val &= ~(VIDEO_DIP_ENABLE_AVI | |
794 | VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | | |
795 | VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); | |
822974ae | 796 | |
6d67415f VS |
797 | if (intel_hdmi_set_gcp_infoframe(encoder)) |
798 | val |= VIDEO_DIP_ENABLE_GCP; | |
799 | ||
822974ae | 800 | I915_WRITE(reg, val); |
9d9740f0 | 801 | POSTING_READ(reg); |
822974ae | 802 | |
687f4d06 PZ |
803 | intel_hdmi_set_avi_infoframe(encoder, adjusted_mode); |
804 | intel_hdmi_set_spd_infoframe(encoder); | |
c8bb75af | 805 | intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode); |
687f4d06 PZ |
806 | } |
807 | ||
808 | static void hsw_set_infoframes(struct drm_encoder *encoder, | |
6897b4b5 | 809 | bool enable, |
687f4d06 PZ |
810 | struct drm_display_mode *adjusted_mode) |
811 | { | |
0c14c7f9 PZ |
812 | struct drm_i915_private *dev_priv = encoder->dev->dev_private; |
813 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); | |
814 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); | |
6e3c9717 | 815 | u32 reg = HSW_TVIDEO_DIP_CTL(intel_crtc->config->cpu_transcoder); |
0dd87d20 | 816 | u32 val = I915_READ(reg); |
0c14c7f9 | 817 | |
afba0188 DV |
818 | assert_hdmi_port_disabled(intel_hdmi); |
819 | ||
0be6f0c8 VS |
820 | val &= ~(VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_AVI_HSW | |
821 | VIDEO_DIP_ENABLE_GCP_HSW | VIDEO_DIP_ENABLE_VS_HSW | | |
822 | VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW); | |
823 | ||
6897b4b5 | 824 | if (!enable) { |
0be6f0c8 | 825 | I915_WRITE(reg, val); |
9d9740f0 | 826 | POSTING_READ(reg); |
0c14c7f9 PZ |
827 | return; |
828 | } | |
829 | ||
6d67415f VS |
830 | if (intel_hdmi_set_gcp_infoframe(encoder)) |
831 | val |= VIDEO_DIP_ENABLE_GCP_HSW; | |
832 | ||
0dd87d20 | 833 | I915_WRITE(reg, val); |
9d9740f0 | 834 | POSTING_READ(reg); |
0dd87d20 | 835 | |
687f4d06 PZ |
836 | intel_hdmi_set_avi_infoframe(encoder, adjusted_mode); |
837 | intel_hdmi_set_spd_infoframe(encoder); | |
c8bb75af | 838 | intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode); |
687f4d06 PZ |
839 | } |
840 | ||
4cde8a21 | 841 | static void intel_hdmi_prepare(struct intel_encoder *encoder) |
7d57382e | 842 | { |
c59423a3 | 843 | struct drm_device *dev = encoder->base.dev; |
7d57382e | 844 | struct drm_i915_private *dev_priv = dev->dev_private; |
c59423a3 DV |
845 | struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); |
846 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); | |
6e3c9717 | 847 | struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode; |
b242b7f7 | 848 | u32 hdmi_val; |
7d57382e | 849 | |
b242b7f7 | 850 | hdmi_val = SDVO_ENCODING_HDMI; |
2af2c490 | 851 | if (!HAS_PCH_SPLIT(dev)) |
b242b7f7 | 852 | hdmi_val |= intel_hdmi->color_range; |
b599c0bc | 853 | if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) |
b242b7f7 | 854 | hdmi_val |= SDVO_VSYNC_ACTIVE_HIGH; |
b599c0bc | 855 | if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) |
b242b7f7 | 856 | hdmi_val |= SDVO_HSYNC_ACTIVE_HIGH; |
7d57382e | 857 | |
6e3c9717 | 858 | if (crtc->config->pipe_bpp > 24) |
4f3a8bc7 | 859 | hdmi_val |= HDMI_COLOR_FORMAT_12bpc; |
020f6704 | 860 | else |
4f3a8bc7 | 861 | hdmi_val |= SDVO_COLOR_FORMAT_8bpc; |
020f6704 | 862 | |
6e3c9717 | 863 | if (crtc->config->has_hdmi_sink) |
dc0fa718 | 864 | hdmi_val |= HDMI_MODE_SELECT_HDMI; |
2e3d6006 | 865 | |
75770564 | 866 | if (HAS_PCH_CPT(dev)) |
c59423a3 | 867 | hdmi_val |= SDVO_PIPE_SEL_CPT(crtc->pipe); |
44f37d1f CML |
868 | else if (IS_CHERRYVIEW(dev)) |
869 | hdmi_val |= SDVO_PIPE_SEL_CHV(crtc->pipe); | |
dc0fa718 | 870 | else |
c59423a3 | 871 | hdmi_val |= SDVO_PIPE_SEL(crtc->pipe); |
7d57382e | 872 | |
b242b7f7 PZ |
873 | I915_WRITE(intel_hdmi->hdmi_reg, hdmi_val); |
874 | POSTING_READ(intel_hdmi->hdmi_reg); | |
7d57382e EA |
875 | } |
876 | ||
85234cdc DV |
877 | static bool intel_hdmi_get_hw_state(struct intel_encoder *encoder, |
878 | enum pipe *pipe) | |
7d57382e | 879 | { |
85234cdc | 880 | struct drm_device *dev = encoder->base.dev; |
7d57382e | 881 | struct drm_i915_private *dev_priv = dev->dev_private; |
85234cdc | 882 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); |
6d129bea | 883 | enum intel_display_power_domain power_domain; |
85234cdc DV |
884 | u32 tmp; |
885 | ||
6d129bea | 886 | power_domain = intel_display_port_power_domain(encoder); |
f458ebbc | 887 | if (!intel_display_power_is_enabled(dev_priv, power_domain)) |
6d129bea ID |
888 | return false; |
889 | ||
b242b7f7 | 890 | tmp = I915_READ(intel_hdmi->hdmi_reg); |
85234cdc DV |
891 | |
892 | if (!(tmp & SDVO_ENABLE)) | |
893 | return false; | |
894 | ||
895 | if (HAS_PCH_CPT(dev)) | |
896 | *pipe = PORT_TO_PIPE_CPT(tmp); | |
71485e0a VS |
897 | else if (IS_CHERRYVIEW(dev)) |
898 | *pipe = SDVO_PORT_TO_PIPE_CHV(tmp); | |
85234cdc DV |
899 | else |
900 | *pipe = PORT_TO_PIPE(tmp); | |
901 | ||
902 | return true; | |
903 | } | |
904 | ||
045ac3b5 | 905 | static void intel_hdmi_get_config(struct intel_encoder *encoder, |
5cec258b | 906 | struct intel_crtc_state *pipe_config) |
045ac3b5 JB |
907 | { |
908 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); | |
8c875fca VS |
909 | struct drm_device *dev = encoder->base.dev; |
910 | struct drm_i915_private *dev_priv = dev->dev_private; | |
045ac3b5 | 911 | u32 tmp, flags = 0; |
18442d08 | 912 | int dotclock; |
045ac3b5 JB |
913 | |
914 | tmp = I915_READ(intel_hdmi->hdmi_reg); | |
915 | ||
916 | if (tmp & SDVO_HSYNC_ACTIVE_HIGH) | |
917 | flags |= DRM_MODE_FLAG_PHSYNC; | |
918 | else | |
919 | flags |= DRM_MODE_FLAG_NHSYNC; | |
920 | ||
921 | if (tmp & SDVO_VSYNC_ACTIVE_HIGH) | |
922 | flags |= DRM_MODE_FLAG_PVSYNC; | |
923 | else | |
924 | flags |= DRM_MODE_FLAG_NVSYNC; | |
925 | ||
6897b4b5 DV |
926 | if (tmp & HDMI_MODE_SELECT_HDMI) |
927 | pipe_config->has_hdmi_sink = true; | |
928 | ||
e43823ec JB |
929 | if (intel_hdmi->infoframe_enabled(&encoder->base)) |
930 | pipe_config->has_infoframe = true; | |
931 | ||
c84db770 | 932 | if (tmp & SDVO_AUDIO_ENABLE) |
9ed109a7 DV |
933 | pipe_config->has_audio = true; |
934 | ||
8c875fca VS |
935 | if (!HAS_PCH_SPLIT(dev) && |
936 | tmp & HDMI_COLOR_RANGE_16_235) | |
937 | pipe_config->limited_color_range = true; | |
938 | ||
2d112de7 | 939 | pipe_config->base.adjusted_mode.flags |= flags; |
18442d08 VS |
940 | |
941 | if ((tmp & SDVO_COLOR_FORMAT_MASK) == HDMI_COLOR_FORMAT_12bpc) | |
942 | dotclock = pipe_config->port_clock * 2 / 3; | |
943 | else | |
944 | dotclock = pipe_config->port_clock; | |
945 | ||
be69a133 VS |
946 | if (pipe_config->pixel_multiplier) |
947 | dotclock /= pipe_config->pixel_multiplier; | |
948 | ||
18442d08 VS |
949 | if (HAS_PCH_SPLIT(dev_priv->dev)) |
950 | ironlake_check_encoder_dotclock(pipe_config, dotclock); | |
951 | ||
2d112de7 | 952 | pipe_config->base.adjusted_mode.crtc_clock = dotclock; |
045ac3b5 JB |
953 | } |
954 | ||
d1b1589c VS |
955 | static void intel_enable_hdmi_audio(struct intel_encoder *encoder) |
956 | { | |
957 | struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); | |
958 | ||
959 | WARN_ON(!crtc->config->has_hdmi_sink); | |
960 | DRM_DEBUG_DRIVER("Enabling HDMI audio on pipe %c\n", | |
961 | pipe_name(crtc->pipe)); | |
962 | intel_audio_codec_enable(encoder); | |
963 | } | |
964 | ||
bf868c7d | 965 | static void g4x_enable_hdmi(struct intel_encoder *encoder) |
7d57382e | 966 | { |
5ab432ef | 967 | struct drm_device *dev = encoder->base.dev; |
7d57382e | 968 | struct drm_i915_private *dev_priv = dev->dev_private; |
bf868c7d | 969 | struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); |
5ab432ef | 970 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); |
7d57382e EA |
971 | u32 temp; |
972 | ||
b242b7f7 | 973 | temp = I915_READ(intel_hdmi->hdmi_reg); |
d8a2d0e0 | 974 | |
bf868c7d VS |
975 | temp |= SDVO_ENABLE; |
976 | if (crtc->config->has_audio) | |
977 | temp |= SDVO_AUDIO_ENABLE; | |
7a87c289 | 978 | |
bf868c7d VS |
979 | I915_WRITE(intel_hdmi->hdmi_reg, temp); |
980 | POSTING_READ(intel_hdmi->hdmi_reg); | |
981 | ||
982 | if (crtc->config->has_audio) | |
983 | intel_enable_hdmi_audio(encoder); | |
984 | } | |
985 | ||
986 | static void ibx_enable_hdmi(struct intel_encoder *encoder) | |
987 | { | |
988 | struct drm_device *dev = encoder->base.dev; | |
989 | struct drm_i915_private *dev_priv = dev->dev_private; | |
990 | struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); | |
991 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); | |
992 | u32 temp; | |
993 | ||
994 | temp = I915_READ(intel_hdmi->hdmi_reg); | |
d8a2d0e0 | 995 | |
bf868c7d VS |
996 | temp |= SDVO_ENABLE; |
997 | if (crtc->config->has_audio) | |
998 | temp |= SDVO_AUDIO_ENABLE; | |
5ab432ef | 999 | |
bf868c7d VS |
1000 | /* |
1001 | * HW workaround, need to write this twice for issue | |
1002 | * that may result in first write getting masked. | |
1003 | */ | |
1004 | I915_WRITE(intel_hdmi->hdmi_reg, temp); | |
1005 | POSTING_READ(intel_hdmi->hdmi_reg); | |
b242b7f7 PZ |
1006 | I915_WRITE(intel_hdmi->hdmi_reg, temp); |
1007 | POSTING_READ(intel_hdmi->hdmi_reg); | |
5ab432ef | 1008 | |
bf868c7d VS |
1009 | /* |
1010 | * HW workaround, need to toggle enable bit off and on | |
1011 | * for 12bpc with pixel repeat. | |
1012 | * | |
1013 | * FIXME: BSpec says this should be done at the end of | |
1014 | * of the modeset sequence, so not sure if this isn't too soon. | |
5ab432ef | 1015 | */ |
bf868c7d VS |
1016 | if (crtc->config->pipe_bpp > 24 && |
1017 | crtc->config->pixel_multiplier > 1) { | |
1018 | I915_WRITE(intel_hdmi->hdmi_reg, temp & ~SDVO_ENABLE); | |
1019 | POSTING_READ(intel_hdmi->hdmi_reg); | |
1020 | ||
1021 | /* | |
1022 | * HW workaround, need to write this twice for issue | |
1023 | * that may result in first write getting masked. | |
1024 | */ | |
1025 | I915_WRITE(intel_hdmi->hdmi_reg, temp); | |
1026 | POSTING_READ(intel_hdmi->hdmi_reg); | |
b242b7f7 PZ |
1027 | I915_WRITE(intel_hdmi->hdmi_reg, temp); |
1028 | POSTING_READ(intel_hdmi->hdmi_reg); | |
7d57382e | 1029 | } |
c1dec79a | 1030 | |
bf868c7d | 1031 | if (crtc->config->has_audio) |
d1b1589c VS |
1032 | intel_enable_hdmi_audio(encoder); |
1033 | } | |
1034 | ||
1035 | static void cpt_enable_hdmi(struct intel_encoder *encoder) | |
1036 | { | |
1037 | struct drm_device *dev = encoder->base.dev; | |
1038 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1039 | struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); | |
1040 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); | |
1041 | enum pipe pipe = crtc->pipe; | |
1042 | u32 temp; | |
1043 | ||
1044 | temp = I915_READ(intel_hdmi->hdmi_reg); | |
1045 | ||
1046 | temp |= SDVO_ENABLE; | |
1047 | if (crtc->config->has_audio) | |
1048 | temp |= SDVO_AUDIO_ENABLE; | |
1049 | ||
1050 | /* | |
1051 | * WaEnableHDMI8bpcBefore12bpc:snb,ivb | |
1052 | * | |
1053 | * The procedure for 12bpc is as follows: | |
1054 | * 1. disable HDMI clock gating | |
1055 | * 2. enable HDMI with 8bpc | |
1056 | * 3. enable HDMI with 12bpc | |
1057 | * 4. enable HDMI clock gating | |
1058 | */ | |
1059 | ||
1060 | if (crtc->config->pipe_bpp > 24) { | |
1061 | I915_WRITE(TRANS_CHICKEN1(pipe), | |
1062 | I915_READ(TRANS_CHICKEN1(pipe)) | | |
1063 | TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE); | |
1064 | ||
1065 | temp &= ~SDVO_COLOR_FORMAT_MASK; | |
1066 | temp |= SDVO_COLOR_FORMAT_8bpc; | |
c1dec79a | 1067 | } |
d1b1589c VS |
1068 | |
1069 | I915_WRITE(intel_hdmi->hdmi_reg, temp); | |
1070 | POSTING_READ(intel_hdmi->hdmi_reg); | |
1071 | ||
1072 | if (crtc->config->pipe_bpp > 24) { | |
1073 | temp &= ~SDVO_COLOR_FORMAT_MASK; | |
1074 | temp |= HDMI_COLOR_FORMAT_12bpc; | |
1075 | ||
1076 | I915_WRITE(intel_hdmi->hdmi_reg, temp); | |
1077 | POSTING_READ(intel_hdmi->hdmi_reg); | |
1078 | ||
1079 | I915_WRITE(TRANS_CHICKEN1(pipe), | |
1080 | I915_READ(TRANS_CHICKEN1(pipe)) & | |
1081 | ~TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE); | |
1082 | } | |
1083 | ||
1084 | if (crtc->config->has_audio) | |
1085 | intel_enable_hdmi_audio(encoder); | |
b76cf76b | 1086 | } |
89b667f8 | 1087 | |
b76cf76b JN |
1088 | static void vlv_enable_hdmi(struct intel_encoder *encoder) |
1089 | { | |
5ab432ef DV |
1090 | } |
1091 | ||
1092 | static void intel_disable_hdmi(struct intel_encoder *encoder) | |
1093 | { | |
1094 | struct drm_device *dev = encoder->base.dev; | |
1095 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1096 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); | |
495a5bb8 | 1097 | struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); |
5ab432ef | 1098 | u32 temp; |
5ab432ef | 1099 | |
b242b7f7 | 1100 | temp = I915_READ(intel_hdmi->hdmi_reg); |
5ab432ef | 1101 | |
1612c8bd | 1102 | temp &= ~(SDVO_ENABLE | SDVO_AUDIO_ENABLE); |
b242b7f7 PZ |
1103 | I915_WRITE(intel_hdmi->hdmi_reg, temp); |
1104 | POSTING_READ(intel_hdmi->hdmi_reg); | |
1612c8bd VS |
1105 | |
1106 | /* | |
1107 | * HW workaround for IBX, we need to move the port | |
1108 | * to transcoder A after disabling it to allow the | |
1109 | * matching DP port to be enabled on transcoder A. | |
1110 | */ | |
1111 | if (HAS_PCH_IBX(dev) && crtc->pipe == PIPE_B) { | |
1112 | temp &= ~SDVO_PIPE_B_SELECT; | |
1113 | temp |= SDVO_ENABLE; | |
1114 | /* | |
1115 | * HW workaround, need to write this twice for issue | |
1116 | * that may result in first write getting masked. | |
1117 | */ | |
1118 | I915_WRITE(intel_hdmi->hdmi_reg, temp); | |
1119 | POSTING_READ(intel_hdmi->hdmi_reg); | |
1120 | I915_WRITE(intel_hdmi->hdmi_reg, temp); | |
1121 | POSTING_READ(intel_hdmi->hdmi_reg); | |
1122 | ||
1123 | temp &= ~SDVO_ENABLE; | |
1124 | I915_WRITE(intel_hdmi->hdmi_reg, temp); | |
1125 | POSTING_READ(intel_hdmi->hdmi_reg); | |
1126 | } | |
6d67415f | 1127 | |
0be6f0c8 | 1128 | intel_hdmi->set_infoframes(&encoder->base, false, NULL); |
7d57382e EA |
1129 | } |
1130 | ||
a4790cec VS |
1131 | static void g4x_disable_hdmi(struct intel_encoder *encoder) |
1132 | { | |
1133 | struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); | |
1134 | ||
1135 | if (crtc->config->has_audio) | |
1136 | intel_audio_codec_disable(encoder); | |
1137 | ||
1138 | intel_disable_hdmi(encoder); | |
1139 | } | |
1140 | ||
1141 | static void pch_disable_hdmi(struct intel_encoder *encoder) | |
1142 | { | |
1143 | struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); | |
1144 | ||
1145 | if (crtc->config->has_audio) | |
1146 | intel_audio_codec_disable(encoder); | |
1147 | } | |
1148 | ||
1149 | static void pch_post_disable_hdmi(struct intel_encoder *encoder) | |
1150 | { | |
1151 | intel_disable_hdmi(encoder); | |
1152 | } | |
1153 | ||
e64e739e | 1154 | static int hdmi_port_clock_limit(struct intel_hdmi *hdmi, bool respect_dvi_limit) |
7d148ef5 DV |
1155 | { |
1156 | struct drm_device *dev = intel_hdmi_to_dev(hdmi); | |
1157 | ||
40478455 | 1158 | if ((respect_dvi_limit && !hdmi->has_hdmi_sink) || IS_G4X(dev)) |
7d148ef5 | 1159 | return 165000; |
e3c33578 | 1160 | else if (IS_HASWELL(dev) || INTEL_INFO(dev)->gen >= 8) |
7d148ef5 DV |
1161 | return 300000; |
1162 | else | |
1163 | return 225000; | |
1164 | } | |
1165 | ||
e64e739e VS |
1166 | static enum drm_mode_status |
1167 | hdmi_port_clock_valid(struct intel_hdmi *hdmi, | |
1168 | int clock, bool respect_dvi_limit) | |
1169 | { | |
1170 | struct drm_device *dev = intel_hdmi_to_dev(hdmi); | |
1171 | ||
1172 | if (clock < 25000) | |
1173 | return MODE_CLOCK_LOW; | |
1174 | if (clock > hdmi_port_clock_limit(hdmi, respect_dvi_limit)) | |
1175 | return MODE_CLOCK_HIGH; | |
1176 | ||
5e6ccc0b VS |
1177 | /* BXT DPLL can't generate 223-240 MHz */ |
1178 | if (IS_BROXTON(dev) && clock > 223333 && clock < 240000) | |
1179 | return MODE_CLOCK_RANGE; | |
1180 | ||
1181 | /* CHV DPLL can't generate 216-240 MHz */ | |
1182 | if (IS_CHERRYVIEW(dev) && clock > 216000 && clock < 240000) | |
e64e739e VS |
1183 | return MODE_CLOCK_RANGE; |
1184 | ||
1185 | return MODE_OK; | |
1186 | } | |
1187 | ||
c19de8eb DL |
1188 | static enum drm_mode_status |
1189 | intel_hdmi_mode_valid(struct drm_connector *connector, | |
1190 | struct drm_display_mode *mode) | |
7d57382e | 1191 | { |
e64e739e VS |
1192 | struct intel_hdmi *hdmi = intel_attached_hdmi(connector); |
1193 | struct drm_device *dev = intel_hdmi_to_dev(hdmi); | |
1194 | enum drm_mode_status status; | |
1195 | int clock; | |
1196 | ||
1197 | if (mode->flags & DRM_MODE_FLAG_DBLSCAN) | |
1198 | return MODE_NO_DBLESCAN; | |
697c4078 | 1199 | |
e64e739e | 1200 | clock = mode->clock; |
697c4078 CT |
1201 | if (mode->flags & DRM_MODE_FLAG_DBLCLK) |
1202 | clock *= 2; | |
1203 | ||
e64e739e VS |
1204 | /* check if we can do 8bpc */ |
1205 | status = hdmi_port_clock_valid(hdmi, clock, true); | |
7d57382e | 1206 | |
e64e739e VS |
1207 | /* if we can't do 8bpc we may still be able to do 12bpc */ |
1208 | if (!HAS_GMCH_DISPLAY(dev) && status != MODE_OK) | |
1209 | status = hdmi_port_clock_valid(hdmi, clock * 3 / 2, true); | |
7d57382e | 1210 | |
e64e739e | 1211 | return status; |
7d57382e EA |
1212 | } |
1213 | ||
77f06c86 | 1214 | static bool hdmi_12bpc_possible(struct intel_crtc_state *crtc_state) |
71800632 | 1215 | { |
77f06c86 ACO |
1216 | struct drm_device *dev = crtc_state->base.crtc->dev; |
1217 | struct drm_atomic_state *state; | |
71800632 | 1218 | struct intel_encoder *encoder; |
da3ced29 | 1219 | struct drm_connector *connector; |
77f06c86 | 1220 | struct drm_connector_state *connector_state; |
71800632 | 1221 | int count = 0, count_hdmi = 0; |
77f06c86 | 1222 | int i; |
71800632 | 1223 | |
f227ae9e | 1224 | if (HAS_GMCH_DISPLAY(dev)) |
71800632 VS |
1225 | return false; |
1226 | ||
77f06c86 ACO |
1227 | state = crtc_state->base.state; |
1228 | ||
da3ced29 | 1229 | for_each_connector_in_state(state, connector, connector_state, i) { |
77f06c86 ACO |
1230 | if (connector_state->crtc != crtc_state->base.crtc) |
1231 | continue; | |
1232 | ||
1233 | encoder = to_intel_encoder(connector_state->best_encoder); | |
1234 | ||
71800632 VS |
1235 | count_hdmi += encoder->type == INTEL_OUTPUT_HDMI; |
1236 | count++; | |
1237 | } | |
1238 | ||
1239 | /* | |
1240 | * HDMI 12bpc affects the clocks, so it's only possible | |
1241 | * when not cloning with other encoder types. | |
1242 | */ | |
1243 | return count_hdmi > 0 && count_hdmi == count; | |
1244 | } | |
1245 | ||
5bfe2ac0 | 1246 | bool intel_hdmi_compute_config(struct intel_encoder *encoder, |
5cec258b | 1247 | struct intel_crtc_state *pipe_config) |
7d57382e | 1248 | { |
5bfe2ac0 DV |
1249 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); |
1250 | struct drm_device *dev = encoder->base.dev; | |
2d112de7 | 1251 | struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; |
e64e739e VS |
1252 | int clock_8bpc = pipe_config->base.adjusted_mode.crtc_clock; |
1253 | int clock_12bpc = clock_8bpc * 3 / 2; | |
e29c22c0 | 1254 | int desired_bpp; |
3685a8f3 | 1255 | |
6897b4b5 DV |
1256 | pipe_config->has_hdmi_sink = intel_hdmi->has_hdmi_sink; |
1257 | ||
e43823ec JB |
1258 | if (pipe_config->has_hdmi_sink) |
1259 | pipe_config->has_infoframe = true; | |
1260 | ||
55bc60db VS |
1261 | if (intel_hdmi->color_range_auto) { |
1262 | /* See CEA-861-E - 5.1 Default Encoding Parameters */ | |
6897b4b5 | 1263 | if (pipe_config->has_hdmi_sink && |
18316c8c | 1264 | drm_match_cea_mode(adjusted_mode) > 1) |
4f3a8bc7 | 1265 | intel_hdmi->color_range = HDMI_COLOR_RANGE_16_235; |
55bc60db VS |
1266 | else |
1267 | intel_hdmi->color_range = 0; | |
1268 | } | |
1269 | ||
697c4078 CT |
1270 | if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK) { |
1271 | pipe_config->pixel_multiplier = 2; | |
e64e739e | 1272 | clock_8bpc *= 2; |
3320e37f | 1273 | clock_12bpc *= 2; |
697c4078 CT |
1274 | } |
1275 | ||
3685a8f3 | 1276 | if (intel_hdmi->color_range) |
50f3b016 | 1277 | pipe_config->limited_color_range = true; |
3685a8f3 | 1278 | |
5bfe2ac0 DV |
1279 | if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev)) |
1280 | pipe_config->has_pch_encoder = true; | |
1281 | ||
9ed109a7 DV |
1282 | if (pipe_config->has_hdmi_sink && intel_hdmi->has_audio) |
1283 | pipe_config->has_audio = true; | |
1284 | ||
4e53c2e0 DV |
1285 | /* |
1286 | * HDMI is either 12 or 8, so if the display lets 10bpc sneak | |
1287 | * through, clamp it down. Note that g4x/vlv don't support 12bpc hdmi | |
325b9d04 DV |
1288 | * outputs. We also need to check that the higher clock still fits |
1289 | * within limits. | |
4e53c2e0 | 1290 | */ |
6897b4b5 | 1291 | if (pipe_config->pipe_bpp > 8*3 && pipe_config->has_hdmi_sink && |
e64e739e | 1292 | hdmi_port_clock_valid(intel_hdmi, clock_12bpc, false) == MODE_OK && |
7a0baa62 | 1293 | hdmi_12bpc_possible(pipe_config)) { |
e29c22c0 DV |
1294 | DRM_DEBUG_KMS("picking bpc to 12 for HDMI output\n"); |
1295 | desired_bpp = 12*3; | |
325b9d04 DV |
1296 | |
1297 | /* Need to adjust the port link by 1.5x for 12bpc. */ | |
ff9a6750 | 1298 | pipe_config->port_clock = clock_12bpc; |
4e53c2e0 | 1299 | } else { |
e29c22c0 DV |
1300 | DRM_DEBUG_KMS("picking bpc to 8 for HDMI output\n"); |
1301 | desired_bpp = 8*3; | |
e64e739e VS |
1302 | |
1303 | pipe_config->port_clock = clock_8bpc; | |
e29c22c0 DV |
1304 | } |
1305 | ||
1306 | if (!pipe_config->bw_constrained) { | |
1307 | DRM_DEBUG_KMS("forcing pipe bpc to %i for HDMI\n", desired_bpp); | |
1308 | pipe_config->pipe_bpp = desired_bpp; | |
4e53c2e0 DV |
1309 | } |
1310 | ||
e64e739e VS |
1311 | if (hdmi_port_clock_valid(intel_hdmi, pipe_config->port_clock, |
1312 | false) != MODE_OK) { | |
1313 | DRM_DEBUG_KMS("unsupported HDMI clock, rejecting mode\n"); | |
325b9d04 DV |
1314 | return false; |
1315 | } | |
1316 | ||
7d57382e EA |
1317 | return true; |
1318 | } | |
1319 | ||
953ece69 CW |
1320 | static void |
1321 | intel_hdmi_unset_edid(struct drm_connector *connector) | |
9dff6af8 | 1322 | { |
df0e9248 | 1323 | struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); |
9dff6af8 | 1324 | |
953ece69 CW |
1325 | intel_hdmi->has_hdmi_sink = false; |
1326 | intel_hdmi->has_audio = false; | |
1327 | intel_hdmi->rgb_quant_range_selectable = false; | |
1328 | ||
1329 | kfree(to_intel_connector(connector)->detect_edid); | |
1330 | to_intel_connector(connector)->detect_edid = NULL; | |
1331 | } | |
1332 | ||
1333 | static bool | |
1334 | intel_hdmi_set_edid(struct drm_connector *connector) | |
1335 | { | |
1336 | struct drm_i915_private *dev_priv = to_i915(connector->dev); | |
1337 | struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); | |
1338 | struct intel_encoder *intel_encoder = | |
1339 | &hdmi_to_dig_port(intel_hdmi)->base; | |
1340 | enum intel_display_power_domain power_domain; | |
1341 | struct edid *edid; | |
1342 | bool connected = false; | |
164c8598 | 1343 | |
671dedd2 ID |
1344 | power_domain = intel_display_port_power_domain(intel_encoder); |
1345 | intel_display_power_get(dev_priv, power_domain); | |
1346 | ||
f899fc64 | 1347 | edid = drm_get_edid(connector, |
3bd7d909 DK |
1348 | intel_gmbus_get_adapter(dev_priv, |
1349 | intel_hdmi->ddc_bus)); | |
2ded9e27 | 1350 | |
953ece69 | 1351 | intel_display_power_put(dev_priv, power_domain); |
30ad48b7 | 1352 | |
953ece69 CW |
1353 | to_intel_connector(connector)->detect_edid = edid; |
1354 | if (edid && edid->input & DRM_EDID_INPUT_DIGITAL) { | |
1355 | intel_hdmi->rgb_quant_range_selectable = | |
1356 | drm_rgb_quant_range_selectable(edid); | |
1357 | ||
1358 | intel_hdmi->has_audio = drm_detect_monitor_audio(edid); | |
b1d7e4b4 WF |
1359 | if (intel_hdmi->force_audio != HDMI_AUDIO_AUTO) |
1360 | intel_hdmi->has_audio = | |
953ece69 CW |
1361 | intel_hdmi->force_audio == HDMI_AUDIO_ON; |
1362 | ||
1363 | if (intel_hdmi->force_audio != HDMI_AUDIO_OFF_DVI) | |
1364 | intel_hdmi->has_hdmi_sink = | |
1365 | drm_detect_hdmi_monitor(edid); | |
1366 | ||
1367 | connected = true; | |
55b7d6e8 CW |
1368 | } |
1369 | ||
953ece69 CW |
1370 | return connected; |
1371 | } | |
1372 | ||
1373 | static enum drm_connector_status | |
1374 | intel_hdmi_detect(struct drm_connector *connector, bool force) | |
1375 | { | |
1376 | enum drm_connector_status status; | |
1377 | ||
1378 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", | |
1379 | connector->base.id, connector->name); | |
1380 | ||
1381 | intel_hdmi_unset_edid(connector); | |
1382 | ||
1383 | if (intel_hdmi_set_edid(connector)) { | |
1384 | struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); | |
1385 | ||
1386 | hdmi_to_dig_port(intel_hdmi)->base.type = INTEL_OUTPUT_HDMI; | |
1387 | status = connector_status_connected; | |
1388 | } else | |
1389 | status = connector_status_disconnected; | |
671dedd2 | 1390 | |
2ded9e27 | 1391 | return status; |
7d57382e EA |
1392 | } |
1393 | ||
953ece69 CW |
1394 | static void |
1395 | intel_hdmi_force(struct drm_connector *connector) | |
7d57382e | 1396 | { |
953ece69 | 1397 | struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); |
7d57382e | 1398 | |
953ece69 CW |
1399 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", |
1400 | connector->base.id, connector->name); | |
7d57382e | 1401 | |
953ece69 | 1402 | intel_hdmi_unset_edid(connector); |
671dedd2 | 1403 | |
953ece69 CW |
1404 | if (connector->status != connector_status_connected) |
1405 | return; | |
671dedd2 | 1406 | |
953ece69 CW |
1407 | intel_hdmi_set_edid(connector); |
1408 | hdmi_to_dig_port(intel_hdmi)->base.type = INTEL_OUTPUT_HDMI; | |
1409 | } | |
671dedd2 | 1410 | |
953ece69 CW |
1411 | static int intel_hdmi_get_modes(struct drm_connector *connector) |
1412 | { | |
1413 | struct edid *edid; | |
1414 | ||
1415 | edid = to_intel_connector(connector)->detect_edid; | |
1416 | if (edid == NULL) | |
1417 | return 0; | |
671dedd2 | 1418 | |
953ece69 | 1419 | return intel_connector_update_modes(connector, edid); |
7d57382e EA |
1420 | } |
1421 | ||
1aad7ac0 CW |
1422 | static bool |
1423 | intel_hdmi_detect_audio(struct drm_connector *connector) | |
1424 | { | |
1aad7ac0 | 1425 | bool has_audio = false; |
953ece69 | 1426 | struct edid *edid; |
1aad7ac0 | 1427 | |
953ece69 CW |
1428 | edid = to_intel_connector(connector)->detect_edid; |
1429 | if (edid && edid->input & DRM_EDID_INPUT_DIGITAL) | |
1430 | has_audio = drm_detect_monitor_audio(edid); | |
671dedd2 | 1431 | |
1aad7ac0 CW |
1432 | return has_audio; |
1433 | } | |
1434 | ||
55b7d6e8 CW |
1435 | static int |
1436 | intel_hdmi_set_property(struct drm_connector *connector, | |
ed517fbb PZ |
1437 | struct drm_property *property, |
1438 | uint64_t val) | |
55b7d6e8 CW |
1439 | { |
1440 | struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); | |
da63a9f2 PZ |
1441 | struct intel_digital_port *intel_dig_port = |
1442 | hdmi_to_dig_port(intel_hdmi); | |
e953fd7b | 1443 | struct drm_i915_private *dev_priv = connector->dev->dev_private; |
55b7d6e8 CW |
1444 | int ret; |
1445 | ||
662595df | 1446 | ret = drm_object_property_set_value(&connector->base, property, val); |
55b7d6e8 CW |
1447 | if (ret) |
1448 | return ret; | |
1449 | ||
3f43c48d | 1450 | if (property == dev_priv->force_audio_property) { |
b1d7e4b4 | 1451 | enum hdmi_force_audio i = val; |
1aad7ac0 CW |
1452 | bool has_audio; |
1453 | ||
1454 | if (i == intel_hdmi->force_audio) | |
55b7d6e8 CW |
1455 | return 0; |
1456 | ||
1aad7ac0 | 1457 | intel_hdmi->force_audio = i; |
55b7d6e8 | 1458 | |
b1d7e4b4 | 1459 | if (i == HDMI_AUDIO_AUTO) |
1aad7ac0 CW |
1460 | has_audio = intel_hdmi_detect_audio(connector); |
1461 | else | |
b1d7e4b4 | 1462 | has_audio = (i == HDMI_AUDIO_ON); |
1aad7ac0 | 1463 | |
b1d7e4b4 WF |
1464 | if (i == HDMI_AUDIO_OFF_DVI) |
1465 | intel_hdmi->has_hdmi_sink = 0; | |
55b7d6e8 | 1466 | |
1aad7ac0 | 1467 | intel_hdmi->has_audio = has_audio; |
55b7d6e8 CW |
1468 | goto done; |
1469 | } | |
1470 | ||
e953fd7b | 1471 | if (property == dev_priv->broadcast_rgb_property) { |
ae4edb80 DV |
1472 | bool old_auto = intel_hdmi->color_range_auto; |
1473 | uint32_t old_range = intel_hdmi->color_range; | |
1474 | ||
55bc60db VS |
1475 | switch (val) { |
1476 | case INTEL_BROADCAST_RGB_AUTO: | |
1477 | intel_hdmi->color_range_auto = true; | |
1478 | break; | |
1479 | case INTEL_BROADCAST_RGB_FULL: | |
1480 | intel_hdmi->color_range_auto = false; | |
1481 | intel_hdmi->color_range = 0; | |
1482 | break; | |
1483 | case INTEL_BROADCAST_RGB_LIMITED: | |
1484 | intel_hdmi->color_range_auto = false; | |
4f3a8bc7 | 1485 | intel_hdmi->color_range = HDMI_COLOR_RANGE_16_235; |
55bc60db VS |
1486 | break; |
1487 | default: | |
1488 | return -EINVAL; | |
1489 | } | |
ae4edb80 DV |
1490 | |
1491 | if (old_auto == intel_hdmi->color_range_auto && | |
1492 | old_range == intel_hdmi->color_range) | |
1493 | return 0; | |
1494 | ||
e953fd7b CW |
1495 | goto done; |
1496 | } | |
1497 | ||
94a11ddc VK |
1498 | if (property == connector->dev->mode_config.aspect_ratio_property) { |
1499 | switch (val) { | |
1500 | case DRM_MODE_PICTURE_ASPECT_NONE: | |
1501 | intel_hdmi->aspect_ratio = HDMI_PICTURE_ASPECT_NONE; | |
1502 | break; | |
1503 | case DRM_MODE_PICTURE_ASPECT_4_3: | |
1504 | intel_hdmi->aspect_ratio = HDMI_PICTURE_ASPECT_4_3; | |
1505 | break; | |
1506 | case DRM_MODE_PICTURE_ASPECT_16_9: | |
1507 | intel_hdmi->aspect_ratio = HDMI_PICTURE_ASPECT_16_9; | |
1508 | break; | |
1509 | default: | |
1510 | return -EINVAL; | |
1511 | } | |
1512 | goto done; | |
1513 | } | |
1514 | ||
55b7d6e8 CW |
1515 | return -EINVAL; |
1516 | ||
1517 | done: | |
c0c36b94 CW |
1518 | if (intel_dig_port->base.base.crtc) |
1519 | intel_crtc_restore_mode(intel_dig_port->base.base.crtc); | |
55b7d6e8 CW |
1520 | |
1521 | return 0; | |
1522 | } | |
1523 | ||
13732ba7 JB |
1524 | static void intel_hdmi_pre_enable(struct intel_encoder *encoder) |
1525 | { | |
1526 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); | |
1527 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); | |
1528 | struct drm_display_mode *adjusted_mode = | |
6e3c9717 | 1529 | &intel_crtc->config->base.adjusted_mode; |
13732ba7 | 1530 | |
4cde8a21 DV |
1531 | intel_hdmi_prepare(encoder); |
1532 | ||
6897b4b5 | 1533 | intel_hdmi->set_infoframes(&encoder->base, |
6e3c9717 | 1534 | intel_crtc->config->has_hdmi_sink, |
6897b4b5 | 1535 | adjusted_mode); |
13732ba7 JB |
1536 | } |
1537 | ||
9514ac6e | 1538 | static void vlv_hdmi_pre_enable(struct intel_encoder *encoder) |
89b667f8 JB |
1539 | { |
1540 | struct intel_digital_port *dport = enc_to_dig_port(&encoder->base); | |
13732ba7 | 1541 | struct intel_hdmi *intel_hdmi = &dport->hdmi; |
89b667f8 JB |
1542 | struct drm_device *dev = encoder->base.dev; |
1543 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1544 | struct intel_crtc *intel_crtc = | |
1545 | to_intel_crtc(encoder->base.crtc); | |
13732ba7 | 1546 | struct drm_display_mode *adjusted_mode = |
6e3c9717 | 1547 | &intel_crtc->config->base.adjusted_mode; |
e4607fcf | 1548 | enum dpio_channel port = vlv_dport_to_channel(dport); |
89b667f8 JB |
1549 | int pipe = intel_crtc->pipe; |
1550 | u32 val; | |
1551 | ||
89b667f8 | 1552 | /* Enable clock channels for this port */ |
a580516d | 1553 | mutex_lock(&dev_priv->sb_lock); |
ab3c759a | 1554 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port)); |
89b667f8 JB |
1555 | val = 0; |
1556 | if (pipe) | |
1557 | val |= (1<<21); | |
1558 | else | |
1559 | val &= ~(1<<21); | |
1560 | val |= 0x001000c4; | |
ab3c759a | 1561 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val); |
89b667f8 JB |
1562 | |
1563 | /* HDMI 1.0V-2dB */ | |
ab3c759a CML |
1564 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0); |
1565 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), 0x2b245f5f); | |
1566 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port), 0x5578b83a); | |
1567 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0c782040); | |
1568 | vlv_dpio_write(dev_priv, pipe, VLV_TX3_DW4(port), 0x2b247878); | |
1569 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000); | |
1570 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), 0x00002000); | |
1571 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), DPIO_TX_OCALINIT_EN); | |
89b667f8 JB |
1572 | |
1573 | /* Program lane clock */ | |
ab3c759a CML |
1574 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018); |
1575 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888); | |
a580516d | 1576 | mutex_unlock(&dev_priv->sb_lock); |
b76cf76b | 1577 | |
6897b4b5 | 1578 | intel_hdmi->set_infoframes(&encoder->base, |
6e3c9717 | 1579 | intel_crtc->config->has_hdmi_sink, |
6897b4b5 | 1580 | adjusted_mode); |
13732ba7 | 1581 | |
bf868c7d | 1582 | g4x_enable_hdmi(encoder); |
b76cf76b | 1583 | |
9b6de0a1 | 1584 | vlv_wait_port_ready(dev_priv, dport, 0x0); |
89b667f8 JB |
1585 | } |
1586 | ||
9514ac6e | 1587 | static void vlv_hdmi_pre_pll_enable(struct intel_encoder *encoder) |
89b667f8 JB |
1588 | { |
1589 | struct intel_digital_port *dport = enc_to_dig_port(&encoder->base); | |
1590 | struct drm_device *dev = encoder->base.dev; | |
1591 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5e69f97f CML |
1592 | struct intel_crtc *intel_crtc = |
1593 | to_intel_crtc(encoder->base.crtc); | |
e4607fcf | 1594 | enum dpio_channel port = vlv_dport_to_channel(dport); |
5e69f97f | 1595 | int pipe = intel_crtc->pipe; |
89b667f8 | 1596 | |
4cde8a21 DV |
1597 | intel_hdmi_prepare(encoder); |
1598 | ||
89b667f8 | 1599 | /* Program Tx lane resets to default */ |
a580516d | 1600 | mutex_lock(&dev_priv->sb_lock); |
ab3c759a | 1601 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port), |
89b667f8 JB |
1602 | DPIO_PCS_TX_LANE2_RESET | |
1603 | DPIO_PCS_TX_LANE1_RESET); | |
ab3c759a | 1604 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port), |
89b667f8 JB |
1605 | DPIO_PCS_CLK_CRI_RXEB_EIOS_EN | |
1606 | DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN | | |
1607 | (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) | | |
1608 | DPIO_PCS_CLK_SOFT_RESET); | |
1609 | ||
1610 | /* Fix up inter-pair skew failure */ | |
ab3c759a CML |
1611 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW12(port), 0x00750f00); |
1612 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW11(port), 0x00001500); | |
1613 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000); | |
1614 | ||
1615 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), 0x00002000); | |
1616 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), DPIO_TX_OCALINIT_EN); | |
a580516d | 1617 | mutex_unlock(&dev_priv->sb_lock); |
89b667f8 JB |
1618 | } |
1619 | ||
9197c88b VS |
1620 | static void chv_hdmi_pre_pll_enable(struct intel_encoder *encoder) |
1621 | { | |
1622 | struct intel_digital_port *dport = enc_to_dig_port(&encoder->base); | |
1623 | struct drm_device *dev = encoder->base.dev; | |
1624 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1625 | struct intel_crtc *intel_crtc = | |
1626 | to_intel_crtc(encoder->base.crtc); | |
1627 | enum dpio_channel ch = vlv_dport_to_channel(dport); | |
1628 | enum pipe pipe = intel_crtc->pipe; | |
1629 | u32 val; | |
1630 | ||
625695f8 VS |
1631 | intel_hdmi_prepare(encoder); |
1632 | ||
a580516d | 1633 | mutex_lock(&dev_priv->sb_lock); |
9197c88b | 1634 | |
b9e5ac3c VS |
1635 | /* program left/right clock distribution */ |
1636 | if (pipe != PIPE_B) { | |
1637 | val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0); | |
1638 | val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK); | |
1639 | if (ch == DPIO_CH0) | |
1640 | val |= CHV_BUFLEFTENA1_FORCE; | |
1641 | if (ch == DPIO_CH1) | |
1642 | val |= CHV_BUFRIGHTENA1_FORCE; | |
1643 | vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val); | |
1644 | } else { | |
1645 | val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1); | |
1646 | val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK); | |
1647 | if (ch == DPIO_CH0) | |
1648 | val |= CHV_BUFLEFTENA2_FORCE; | |
1649 | if (ch == DPIO_CH1) | |
1650 | val |= CHV_BUFRIGHTENA2_FORCE; | |
1651 | vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val); | |
1652 | } | |
1653 | ||
9197c88b VS |
1654 | /* program clock channel usage */ |
1655 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(ch)); | |
1656 | val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE; | |
1657 | if (pipe != PIPE_B) | |
1658 | val &= ~CHV_PCS_USEDCLKCHANNEL; | |
1659 | else | |
1660 | val |= CHV_PCS_USEDCLKCHANNEL; | |
1661 | vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW8(ch), val); | |
1662 | ||
1663 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW8(ch)); | |
1664 | val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE; | |
1665 | if (pipe != PIPE_B) | |
1666 | val &= ~CHV_PCS_USEDCLKCHANNEL; | |
1667 | else | |
1668 | val |= CHV_PCS_USEDCLKCHANNEL; | |
1669 | vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW8(ch), val); | |
1670 | ||
1671 | /* | |
1672 | * This a a bit weird since generally CL | |
1673 | * matches the pipe, but here we need to | |
1674 | * pick the CL based on the port. | |
1675 | */ | |
1676 | val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW19(ch)); | |
1677 | if (pipe != PIPE_B) | |
1678 | val &= ~CHV_CMN_USEDCLKCHANNEL; | |
1679 | else | |
1680 | val |= CHV_CMN_USEDCLKCHANNEL; | |
1681 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW19(ch), val); | |
1682 | ||
a580516d | 1683 | mutex_unlock(&dev_priv->sb_lock); |
9197c88b VS |
1684 | } |
1685 | ||
9514ac6e | 1686 | static void vlv_hdmi_post_disable(struct intel_encoder *encoder) |
89b667f8 JB |
1687 | { |
1688 | struct intel_digital_port *dport = enc_to_dig_port(&encoder->base); | |
1689 | struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; | |
5e69f97f CML |
1690 | struct intel_crtc *intel_crtc = |
1691 | to_intel_crtc(encoder->base.crtc); | |
e4607fcf | 1692 | enum dpio_channel port = vlv_dport_to_channel(dport); |
5e69f97f | 1693 | int pipe = intel_crtc->pipe; |
89b667f8 JB |
1694 | |
1695 | /* Reset lanes to avoid HDMI flicker (VLV w/a) */ | |
a580516d | 1696 | mutex_lock(&dev_priv->sb_lock); |
ab3c759a CML |
1697 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port), 0x00000000); |
1698 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port), 0x00e00060); | |
a580516d | 1699 | mutex_unlock(&dev_priv->sb_lock); |
89b667f8 JB |
1700 | } |
1701 | ||
580d3811 VS |
1702 | static void chv_hdmi_post_disable(struct intel_encoder *encoder) |
1703 | { | |
1704 | struct intel_digital_port *dport = enc_to_dig_port(&encoder->base); | |
1705 | struct drm_device *dev = encoder->base.dev; | |
1706 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1707 | struct intel_crtc *intel_crtc = | |
1708 | to_intel_crtc(encoder->base.crtc); | |
1709 | enum dpio_channel ch = vlv_dport_to_channel(dport); | |
1710 | enum pipe pipe = intel_crtc->pipe; | |
1711 | u32 val; | |
1712 | ||
a580516d | 1713 | mutex_lock(&dev_priv->sb_lock); |
580d3811 VS |
1714 | |
1715 | /* Propagate soft reset to data lane reset */ | |
97fd4d5c | 1716 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch)); |
d2152b25 | 1717 | val |= CHV_PCS_REQ_SOFTRESET_EN; |
97fd4d5c | 1718 | vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val); |
d2152b25 | 1719 | |
97fd4d5c VS |
1720 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch)); |
1721 | val |= CHV_PCS_REQ_SOFTRESET_EN; | |
1722 | vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val); | |
1723 | ||
1724 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch)); | |
1725 | val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET); | |
1726 | vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val); | |
1727 | ||
1728 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch)); | |
580d3811 | 1729 | val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET); |
97fd4d5c | 1730 | vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val); |
580d3811 | 1731 | |
a580516d | 1732 | mutex_unlock(&dev_priv->sb_lock); |
580d3811 VS |
1733 | } |
1734 | ||
e4a1d846 CML |
1735 | static void chv_hdmi_pre_enable(struct intel_encoder *encoder) |
1736 | { | |
1737 | struct intel_digital_port *dport = enc_to_dig_port(&encoder->base); | |
b4eb1564 | 1738 | struct intel_hdmi *intel_hdmi = &dport->hdmi; |
e4a1d846 CML |
1739 | struct drm_device *dev = encoder->base.dev; |
1740 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1741 | struct intel_crtc *intel_crtc = | |
1742 | to_intel_crtc(encoder->base.crtc); | |
b4eb1564 | 1743 | struct drm_display_mode *adjusted_mode = |
6e3c9717 | 1744 | &intel_crtc->config->base.adjusted_mode; |
e4a1d846 CML |
1745 | enum dpio_channel ch = vlv_dport_to_channel(dport); |
1746 | int pipe = intel_crtc->pipe; | |
2e523e98 | 1747 | int data, i, stagger; |
e4a1d846 CML |
1748 | u32 val; |
1749 | ||
a580516d | 1750 | mutex_lock(&dev_priv->sb_lock); |
949c1d43 | 1751 | |
570e2a74 VS |
1752 | /* allow hardware to manage TX FIFO reset source */ |
1753 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch)); | |
1754 | val &= ~DPIO_LANEDESKEW_STRAP_OVRD; | |
1755 | vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val); | |
1756 | ||
1757 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch)); | |
1758 | val &= ~DPIO_LANEDESKEW_STRAP_OVRD; | |
1759 | vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val); | |
1760 | ||
949c1d43 | 1761 | /* Deassert soft data lane reset*/ |
97fd4d5c | 1762 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch)); |
d2152b25 | 1763 | val |= CHV_PCS_REQ_SOFTRESET_EN; |
97fd4d5c VS |
1764 | vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val); |
1765 | ||
1766 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch)); | |
1767 | val |= CHV_PCS_REQ_SOFTRESET_EN; | |
1768 | vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val); | |
1769 | ||
1770 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch)); | |
1771 | val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET); | |
1772 | vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val); | |
d2152b25 | 1773 | |
97fd4d5c | 1774 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch)); |
949c1d43 | 1775 | val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET); |
97fd4d5c | 1776 | vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val); |
949c1d43 VS |
1777 | |
1778 | /* Program Tx latency optimal setting */ | |
e4a1d846 | 1779 | for (i = 0; i < 4; i++) { |
e4a1d846 CML |
1780 | /* Set the upar bit */ |
1781 | data = (i == 1) ? 0x0 : 0x1; | |
1782 | vlv_dpio_write(dev_priv, pipe, CHV_TX_DW14(ch, i), | |
1783 | data << DPIO_UPAR_SHIFT); | |
1784 | } | |
1785 | ||
1786 | /* Data lane stagger programming */ | |
2e523e98 VS |
1787 | if (intel_crtc->config->port_clock > 270000) |
1788 | stagger = 0x18; | |
1789 | else if (intel_crtc->config->port_clock > 135000) | |
1790 | stagger = 0xd; | |
1791 | else if (intel_crtc->config->port_clock > 67500) | |
1792 | stagger = 0x7; | |
1793 | else if (intel_crtc->config->port_clock > 33750) | |
1794 | stagger = 0x4; | |
1795 | else | |
1796 | stagger = 0x2; | |
1797 | ||
1798 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch)); | |
1799 | val |= DPIO_TX2_STAGGER_MASK(0x1f); | |
1800 | vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val); | |
1801 | ||
1802 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch)); | |
1803 | val |= DPIO_TX2_STAGGER_MASK(0x1f); | |
1804 | vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val); | |
1805 | ||
1806 | vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW12(ch), | |
1807 | DPIO_LANESTAGGER_STRAP(stagger) | | |
1808 | DPIO_LANESTAGGER_STRAP_OVRD | | |
1809 | DPIO_TX1_STAGGER_MASK(0x1f) | | |
1810 | DPIO_TX1_STAGGER_MULT(6) | | |
1811 | DPIO_TX2_STAGGER_MULT(0)); | |
1812 | ||
1813 | vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW12(ch), | |
1814 | DPIO_LANESTAGGER_STRAP(stagger) | | |
1815 | DPIO_LANESTAGGER_STRAP_OVRD | | |
1816 | DPIO_TX1_STAGGER_MASK(0x1f) | | |
1817 | DPIO_TX1_STAGGER_MULT(7) | | |
1818 | DPIO_TX2_STAGGER_MULT(5)); | |
e4a1d846 CML |
1819 | |
1820 | /* Clear calc init */ | |
1966e59e VS |
1821 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch)); |
1822 | val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3); | |
a02ef3c7 VS |
1823 | val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK); |
1824 | val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5; | |
1966e59e VS |
1825 | vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val); |
1826 | ||
1827 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch)); | |
1828 | val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3); | |
a02ef3c7 VS |
1829 | val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK); |
1830 | val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5; | |
1966e59e | 1831 | vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val); |
e4a1d846 | 1832 | |
a02ef3c7 VS |
1833 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW9(ch)); |
1834 | val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK); | |
1835 | val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000; | |
1836 | vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW9(ch), val); | |
1837 | ||
1838 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW9(ch)); | |
1839 | val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK); | |
1840 | val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000; | |
1841 | vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW9(ch), val); | |
1842 | ||
e4a1d846 CML |
1843 | /* FIXME: Program the support xxx V-dB */ |
1844 | /* Use 800mV-0dB */ | |
f72df8db VS |
1845 | for (i = 0; i < 4; i++) { |
1846 | val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW4(ch, i)); | |
1847 | val &= ~DPIO_SWING_DEEMPH9P5_MASK; | |
1848 | val |= 128 << DPIO_SWING_DEEMPH9P5_SHIFT; | |
1849 | vlv_dpio_write(dev_priv, pipe, CHV_TX_DW4(ch, i), val); | |
1850 | } | |
e4a1d846 | 1851 | |
f72df8db VS |
1852 | for (i = 0; i < 4; i++) { |
1853 | val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i)); | |
1fb44505 VS |
1854 | val &= ~DPIO_SWING_MARGIN000_MASK; |
1855 | val |= 102 << DPIO_SWING_MARGIN000_SHIFT; | |
f72df8db VS |
1856 | vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val); |
1857 | } | |
e4a1d846 CML |
1858 | |
1859 | /* Disable unique transition scale */ | |
f72df8db VS |
1860 | for (i = 0; i < 4; i++) { |
1861 | val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i)); | |
1862 | val &= ~DPIO_TX_UNIQ_TRANS_SCALE_EN; | |
1863 | vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val); | |
1864 | } | |
e4a1d846 CML |
1865 | |
1866 | /* Additional steps for 1200mV-0dB */ | |
1867 | #if 0 | |
1868 | val = vlv_dpio_read(dev_priv, pipe, VLV_TX_DW3(ch)); | |
1869 | if (ch) | |
1870 | val |= DPIO_TX_UNIQ_TRANS_SCALE_CH1; | |
1871 | else | |
1872 | val |= DPIO_TX_UNIQ_TRANS_SCALE_CH0; | |
1873 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(ch), val); | |
1874 | ||
1875 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(ch), | |
1876 | vlv_dpio_read(dev_priv, pipe, VLV_TX_DW2(ch)) | | |
1877 | (0x9a << DPIO_UNIQ_TRANS_SCALE_SHIFT)); | |
1878 | #endif | |
1879 | /* Start swing calculation */ | |
1966e59e VS |
1880 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch)); |
1881 | val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3; | |
1882 | vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val); | |
1883 | ||
1884 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch)); | |
1885 | val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3; | |
1886 | vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val); | |
e4a1d846 CML |
1887 | |
1888 | /* LRC Bypass */ | |
1889 | val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW30); | |
1890 | val |= DPIO_LRC_BYPASS; | |
1891 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW30, val); | |
1892 | ||
a580516d | 1893 | mutex_unlock(&dev_priv->sb_lock); |
e4a1d846 | 1894 | |
b4eb1564 | 1895 | intel_hdmi->set_infoframes(&encoder->base, |
6e3c9717 | 1896 | intel_crtc->config->has_hdmi_sink, |
b4eb1564 CT |
1897 | adjusted_mode); |
1898 | ||
bf868c7d | 1899 | g4x_enable_hdmi(encoder); |
e4a1d846 | 1900 | |
9b6de0a1 | 1901 | vlv_wait_port_ready(dev_priv, dport, 0x0); |
e4a1d846 CML |
1902 | } |
1903 | ||
7d57382e EA |
1904 | static void intel_hdmi_destroy(struct drm_connector *connector) |
1905 | { | |
10e972d3 | 1906 | kfree(to_intel_connector(connector)->detect_edid); |
7d57382e | 1907 | drm_connector_cleanup(connector); |
674e2d08 | 1908 | kfree(connector); |
7d57382e EA |
1909 | } |
1910 | ||
7d57382e | 1911 | static const struct drm_connector_funcs intel_hdmi_connector_funcs = { |
5ab432ef | 1912 | .dpms = intel_connector_dpms, |
7d57382e | 1913 | .detect = intel_hdmi_detect, |
953ece69 | 1914 | .force = intel_hdmi_force, |
7d57382e | 1915 | .fill_modes = drm_helper_probe_single_connector_modes, |
55b7d6e8 | 1916 | .set_property = intel_hdmi_set_property, |
2545e4a6 | 1917 | .atomic_get_property = intel_connector_atomic_get_property, |
7d57382e | 1918 | .destroy = intel_hdmi_destroy, |
c6f95f27 | 1919 | .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, |
98969725 | 1920 | .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, |
7d57382e EA |
1921 | }; |
1922 | ||
1923 | static const struct drm_connector_helper_funcs intel_hdmi_connector_helper_funcs = { | |
1924 | .get_modes = intel_hdmi_get_modes, | |
1925 | .mode_valid = intel_hdmi_mode_valid, | |
df0e9248 | 1926 | .best_encoder = intel_best_encoder, |
7d57382e EA |
1927 | }; |
1928 | ||
7d57382e | 1929 | static const struct drm_encoder_funcs intel_hdmi_enc_funcs = { |
ea5b213a | 1930 | .destroy = intel_encoder_destroy, |
7d57382e EA |
1931 | }; |
1932 | ||
94a11ddc VK |
1933 | static void |
1934 | intel_attach_aspect_ratio_property(struct drm_connector *connector) | |
1935 | { | |
1936 | if (!drm_mode_create_aspect_ratio_property(connector->dev)) | |
1937 | drm_object_attach_property(&connector->base, | |
1938 | connector->dev->mode_config.aspect_ratio_property, | |
1939 | DRM_MODE_PICTURE_ASPECT_NONE); | |
1940 | } | |
1941 | ||
55b7d6e8 CW |
1942 | static void |
1943 | intel_hdmi_add_properties(struct intel_hdmi *intel_hdmi, struct drm_connector *connector) | |
1944 | { | |
3f43c48d | 1945 | intel_attach_force_audio_property(connector); |
e953fd7b | 1946 | intel_attach_broadcast_rgb_property(connector); |
55bc60db | 1947 | intel_hdmi->color_range_auto = true; |
94a11ddc VK |
1948 | intel_attach_aspect_ratio_property(connector); |
1949 | intel_hdmi->aspect_ratio = HDMI_PICTURE_ASPECT_NONE; | |
55b7d6e8 CW |
1950 | } |
1951 | ||
00c09d70 PZ |
1952 | void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port, |
1953 | struct intel_connector *intel_connector) | |
7d57382e | 1954 | { |
b9cb234c PZ |
1955 | struct drm_connector *connector = &intel_connector->base; |
1956 | struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi; | |
1957 | struct intel_encoder *intel_encoder = &intel_dig_port->base; | |
1958 | struct drm_device *dev = intel_encoder->base.dev; | |
7d57382e | 1959 | struct drm_i915_private *dev_priv = dev->dev_private; |
174edf1f | 1960 | enum port port = intel_dig_port->port; |
373a3cf7 | 1961 | |
7d57382e | 1962 | drm_connector_init(dev, connector, &intel_hdmi_connector_funcs, |
8d91104a | 1963 | DRM_MODE_CONNECTOR_HDMIA); |
7d57382e EA |
1964 | drm_connector_helper_add(connector, &intel_hdmi_connector_helper_funcs); |
1965 | ||
c3febcc4 | 1966 | connector->interlace_allowed = 1; |
7d57382e | 1967 | connector->doublescan_allowed = 0; |
573e74ad | 1968 | connector->stereo_allowed = 1; |
66a9278e | 1969 | |
08d644ad DV |
1970 | switch (port) { |
1971 | case PORT_B: | |
4c272834 JN |
1972 | if (IS_BROXTON(dev_priv)) |
1973 | intel_hdmi->ddc_bus = GMBUS_PIN_1_BXT; | |
1974 | else | |
1975 | intel_hdmi->ddc_bus = GMBUS_PIN_DPB; | |
1d843f9d | 1976 | intel_encoder->hpd_pin = HPD_PORT_B; |
08d644ad DV |
1977 | break; |
1978 | case PORT_C: | |
4c272834 JN |
1979 | if (IS_BROXTON(dev_priv)) |
1980 | intel_hdmi->ddc_bus = GMBUS_PIN_2_BXT; | |
1981 | else | |
1982 | intel_hdmi->ddc_bus = GMBUS_PIN_DPC; | |
1d843f9d | 1983 | intel_encoder->hpd_pin = HPD_PORT_C; |
08d644ad DV |
1984 | break; |
1985 | case PORT_D: | |
4c272834 JN |
1986 | if (WARN_ON(IS_BROXTON(dev_priv))) |
1987 | intel_hdmi->ddc_bus = GMBUS_PIN_DISABLED; | |
1988 | else if (IS_CHERRYVIEW(dev_priv)) | |
988c7015 | 1989 | intel_hdmi->ddc_bus = GMBUS_PIN_DPD_CHV; |
c0c35329 | 1990 | else |
988c7015 | 1991 | intel_hdmi->ddc_bus = GMBUS_PIN_DPD; |
1d843f9d | 1992 | intel_encoder->hpd_pin = HPD_PORT_D; |
08d644ad DV |
1993 | break; |
1994 | case PORT_A: | |
1d843f9d | 1995 | intel_encoder->hpd_pin = HPD_PORT_A; |
08d644ad DV |
1996 | /* Internal port only for eDP. */ |
1997 | default: | |
6e4c1677 | 1998 | BUG(); |
f8aed700 | 1999 | } |
7d57382e | 2000 | |
7637bfdb | 2001 | if (IS_VALLEYVIEW(dev)) { |
90b107c8 | 2002 | intel_hdmi->write_infoframe = vlv_write_infoframe; |
687f4d06 | 2003 | intel_hdmi->set_infoframes = vlv_set_infoframes; |
e43823ec | 2004 | intel_hdmi->infoframe_enabled = vlv_infoframe_enabled; |
b98856a8 | 2005 | } else if (IS_G4X(dev)) { |
7637bfdb JB |
2006 | intel_hdmi->write_infoframe = g4x_write_infoframe; |
2007 | intel_hdmi->set_infoframes = g4x_set_infoframes; | |
e43823ec | 2008 | intel_hdmi->infoframe_enabled = g4x_infoframe_enabled; |
22b8bf17 | 2009 | } else if (HAS_DDI(dev)) { |
8c5f5f7c | 2010 | intel_hdmi->write_infoframe = hsw_write_infoframe; |
687f4d06 | 2011 | intel_hdmi->set_infoframes = hsw_set_infoframes; |
e43823ec | 2012 | intel_hdmi->infoframe_enabled = hsw_infoframe_enabled; |
fdf1250a PZ |
2013 | } else if (HAS_PCH_IBX(dev)) { |
2014 | intel_hdmi->write_infoframe = ibx_write_infoframe; | |
687f4d06 | 2015 | intel_hdmi->set_infoframes = ibx_set_infoframes; |
e43823ec | 2016 | intel_hdmi->infoframe_enabled = ibx_infoframe_enabled; |
fdf1250a PZ |
2017 | } else { |
2018 | intel_hdmi->write_infoframe = cpt_write_infoframe; | |
687f4d06 | 2019 | intel_hdmi->set_infoframes = cpt_set_infoframes; |
e43823ec | 2020 | intel_hdmi->infoframe_enabled = cpt_infoframe_enabled; |
64a8fc01 | 2021 | } |
45187ace | 2022 | |
affa9354 | 2023 | if (HAS_DDI(dev)) |
bcbc889b PZ |
2024 | intel_connector->get_hw_state = intel_ddi_connector_get_hw_state; |
2025 | else | |
2026 | intel_connector->get_hw_state = intel_connector_get_hw_state; | |
4932e2c3 | 2027 | intel_connector->unregister = intel_connector_unregister; |
b9cb234c PZ |
2028 | |
2029 | intel_hdmi_add_properties(intel_hdmi, connector); | |
2030 | ||
2031 | intel_connector_attach_encoder(intel_connector, intel_encoder); | |
34ea3d38 | 2032 | drm_connector_register(connector); |
b9cb234c PZ |
2033 | |
2034 | /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written | |
2035 | * 0xd. Failure to do so will result in spurious interrupts being | |
2036 | * generated on the port when a cable is not attached. | |
2037 | */ | |
2038 | if (IS_G4X(dev) && !IS_GM45(dev)) { | |
2039 | u32 temp = I915_READ(PEG_BAND_GAP_DATA); | |
2040 | I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd); | |
2041 | } | |
2042 | } | |
2043 | ||
b242b7f7 | 2044 | void intel_hdmi_init(struct drm_device *dev, int hdmi_reg, enum port port) |
b9cb234c PZ |
2045 | { |
2046 | struct intel_digital_port *intel_dig_port; | |
2047 | struct intel_encoder *intel_encoder; | |
b9cb234c PZ |
2048 | struct intel_connector *intel_connector; |
2049 | ||
b14c5679 | 2050 | intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL); |
b9cb234c PZ |
2051 | if (!intel_dig_port) |
2052 | return; | |
2053 | ||
08d9bc92 | 2054 | intel_connector = intel_connector_alloc(); |
b9cb234c PZ |
2055 | if (!intel_connector) { |
2056 | kfree(intel_dig_port); | |
2057 | return; | |
2058 | } | |
2059 | ||
2060 | intel_encoder = &intel_dig_port->base; | |
b9cb234c PZ |
2061 | |
2062 | drm_encoder_init(dev, &intel_encoder->base, &intel_hdmi_enc_funcs, | |
2063 | DRM_MODE_ENCODER_TMDS); | |
00c09d70 | 2064 | |
5bfe2ac0 | 2065 | intel_encoder->compute_config = intel_hdmi_compute_config; |
a4790cec VS |
2066 | if (HAS_PCH_SPLIT(dev)) { |
2067 | intel_encoder->disable = pch_disable_hdmi; | |
2068 | intel_encoder->post_disable = pch_post_disable_hdmi; | |
2069 | } else { | |
2070 | intel_encoder->disable = g4x_disable_hdmi; | |
2071 | } | |
00c09d70 | 2072 | intel_encoder->get_hw_state = intel_hdmi_get_hw_state; |
045ac3b5 | 2073 | intel_encoder->get_config = intel_hdmi_get_config; |
e4a1d846 | 2074 | if (IS_CHERRYVIEW(dev)) { |
9197c88b | 2075 | intel_encoder->pre_pll_enable = chv_hdmi_pre_pll_enable; |
e4a1d846 CML |
2076 | intel_encoder->pre_enable = chv_hdmi_pre_enable; |
2077 | intel_encoder->enable = vlv_enable_hdmi; | |
580d3811 | 2078 | intel_encoder->post_disable = chv_hdmi_post_disable; |
e4a1d846 | 2079 | } else if (IS_VALLEYVIEW(dev)) { |
9514ac6e CML |
2080 | intel_encoder->pre_pll_enable = vlv_hdmi_pre_pll_enable; |
2081 | intel_encoder->pre_enable = vlv_hdmi_pre_enable; | |
b76cf76b | 2082 | intel_encoder->enable = vlv_enable_hdmi; |
9514ac6e | 2083 | intel_encoder->post_disable = vlv_hdmi_post_disable; |
b76cf76b | 2084 | } else { |
13732ba7 | 2085 | intel_encoder->pre_enable = intel_hdmi_pre_enable; |
d1b1589c VS |
2086 | if (HAS_PCH_CPT(dev)) |
2087 | intel_encoder->enable = cpt_enable_hdmi; | |
bf868c7d VS |
2088 | else if (HAS_PCH_IBX(dev)) |
2089 | intel_encoder->enable = ibx_enable_hdmi; | |
d1b1589c | 2090 | else |
bf868c7d | 2091 | intel_encoder->enable = g4x_enable_hdmi; |
89b667f8 | 2092 | } |
5ab432ef | 2093 | |
b9cb234c | 2094 | intel_encoder->type = INTEL_OUTPUT_HDMI; |
882ec384 VS |
2095 | if (IS_CHERRYVIEW(dev)) { |
2096 | if (port == PORT_D) | |
2097 | intel_encoder->crtc_mask = 1 << 2; | |
2098 | else | |
2099 | intel_encoder->crtc_mask = (1 << 0) | (1 << 1); | |
2100 | } else { | |
2101 | intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2); | |
2102 | } | |
301ea74a | 2103 | intel_encoder->cloneable = 1 << INTEL_OUTPUT_ANALOG; |
c6f1495d VS |
2104 | /* |
2105 | * BSpec is unclear about HDMI+HDMI cloning on g4x, but it seems | |
2106 | * to work on real hardware. And since g4x can send infoframes to | |
2107 | * only one port anyway, nothing is lost by allowing it. | |
2108 | */ | |
2109 | if (IS_G4X(dev)) | |
2110 | intel_encoder->cloneable |= 1 << INTEL_OUTPUT_HDMI; | |
7d57382e | 2111 | |
174edf1f | 2112 | intel_dig_port->port = port; |
b242b7f7 | 2113 | intel_dig_port->hdmi.hdmi_reg = hdmi_reg; |
b9cb234c | 2114 | intel_dig_port->dp.output_reg = 0; |
55b7d6e8 | 2115 | |
b9cb234c | 2116 | intel_hdmi_init_connector(intel_dig_port, intel_connector); |
7d57382e | 2117 | } |