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7d57382e EA |
1 | /* |
2 | * Copyright 2006 Dave Airlie <airlied@linux.ie> | |
3 | * Copyright © 2006-2009 Intel Corporation | |
4 | * | |
5 | * Permission is hereby granted, free of charge, to any person obtaining a | |
6 | * copy of this software and associated documentation files (the "Software"), | |
7 | * to deal in the Software without restriction, including without limitation | |
8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
9 | * and/or sell copies of the Software, and to permit persons to whom the | |
10 | * Software is furnished to do so, subject to the following conditions: | |
11 | * | |
12 | * The above copyright notice and this permission notice (including the next | |
13 | * paragraph) shall be included in all copies or substantial portions of the | |
14 | * Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
21 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
22 | * DEALINGS IN THE SOFTWARE. | |
23 | * | |
24 | * Authors: | |
25 | * Eric Anholt <eric@anholt.net> | |
26 | * Jesse Barnes <jesse.barnes@intel.com> | |
27 | */ | |
28 | ||
29 | #include <linux/i2c.h> | |
5a0e3ad6 | 30 | #include <linux/slab.h> |
7d57382e EA |
31 | #include <linux/delay.h> |
32 | #include "drmP.h" | |
33 | #include "drm.h" | |
34 | #include "drm_crtc.h" | |
aa93d632 | 35 | #include "drm_edid.h" |
7d57382e EA |
36 | #include "intel_drv.h" |
37 | #include "i915_drm.h" | |
38 | #include "i915_drv.h" | |
39 | ||
afba0188 DV |
40 | static void |
41 | assert_hdmi_port_disabled(struct intel_hdmi *intel_hdmi) | |
42 | { | |
43 | struct drm_device *dev = intel_hdmi->base.base.dev; | |
44 | struct drm_i915_private *dev_priv = dev->dev_private; | |
45 | uint32_t enabled_bits; | |
46 | ||
47 | enabled_bits = IS_HASWELL(dev) ? DDI_BUF_CTL_ENABLE : SDVO_ENABLE; | |
48 | ||
49 | WARN(I915_READ(intel_hdmi->sdvox_reg) & enabled_bits, | |
50 | "HDMI port enabled, expecting disabled\n"); | |
51 | } | |
52 | ||
f5bbfca3 | 53 | struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder) |
ea5b213a | 54 | { |
4ef69c7a | 55 | return container_of(encoder, struct intel_hdmi, base.base); |
ea5b213a CW |
56 | } |
57 | ||
df0e9248 CW |
58 | static struct intel_hdmi *intel_attached_hdmi(struct drm_connector *connector) |
59 | { | |
60 | return container_of(intel_attached_encoder(connector), | |
61 | struct intel_hdmi, base); | |
62 | } | |
63 | ||
45187ace | 64 | void intel_dip_infoframe_csum(struct dip_infoframe *frame) |
3c17fe4b | 65 | { |
45187ace | 66 | uint8_t *data = (uint8_t *)frame; |
3c17fe4b DH |
67 | uint8_t sum = 0; |
68 | unsigned i; | |
69 | ||
45187ace JB |
70 | frame->checksum = 0; |
71 | frame->ecc = 0; | |
3c17fe4b | 72 | |
64a8fc01 | 73 | for (i = 0; i < frame->len + DIP_HEADER_SIZE; i++) |
3c17fe4b DH |
74 | sum += data[i]; |
75 | ||
45187ace | 76 | frame->checksum = 0x100 - sum; |
3c17fe4b DH |
77 | } |
78 | ||
bc2481f3 | 79 | static u32 g4x_infoframe_index(struct dip_infoframe *frame) |
3c17fe4b | 80 | { |
45187ace JB |
81 | switch (frame->type) { |
82 | case DIP_TYPE_AVI: | |
ed517fbb | 83 | return VIDEO_DIP_SELECT_AVI; |
45187ace | 84 | case DIP_TYPE_SPD: |
ed517fbb | 85 | return VIDEO_DIP_SELECT_SPD; |
45187ace JB |
86 | default: |
87 | DRM_DEBUG_DRIVER("unknown info frame type %d\n", frame->type); | |
ed517fbb | 88 | return 0; |
45187ace | 89 | } |
45187ace JB |
90 | } |
91 | ||
bc2481f3 | 92 | static u32 g4x_infoframe_enable(struct dip_infoframe *frame) |
45187ace | 93 | { |
45187ace JB |
94 | switch (frame->type) { |
95 | case DIP_TYPE_AVI: | |
ed517fbb | 96 | return VIDEO_DIP_ENABLE_AVI; |
45187ace | 97 | case DIP_TYPE_SPD: |
ed517fbb | 98 | return VIDEO_DIP_ENABLE_SPD; |
fa193ff7 PZ |
99 | default: |
100 | DRM_DEBUG_DRIVER("unknown info frame type %d\n", frame->type); | |
ed517fbb | 101 | return 0; |
fa193ff7 | 102 | } |
fa193ff7 PZ |
103 | } |
104 | ||
2da8af54 PZ |
105 | static u32 hsw_infoframe_enable(struct dip_infoframe *frame) |
106 | { | |
107 | switch (frame->type) { | |
108 | case DIP_TYPE_AVI: | |
109 | return VIDEO_DIP_ENABLE_AVI_HSW; | |
110 | case DIP_TYPE_SPD: | |
111 | return VIDEO_DIP_ENABLE_SPD_HSW; | |
112 | default: | |
113 | DRM_DEBUG_DRIVER("unknown info frame type %d\n", frame->type); | |
114 | return 0; | |
115 | } | |
116 | } | |
117 | ||
118 | static u32 hsw_infoframe_data_reg(struct dip_infoframe *frame, enum pipe pipe) | |
119 | { | |
120 | switch (frame->type) { | |
121 | case DIP_TYPE_AVI: | |
122 | return HSW_TVIDEO_DIP_AVI_DATA(pipe); | |
123 | case DIP_TYPE_SPD: | |
124 | return HSW_TVIDEO_DIP_SPD_DATA(pipe); | |
125 | default: | |
126 | DRM_DEBUG_DRIVER("unknown info frame type %d\n", frame->type); | |
127 | return 0; | |
128 | } | |
129 | } | |
130 | ||
a3da1df7 DV |
131 | static void g4x_write_infoframe(struct drm_encoder *encoder, |
132 | struct dip_infoframe *frame) | |
45187ace JB |
133 | { |
134 | uint32_t *data = (uint32_t *)frame; | |
3c17fe4b DH |
135 | struct drm_device *dev = encoder->dev; |
136 | struct drm_i915_private *dev_priv = dev->dev_private; | |
22509ec8 | 137 | u32 val = I915_READ(VIDEO_DIP_CTL); |
45187ace | 138 | unsigned i, len = DIP_HEADER_SIZE + frame->len; |
3c17fe4b | 139 | |
822974ae PZ |
140 | WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n"); |
141 | ||
1d4f85ac | 142 | val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ |
bc2481f3 | 143 | val |= g4x_infoframe_index(frame); |
22509ec8 | 144 | |
bc2481f3 | 145 | val &= ~g4x_infoframe_enable(frame); |
45187ace | 146 | |
22509ec8 | 147 | I915_WRITE(VIDEO_DIP_CTL, val); |
3c17fe4b | 148 | |
9d9740f0 | 149 | mmiowb(); |
45187ace | 150 | for (i = 0; i < len; i += 4) { |
3c17fe4b DH |
151 | I915_WRITE(VIDEO_DIP_DATA, *data); |
152 | data++; | |
153 | } | |
9d9740f0 | 154 | mmiowb(); |
3c17fe4b | 155 | |
bc2481f3 | 156 | val |= g4x_infoframe_enable(frame); |
60c5ea2d | 157 | val &= ~VIDEO_DIP_FREQ_MASK; |
4b24c933 | 158 | val |= VIDEO_DIP_FREQ_VSYNC; |
45187ace | 159 | |
22509ec8 | 160 | I915_WRITE(VIDEO_DIP_CTL, val); |
9d9740f0 | 161 | POSTING_READ(VIDEO_DIP_CTL); |
3c17fe4b DH |
162 | } |
163 | ||
fdf1250a PZ |
164 | static void ibx_write_infoframe(struct drm_encoder *encoder, |
165 | struct dip_infoframe *frame) | |
166 | { | |
167 | uint32_t *data = (uint32_t *)frame; | |
168 | struct drm_device *dev = encoder->dev; | |
169 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ed517fbb | 170 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); |
fdf1250a PZ |
171 | int reg = TVIDEO_DIP_CTL(intel_crtc->pipe); |
172 | unsigned i, len = DIP_HEADER_SIZE + frame->len; | |
173 | u32 val = I915_READ(reg); | |
174 | ||
822974ae PZ |
175 | WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n"); |
176 | ||
fdf1250a | 177 | val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ |
bc2481f3 | 178 | val |= g4x_infoframe_index(frame); |
fdf1250a | 179 | |
bc2481f3 | 180 | val &= ~g4x_infoframe_enable(frame); |
fdf1250a PZ |
181 | |
182 | I915_WRITE(reg, val); | |
183 | ||
9d9740f0 | 184 | mmiowb(); |
fdf1250a PZ |
185 | for (i = 0; i < len; i += 4) { |
186 | I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data); | |
187 | data++; | |
188 | } | |
9d9740f0 | 189 | mmiowb(); |
fdf1250a | 190 | |
bc2481f3 | 191 | val |= g4x_infoframe_enable(frame); |
fdf1250a | 192 | val &= ~VIDEO_DIP_FREQ_MASK; |
4b24c933 | 193 | val |= VIDEO_DIP_FREQ_VSYNC; |
fdf1250a PZ |
194 | |
195 | I915_WRITE(reg, val); | |
9d9740f0 | 196 | POSTING_READ(reg); |
fdf1250a PZ |
197 | } |
198 | ||
199 | static void cpt_write_infoframe(struct drm_encoder *encoder, | |
200 | struct dip_infoframe *frame) | |
b055c8f3 | 201 | { |
45187ace | 202 | uint32_t *data = (uint32_t *)frame; |
b055c8f3 JB |
203 | struct drm_device *dev = encoder->dev; |
204 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ed517fbb | 205 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); |
b055c8f3 | 206 | int reg = TVIDEO_DIP_CTL(intel_crtc->pipe); |
45187ace | 207 | unsigned i, len = DIP_HEADER_SIZE + frame->len; |
22509ec8 | 208 | u32 val = I915_READ(reg); |
b055c8f3 | 209 | |
822974ae PZ |
210 | WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n"); |
211 | ||
64a8fc01 | 212 | val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ |
bc2481f3 | 213 | val |= g4x_infoframe_index(frame); |
45187ace | 214 | |
ecb97851 PZ |
215 | /* The DIP control register spec says that we need to update the AVI |
216 | * infoframe without clearing its enable bit */ | |
822974ae | 217 | if (frame->type != DIP_TYPE_AVI) |
bc2481f3 | 218 | val &= ~g4x_infoframe_enable(frame); |
ecb97851 | 219 | |
22509ec8 | 220 | I915_WRITE(reg, val); |
45187ace | 221 | |
9d9740f0 | 222 | mmiowb(); |
45187ace | 223 | for (i = 0; i < len; i += 4) { |
b055c8f3 JB |
224 | I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data); |
225 | data++; | |
226 | } | |
9d9740f0 | 227 | mmiowb(); |
b055c8f3 | 228 | |
bc2481f3 | 229 | val |= g4x_infoframe_enable(frame); |
60c5ea2d | 230 | val &= ~VIDEO_DIP_FREQ_MASK; |
4b24c933 | 231 | val |= VIDEO_DIP_FREQ_VSYNC; |
45187ace | 232 | |
22509ec8 | 233 | I915_WRITE(reg, val); |
9d9740f0 | 234 | POSTING_READ(reg); |
45187ace | 235 | } |
90b107c8 SK |
236 | |
237 | static void vlv_write_infoframe(struct drm_encoder *encoder, | |
238 | struct dip_infoframe *frame) | |
239 | { | |
240 | uint32_t *data = (uint32_t *)frame; | |
241 | struct drm_device *dev = encoder->dev; | |
242 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ed517fbb | 243 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); |
90b107c8 SK |
244 | int reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe); |
245 | unsigned i, len = DIP_HEADER_SIZE + frame->len; | |
22509ec8 | 246 | u32 val = I915_READ(reg); |
90b107c8 | 247 | |
822974ae PZ |
248 | WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n"); |
249 | ||
90b107c8 | 250 | val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ |
bc2481f3 | 251 | val |= g4x_infoframe_index(frame); |
22509ec8 | 252 | |
bc2481f3 | 253 | val &= ~g4x_infoframe_enable(frame); |
90b107c8 | 254 | |
22509ec8 | 255 | I915_WRITE(reg, val); |
90b107c8 | 256 | |
9d9740f0 | 257 | mmiowb(); |
90b107c8 SK |
258 | for (i = 0; i < len; i += 4) { |
259 | I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), *data); | |
260 | data++; | |
261 | } | |
9d9740f0 | 262 | mmiowb(); |
90b107c8 | 263 | |
bc2481f3 | 264 | val |= g4x_infoframe_enable(frame); |
60c5ea2d | 265 | val &= ~VIDEO_DIP_FREQ_MASK; |
4b24c933 | 266 | val |= VIDEO_DIP_FREQ_VSYNC; |
90b107c8 | 267 | |
22509ec8 | 268 | I915_WRITE(reg, val); |
9d9740f0 | 269 | POSTING_READ(reg); |
90b107c8 SK |
270 | } |
271 | ||
8c5f5f7c | 272 | static void hsw_write_infoframe(struct drm_encoder *encoder, |
ed517fbb | 273 | struct dip_infoframe *frame) |
8c5f5f7c | 274 | { |
2da8af54 PZ |
275 | uint32_t *data = (uint32_t *)frame; |
276 | struct drm_device *dev = encoder->dev; | |
277 | struct drm_i915_private *dev_priv = dev->dev_private; | |
278 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); | |
279 | u32 ctl_reg = HSW_TVIDEO_DIP_CTL(intel_crtc->pipe); | |
280 | u32 data_reg = hsw_infoframe_data_reg(frame, intel_crtc->pipe); | |
281 | unsigned int i, len = DIP_HEADER_SIZE + frame->len; | |
282 | u32 val = I915_READ(ctl_reg); | |
8c5f5f7c | 283 | |
2da8af54 PZ |
284 | if (data_reg == 0) |
285 | return; | |
286 | ||
2da8af54 PZ |
287 | val &= ~hsw_infoframe_enable(frame); |
288 | I915_WRITE(ctl_reg, val); | |
289 | ||
9d9740f0 | 290 | mmiowb(); |
2da8af54 PZ |
291 | for (i = 0; i < len; i += 4) { |
292 | I915_WRITE(data_reg + i, *data); | |
293 | data++; | |
294 | } | |
9d9740f0 | 295 | mmiowb(); |
8c5f5f7c | 296 | |
2da8af54 PZ |
297 | val |= hsw_infoframe_enable(frame); |
298 | I915_WRITE(ctl_reg, val); | |
9d9740f0 | 299 | POSTING_READ(ctl_reg); |
8c5f5f7c ED |
300 | } |
301 | ||
45187ace JB |
302 | static void intel_set_infoframe(struct drm_encoder *encoder, |
303 | struct dip_infoframe *frame) | |
304 | { | |
305 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); | |
306 | ||
45187ace JB |
307 | intel_dip_infoframe_csum(frame); |
308 | intel_hdmi->write_infoframe(encoder, frame); | |
309 | } | |
310 | ||
687f4d06 | 311 | static void intel_hdmi_set_avi_infoframe(struct drm_encoder *encoder, |
c846b619 | 312 | struct drm_display_mode *adjusted_mode) |
45187ace JB |
313 | { |
314 | struct dip_infoframe avi_if = { | |
315 | .type = DIP_TYPE_AVI, | |
316 | .ver = DIP_VERSION_AVI, | |
317 | .len = DIP_LEN_AVI, | |
318 | }; | |
319 | ||
c846b619 PZ |
320 | if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK) |
321 | avi_if.body.avi.YQ_CN_PR |= DIP_AVI_PR_2; | |
322 | ||
45187ace | 323 | intel_set_infoframe(encoder, &avi_if); |
b055c8f3 JB |
324 | } |
325 | ||
687f4d06 | 326 | static void intel_hdmi_set_spd_infoframe(struct drm_encoder *encoder) |
c0864cb3 JB |
327 | { |
328 | struct dip_infoframe spd_if; | |
329 | ||
330 | memset(&spd_if, 0, sizeof(spd_if)); | |
331 | spd_if.type = DIP_TYPE_SPD; | |
332 | spd_if.ver = DIP_VERSION_SPD; | |
333 | spd_if.len = DIP_LEN_SPD; | |
334 | strcpy(spd_if.body.spd.vn, "Intel"); | |
335 | strcpy(spd_if.body.spd.pd, "Integrated gfx"); | |
336 | spd_if.body.spd.sdi = DIP_SPD_PC; | |
337 | ||
338 | intel_set_infoframe(encoder, &spd_if); | |
339 | } | |
340 | ||
687f4d06 PZ |
341 | static void g4x_set_infoframes(struct drm_encoder *encoder, |
342 | struct drm_display_mode *adjusted_mode) | |
343 | { | |
0c14c7f9 PZ |
344 | struct drm_i915_private *dev_priv = encoder->dev->dev_private; |
345 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); | |
346 | u32 reg = VIDEO_DIP_CTL; | |
347 | u32 val = I915_READ(reg); | |
72b78c9d | 348 | u32 port; |
0c14c7f9 | 349 | |
afba0188 DV |
350 | assert_hdmi_port_disabled(intel_hdmi); |
351 | ||
0c14c7f9 PZ |
352 | /* If the registers were not initialized yet, they might be zeroes, |
353 | * which means we're selecting the AVI DIP and we're setting its | |
354 | * frequency to once. This seems to really confuse the HW and make | |
355 | * things stop working (the register spec says the AVI always needs to | |
356 | * be sent every VSync). So here we avoid writing to the register more | |
357 | * than we need and also explicitly select the AVI DIP and explicitly | |
358 | * set its frequency to every VSync. Avoiding to write it twice seems to | |
359 | * be enough to solve the problem, but being defensive shouldn't hurt us | |
360 | * either. */ | |
361 | val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; | |
362 | ||
363 | if (!intel_hdmi->has_hdmi_sink) { | |
364 | if (!(val & VIDEO_DIP_ENABLE)) | |
365 | return; | |
366 | val &= ~VIDEO_DIP_ENABLE; | |
367 | I915_WRITE(reg, val); | |
9d9740f0 | 368 | POSTING_READ(reg); |
0c14c7f9 PZ |
369 | return; |
370 | } | |
371 | ||
f278d972 PZ |
372 | switch (intel_hdmi->sdvox_reg) { |
373 | case SDVOB: | |
72b78c9d | 374 | port = VIDEO_DIP_PORT_B; |
f278d972 PZ |
375 | break; |
376 | case SDVOC: | |
72b78c9d | 377 | port = VIDEO_DIP_PORT_C; |
f278d972 PZ |
378 | break; |
379 | default: | |
380 | return; | |
381 | } | |
382 | ||
72b78c9d PZ |
383 | if (port != (val & VIDEO_DIP_PORT_MASK)) { |
384 | if (val & VIDEO_DIP_ENABLE) { | |
385 | val &= ~VIDEO_DIP_ENABLE; | |
386 | I915_WRITE(reg, val); | |
9d9740f0 | 387 | POSTING_READ(reg); |
72b78c9d PZ |
388 | } |
389 | val &= ~VIDEO_DIP_PORT_MASK; | |
390 | val |= port; | |
391 | } | |
392 | ||
822974ae | 393 | val |= VIDEO_DIP_ENABLE; |
0dd87d20 | 394 | val &= ~VIDEO_DIP_ENABLE_VENDOR; |
822974ae | 395 | |
f278d972 | 396 | I915_WRITE(reg, val); |
9d9740f0 | 397 | POSTING_READ(reg); |
f278d972 | 398 | |
687f4d06 PZ |
399 | intel_hdmi_set_avi_infoframe(encoder, adjusted_mode); |
400 | intel_hdmi_set_spd_infoframe(encoder); | |
401 | } | |
402 | ||
403 | static void ibx_set_infoframes(struct drm_encoder *encoder, | |
404 | struct drm_display_mode *adjusted_mode) | |
405 | { | |
0c14c7f9 PZ |
406 | struct drm_i915_private *dev_priv = encoder->dev->dev_private; |
407 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); | |
408 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); | |
409 | u32 reg = TVIDEO_DIP_CTL(intel_crtc->pipe); | |
410 | u32 val = I915_READ(reg); | |
72b78c9d | 411 | u32 port; |
0c14c7f9 | 412 | |
afba0188 DV |
413 | assert_hdmi_port_disabled(intel_hdmi); |
414 | ||
0c14c7f9 PZ |
415 | /* See the big comment in g4x_set_infoframes() */ |
416 | val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; | |
417 | ||
418 | if (!intel_hdmi->has_hdmi_sink) { | |
419 | if (!(val & VIDEO_DIP_ENABLE)) | |
420 | return; | |
421 | val &= ~VIDEO_DIP_ENABLE; | |
422 | I915_WRITE(reg, val); | |
9d9740f0 | 423 | POSTING_READ(reg); |
0c14c7f9 PZ |
424 | return; |
425 | } | |
426 | ||
f278d972 PZ |
427 | switch (intel_hdmi->sdvox_reg) { |
428 | case HDMIB: | |
72b78c9d | 429 | port = VIDEO_DIP_PORT_B; |
f278d972 PZ |
430 | break; |
431 | case HDMIC: | |
72b78c9d | 432 | port = VIDEO_DIP_PORT_C; |
f278d972 PZ |
433 | break; |
434 | case HDMID: | |
72b78c9d | 435 | port = VIDEO_DIP_PORT_D; |
f278d972 PZ |
436 | break; |
437 | default: | |
438 | return; | |
439 | } | |
440 | ||
72b78c9d PZ |
441 | if (port != (val & VIDEO_DIP_PORT_MASK)) { |
442 | if (val & VIDEO_DIP_ENABLE) { | |
443 | val &= ~VIDEO_DIP_ENABLE; | |
444 | I915_WRITE(reg, val); | |
9d9740f0 | 445 | POSTING_READ(reg); |
72b78c9d PZ |
446 | } |
447 | val &= ~VIDEO_DIP_PORT_MASK; | |
448 | val |= port; | |
449 | } | |
450 | ||
822974ae | 451 | val |= VIDEO_DIP_ENABLE; |
0dd87d20 PZ |
452 | val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | |
453 | VIDEO_DIP_ENABLE_GCP); | |
822974ae | 454 | |
f278d972 | 455 | I915_WRITE(reg, val); |
9d9740f0 | 456 | POSTING_READ(reg); |
f278d972 | 457 | |
687f4d06 PZ |
458 | intel_hdmi_set_avi_infoframe(encoder, adjusted_mode); |
459 | intel_hdmi_set_spd_infoframe(encoder); | |
460 | } | |
461 | ||
462 | static void cpt_set_infoframes(struct drm_encoder *encoder, | |
463 | struct drm_display_mode *adjusted_mode) | |
464 | { | |
0c14c7f9 PZ |
465 | struct drm_i915_private *dev_priv = encoder->dev->dev_private; |
466 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); | |
467 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); | |
468 | u32 reg = TVIDEO_DIP_CTL(intel_crtc->pipe); | |
469 | u32 val = I915_READ(reg); | |
470 | ||
afba0188 DV |
471 | assert_hdmi_port_disabled(intel_hdmi); |
472 | ||
0c14c7f9 PZ |
473 | /* See the big comment in g4x_set_infoframes() */ |
474 | val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; | |
475 | ||
476 | if (!intel_hdmi->has_hdmi_sink) { | |
477 | if (!(val & VIDEO_DIP_ENABLE)) | |
478 | return; | |
479 | val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI); | |
480 | I915_WRITE(reg, val); | |
9d9740f0 | 481 | POSTING_READ(reg); |
0c14c7f9 PZ |
482 | return; |
483 | } | |
484 | ||
822974ae PZ |
485 | /* Set both together, unset both together: see the spec. */ |
486 | val |= VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI; | |
0dd87d20 PZ |
487 | val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | |
488 | VIDEO_DIP_ENABLE_GCP); | |
822974ae PZ |
489 | |
490 | I915_WRITE(reg, val); | |
9d9740f0 | 491 | POSTING_READ(reg); |
822974ae | 492 | |
687f4d06 PZ |
493 | intel_hdmi_set_avi_infoframe(encoder, adjusted_mode); |
494 | intel_hdmi_set_spd_infoframe(encoder); | |
495 | } | |
496 | ||
497 | static void vlv_set_infoframes(struct drm_encoder *encoder, | |
498 | struct drm_display_mode *adjusted_mode) | |
499 | { | |
0c14c7f9 PZ |
500 | struct drm_i915_private *dev_priv = encoder->dev->dev_private; |
501 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); | |
502 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); | |
503 | u32 reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe); | |
504 | u32 val = I915_READ(reg); | |
505 | ||
afba0188 DV |
506 | assert_hdmi_port_disabled(intel_hdmi); |
507 | ||
0c14c7f9 PZ |
508 | /* See the big comment in g4x_set_infoframes() */ |
509 | val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; | |
510 | ||
511 | if (!intel_hdmi->has_hdmi_sink) { | |
512 | if (!(val & VIDEO_DIP_ENABLE)) | |
513 | return; | |
514 | val &= ~VIDEO_DIP_ENABLE; | |
515 | I915_WRITE(reg, val); | |
9d9740f0 | 516 | POSTING_READ(reg); |
0c14c7f9 PZ |
517 | return; |
518 | } | |
519 | ||
822974ae | 520 | val |= VIDEO_DIP_ENABLE; |
0dd87d20 PZ |
521 | val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | |
522 | VIDEO_DIP_ENABLE_GCP); | |
822974ae PZ |
523 | |
524 | I915_WRITE(reg, val); | |
9d9740f0 | 525 | POSTING_READ(reg); |
822974ae | 526 | |
687f4d06 PZ |
527 | intel_hdmi_set_avi_infoframe(encoder, adjusted_mode); |
528 | intel_hdmi_set_spd_infoframe(encoder); | |
529 | } | |
530 | ||
531 | static void hsw_set_infoframes(struct drm_encoder *encoder, | |
532 | struct drm_display_mode *adjusted_mode) | |
533 | { | |
0c14c7f9 PZ |
534 | struct drm_i915_private *dev_priv = encoder->dev->dev_private; |
535 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); | |
536 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); | |
537 | u32 reg = HSW_TVIDEO_DIP_CTL(intel_crtc->pipe); | |
0dd87d20 | 538 | u32 val = I915_READ(reg); |
0c14c7f9 | 539 | |
afba0188 DV |
540 | assert_hdmi_port_disabled(intel_hdmi); |
541 | ||
0c14c7f9 PZ |
542 | if (!intel_hdmi->has_hdmi_sink) { |
543 | I915_WRITE(reg, 0); | |
9d9740f0 | 544 | POSTING_READ(reg); |
0c14c7f9 PZ |
545 | return; |
546 | } | |
547 | ||
0dd87d20 PZ |
548 | val &= ~(VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_GCP_HSW | |
549 | VIDEO_DIP_ENABLE_VS_HSW | VIDEO_DIP_ENABLE_GMP_HSW); | |
550 | ||
551 | I915_WRITE(reg, val); | |
9d9740f0 | 552 | POSTING_READ(reg); |
0dd87d20 | 553 | |
687f4d06 PZ |
554 | intel_hdmi_set_avi_infoframe(encoder, adjusted_mode); |
555 | intel_hdmi_set_spd_infoframe(encoder); | |
556 | } | |
557 | ||
7d57382e EA |
558 | static void intel_hdmi_mode_set(struct drm_encoder *encoder, |
559 | struct drm_display_mode *mode, | |
560 | struct drm_display_mode *adjusted_mode) | |
561 | { | |
562 | struct drm_device *dev = encoder->dev; | |
563 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ed517fbb | 564 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); |
ea5b213a | 565 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); |
7d57382e EA |
566 | u32 sdvox; |
567 | ||
b659c3db | 568 | sdvox = SDVO_ENCODING_HDMI; |
5d4fac97 JB |
569 | if (!HAS_PCH_SPLIT(dev)) |
570 | sdvox |= intel_hdmi->color_range; | |
b599c0bc AJ |
571 | if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) |
572 | sdvox |= SDVO_VSYNC_ACTIVE_HIGH; | |
573 | if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) | |
574 | sdvox |= SDVO_HSYNC_ACTIVE_HIGH; | |
7d57382e | 575 | |
020f6704 JB |
576 | if (intel_crtc->bpp > 24) |
577 | sdvox |= COLOR_FORMAT_12bpc; | |
578 | else | |
579 | sdvox |= COLOR_FORMAT_8bpc; | |
580 | ||
2e3d6006 ZW |
581 | /* Required on CPT */ |
582 | if (intel_hdmi->has_hdmi_sink && HAS_PCH_CPT(dev)) | |
583 | sdvox |= HDMI_MODE_SELECT; | |
584 | ||
3c17fe4b | 585 | if (intel_hdmi->has_audio) { |
e0dac65e WF |
586 | DRM_DEBUG_DRIVER("Enabling HDMI audio on pipe %c\n", |
587 | pipe_name(intel_crtc->pipe)); | |
7d57382e | 588 | sdvox |= SDVO_AUDIO_ENABLE; |
3c17fe4b | 589 | sdvox |= SDVO_NULL_PACKETS_DURING_VSYNC; |
e0dac65e | 590 | intel_write_eld(encoder, adjusted_mode); |
3c17fe4b | 591 | } |
7d57382e | 592 | |
75770564 JB |
593 | if (HAS_PCH_CPT(dev)) |
594 | sdvox |= PORT_TRANS_SEL_CPT(intel_crtc->pipe); | |
7a87c289 | 595 | else if (intel_crtc->pipe == PIPE_B) |
75770564 | 596 | sdvox |= SDVO_PIPE_B_SELECT; |
7d57382e | 597 | |
ea5b213a CW |
598 | I915_WRITE(intel_hdmi->sdvox_reg, sdvox); |
599 | POSTING_READ(intel_hdmi->sdvox_reg); | |
3c17fe4b | 600 | |
687f4d06 | 601 | intel_hdmi->set_infoframes(encoder, adjusted_mode); |
7d57382e EA |
602 | } |
603 | ||
604 | static void intel_hdmi_dpms(struct drm_encoder *encoder, int mode) | |
605 | { | |
606 | struct drm_device *dev = encoder->dev; | |
607 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ea5b213a | 608 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); |
7d57382e | 609 | u32 temp; |
2deed761 WF |
610 | u32 enable_bits = SDVO_ENABLE; |
611 | ||
612 | if (intel_hdmi->has_audio) | |
613 | enable_bits |= SDVO_AUDIO_ENABLE; | |
7d57382e | 614 | |
ea5b213a | 615 | temp = I915_READ(intel_hdmi->sdvox_reg); |
d8a2d0e0 | 616 | |
7a87c289 DV |
617 | /* HW workaround for IBX, we need to move the port to transcoder A |
618 | * before disabling it. */ | |
619 | if (HAS_PCH_IBX(dev)) { | |
620 | struct drm_crtc *crtc = encoder->crtc; | |
621 | int pipe = crtc ? to_intel_crtc(crtc)->pipe : -1; | |
622 | ||
623 | if (mode != DRM_MODE_DPMS_ON) { | |
624 | if (temp & SDVO_PIPE_B_SELECT) { | |
625 | temp &= ~SDVO_PIPE_B_SELECT; | |
626 | I915_WRITE(intel_hdmi->sdvox_reg, temp); | |
627 | POSTING_READ(intel_hdmi->sdvox_reg); | |
628 | ||
629 | /* Again we need to write this twice. */ | |
630 | I915_WRITE(intel_hdmi->sdvox_reg, temp); | |
631 | POSTING_READ(intel_hdmi->sdvox_reg); | |
632 | ||
633 | /* Transcoder selection bits only update | |
634 | * effectively on vblank. */ | |
635 | if (crtc) | |
636 | intel_wait_for_vblank(dev, pipe); | |
637 | else | |
638 | msleep(50); | |
639 | } | |
640 | } else { | |
641 | /* Restore the transcoder select bit. */ | |
642 | if (pipe == PIPE_B) | |
643 | enable_bits |= SDVO_PIPE_B_SELECT; | |
644 | } | |
645 | } | |
646 | ||
d8a2d0e0 ZW |
647 | /* HW workaround, need to toggle enable bit off and on for 12bpc, but |
648 | * we do this anyway which shows more stable in testing. | |
649 | */ | |
c619eed4 | 650 | if (HAS_PCH_SPLIT(dev)) { |
ea5b213a CW |
651 | I915_WRITE(intel_hdmi->sdvox_reg, temp & ~SDVO_ENABLE); |
652 | POSTING_READ(intel_hdmi->sdvox_reg); | |
d8a2d0e0 ZW |
653 | } |
654 | ||
655 | if (mode != DRM_MODE_DPMS_ON) { | |
2deed761 | 656 | temp &= ~enable_bits; |
7d57382e | 657 | } else { |
2deed761 | 658 | temp |= enable_bits; |
7d57382e | 659 | } |
d8a2d0e0 | 660 | |
ea5b213a CW |
661 | I915_WRITE(intel_hdmi->sdvox_reg, temp); |
662 | POSTING_READ(intel_hdmi->sdvox_reg); | |
d8a2d0e0 ZW |
663 | |
664 | /* HW workaround, need to write this twice for issue that may result | |
665 | * in first write getting masked. | |
666 | */ | |
c619eed4 | 667 | if (HAS_PCH_SPLIT(dev)) { |
ea5b213a CW |
668 | I915_WRITE(intel_hdmi->sdvox_reg, temp); |
669 | POSTING_READ(intel_hdmi->sdvox_reg); | |
d8a2d0e0 | 670 | } |
7d57382e EA |
671 | } |
672 | ||
7d57382e EA |
673 | static int intel_hdmi_mode_valid(struct drm_connector *connector, |
674 | struct drm_display_mode *mode) | |
675 | { | |
676 | if (mode->clock > 165000) | |
677 | return MODE_CLOCK_HIGH; | |
678 | if (mode->clock < 20000) | |
5cbba41d | 679 | return MODE_CLOCK_LOW; |
7d57382e EA |
680 | |
681 | if (mode->flags & DRM_MODE_FLAG_DBLSCAN) | |
682 | return MODE_NO_DBLESCAN; | |
683 | ||
684 | return MODE_OK; | |
685 | } | |
686 | ||
687 | static bool intel_hdmi_mode_fixup(struct drm_encoder *encoder, | |
e811f5ae | 688 | const struct drm_display_mode *mode, |
7d57382e EA |
689 | struct drm_display_mode *adjusted_mode) |
690 | { | |
691 | return true; | |
692 | } | |
693 | ||
8ec22b21 CW |
694 | static bool g4x_hdmi_connected(struct intel_hdmi *intel_hdmi) |
695 | { | |
696 | struct drm_device *dev = intel_hdmi->base.base.dev; | |
697 | struct drm_i915_private *dev_priv = dev->dev_private; | |
698 | uint32_t bit; | |
699 | ||
700 | switch (intel_hdmi->sdvox_reg) { | |
eeafaaca | 701 | case SDVOB: |
8ec22b21 CW |
702 | bit = HDMIB_HOTPLUG_LIVE_STATUS; |
703 | break; | |
eeafaaca | 704 | case SDVOC: |
8ec22b21 CW |
705 | bit = HDMIC_HOTPLUG_LIVE_STATUS; |
706 | break; | |
8ec22b21 CW |
707 | default: |
708 | bit = 0; | |
709 | break; | |
710 | } | |
711 | ||
712 | return I915_READ(PORT_HOTPLUG_STAT) & bit; | |
713 | } | |
714 | ||
aa93d632 | 715 | static enum drm_connector_status |
930a9e28 | 716 | intel_hdmi_detect(struct drm_connector *connector, bool force) |
9dff6af8 | 717 | { |
df0e9248 | 718 | struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); |
f899fc64 CW |
719 | struct drm_i915_private *dev_priv = connector->dev->dev_private; |
720 | struct edid *edid; | |
aa93d632 | 721 | enum drm_connector_status status = connector_status_disconnected; |
9dff6af8 | 722 | |
8ec22b21 CW |
723 | if (IS_G4X(connector->dev) && !g4x_hdmi_connected(intel_hdmi)) |
724 | return status; | |
725 | ||
ea5b213a | 726 | intel_hdmi->has_hdmi_sink = false; |
2e3d6006 | 727 | intel_hdmi->has_audio = false; |
f899fc64 | 728 | edid = drm_get_edid(connector, |
3bd7d909 DK |
729 | intel_gmbus_get_adapter(dev_priv, |
730 | intel_hdmi->ddc_bus)); | |
2ded9e27 | 731 | |
aa93d632 | 732 | if (edid) { |
be9f1c4f | 733 | if (edid->input & DRM_EDID_INPUT_DIGITAL) { |
aa93d632 | 734 | status = connector_status_connected; |
b1d7e4b4 WF |
735 | if (intel_hdmi->force_audio != HDMI_AUDIO_OFF_DVI) |
736 | intel_hdmi->has_hdmi_sink = | |
737 | drm_detect_hdmi_monitor(edid); | |
2e3d6006 | 738 | intel_hdmi->has_audio = drm_detect_monitor_audio(edid); |
aa93d632 | 739 | } |
674e2d08 | 740 | connector->display_info.raw_edid = NULL; |
aa93d632 | 741 | kfree(edid); |
9dff6af8 | 742 | } |
30ad48b7 | 743 | |
55b7d6e8 | 744 | if (status == connector_status_connected) { |
b1d7e4b4 WF |
745 | if (intel_hdmi->force_audio != HDMI_AUDIO_AUTO) |
746 | intel_hdmi->has_audio = | |
747 | (intel_hdmi->force_audio == HDMI_AUDIO_ON); | |
55b7d6e8 CW |
748 | } |
749 | ||
2ded9e27 | 750 | return status; |
7d57382e EA |
751 | } |
752 | ||
753 | static int intel_hdmi_get_modes(struct drm_connector *connector) | |
754 | { | |
df0e9248 | 755 | struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); |
f899fc64 | 756 | struct drm_i915_private *dev_priv = connector->dev->dev_private; |
7d57382e EA |
757 | |
758 | /* We should parse the EDID data and find out if it's an HDMI sink so | |
759 | * we can send audio to it. | |
760 | */ | |
761 | ||
f899fc64 | 762 | return intel_ddc_get_modes(connector, |
3bd7d909 DK |
763 | intel_gmbus_get_adapter(dev_priv, |
764 | intel_hdmi->ddc_bus)); | |
7d57382e EA |
765 | } |
766 | ||
1aad7ac0 CW |
767 | static bool |
768 | intel_hdmi_detect_audio(struct drm_connector *connector) | |
769 | { | |
770 | struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); | |
771 | struct drm_i915_private *dev_priv = connector->dev->dev_private; | |
772 | struct edid *edid; | |
773 | bool has_audio = false; | |
774 | ||
775 | edid = drm_get_edid(connector, | |
3bd7d909 DK |
776 | intel_gmbus_get_adapter(dev_priv, |
777 | intel_hdmi->ddc_bus)); | |
1aad7ac0 CW |
778 | if (edid) { |
779 | if (edid->input & DRM_EDID_INPUT_DIGITAL) | |
780 | has_audio = drm_detect_monitor_audio(edid); | |
781 | ||
782 | connector->display_info.raw_edid = NULL; | |
783 | kfree(edid); | |
784 | } | |
785 | ||
786 | return has_audio; | |
787 | } | |
788 | ||
55b7d6e8 CW |
789 | static int |
790 | intel_hdmi_set_property(struct drm_connector *connector, | |
ed517fbb PZ |
791 | struct drm_property *property, |
792 | uint64_t val) | |
55b7d6e8 CW |
793 | { |
794 | struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); | |
e953fd7b | 795 | struct drm_i915_private *dev_priv = connector->dev->dev_private; |
55b7d6e8 CW |
796 | int ret; |
797 | ||
798 | ret = drm_connector_property_set_value(connector, property, val); | |
799 | if (ret) | |
800 | return ret; | |
801 | ||
3f43c48d | 802 | if (property == dev_priv->force_audio_property) { |
b1d7e4b4 | 803 | enum hdmi_force_audio i = val; |
1aad7ac0 CW |
804 | bool has_audio; |
805 | ||
806 | if (i == intel_hdmi->force_audio) | |
55b7d6e8 CW |
807 | return 0; |
808 | ||
1aad7ac0 | 809 | intel_hdmi->force_audio = i; |
55b7d6e8 | 810 | |
b1d7e4b4 | 811 | if (i == HDMI_AUDIO_AUTO) |
1aad7ac0 CW |
812 | has_audio = intel_hdmi_detect_audio(connector); |
813 | else | |
b1d7e4b4 | 814 | has_audio = (i == HDMI_AUDIO_ON); |
1aad7ac0 | 815 | |
b1d7e4b4 WF |
816 | if (i == HDMI_AUDIO_OFF_DVI) |
817 | intel_hdmi->has_hdmi_sink = 0; | |
55b7d6e8 | 818 | |
1aad7ac0 | 819 | intel_hdmi->has_audio = has_audio; |
55b7d6e8 CW |
820 | goto done; |
821 | } | |
822 | ||
e953fd7b CW |
823 | if (property == dev_priv->broadcast_rgb_property) { |
824 | if (val == !!intel_hdmi->color_range) | |
825 | return 0; | |
826 | ||
827 | intel_hdmi->color_range = val ? SDVO_COLOR_RANGE_16_235 : 0; | |
828 | goto done; | |
829 | } | |
830 | ||
55b7d6e8 CW |
831 | return -EINVAL; |
832 | ||
833 | done: | |
834 | if (intel_hdmi->base.base.crtc) { | |
835 | struct drm_crtc *crtc = intel_hdmi->base.base.crtc; | |
836 | drm_crtc_helper_set_mode(crtc, &crtc->mode, | |
837 | crtc->x, crtc->y, | |
838 | crtc->fb); | |
839 | } | |
840 | ||
841 | return 0; | |
842 | } | |
843 | ||
7d57382e EA |
844 | static void intel_hdmi_destroy(struct drm_connector *connector) |
845 | { | |
7d57382e EA |
846 | drm_sysfs_connector_remove(connector); |
847 | drm_connector_cleanup(connector); | |
674e2d08 | 848 | kfree(connector); |
7d57382e EA |
849 | } |
850 | ||
72662e10 ED |
851 | static const struct drm_encoder_helper_funcs intel_hdmi_helper_funcs_hsw = { |
852 | .dpms = intel_ddi_dpms, | |
853 | .mode_fixup = intel_hdmi_mode_fixup, | |
854 | .prepare = intel_encoder_prepare, | |
855 | .mode_set = intel_ddi_mode_set, | |
856 | .commit = intel_encoder_commit, | |
857 | }; | |
858 | ||
7d57382e EA |
859 | static const struct drm_encoder_helper_funcs intel_hdmi_helper_funcs = { |
860 | .dpms = intel_hdmi_dpms, | |
861 | .mode_fixup = intel_hdmi_mode_fixup, | |
862 | .prepare = intel_encoder_prepare, | |
863 | .mode_set = intel_hdmi_mode_set, | |
864 | .commit = intel_encoder_commit, | |
865 | }; | |
866 | ||
867 | static const struct drm_connector_funcs intel_hdmi_connector_funcs = { | |
c9fb15f6 | 868 | .dpms = drm_helper_connector_dpms, |
7d57382e EA |
869 | .detect = intel_hdmi_detect, |
870 | .fill_modes = drm_helper_probe_single_connector_modes, | |
55b7d6e8 | 871 | .set_property = intel_hdmi_set_property, |
7d57382e EA |
872 | .destroy = intel_hdmi_destroy, |
873 | }; | |
874 | ||
875 | static const struct drm_connector_helper_funcs intel_hdmi_connector_helper_funcs = { | |
876 | .get_modes = intel_hdmi_get_modes, | |
877 | .mode_valid = intel_hdmi_mode_valid, | |
df0e9248 | 878 | .best_encoder = intel_best_encoder, |
7d57382e EA |
879 | }; |
880 | ||
7d57382e | 881 | static const struct drm_encoder_funcs intel_hdmi_enc_funcs = { |
ea5b213a | 882 | .destroy = intel_encoder_destroy, |
7d57382e EA |
883 | }; |
884 | ||
55b7d6e8 CW |
885 | static void |
886 | intel_hdmi_add_properties(struct intel_hdmi *intel_hdmi, struct drm_connector *connector) | |
887 | { | |
3f43c48d | 888 | intel_attach_force_audio_property(connector); |
e953fd7b | 889 | intel_attach_broadcast_rgb_property(connector); |
55b7d6e8 CW |
890 | } |
891 | ||
7d57382e EA |
892 | void intel_hdmi_init(struct drm_device *dev, int sdvox_reg) |
893 | { | |
894 | struct drm_i915_private *dev_priv = dev->dev_private; | |
895 | struct drm_connector *connector; | |
21d40d37 | 896 | struct intel_encoder *intel_encoder; |
674e2d08 | 897 | struct intel_connector *intel_connector; |
ea5b213a | 898 | struct intel_hdmi *intel_hdmi; |
7d57382e | 899 | |
ea5b213a CW |
900 | intel_hdmi = kzalloc(sizeof(struct intel_hdmi), GFP_KERNEL); |
901 | if (!intel_hdmi) | |
7d57382e | 902 | return; |
674e2d08 ZW |
903 | |
904 | intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL); | |
905 | if (!intel_connector) { | |
ea5b213a | 906 | kfree(intel_hdmi); |
674e2d08 ZW |
907 | return; |
908 | } | |
909 | ||
ea5b213a | 910 | intel_encoder = &intel_hdmi->base; |
373a3cf7 CW |
911 | drm_encoder_init(dev, &intel_encoder->base, &intel_hdmi_enc_funcs, |
912 | DRM_MODE_ENCODER_TMDS); | |
913 | ||
674e2d08 | 914 | connector = &intel_connector->base; |
7d57382e | 915 | drm_connector_init(dev, connector, &intel_hdmi_connector_funcs, |
8d91104a | 916 | DRM_MODE_CONNECTOR_HDMIA); |
7d57382e EA |
917 | drm_connector_helper_add(connector, &intel_hdmi_connector_helper_funcs); |
918 | ||
21d40d37 | 919 | intel_encoder->type = INTEL_OUTPUT_HDMI; |
7d57382e | 920 | |
eb1f8e4f | 921 | connector->polled = DRM_CONNECTOR_POLL_HPD; |
c3febcc4 | 922 | connector->interlace_allowed = 1; |
7d57382e | 923 | connector->doublescan_allowed = 0; |
27f8227b | 924 | intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2); |
7d57382e | 925 | |
66a9278e DV |
926 | intel_encoder->cloneable = false; |
927 | ||
7d57382e | 928 | /* Set up the DDC bus. */ |
f8aed700 | 929 | if (sdvox_reg == SDVOB) { |
f899fc64 | 930 | intel_hdmi->ddc_bus = GMBUS_PORT_DPB; |
b01f2c3a | 931 | dev_priv->hotplug_supported_mask |= HDMIB_HOTPLUG_INT_STATUS; |
f8aed700 | 932 | } else if (sdvox_reg == SDVOC) { |
f899fc64 | 933 | intel_hdmi->ddc_bus = GMBUS_PORT_DPC; |
b01f2c3a | 934 | dev_priv->hotplug_supported_mask |= HDMIC_HOTPLUG_INT_STATUS; |
f8aed700 | 935 | } else if (sdvox_reg == HDMIB) { |
f899fc64 | 936 | intel_hdmi->ddc_bus = GMBUS_PORT_DPB; |
b01f2c3a | 937 | dev_priv->hotplug_supported_mask |= HDMIB_HOTPLUG_INT_STATUS; |
f8aed700 | 938 | } else if (sdvox_reg == HDMIC) { |
f899fc64 | 939 | intel_hdmi->ddc_bus = GMBUS_PORT_DPC; |
b01f2c3a | 940 | dev_priv->hotplug_supported_mask |= HDMIC_HOTPLUG_INT_STATUS; |
f8aed700 | 941 | } else if (sdvox_reg == HDMID) { |
f899fc64 | 942 | intel_hdmi->ddc_bus = GMBUS_PORT_DPD; |
b01f2c3a | 943 | dev_priv->hotplug_supported_mask |= HDMID_HOTPLUG_INT_STATUS; |
7ceae0a5 ED |
944 | } else if (sdvox_reg == DDI_BUF_CTL(PORT_B)) { |
945 | DRM_DEBUG_DRIVER("LPT: detected output on DDI B\n"); | |
7ceae0a5 ED |
946 | intel_hdmi->ddc_bus = GMBUS_PORT_DPB; |
947 | intel_hdmi->ddi_port = PORT_B; | |
948 | dev_priv->hotplug_supported_mask |= HDMIB_HOTPLUG_INT_STATUS; | |
949 | } else if (sdvox_reg == DDI_BUF_CTL(PORT_C)) { | |
950 | DRM_DEBUG_DRIVER("LPT: detected output on DDI C\n"); | |
7ceae0a5 ED |
951 | intel_hdmi->ddc_bus = GMBUS_PORT_DPC; |
952 | intel_hdmi->ddi_port = PORT_C; | |
953 | dev_priv->hotplug_supported_mask |= HDMIC_HOTPLUG_INT_STATUS; | |
954 | } else if (sdvox_reg == DDI_BUF_CTL(PORT_D)) { | |
955 | DRM_DEBUG_DRIVER("LPT: detected output on DDI D\n"); | |
7ceae0a5 ED |
956 | intel_hdmi->ddc_bus = GMBUS_PORT_DPD; |
957 | intel_hdmi->ddi_port = PORT_D; | |
958 | dev_priv->hotplug_supported_mask |= HDMID_HOTPLUG_INT_STATUS; | |
6e4c1677 ED |
959 | } else { |
960 | /* If we got an unknown sdvox_reg, things are pretty much broken | |
961 | * in a way that we should let the kernel know about it */ | |
962 | BUG(); | |
f8aed700 | 963 | } |
7d57382e | 964 | |
ea5b213a | 965 | intel_hdmi->sdvox_reg = sdvox_reg; |
7d57382e | 966 | |
64a8fc01 | 967 | if (!HAS_PCH_SPLIT(dev)) { |
a3da1df7 | 968 | intel_hdmi->write_infoframe = g4x_write_infoframe; |
687f4d06 | 969 | intel_hdmi->set_infoframes = g4x_set_infoframes; |
90b107c8 SK |
970 | } else if (IS_VALLEYVIEW(dev)) { |
971 | intel_hdmi->write_infoframe = vlv_write_infoframe; | |
687f4d06 | 972 | intel_hdmi->set_infoframes = vlv_set_infoframes; |
8c5f5f7c | 973 | } else if (IS_HASWELL(dev)) { |
8c5f5f7c | 974 | intel_hdmi->write_infoframe = hsw_write_infoframe; |
687f4d06 | 975 | intel_hdmi->set_infoframes = hsw_set_infoframes; |
fdf1250a PZ |
976 | } else if (HAS_PCH_IBX(dev)) { |
977 | intel_hdmi->write_infoframe = ibx_write_infoframe; | |
687f4d06 | 978 | intel_hdmi->set_infoframes = ibx_set_infoframes; |
fdf1250a PZ |
979 | } else { |
980 | intel_hdmi->write_infoframe = cpt_write_infoframe; | |
687f4d06 | 981 | intel_hdmi->set_infoframes = cpt_set_infoframes; |
64a8fc01 | 982 | } |
45187ace | 983 | |
72662e10 ED |
984 | if (IS_HASWELL(dev)) |
985 | drm_encoder_helper_add(&intel_encoder->base, &intel_hdmi_helper_funcs_hsw); | |
986 | else | |
987 | drm_encoder_helper_add(&intel_encoder->base, &intel_hdmi_helper_funcs); | |
7d57382e | 988 | |
55b7d6e8 CW |
989 | intel_hdmi_add_properties(intel_hdmi, connector); |
990 | ||
df0e9248 | 991 | intel_connector_attach_encoder(intel_connector, intel_encoder); |
7d57382e EA |
992 | drm_sysfs_connector_add(connector); |
993 | ||
994 | /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written | |
995 | * 0xd. Failure to do so will result in spurious interrupts being | |
996 | * generated on the port when a cable is not attached. | |
997 | */ | |
998 | if (IS_G4X(dev) && !IS_GM45(dev)) { | |
999 | u32 temp = I915_READ(PEG_BAND_GAP_DATA); | |
1000 | I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd); | |
1001 | } | |
7d57382e | 1002 | } |