]>
Commit | Line | Data |
---|---|---|
7d57382e EA |
1 | /* |
2 | * Copyright 2006 Dave Airlie <airlied@linux.ie> | |
3 | * Copyright © 2006-2009 Intel Corporation | |
4 | * | |
5 | * Permission is hereby granted, free of charge, to any person obtaining a | |
6 | * copy of this software and associated documentation files (the "Software"), | |
7 | * to deal in the Software without restriction, including without limitation | |
8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
9 | * and/or sell copies of the Software, and to permit persons to whom the | |
10 | * Software is furnished to do so, subject to the following conditions: | |
11 | * | |
12 | * The above copyright notice and this permission notice (including the next | |
13 | * paragraph) shall be included in all copies or substantial portions of the | |
14 | * Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
21 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
22 | * DEALINGS IN THE SOFTWARE. | |
23 | * | |
24 | * Authors: | |
25 | * Eric Anholt <eric@anholt.net> | |
26 | * Jesse Barnes <jesse.barnes@intel.com> | |
27 | */ | |
28 | ||
29 | #include <linux/i2c.h> | |
5a0e3ad6 | 30 | #include <linux/slab.h> |
7d57382e | 31 | #include <linux/delay.h> |
178f736a | 32 | #include <linux/hdmi.h> |
760285e7 DH |
33 | #include <drm/drmP.h> |
34 | #include <drm/drm_crtc.h> | |
35 | #include <drm/drm_edid.h> | |
7d57382e | 36 | #include "intel_drv.h" |
760285e7 | 37 | #include <drm/i915_drm.h> |
7d57382e EA |
38 | #include "i915_drv.h" |
39 | ||
30add22d PZ |
40 | static struct drm_device *intel_hdmi_to_dev(struct intel_hdmi *intel_hdmi) |
41 | { | |
da63a9f2 | 42 | return hdmi_to_dig_port(intel_hdmi)->base.base.dev; |
30add22d PZ |
43 | } |
44 | ||
afba0188 DV |
45 | static void |
46 | assert_hdmi_port_disabled(struct intel_hdmi *intel_hdmi) | |
47 | { | |
30add22d | 48 | struct drm_device *dev = intel_hdmi_to_dev(intel_hdmi); |
afba0188 DV |
49 | struct drm_i915_private *dev_priv = dev->dev_private; |
50 | uint32_t enabled_bits; | |
51 | ||
affa9354 | 52 | enabled_bits = HAS_DDI(dev) ? DDI_BUF_CTL_ENABLE : SDVO_ENABLE; |
afba0188 | 53 | |
b242b7f7 | 54 | WARN(I915_READ(intel_hdmi->hdmi_reg) & enabled_bits, |
afba0188 DV |
55 | "HDMI port enabled, expecting disabled\n"); |
56 | } | |
57 | ||
f5bbfca3 | 58 | struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder) |
ea5b213a | 59 | { |
da63a9f2 PZ |
60 | struct intel_digital_port *intel_dig_port = |
61 | container_of(encoder, struct intel_digital_port, base.base); | |
62 | return &intel_dig_port->hdmi; | |
ea5b213a CW |
63 | } |
64 | ||
df0e9248 CW |
65 | static struct intel_hdmi *intel_attached_hdmi(struct drm_connector *connector) |
66 | { | |
da63a9f2 | 67 | return enc_to_intel_hdmi(&intel_attached_encoder(connector)->base); |
df0e9248 CW |
68 | } |
69 | ||
178f736a | 70 | static u32 g4x_infoframe_index(enum hdmi_infoframe_type type) |
3c17fe4b | 71 | { |
178f736a DL |
72 | switch (type) { |
73 | case HDMI_INFOFRAME_TYPE_AVI: | |
ed517fbb | 74 | return VIDEO_DIP_SELECT_AVI; |
178f736a | 75 | case HDMI_INFOFRAME_TYPE_SPD: |
ed517fbb | 76 | return VIDEO_DIP_SELECT_SPD; |
c8bb75af LD |
77 | case HDMI_INFOFRAME_TYPE_VENDOR: |
78 | return VIDEO_DIP_SELECT_VENDOR; | |
45187ace | 79 | default: |
178f736a | 80 | DRM_DEBUG_DRIVER("unknown info frame type %d\n", type); |
ed517fbb | 81 | return 0; |
45187ace | 82 | } |
45187ace JB |
83 | } |
84 | ||
178f736a | 85 | static u32 g4x_infoframe_enable(enum hdmi_infoframe_type type) |
45187ace | 86 | { |
178f736a DL |
87 | switch (type) { |
88 | case HDMI_INFOFRAME_TYPE_AVI: | |
ed517fbb | 89 | return VIDEO_DIP_ENABLE_AVI; |
178f736a | 90 | case HDMI_INFOFRAME_TYPE_SPD: |
ed517fbb | 91 | return VIDEO_DIP_ENABLE_SPD; |
c8bb75af LD |
92 | case HDMI_INFOFRAME_TYPE_VENDOR: |
93 | return VIDEO_DIP_ENABLE_VENDOR; | |
fa193ff7 | 94 | default: |
178f736a | 95 | DRM_DEBUG_DRIVER("unknown info frame type %d\n", type); |
ed517fbb | 96 | return 0; |
fa193ff7 | 97 | } |
fa193ff7 PZ |
98 | } |
99 | ||
178f736a | 100 | static u32 hsw_infoframe_enable(enum hdmi_infoframe_type type) |
2da8af54 | 101 | { |
178f736a DL |
102 | switch (type) { |
103 | case HDMI_INFOFRAME_TYPE_AVI: | |
2da8af54 | 104 | return VIDEO_DIP_ENABLE_AVI_HSW; |
178f736a | 105 | case HDMI_INFOFRAME_TYPE_SPD: |
2da8af54 | 106 | return VIDEO_DIP_ENABLE_SPD_HSW; |
c8bb75af LD |
107 | case HDMI_INFOFRAME_TYPE_VENDOR: |
108 | return VIDEO_DIP_ENABLE_VS_HSW; | |
2da8af54 | 109 | default: |
178f736a | 110 | DRM_DEBUG_DRIVER("unknown info frame type %d\n", type); |
2da8af54 PZ |
111 | return 0; |
112 | } | |
113 | } | |
114 | ||
178f736a | 115 | static u32 hsw_infoframe_data_reg(enum hdmi_infoframe_type type, |
a57c774a AK |
116 | enum transcoder cpu_transcoder, |
117 | struct drm_i915_private *dev_priv) | |
2da8af54 | 118 | { |
178f736a DL |
119 | switch (type) { |
120 | case HDMI_INFOFRAME_TYPE_AVI: | |
7d9bcebe | 121 | return HSW_TVIDEO_DIP_AVI_DATA(cpu_transcoder); |
178f736a | 122 | case HDMI_INFOFRAME_TYPE_SPD: |
7d9bcebe | 123 | return HSW_TVIDEO_DIP_SPD_DATA(cpu_transcoder); |
c8bb75af LD |
124 | case HDMI_INFOFRAME_TYPE_VENDOR: |
125 | return HSW_TVIDEO_DIP_VS_DATA(cpu_transcoder); | |
2da8af54 | 126 | default: |
178f736a | 127 | DRM_DEBUG_DRIVER("unknown info frame type %d\n", type); |
2da8af54 PZ |
128 | return 0; |
129 | } | |
130 | } | |
131 | ||
a3da1df7 | 132 | static void g4x_write_infoframe(struct drm_encoder *encoder, |
178f736a | 133 | enum hdmi_infoframe_type type, |
fff63867 | 134 | const void *frame, ssize_t len) |
45187ace | 135 | { |
fff63867 | 136 | const uint32_t *data = frame; |
3c17fe4b DH |
137 | struct drm_device *dev = encoder->dev; |
138 | struct drm_i915_private *dev_priv = dev->dev_private; | |
22509ec8 | 139 | u32 val = I915_READ(VIDEO_DIP_CTL); |
178f736a | 140 | int i; |
3c17fe4b | 141 | |
822974ae PZ |
142 | WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n"); |
143 | ||
1d4f85ac | 144 | val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ |
178f736a | 145 | val |= g4x_infoframe_index(type); |
22509ec8 | 146 | |
178f736a | 147 | val &= ~g4x_infoframe_enable(type); |
45187ace | 148 | |
22509ec8 | 149 | I915_WRITE(VIDEO_DIP_CTL, val); |
3c17fe4b | 150 | |
9d9740f0 | 151 | mmiowb(); |
45187ace | 152 | for (i = 0; i < len; i += 4) { |
3c17fe4b DH |
153 | I915_WRITE(VIDEO_DIP_DATA, *data); |
154 | data++; | |
155 | } | |
adf00b26 PZ |
156 | /* Write every possible data byte to force correct ECC calculation. */ |
157 | for (; i < VIDEO_DIP_DATA_SIZE; i += 4) | |
158 | I915_WRITE(VIDEO_DIP_DATA, 0); | |
9d9740f0 | 159 | mmiowb(); |
3c17fe4b | 160 | |
178f736a | 161 | val |= g4x_infoframe_enable(type); |
60c5ea2d | 162 | val &= ~VIDEO_DIP_FREQ_MASK; |
4b24c933 | 163 | val |= VIDEO_DIP_FREQ_VSYNC; |
45187ace | 164 | |
22509ec8 | 165 | I915_WRITE(VIDEO_DIP_CTL, val); |
9d9740f0 | 166 | POSTING_READ(VIDEO_DIP_CTL); |
3c17fe4b DH |
167 | } |
168 | ||
e43823ec JB |
169 | static bool g4x_infoframe_enabled(struct drm_encoder *encoder) |
170 | { | |
171 | struct drm_device *dev = encoder->dev; | |
172 | struct drm_i915_private *dev_priv = dev->dev_private; | |
89a35ecd | 173 | struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); |
e43823ec JB |
174 | u32 val = I915_READ(VIDEO_DIP_CTL); |
175 | ||
89a35ecd JB |
176 | if (VIDEO_DIP_PORT(intel_dig_port->port) == (val & VIDEO_DIP_PORT_MASK)) |
177 | return val & VIDEO_DIP_ENABLE; | |
178 | ||
179 | return false; | |
e43823ec JB |
180 | } |
181 | ||
fdf1250a | 182 | static void ibx_write_infoframe(struct drm_encoder *encoder, |
178f736a | 183 | enum hdmi_infoframe_type type, |
fff63867 | 184 | const void *frame, ssize_t len) |
fdf1250a | 185 | { |
fff63867 | 186 | const uint32_t *data = frame; |
fdf1250a PZ |
187 | struct drm_device *dev = encoder->dev; |
188 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ed517fbb | 189 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); |
178f736a | 190 | int i, reg = TVIDEO_DIP_CTL(intel_crtc->pipe); |
fdf1250a PZ |
191 | u32 val = I915_READ(reg); |
192 | ||
822974ae PZ |
193 | WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n"); |
194 | ||
fdf1250a | 195 | val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ |
178f736a | 196 | val |= g4x_infoframe_index(type); |
fdf1250a | 197 | |
178f736a | 198 | val &= ~g4x_infoframe_enable(type); |
fdf1250a PZ |
199 | |
200 | I915_WRITE(reg, val); | |
201 | ||
9d9740f0 | 202 | mmiowb(); |
fdf1250a PZ |
203 | for (i = 0; i < len; i += 4) { |
204 | I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data); | |
205 | data++; | |
206 | } | |
adf00b26 PZ |
207 | /* Write every possible data byte to force correct ECC calculation. */ |
208 | for (; i < VIDEO_DIP_DATA_SIZE; i += 4) | |
209 | I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0); | |
9d9740f0 | 210 | mmiowb(); |
fdf1250a | 211 | |
178f736a | 212 | val |= g4x_infoframe_enable(type); |
fdf1250a | 213 | val &= ~VIDEO_DIP_FREQ_MASK; |
4b24c933 | 214 | val |= VIDEO_DIP_FREQ_VSYNC; |
fdf1250a PZ |
215 | |
216 | I915_WRITE(reg, val); | |
9d9740f0 | 217 | POSTING_READ(reg); |
fdf1250a PZ |
218 | } |
219 | ||
e43823ec JB |
220 | static bool ibx_infoframe_enabled(struct drm_encoder *encoder) |
221 | { | |
222 | struct drm_device *dev = encoder->dev; | |
223 | struct drm_i915_private *dev_priv = dev->dev_private; | |
224 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); | |
225 | int reg = TVIDEO_DIP_CTL(intel_crtc->pipe); | |
226 | u32 val = I915_READ(reg); | |
227 | ||
228 | return val & VIDEO_DIP_ENABLE; | |
229 | } | |
230 | ||
fdf1250a | 231 | static void cpt_write_infoframe(struct drm_encoder *encoder, |
178f736a | 232 | enum hdmi_infoframe_type type, |
fff63867 | 233 | const void *frame, ssize_t len) |
b055c8f3 | 234 | { |
fff63867 | 235 | const uint32_t *data = frame; |
b055c8f3 JB |
236 | struct drm_device *dev = encoder->dev; |
237 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ed517fbb | 238 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); |
178f736a | 239 | int i, reg = TVIDEO_DIP_CTL(intel_crtc->pipe); |
22509ec8 | 240 | u32 val = I915_READ(reg); |
b055c8f3 | 241 | |
822974ae PZ |
242 | WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n"); |
243 | ||
64a8fc01 | 244 | val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ |
178f736a | 245 | val |= g4x_infoframe_index(type); |
45187ace | 246 | |
ecb97851 PZ |
247 | /* The DIP control register spec says that we need to update the AVI |
248 | * infoframe without clearing its enable bit */ | |
178f736a DL |
249 | if (type != HDMI_INFOFRAME_TYPE_AVI) |
250 | val &= ~g4x_infoframe_enable(type); | |
ecb97851 | 251 | |
22509ec8 | 252 | I915_WRITE(reg, val); |
45187ace | 253 | |
9d9740f0 | 254 | mmiowb(); |
45187ace | 255 | for (i = 0; i < len; i += 4) { |
b055c8f3 JB |
256 | I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data); |
257 | data++; | |
258 | } | |
adf00b26 PZ |
259 | /* Write every possible data byte to force correct ECC calculation. */ |
260 | for (; i < VIDEO_DIP_DATA_SIZE; i += 4) | |
261 | I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0); | |
9d9740f0 | 262 | mmiowb(); |
b055c8f3 | 263 | |
178f736a | 264 | val |= g4x_infoframe_enable(type); |
60c5ea2d | 265 | val &= ~VIDEO_DIP_FREQ_MASK; |
4b24c933 | 266 | val |= VIDEO_DIP_FREQ_VSYNC; |
45187ace | 267 | |
22509ec8 | 268 | I915_WRITE(reg, val); |
9d9740f0 | 269 | POSTING_READ(reg); |
45187ace | 270 | } |
90b107c8 | 271 | |
e43823ec JB |
272 | static bool cpt_infoframe_enabled(struct drm_encoder *encoder) |
273 | { | |
274 | struct drm_device *dev = encoder->dev; | |
275 | struct drm_i915_private *dev_priv = dev->dev_private; | |
276 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); | |
277 | int reg = TVIDEO_DIP_CTL(intel_crtc->pipe); | |
278 | u32 val = I915_READ(reg); | |
279 | ||
280 | return val & VIDEO_DIP_ENABLE; | |
281 | } | |
282 | ||
90b107c8 | 283 | static void vlv_write_infoframe(struct drm_encoder *encoder, |
178f736a | 284 | enum hdmi_infoframe_type type, |
fff63867 | 285 | const void *frame, ssize_t len) |
90b107c8 | 286 | { |
fff63867 | 287 | const uint32_t *data = frame; |
90b107c8 SK |
288 | struct drm_device *dev = encoder->dev; |
289 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ed517fbb | 290 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); |
178f736a | 291 | int i, reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe); |
22509ec8 | 292 | u32 val = I915_READ(reg); |
90b107c8 | 293 | |
822974ae PZ |
294 | WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n"); |
295 | ||
90b107c8 | 296 | val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ |
178f736a | 297 | val |= g4x_infoframe_index(type); |
22509ec8 | 298 | |
178f736a | 299 | val &= ~g4x_infoframe_enable(type); |
90b107c8 | 300 | |
22509ec8 | 301 | I915_WRITE(reg, val); |
90b107c8 | 302 | |
9d9740f0 | 303 | mmiowb(); |
90b107c8 SK |
304 | for (i = 0; i < len; i += 4) { |
305 | I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), *data); | |
306 | data++; | |
307 | } | |
adf00b26 PZ |
308 | /* Write every possible data byte to force correct ECC calculation. */ |
309 | for (; i < VIDEO_DIP_DATA_SIZE; i += 4) | |
310 | I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), 0); | |
9d9740f0 | 311 | mmiowb(); |
90b107c8 | 312 | |
178f736a | 313 | val |= g4x_infoframe_enable(type); |
60c5ea2d | 314 | val &= ~VIDEO_DIP_FREQ_MASK; |
4b24c933 | 315 | val |= VIDEO_DIP_FREQ_VSYNC; |
90b107c8 | 316 | |
22509ec8 | 317 | I915_WRITE(reg, val); |
9d9740f0 | 318 | POSTING_READ(reg); |
90b107c8 SK |
319 | } |
320 | ||
e43823ec JB |
321 | static bool vlv_infoframe_enabled(struct drm_encoder *encoder) |
322 | { | |
323 | struct drm_device *dev = encoder->dev; | |
324 | struct drm_i915_private *dev_priv = dev->dev_private; | |
325 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); | |
326 | int reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe); | |
327 | u32 val = I915_READ(reg); | |
328 | ||
329 | return val & VIDEO_DIP_ENABLE; | |
330 | } | |
331 | ||
8c5f5f7c | 332 | static void hsw_write_infoframe(struct drm_encoder *encoder, |
178f736a | 333 | enum hdmi_infoframe_type type, |
fff63867 | 334 | const void *frame, ssize_t len) |
8c5f5f7c | 335 | { |
fff63867 | 336 | const uint32_t *data = frame; |
2da8af54 PZ |
337 | struct drm_device *dev = encoder->dev; |
338 | struct drm_i915_private *dev_priv = dev->dev_private; | |
339 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); | |
6e3c9717 | 340 | u32 ctl_reg = HSW_TVIDEO_DIP_CTL(intel_crtc->config->cpu_transcoder); |
178f736a DL |
341 | u32 data_reg; |
342 | int i; | |
2da8af54 | 343 | u32 val = I915_READ(ctl_reg); |
8c5f5f7c | 344 | |
178f736a | 345 | data_reg = hsw_infoframe_data_reg(type, |
6e3c9717 | 346 | intel_crtc->config->cpu_transcoder, |
a57c774a | 347 | dev_priv); |
2da8af54 PZ |
348 | if (data_reg == 0) |
349 | return; | |
350 | ||
178f736a | 351 | val &= ~hsw_infoframe_enable(type); |
2da8af54 PZ |
352 | I915_WRITE(ctl_reg, val); |
353 | ||
9d9740f0 | 354 | mmiowb(); |
2da8af54 PZ |
355 | for (i = 0; i < len; i += 4) { |
356 | I915_WRITE(data_reg + i, *data); | |
357 | data++; | |
358 | } | |
adf00b26 PZ |
359 | /* Write every possible data byte to force correct ECC calculation. */ |
360 | for (; i < VIDEO_DIP_DATA_SIZE; i += 4) | |
361 | I915_WRITE(data_reg + i, 0); | |
9d9740f0 | 362 | mmiowb(); |
8c5f5f7c | 363 | |
178f736a | 364 | val |= hsw_infoframe_enable(type); |
2da8af54 | 365 | I915_WRITE(ctl_reg, val); |
9d9740f0 | 366 | POSTING_READ(ctl_reg); |
8c5f5f7c ED |
367 | } |
368 | ||
e43823ec JB |
369 | static bool hsw_infoframe_enabled(struct drm_encoder *encoder) |
370 | { | |
371 | struct drm_device *dev = encoder->dev; | |
372 | struct drm_i915_private *dev_priv = dev->dev_private; | |
373 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); | |
6e3c9717 | 374 | u32 ctl_reg = HSW_TVIDEO_DIP_CTL(intel_crtc->config->cpu_transcoder); |
e43823ec JB |
375 | u32 val = I915_READ(ctl_reg); |
376 | ||
377 | return val & (VIDEO_DIP_ENABLE_AVI_HSW | VIDEO_DIP_ENABLE_SPD_HSW | | |
378 | VIDEO_DIP_ENABLE_VS_HSW); | |
379 | } | |
380 | ||
5adaea79 DL |
381 | /* |
382 | * The data we write to the DIP data buffer registers is 1 byte bigger than the | |
383 | * HDMI infoframe size because of an ECC/reserved byte at position 3 (starting | |
384 | * at 0). It's also a byte used by DisplayPort so the same DIP registers can be | |
385 | * used for both technologies. | |
386 | * | |
387 | * DW0: Reserved/ECC/DP | HB2 | HB1 | HB0 | |
388 | * DW1: DB3 | DB2 | DB1 | DB0 | |
389 | * DW2: DB7 | DB6 | DB5 | DB4 | |
390 | * DW3: ... | |
391 | * | |
392 | * (HB is Header Byte, DB is Data Byte) | |
393 | * | |
394 | * The hdmi pack() functions don't know about that hardware specific hole so we | |
395 | * trick them by giving an offset into the buffer and moving back the header | |
396 | * bytes by one. | |
397 | */ | |
9198ee5b DL |
398 | static void intel_write_infoframe(struct drm_encoder *encoder, |
399 | union hdmi_infoframe *frame) | |
45187ace JB |
400 | { |
401 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); | |
5adaea79 DL |
402 | uint8_t buffer[VIDEO_DIP_DATA_SIZE]; |
403 | ssize_t len; | |
45187ace | 404 | |
5adaea79 DL |
405 | /* see comment above for the reason for this offset */ |
406 | len = hdmi_infoframe_pack(frame, buffer + 1, sizeof(buffer) - 1); | |
407 | if (len < 0) | |
408 | return; | |
409 | ||
410 | /* Insert the 'hole' (see big comment above) at position 3 */ | |
411 | buffer[0] = buffer[1]; | |
412 | buffer[1] = buffer[2]; | |
413 | buffer[2] = buffer[3]; | |
414 | buffer[3] = 0; | |
415 | len++; | |
45187ace | 416 | |
5adaea79 | 417 | intel_hdmi->write_infoframe(encoder, frame->any.type, buffer, len); |
45187ace JB |
418 | } |
419 | ||
687f4d06 | 420 | static void intel_hdmi_set_avi_infoframe(struct drm_encoder *encoder, |
c846b619 | 421 | struct drm_display_mode *adjusted_mode) |
45187ace | 422 | { |
abedc077 | 423 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); |
50f3b016 | 424 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); |
5adaea79 DL |
425 | union hdmi_infoframe frame; |
426 | int ret; | |
45187ace | 427 | |
94a11ddc VK |
428 | /* Set user selected PAR to incoming mode's member */ |
429 | adjusted_mode->picture_aspect_ratio = intel_hdmi->aspect_ratio; | |
430 | ||
5adaea79 DL |
431 | ret = drm_hdmi_avi_infoframe_from_display_mode(&frame.avi, |
432 | adjusted_mode); | |
433 | if (ret < 0) { | |
434 | DRM_ERROR("couldn't fill AVI infoframe\n"); | |
435 | return; | |
436 | } | |
c846b619 | 437 | |
abedc077 | 438 | if (intel_hdmi->rgb_quant_range_selectable) { |
6e3c9717 | 439 | if (intel_crtc->config->limited_color_range) |
5adaea79 DL |
440 | frame.avi.quantization_range = |
441 | HDMI_QUANTIZATION_RANGE_LIMITED; | |
abedc077 | 442 | else |
5adaea79 DL |
443 | frame.avi.quantization_range = |
444 | HDMI_QUANTIZATION_RANGE_FULL; | |
abedc077 VS |
445 | } |
446 | ||
9198ee5b | 447 | intel_write_infoframe(encoder, &frame); |
b055c8f3 JB |
448 | } |
449 | ||
687f4d06 | 450 | static void intel_hdmi_set_spd_infoframe(struct drm_encoder *encoder) |
c0864cb3 | 451 | { |
5adaea79 DL |
452 | union hdmi_infoframe frame; |
453 | int ret; | |
454 | ||
455 | ret = hdmi_spd_infoframe_init(&frame.spd, "Intel", "Integrated gfx"); | |
456 | if (ret < 0) { | |
457 | DRM_ERROR("couldn't fill SPD infoframe\n"); | |
458 | return; | |
459 | } | |
c0864cb3 | 460 | |
5adaea79 | 461 | frame.spd.sdi = HDMI_SPD_SDI_PC; |
c0864cb3 | 462 | |
9198ee5b | 463 | intel_write_infoframe(encoder, &frame); |
c0864cb3 JB |
464 | } |
465 | ||
c8bb75af LD |
466 | static void |
467 | intel_hdmi_set_hdmi_infoframe(struct drm_encoder *encoder, | |
468 | struct drm_display_mode *adjusted_mode) | |
469 | { | |
470 | union hdmi_infoframe frame; | |
471 | int ret; | |
472 | ||
473 | ret = drm_hdmi_vendor_infoframe_from_display_mode(&frame.vendor.hdmi, | |
474 | adjusted_mode); | |
475 | if (ret < 0) | |
476 | return; | |
477 | ||
478 | intel_write_infoframe(encoder, &frame); | |
479 | } | |
480 | ||
687f4d06 | 481 | static void g4x_set_infoframes(struct drm_encoder *encoder, |
6897b4b5 | 482 | bool enable, |
687f4d06 PZ |
483 | struct drm_display_mode *adjusted_mode) |
484 | { | |
0c14c7f9 | 485 | struct drm_i915_private *dev_priv = encoder->dev->dev_private; |
69fde0a6 VS |
486 | struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); |
487 | struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi; | |
0c14c7f9 PZ |
488 | u32 reg = VIDEO_DIP_CTL; |
489 | u32 val = I915_READ(reg); | |
822cdc52 | 490 | u32 port = VIDEO_DIP_PORT(intel_dig_port->port); |
0c14c7f9 | 491 | |
afba0188 DV |
492 | assert_hdmi_port_disabled(intel_hdmi); |
493 | ||
0c14c7f9 PZ |
494 | /* If the registers were not initialized yet, they might be zeroes, |
495 | * which means we're selecting the AVI DIP and we're setting its | |
496 | * frequency to once. This seems to really confuse the HW and make | |
497 | * things stop working (the register spec says the AVI always needs to | |
498 | * be sent every VSync). So here we avoid writing to the register more | |
499 | * than we need and also explicitly select the AVI DIP and explicitly | |
500 | * set its frequency to every VSync. Avoiding to write it twice seems to | |
501 | * be enough to solve the problem, but being defensive shouldn't hurt us | |
502 | * either. */ | |
503 | val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; | |
504 | ||
6897b4b5 | 505 | if (!enable) { |
0c14c7f9 PZ |
506 | if (!(val & VIDEO_DIP_ENABLE)) |
507 | return; | |
508 | val &= ~VIDEO_DIP_ENABLE; | |
509 | I915_WRITE(reg, val); | |
9d9740f0 | 510 | POSTING_READ(reg); |
0c14c7f9 PZ |
511 | return; |
512 | } | |
513 | ||
72b78c9d PZ |
514 | if (port != (val & VIDEO_DIP_PORT_MASK)) { |
515 | if (val & VIDEO_DIP_ENABLE) { | |
516 | val &= ~VIDEO_DIP_ENABLE; | |
517 | I915_WRITE(reg, val); | |
9d9740f0 | 518 | POSTING_READ(reg); |
72b78c9d PZ |
519 | } |
520 | val &= ~VIDEO_DIP_PORT_MASK; | |
521 | val |= port; | |
522 | } | |
523 | ||
822974ae | 524 | val |= VIDEO_DIP_ENABLE; |
0dd87d20 | 525 | val &= ~VIDEO_DIP_ENABLE_VENDOR; |
822974ae | 526 | |
f278d972 | 527 | I915_WRITE(reg, val); |
9d9740f0 | 528 | POSTING_READ(reg); |
f278d972 | 529 | |
687f4d06 PZ |
530 | intel_hdmi_set_avi_infoframe(encoder, adjusted_mode); |
531 | intel_hdmi_set_spd_infoframe(encoder); | |
c8bb75af | 532 | intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode); |
687f4d06 PZ |
533 | } |
534 | ||
535 | static void ibx_set_infoframes(struct drm_encoder *encoder, | |
6897b4b5 | 536 | bool enable, |
687f4d06 PZ |
537 | struct drm_display_mode *adjusted_mode) |
538 | { | |
0c14c7f9 PZ |
539 | struct drm_i915_private *dev_priv = encoder->dev->dev_private; |
540 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); | |
69fde0a6 VS |
541 | struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); |
542 | struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi; | |
0c14c7f9 PZ |
543 | u32 reg = TVIDEO_DIP_CTL(intel_crtc->pipe); |
544 | u32 val = I915_READ(reg); | |
822cdc52 | 545 | u32 port = VIDEO_DIP_PORT(intel_dig_port->port); |
0c14c7f9 | 546 | |
afba0188 DV |
547 | assert_hdmi_port_disabled(intel_hdmi); |
548 | ||
0c14c7f9 PZ |
549 | /* See the big comment in g4x_set_infoframes() */ |
550 | val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; | |
551 | ||
6897b4b5 | 552 | if (!enable) { |
0c14c7f9 PZ |
553 | if (!(val & VIDEO_DIP_ENABLE)) |
554 | return; | |
555 | val &= ~VIDEO_DIP_ENABLE; | |
556 | I915_WRITE(reg, val); | |
9d9740f0 | 557 | POSTING_READ(reg); |
0c14c7f9 PZ |
558 | return; |
559 | } | |
560 | ||
72b78c9d PZ |
561 | if (port != (val & VIDEO_DIP_PORT_MASK)) { |
562 | if (val & VIDEO_DIP_ENABLE) { | |
563 | val &= ~VIDEO_DIP_ENABLE; | |
564 | I915_WRITE(reg, val); | |
9d9740f0 | 565 | POSTING_READ(reg); |
72b78c9d PZ |
566 | } |
567 | val &= ~VIDEO_DIP_PORT_MASK; | |
568 | val |= port; | |
569 | } | |
570 | ||
822974ae | 571 | val |= VIDEO_DIP_ENABLE; |
0dd87d20 PZ |
572 | val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | |
573 | VIDEO_DIP_ENABLE_GCP); | |
822974ae | 574 | |
f278d972 | 575 | I915_WRITE(reg, val); |
9d9740f0 | 576 | POSTING_READ(reg); |
f278d972 | 577 | |
687f4d06 PZ |
578 | intel_hdmi_set_avi_infoframe(encoder, adjusted_mode); |
579 | intel_hdmi_set_spd_infoframe(encoder); | |
c8bb75af | 580 | intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode); |
687f4d06 PZ |
581 | } |
582 | ||
583 | static void cpt_set_infoframes(struct drm_encoder *encoder, | |
6897b4b5 | 584 | bool enable, |
687f4d06 PZ |
585 | struct drm_display_mode *adjusted_mode) |
586 | { | |
0c14c7f9 PZ |
587 | struct drm_i915_private *dev_priv = encoder->dev->dev_private; |
588 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); | |
589 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); | |
590 | u32 reg = TVIDEO_DIP_CTL(intel_crtc->pipe); | |
591 | u32 val = I915_READ(reg); | |
592 | ||
afba0188 DV |
593 | assert_hdmi_port_disabled(intel_hdmi); |
594 | ||
0c14c7f9 PZ |
595 | /* See the big comment in g4x_set_infoframes() */ |
596 | val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; | |
597 | ||
6897b4b5 | 598 | if (!enable) { |
0c14c7f9 PZ |
599 | if (!(val & VIDEO_DIP_ENABLE)) |
600 | return; | |
601 | val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI); | |
602 | I915_WRITE(reg, val); | |
9d9740f0 | 603 | POSTING_READ(reg); |
0c14c7f9 PZ |
604 | return; |
605 | } | |
606 | ||
822974ae PZ |
607 | /* Set both together, unset both together: see the spec. */ |
608 | val |= VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI; | |
0dd87d20 PZ |
609 | val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | |
610 | VIDEO_DIP_ENABLE_GCP); | |
822974ae PZ |
611 | |
612 | I915_WRITE(reg, val); | |
9d9740f0 | 613 | POSTING_READ(reg); |
822974ae | 614 | |
687f4d06 PZ |
615 | intel_hdmi_set_avi_infoframe(encoder, adjusted_mode); |
616 | intel_hdmi_set_spd_infoframe(encoder); | |
c8bb75af | 617 | intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode); |
687f4d06 PZ |
618 | } |
619 | ||
620 | static void vlv_set_infoframes(struct drm_encoder *encoder, | |
6897b4b5 | 621 | bool enable, |
687f4d06 PZ |
622 | struct drm_display_mode *adjusted_mode) |
623 | { | |
0c14c7f9 | 624 | struct drm_i915_private *dev_priv = encoder->dev->dev_private; |
6a2b8021 | 625 | struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); |
0c14c7f9 PZ |
626 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); |
627 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); | |
628 | u32 reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe); | |
629 | u32 val = I915_READ(reg); | |
6a2b8021 | 630 | u32 port = VIDEO_DIP_PORT(intel_dig_port->port); |
0c14c7f9 | 631 | |
afba0188 DV |
632 | assert_hdmi_port_disabled(intel_hdmi); |
633 | ||
0c14c7f9 PZ |
634 | /* See the big comment in g4x_set_infoframes() */ |
635 | val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; | |
636 | ||
6897b4b5 | 637 | if (!enable) { |
0c14c7f9 PZ |
638 | if (!(val & VIDEO_DIP_ENABLE)) |
639 | return; | |
640 | val &= ~VIDEO_DIP_ENABLE; | |
641 | I915_WRITE(reg, val); | |
9d9740f0 | 642 | POSTING_READ(reg); |
0c14c7f9 PZ |
643 | return; |
644 | } | |
645 | ||
6a2b8021 JB |
646 | if (port != (val & VIDEO_DIP_PORT_MASK)) { |
647 | if (val & VIDEO_DIP_ENABLE) { | |
648 | val &= ~VIDEO_DIP_ENABLE; | |
649 | I915_WRITE(reg, val); | |
650 | POSTING_READ(reg); | |
651 | } | |
652 | val &= ~VIDEO_DIP_PORT_MASK; | |
653 | val |= port; | |
654 | } | |
655 | ||
822974ae | 656 | val |= VIDEO_DIP_ENABLE; |
4d47dfb8 JB |
657 | val &= ~(VIDEO_DIP_ENABLE_AVI | VIDEO_DIP_ENABLE_VENDOR | |
658 | VIDEO_DIP_ENABLE_GAMUT | VIDEO_DIP_ENABLE_GCP); | |
822974ae PZ |
659 | |
660 | I915_WRITE(reg, val); | |
9d9740f0 | 661 | POSTING_READ(reg); |
822974ae | 662 | |
687f4d06 PZ |
663 | intel_hdmi_set_avi_infoframe(encoder, adjusted_mode); |
664 | intel_hdmi_set_spd_infoframe(encoder); | |
c8bb75af | 665 | intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode); |
687f4d06 PZ |
666 | } |
667 | ||
668 | static void hsw_set_infoframes(struct drm_encoder *encoder, | |
6897b4b5 | 669 | bool enable, |
687f4d06 PZ |
670 | struct drm_display_mode *adjusted_mode) |
671 | { | |
0c14c7f9 PZ |
672 | struct drm_i915_private *dev_priv = encoder->dev->dev_private; |
673 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); | |
674 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); | |
6e3c9717 | 675 | u32 reg = HSW_TVIDEO_DIP_CTL(intel_crtc->config->cpu_transcoder); |
0dd87d20 | 676 | u32 val = I915_READ(reg); |
0c14c7f9 | 677 | |
afba0188 DV |
678 | assert_hdmi_port_disabled(intel_hdmi); |
679 | ||
6897b4b5 | 680 | if (!enable) { |
0c14c7f9 | 681 | I915_WRITE(reg, 0); |
9d9740f0 | 682 | POSTING_READ(reg); |
0c14c7f9 PZ |
683 | return; |
684 | } | |
685 | ||
0dd87d20 PZ |
686 | val &= ~(VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_GCP_HSW | |
687 | VIDEO_DIP_ENABLE_VS_HSW | VIDEO_DIP_ENABLE_GMP_HSW); | |
688 | ||
689 | I915_WRITE(reg, val); | |
9d9740f0 | 690 | POSTING_READ(reg); |
0dd87d20 | 691 | |
687f4d06 PZ |
692 | intel_hdmi_set_avi_infoframe(encoder, adjusted_mode); |
693 | intel_hdmi_set_spd_infoframe(encoder); | |
c8bb75af | 694 | intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode); |
687f4d06 PZ |
695 | } |
696 | ||
4cde8a21 | 697 | static void intel_hdmi_prepare(struct intel_encoder *encoder) |
7d57382e | 698 | { |
c59423a3 | 699 | struct drm_device *dev = encoder->base.dev; |
7d57382e | 700 | struct drm_i915_private *dev_priv = dev->dev_private; |
c59423a3 DV |
701 | struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); |
702 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); | |
6e3c9717 | 703 | struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode; |
b242b7f7 | 704 | u32 hdmi_val; |
7d57382e | 705 | |
b242b7f7 | 706 | hdmi_val = SDVO_ENCODING_HDMI; |
2af2c490 | 707 | if (!HAS_PCH_SPLIT(dev)) |
b242b7f7 | 708 | hdmi_val |= intel_hdmi->color_range; |
b599c0bc | 709 | if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) |
b242b7f7 | 710 | hdmi_val |= SDVO_VSYNC_ACTIVE_HIGH; |
b599c0bc | 711 | if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) |
b242b7f7 | 712 | hdmi_val |= SDVO_HSYNC_ACTIVE_HIGH; |
7d57382e | 713 | |
6e3c9717 | 714 | if (crtc->config->pipe_bpp > 24) |
4f3a8bc7 | 715 | hdmi_val |= HDMI_COLOR_FORMAT_12bpc; |
020f6704 | 716 | else |
4f3a8bc7 | 717 | hdmi_val |= SDVO_COLOR_FORMAT_8bpc; |
020f6704 | 718 | |
6e3c9717 | 719 | if (crtc->config->has_hdmi_sink) |
dc0fa718 | 720 | hdmi_val |= HDMI_MODE_SELECT_HDMI; |
2e3d6006 | 721 | |
75770564 | 722 | if (HAS_PCH_CPT(dev)) |
c59423a3 | 723 | hdmi_val |= SDVO_PIPE_SEL_CPT(crtc->pipe); |
44f37d1f CML |
724 | else if (IS_CHERRYVIEW(dev)) |
725 | hdmi_val |= SDVO_PIPE_SEL_CHV(crtc->pipe); | |
dc0fa718 | 726 | else |
c59423a3 | 727 | hdmi_val |= SDVO_PIPE_SEL(crtc->pipe); |
7d57382e | 728 | |
b242b7f7 PZ |
729 | I915_WRITE(intel_hdmi->hdmi_reg, hdmi_val); |
730 | POSTING_READ(intel_hdmi->hdmi_reg); | |
7d57382e EA |
731 | } |
732 | ||
85234cdc DV |
733 | static bool intel_hdmi_get_hw_state(struct intel_encoder *encoder, |
734 | enum pipe *pipe) | |
7d57382e | 735 | { |
85234cdc | 736 | struct drm_device *dev = encoder->base.dev; |
7d57382e | 737 | struct drm_i915_private *dev_priv = dev->dev_private; |
85234cdc | 738 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); |
6d129bea | 739 | enum intel_display_power_domain power_domain; |
85234cdc DV |
740 | u32 tmp; |
741 | ||
6d129bea | 742 | power_domain = intel_display_port_power_domain(encoder); |
f458ebbc | 743 | if (!intel_display_power_is_enabled(dev_priv, power_domain)) |
6d129bea ID |
744 | return false; |
745 | ||
b242b7f7 | 746 | tmp = I915_READ(intel_hdmi->hdmi_reg); |
85234cdc DV |
747 | |
748 | if (!(tmp & SDVO_ENABLE)) | |
749 | return false; | |
750 | ||
751 | if (HAS_PCH_CPT(dev)) | |
752 | *pipe = PORT_TO_PIPE_CPT(tmp); | |
71485e0a VS |
753 | else if (IS_CHERRYVIEW(dev)) |
754 | *pipe = SDVO_PORT_TO_PIPE_CHV(tmp); | |
85234cdc DV |
755 | else |
756 | *pipe = PORT_TO_PIPE(tmp); | |
757 | ||
758 | return true; | |
759 | } | |
760 | ||
045ac3b5 | 761 | static void intel_hdmi_get_config(struct intel_encoder *encoder, |
5cec258b | 762 | struct intel_crtc_state *pipe_config) |
045ac3b5 JB |
763 | { |
764 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); | |
8c875fca VS |
765 | struct drm_device *dev = encoder->base.dev; |
766 | struct drm_i915_private *dev_priv = dev->dev_private; | |
045ac3b5 | 767 | u32 tmp, flags = 0; |
18442d08 | 768 | int dotclock; |
045ac3b5 JB |
769 | |
770 | tmp = I915_READ(intel_hdmi->hdmi_reg); | |
771 | ||
772 | if (tmp & SDVO_HSYNC_ACTIVE_HIGH) | |
773 | flags |= DRM_MODE_FLAG_PHSYNC; | |
774 | else | |
775 | flags |= DRM_MODE_FLAG_NHSYNC; | |
776 | ||
777 | if (tmp & SDVO_VSYNC_ACTIVE_HIGH) | |
778 | flags |= DRM_MODE_FLAG_PVSYNC; | |
779 | else | |
780 | flags |= DRM_MODE_FLAG_NVSYNC; | |
781 | ||
6897b4b5 DV |
782 | if (tmp & HDMI_MODE_SELECT_HDMI) |
783 | pipe_config->has_hdmi_sink = true; | |
784 | ||
e43823ec JB |
785 | if (intel_hdmi->infoframe_enabled(&encoder->base)) |
786 | pipe_config->has_infoframe = true; | |
787 | ||
c84db770 | 788 | if (tmp & SDVO_AUDIO_ENABLE) |
9ed109a7 DV |
789 | pipe_config->has_audio = true; |
790 | ||
8c875fca VS |
791 | if (!HAS_PCH_SPLIT(dev) && |
792 | tmp & HDMI_COLOR_RANGE_16_235) | |
793 | pipe_config->limited_color_range = true; | |
794 | ||
2d112de7 | 795 | pipe_config->base.adjusted_mode.flags |= flags; |
18442d08 VS |
796 | |
797 | if ((tmp & SDVO_COLOR_FORMAT_MASK) == HDMI_COLOR_FORMAT_12bpc) | |
798 | dotclock = pipe_config->port_clock * 2 / 3; | |
799 | else | |
800 | dotclock = pipe_config->port_clock; | |
801 | ||
802 | if (HAS_PCH_SPLIT(dev_priv->dev)) | |
803 | ironlake_check_encoder_dotclock(pipe_config, dotclock); | |
804 | ||
2d112de7 | 805 | pipe_config->base.adjusted_mode.crtc_clock = dotclock; |
045ac3b5 JB |
806 | } |
807 | ||
5ab432ef | 808 | static void intel_enable_hdmi(struct intel_encoder *encoder) |
7d57382e | 809 | { |
5ab432ef | 810 | struct drm_device *dev = encoder->base.dev; |
7d57382e | 811 | struct drm_i915_private *dev_priv = dev->dev_private; |
dc0fa718 | 812 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); |
5ab432ef | 813 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); |
7d57382e | 814 | u32 temp; |
2deed761 WF |
815 | u32 enable_bits = SDVO_ENABLE; |
816 | ||
6e3c9717 | 817 | if (intel_crtc->config->has_audio) |
2deed761 | 818 | enable_bits |= SDVO_AUDIO_ENABLE; |
7d57382e | 819 | |
b242b7f7 | 820 | temp = I915_READ(intel_hdmi->hdmi_reg); |
d8a2d0e0 | 821 | |
7a87c289 | 822 | /* HW workaround for IBX, we need to move the port to transcoder A |
dc0fa718 PZ |
823 | * before disabling it, so restore the transcoder select bit here. */ |
824 | if (HAS_PCH_IBX(dev)) | |
825 | enable_bits |= SDVO_PIPE_SEL(intel_crtc->pipe); | |
7a87c289 | 826 | |
d8a2d0e0 ZW |
827 | /* HW workaround, need to toggle enable bit off and on for 12bpc, but |
828 | * we do this anyway which shows more stable in testing. | |
829 | */ | |
c619eed4 | 830 | if (HAS_PCH_SPLIT(dev)) { |
b242b7f7 PZ |
831 | I915_WRITE(intel_hdmi->hdmi_reg, temp & ~SDVO_ENABLE); |
832 | POSTING_READ(intel_hdmi->hdmi_reg); | |
d8a2d0e0 ZW |
833 | } |
834 | ||
5ab432ef DV |
835 | temp |= enable_bits; |
836 | ||
b242b7f7 PZ |
837 | I915_WRITE(intel_hdmi->hdmi_reg, temp); |
838 | POSTING_READ(intel_hdmi->hdmi_reg); | |
5ab432ef DV |
839 | |
840 | /* HW workaround, need to write this twice for issue that may result | |
841 | * in first write getting masked. | |
842 | */ | |
843 | if (HAS_PCH_SPLIT(dev)) { | |
b242b7f7 PZ |
844 | I915_WRITE(intel_hdmi->hdmi_reg, temp); |
845 | POSTING_READ(intel_hdmi->hdmi_reg); | |
7d57382e | 846 | } |
c1dec79a | 847 | |
6e3c9717 ACO |
848 | if (intel_crtc->config->has_audio) { |
849 | WARN_ON(!intel_crtc->config->has_hdmi_sink); | |
c1dec79a JN |
850 | DRM_DEBUG_DRIVER("Enabling HDMI audio on pipe %c\n", |
851 | pipe_name(intel_crtc->pipe)); | |
852 | intel_audio_codec_enable(encoder); | |
853 | } | |
b76cf76b | 854 | } |
89b667f8 | 855 | |
b76cf76b JN |
856 | static void vlv_enable_hdmi(struct intel_encoder *encoder) |
857 | { | |
5ab432ef DV |
858 | } |
859 | ||
860 | static void intel_disable_hdmi(struct intel_encoder *encoder) | |
861 | { | |
862 | struct drm_device *dev = encoder->base.dev; | |
863 | struct drm_i915_private *dev_priv = dev->dev_private; | |
864 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); | |
495a5bb8 | 865 | struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); |
5ab432ef | 866 | u32 temp; |
3cce574f | 867 | u32 enable_bits = SDVO_ENABLE | SDVO_AUDIO_ENABLE; |
5ab432ef | 868 | |
6e3c9717 | 869 | if (crtc->config->has_audio) |
495a5bb8 JN |
870 | intel_audio_codec_disable(encoder); |
871 | ||
b242b7f7 | 872 | temp = I915_READ(intel_hdmi->hdmi_reg); |
5ab432ef DV |
873 | |
874 | /* HW workaround for IBX, we need to move the port to transcoder A | |
875 | * before disabling it. */ | |
876 | if (HAS_PCH_IBX(dev)) { | |
877 | struct drm_crtc *crtc = encoder->base.crtc; | |
878 | int pipe = crtc ? to_intel_crtc(crtc)->pipe : -1; | |
879 | ||
880 | if (temp & SDVO_PIPE_B_SELECT) { | |
881 | temp &= ~SDVO_PIPE_B_SELECT; | |
b242b7f7 PZ |
882 | I915_WRITE(intel_hdmi->hdmi_reg, temp); |
883 | POSTING_READ(intel_hdmi->hdmi_reg); | |
5ab432ef DV |
884 | |
885 | /* Again we need to write this twice. */ | |
b242b7f7 PZ |
886 | I915_WRITE(intel_hdmi->hdmi_reg, temp); |
887 | POSTING_READ(intel_hdmi->hdmi_reg); | |
5ab432ef DV |
888 | |
889 | /* Transcoder selection bits only update | |
890 | * effectively on vblank. */ | |
891 | if (crtc) | |
892 | intel_wait_for_vblank(dev, pipe); | |
893 | else | |
894 | msleep(50); | |
895 | } | |
7d57382e | 896 | } |
d8a2d0e0 | 897 | |
5ab432ef DV |
898 | /* HW workaround, need to toggle enable bit off and on for 12bpc, but |
899 | * we do this anyway which shows more stable in testing. | |
900 | */ | |
901 | if (HAS_PCH_SPLIT(dev)) { | |
b242b7f7 PZ |
902 | I915_WRITE(intel_hdmi->hdmi_reg, temp & ~SDVO_ENABLE); |
903 | POSTING_READ(intel_hdmi->hdmi_reg); | |
5ab432ef DV |
904 | } |
905 | ||
906 | temp &= ~enable_bits; | |
d8a2d0e0 | 907 | |
b242b7f7 PZ |
908 | I915_WRITE(intel_hdmi->hdmi_reg, temp); |
909 | POSTING_READ(intel_hdmi->hdmi_reg); | |
d8a2d0e0 ZW |
910 | |
911 | /* HW workaround, need to write this twice for issue that may result | |
912 | * in first write getting masked. | |
913 | */ | |
c619eed4 | 914 | if (HAS_PCH_SPLIT(dev)) { |
b242b7f7 PZ |
915 | I915_WRITE(intel_hdmi->hdmi_reg, temp); |
916 | POSTING_READ(intel_hdmi->hdmi_reg); | |
d8a2d0e0 | 917 | } |
7d57382e EA |
918 | } |
919 | ||
40478455 | 920 | static int hdmi_portclock_limit(struct intel_hdmi *hdmi, bool respect_dvi_limit) |
7d148ef5 DV |
921 | { |
922 | struct drm_device *dev = intel_hdmi_to_dev(hdmi); | |
923 | ||
40478455 | 924 | if ((respect_dvi_limit && !hdmi->has_hdmi_sink) || IS_G4X(dev)) |
7d148ef5 | 925 | return 165000; |
e3c33578 | 926 | else if (IS_HASWELL(dev) || INTEL_INFO(dev)->gen >= 8) |
7d148ef5 DV |
927 | return 300000; |
928 | else | |
929 | return 225000; | |
930 | } | |
931 | ||
c19de8eb DL |
932 | static enum drm_mode_status |
933 | intel_hdmi_mode_valid(struct drm_connector *connector, | |
934 | struct drm_display_mode *mode) | |
7d57382e | 935 | { |
697c4078 CT |
936 | int clock = mode->clock; |
937 | ||
938 | if (mode->flags & DRM_MODE_FLAG_DBLCLK) | |
939 | clock *= 2; | |
940 | ||
941 | if (clock > hdmi_portclock_limit(intel_attached_hdmi(connector), | |
942 | true)) | |
7d57382e | 943 | return MODE_CLOCK_HIGH; |
697c4078 | 944 | if (clock < 20000) |
5cbba41d | 945 | return MODE_CLOCK_LOW; |
7d57382e EA |
946 | |
947 | if (mode->flags & DRM_MODE_FLAG_DBLSCAN) | |
948 | return MODE_NO_DBLESCAN; | |
949 | ||
950 | return MODE_OK; | |
951 | } | |
952 | ||
71800632 VS |
953 | static bool hdmi_12bpc_possible(struct intel_crtc *crtc) |
954 | { | |
955 | struct drm_device *dev = crtc->base.dev; | |
956 | struct intel_encoder *encoder; | |
957 | int count = 0, count_hdmi = 0; | |
958 | ||
f227ae9e | 959 | if (HAS_GMCH_DISPLAY(dev)) |
71800632 VS |
960 | return false; |
961 | ||
b2784e15 | 962 | for_each_intel_encoder(dev, encoder) { |
71800632 VS |
963 | if (encoder->new_crtc != crtc) |
964 | continue; | |
965 | ||
966 | count_hdmi += encoder->type == INTEL_OUTPUT_HDMI; | |
967 | count++; | |
968 | } | |
969 | ||
970 | /* | |
971 | * HDMI 12bpc affects the clocks, so it's only possible | |
972 | * when not cloning with other encoder types. | |
973 | */ | |
974 | return count_hdmi > 0 && count_hdmi == count; | |
975 | } | |
976 | ||
5bfe2ac0 | 977 | bool intel_hdmi_compute_config(struct intel_encoder *encoder, |
5cec258b | 978 | struct intel_crtc_state *pipe_config) |
7d57382e | 979 | { |
5bfe2ac0 DV |
980 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); |
981 | struct drm_device *dev = encoder->base.dev; | |
2d112de7 ACO |
982 | struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; |
983 | int clock_12bpc = pipe_config->base.adjusted_mode.crtc_clock * 3 / 2; | |
40478455 | 984 | int portclock_limit = hdmi_portclock_limit(intel_hdmi, false); |
e29c22c0 | 985 | int desired_bpp; |
3685a8f3 | 986 | |
6897b4b5 DV |
987 | pipe_config->has_hdmi_sink = intel_hdmi->has_hdmi_sink; |
988 | ||
e43823ec JB |
989 | if (pipe_config->has_hdmi_sink) |
990 | pipe_config->has_infoframe = true; | |
991 | ||
55bc60db VS |
992 | if (intel_hdmi->color_range_auto) { |
993 | /* See CEA-861-E - 5.1 Default Encoding Parameters */ | |
6897b4b5 | 994 | if (pipe_config->has_hdmi_sink && |
18316c8c | 995 | drm_match_cea_mode(adjusted_mode) > 1) |
4f3a8bc7 | 996 | intel_hdmi->color_range = HDMI_COLOR_RANGE_16_235; |
55bc60db VS |
997 | else |
998 | intel_hdmi->color_range = 0; | |
999 | } | |
1000 | ||
697c4078 CT |
1001 | if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK) { |
1002 | pipe_config->pixel_multiplier = 2; | |
1003 | } | |
1004 | ||
3685a8f3 | 1005 | if (intel_hdmi->color_range) |
50f3b016 | 1006 | pipe_config->limited_color_range = true; |
3685a8f3 | 1007 | |
5bfe2ac0 DV |
1008 | if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev)) |
1009 | pipe_config->has_pch_encoder = true; | |
1010 | ||
9ed109a7 DV |
1011 | if (pipe_config->has_hdmi_sink && intel_hdmi->has_audio) |
1012 | pipe_config->has_audio = true; | |
1013 | ||
4e53c2e0 DV |
1014 | /* |
1015 | * HDMI is either 12 or 8, so if the display lets 10bpc sneak | |
1016 | * through, clamp it down. Note that g4x/vlv don't support 12bpc hdmi | |
325b9d04 DV |
1017 | * outputs. We also need to check that the higher clock still fits |
1018 | * within limits. | |
4e53c2e0 | 1019 | */ |
6897b4b5 | 1020 | if (pipe_config->pipe_bpp > 8*3 && pipe_config->has_hdmi_sink && |
71800632 VS |
1021 | clock_12bpc <= portclock_limit && |
1022 | hdmi_12bpc_possible(encoder->new_crtc)) { | |
e29c22c0 DV |
1023 | DRM_DEBUG_KMS("picking bpc to 12 for HDMI output\n"); |
1024 | desired_bpp = 12*3; | |
325b9d04 DV |
1025 | |
1026 | /* Need to adjust the port link by 1.5x for 12bpc. */ | |
ff9a6750 | 1027 | pipe_config->port_clock = clock_12bpc; |
4e53c2e0 | 1028 | } else { |
e29c22c0 DV |
1029 | DRM_DEBUG_KMS("picking bpc to 8 for HDMI output\n"); |
1030 | desired_bpp = 8*3; | |
1031 | } | |
1032 | ||
1033 | if (!pipe_config->bw_constrained) { | |
1034 | DRM_DEBUG_KMS("forcing pipe bpc to %i for HDMI\n", desired_bpp); | |
1035 | pipe_config->pipe_bpp = desired_bpp; | |
4e53c2e0 DV |
1036 | } |
1037 | ||
241bfc38 | 1038 | if (adjusted_mode->crtc_clock > portclock_limit) { |
325b9d04 DV |
1039 | DRM_DEBUG_KMS("too high HDMI clock, rejecting mode\n"); |
1040 | return false; | |
1041 | } | |
1042 | ||
7d57382e EA |
1043 | return true; |
1044 | } | |
1045 | ||
953ece69 CW |
1046 | static void |
1047 | intel_hdmi_unset_edid(struct drm_connector *connector) | |
9dff6af8 | 1048 | { |
df0e9248 | 1049 | struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); |
9dff6af8 | 1050 | |
953ece69 CW |
1051 | intel_hdmi->has_hdmi_sink = false; |
1052 | intel_hdmi->has_audio = false; | |
1053 | intel_hdmi->rgb_quant_range_selectable = false; | |
1054 | ||
1055 | kfree(to_intel_connector(connector)->detect_edid); | |
1056 | to_intel_connector(connector)->detect_edid = NULL; | |
1057 | } | |
1058 | ||
1059 | static bool | |
1060 | intel_hdmi_set_edid(struct drm_connector *connector) | |
1061 | { | |
1062 | struct drm_i915_private *dev_priv = to_i915(connector->dev); | |
1063 | struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); | |
1064 | struct intel_encoder *intel_encoder = | |
1065 | &hdmi_to_dig_port(intel_hdmi)->base; | |
1066 | enum intel_display_power_domain power_domain; | |
1067 | struct edid *edid; | |
1068 | bool connected = false; | |
164c8598 | 1069 | |
671dedd2 ID |
1070 | power_domain = intel_display_port_power_domain(intel_encoder); |
1071 | intel_display_power_get(dev_priv, power_domain); | |
1072 | ||
f899fc64 | 1073 | edid = drm_get_edid(connector, |
3bd7d909 DK |
1074 | intel_gmbus_get_adapter(dev_priv, |
1075 | intel_hdmi->ddc_bus)); | |
2ded9e27 | 1076 | |
953ece69 | 1077 | intel_display_power_put(dev_priv, power_domain); |
30ad48b7 | 1078 | |
953ece69 CW |
1079 | to_intel_connector(connector)->detect_edid = edid; |
1080 | if (edid && edid->input & DRM_EDID_INPUT_DIGITAL) { | |
1081 | intel_hdmi->rgb_quant_range_selectable = | |
1082 | drm_rgb_quant_range_selectable(edid); | |
1083 | ||
1084 | intel_hdmi->has_audio = drm_detect_monitor_audio(edid); | |
b1d7e4b4 WF |
1085 | if (intel_hdmi->force_audio != HDMI_AUDIO_AUTO) |
1086 | intel_hdmi->has_audio = | |
953ece69 CW |
1087 | intel_hdmi->force_audio == HDMI_AUDIO_ON; |
1088 | ||
1089 | if (intel_hdmi->force_audio != HDMI_AUDIO_OFF_DVI) | |
1090 | intel_hdmi->has_hdmi_sink = | |
1091 | drm_detect_hdmi_monitor(edid); | |
1092 | ||
1093 | connected = true; | |
55b7d6e8 CW |
1094 | } |
1095 | ||
953ece69 CW |
1096 | return connected; |
1097 | } | |
1098 | ||
1099 | static enum drm_connector_status | |
1100 | intel_hdmi_detect(struct drm_connector *connector, bool force) | |
1101 | { | |
1102 | enum drm_connector_status status; | |
1103 | ||
1104 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", | |
1105 | connector->base.id, connector->name); | |
1106 | ||
1107 | intel_hdmi_unset_edid(connector); | |
1108 | ||
1109 | if (intel_hdmi_set_edid(connector)) { | |
1110 | struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); | |
1111 | ||
1112 | hdmi_to_dig_port(intel_hdmi)->base.type = INTEL_OUTPUT_HDMI; | |
1113 | status = connector_status_connected; | |
1114 | } else | |
1115 | status = connector_status_disconnected; | |
671dedd2 | 1116 | |
2ded9e27 | 1117 | return status; |
7d57382e EA |
1118 | } |
1119 | ||
953ece69 CW |
1120 | static void |
1121 | intel_hdmi_force(struct drm_connector *connector) | |
7d57382e | 1122 | { |
953ece69 | 1123 | struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); |
7d57382e | 1124 | |
953ece69 CW |
1125 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", |
1126 | connector->base.id, connector->name); | |
7d57382e | 1127 | |
953ece69 | 1128 | intel_hdmi_unset_edid(connector); |
671dedd2 | 1129 | |
953ece69 CW |
1130 | if (connector->status != connector_status_connected) |
1131 | return; | |
671dedd2 | 1132 | |
953ece69 CW |
1133 | intel_hdmi_set_edid(connector); |
1134 | hdmi_to_dig_port(intel_hdmi)->base.type = INTEL_OUTPUT_HDMI; | |
1135 | } | |
671dedd2 | 1136 | |
953ece69 CW |
1137 | static int intel_hdmi_get_modes(struct drm_connector *connector) |
1138 | { | |
1139 | struct edid *edid; | |
1140 | ||
1141 | edid = to_intel_connector(connector)->detect_edid; | |
1142 | if (edid == NULL) | |
1143 | return 0; | |
671dedd2 | 1144 | |
953ece69 | 1145 | return intel_connector_update_modes(connector, edid); |
7d57382e EA |
1146 | } |
1147 | ||
1aad7ac0 CW |
1148 | static bool |
1149 | intel_hdmi_detect_audio(struct drm_connector *connector) | |
1150 | { | |
1aad7ac0 | 1151 | bool has_audio = false; |
953ece69 | 1152 | struct edid *edid; |
1aad7ac0 | 1153 | |
953ece69 CW |
1154 | edid = to_intel_connector(connector)->detect_edid; |
1155 | if (edid && edid->input & DRM_EDID_INPUT_DIGITAL) | |
1156 | has_audio = drm_detect_monitor_audio(edid); | |
671dedd2 | 1157 | |
1aad7ac0 CW |
1158 | return has_audio; |
1159 | } | |
1160 | ||
55b7d6e8 CW |
1161 | static int |
1162 | intel_hdmi_set_property(struct drm_connector *connector, | |
ed517fbb PZ |
1163 | struct drm_property *property, |
1164 | uint64_t val) | |
55b7d6e8 CW |
1165 | { |
1166 | struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); | |
da63a9f2 PZ |
1167 | struct intel_digital_port *intel_dig_port = |
1168 | hdmi_to_dig_port(intel_hdmi); | |
e953fd7b | 1169 | struct drm_i915_private *dev_priv = connector->dev->dev_private; |
55b7d6e8 CW |
1170 | int ret; |
1171 | ||
662595df | 1172 | ret = drm_object_property_set_value(&connector->base, property, val); |
55b7d6e8 CW |
1173 | if (ret) |
1174 | return ret; | |
1175 | ||
3f43c48d | 1176 | if (property == dev_priv->force_audio_property) { |
b1d7e4b4 | 1177 | enum hdmi_force_audio i = val; |
1aad7ac0 CW |
1178 | bool has_audio; |
1179 | ||
1180 | if (i == intel_hdmi->force_audio) | |
55b7d6e8 CW |
1181 | return 0; |
1182 | ||
1aad7ac0 | 1183 | intel_hdmi->force_audio = i; |
55b7d6e8 | 1184 | |
b1d7e4b4 | 1185 | if (i == HDMI_AUDIO_AUTO) |
1aad7ac0 CW |
1186 | has_audio = intel_hdmi_detect_audio(connector); |
1187 | else | |
b1d7e4b4 | 1188 | has_audio = (i == HDMI_AUDIO_ON); |
1aad7ac0 | 1189 | |
b1d7e4b4 WF |
1190 | if (i == HDMI_AUDIO_OFF_DVI) |
1191 | intel_hdmi->has_hdmi_sink = 0; | |
55b7d6e8 | 1192 | |
1aad7ac0 | 1193 | intel_hdmi->has_audio = has_audio; |
55b7d6e8 CW |
1194 | goto done; |
1195 | } | |
1196 | ||
e953fd7b | 1197 | if (property == dev_priv->broadcast_rgb_property) { |
ae4edb80 DV |
1198 | bool old_auto = intel_hdmi->color_range_auto; |
1199 | uint32_t old_range = intel_hdmi->color_range; | |
1200 | ||
55bc60db VS |
1201 | switch (val) { |
1202 | case INTEL_BROADCAST_RGB_AUTO: | |
1203 | intel_hdmi->color_range_auto = true; | |
1204 | break; | |
1205 | case INTEL_BROADCAST_RGB_FULL: | |
1206 | intel_hdmi->color_range_auto = false; | |
1207 | intel_hdmi->color_range = 0; | |
1208 | break; | |
1209 | case INTEL_BROADCAST_RGB_LIMITED: | |
1210 | intel_hdmi->color_range_auto = false; | |
4f3a8bc7 | 1211 | intel_hdmi->color_range = HDMI_COLOR_RANGE_16_235; |
55bc60db VS |
1212 | break; |
1213 | default: | |
1214 | return -EINVAL; | |
1215 | } | |
ae4edb80 DV |
1216 | |
1217 | if (old_auto == intel_hdmi->color_range_auto && | |
1218 | old_range == intel_hdmi->color_range) | |
1219 | return 0; | |
1220 | ||
e953fd7b CW |
1221 | goto done; |
1222 | } | |
1223 | ||
94a11ddc VK |
1224 | if (property == connector->dev->mode_config.aspect_ratio_property) { |
1225 | switch (val) { | |
1226 | case DRM_MODE_PICTURE_ASPECT_NONE: | |
1227 | intel_hdmi->aspect_ratio = HDMI_PICTURE_ASPECT_NONE; | |
1228 | break; | |
1229 | case DRM_MODE_PICTURE_ASPECT_4_3: | |
1230 | intel_hdmi->aspect_ratio = HDMI_PICTURE_ASPECT_4_3; | |
1231 | break; | |
1232 | case DRM_MODE_PICTURE_ASPECT_16_9: | |
1233 | intel_hdmi->aspect_ratio = HDMI_PICTURE_ASPECT_16_9; | |
1234 | break; | |
1235 | default: | |
1236 | return -EINVAL; | |
1237 | } | |
1238 | goto done; | |
1239 | } | |
1240 | ||
55b7d6e8 CW |
1241 | return -EINVAL; |
1242 | ||
1243 | done: | |
c0c36b94 CW |
1244 | if (intel_dig_port->base.base.crtc) |
1245 | intel_crtc_restore_mode(intel_dig_port->base.base.crtc); | |
55b7d6e8 CW |
1246 | |
1247 | return 0; | |
1248 | } | |
1249 | ||
13732ba7 JB |
1250 | static void intel_hdmi_pre_enable(struct intel_encoder *encoder) |
1251 | { | |
1252 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); | |
1253 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); | |
1254 | struct drm_display_mode *adjusted_mode = | |
6e3c9717 | 1255 | &intel_crtc->config->base.adjusted_mode; |
13732ba7 | 1256 | |
4cde8a21 DV |
1257 | intel_hdmi_prepare(encoder); |
1258 | ||
6897b4b5 | 1259 | intel_hdmi->set_infoframes(&encoder->base, |
6e3c9717 | 1260 | intel_crtc->config->has_hdmi_sink, |
6897b4b5 | 1261 | adjusted_mode); |
13732ba7 JB |
1262 | } |
1263 | ||
9514ac6e | 1264 | static void vlv_hdmi_pre_enable(struct intel_encoder *encoder) |
89b667f8 JB |
1265 | { |
1266 | struct intel_digital_port *dport = enc_to_dig_port(&encoder->base); | |
13732ba7 | 1267 | struct intel_hdmi *intel_hdmi = &dport->hdmi; |
89b667f8 JB |
1268 | struct drm_device *dev = encoder->base.dev; |
1269 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1270 | struct intel_crtc *intel_crtc = | |
1271 | to_intel_crtc(encoder->base.crtc); | |
13732ba7 | 1272 | struct drm_display_mode *adjusted_mode = |
6e3c9717 | 1273 | &intel_crtc->config->base.adjusted_mode; |
e4607fcf | 1274 | enum dpio_channel port = vlv_dport_to_channel(dport); |
89b667f8 JB |
1275 | int pipe = intel_crtc->pipe; |
1276 | u32 val; | |
1277 | ||
89b667f8 | 1278 | /* Enable clock channels for this port */ |
0980a60f | 1279 | mutex_lock(&dev_priv->dpio_lock); |
ab3c759a | 1280 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port)); |
89b667f8 JB |
1281 | val = 0; |
1282 | if (pipe) | |
1283 | val |= (1<<21); | |
1284 | else | |
1285 | val &= ~(1<<21); | |
1286 | val |= 0x001000c4; | |
ab3c759a | 1287 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val); |
89b667f8 JB |
1288 | |
1289 | /* HDMI 1.0V-2dB */ | |
ab3c759a CML |
1290 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0); |
1291 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), 0x2b245f5f); | |
1292 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port), 0x5578b83a); | |
1293 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0c782040); | |
1294 | vlv_dpio_write(dev_priv, pipe, VLV_TX3_DW4(port), 0x2b247878); | |
1295 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000); | |
1296 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), 0x00002000); | |
1297 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), DPIO_TX_OCALINIT_EN); | |
89b667f8 JB |
1298 | |
1299 | /* Program lane clock */ | |
ab3c759a CML |
1300 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018); |
1301 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888); | |
0980a60f | 1302 | mutex_unlock(&dev_priv->dpio_lock); |
b76cf76b | 1303 | |
6897b4b5 | 1304 | intel_hdmi->set_infoframes(&encoder->base, |
6e3c9717 | 1305 | intel_crtc->config->has_hdmi_sink, |
6897b4b5 | 1306 | adjusted_mode); |
13732ba7 | 1307 | |
b76cf76b JN |
1308 | intel_enable_hdmi(encoder); |
1309 | ||
e4607fcf | 1310 | vlv_wait_port_ready(dev_priv, dport); |
89b667f8 JB |
1311 | } |
1312 | ||
9514ac6e | 1313 | static void vlv_hdmi_pre_pll_enable(struct intel_encoder *encoder) |
89b667f8 JB |
1314 | { |
1315 | struct intel_digital_port *dport = enc_to_dig_port(&encoder->base); | |
1316 | struct drm_device *dev = encoder->base.dev; | |
1317 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5e69f97f CML |
1318 | struct intel_crtc *intel_crtc = |
1319 | to_intel_crtc(encoder->base.crtc); | |
e4607fcf | 1320 | enum dpio_channel port = vlv_dport_to_channel(dport); |
5e69f97f | 1321 | int pipe = intel_crtc->pipe; |
89b667f8 | 1322 | |
4cde8a21 DV |
1323 | intel_hdmi_prepare(encoder); |
1324 | ||
89b667f8 | 1325 | /* Program Tx lane resets to default */ |
0980a60f | 1326 | mutex_lock(&dev_priv->dpio_lock); |
ab3c759a | 1327 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port), |
89b667f8 JB |
1328 | DPIO_PCS_TX_LANE2_RESET | |
1329 | DPIO_PCS_TX_LANE1_RESET); | |
ab3c759a | 1330 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port), |
89b667f8 JB |
1331 | DPIO_PCS_CLK_CRI_RXEB_EIOS_EN | |
1332 | DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN | | |
1333 | (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) | | |
1334 | DPIO_PCS_CLK_SOFT_RESET); | |
1335 | ||
1336 | /* Fix up inter-pair skew failure */ | |
ab3c759a CML |
1337 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW12(port), 0x00750f00); |
1338 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW11(port), 0x00001500); | |
1339 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000); | |
1340 | ||
1341 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), 0x00002000); | |
1342 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), DPIO_TX_OCALINIT_EN); | |
0980a60f | 1343 | mutex_unlock(&dev_priv->dpio_lock); |
89b667f8 JB |
1344 | } |
1345 | ||
9197c88b VS |
1346 | static void chv_hdmi_pre_pll_enable(struct intel_encoder *encoder) |
1347 | { | |
1348 | struct intel_digital_port *dport = enc_to_dig_port(&encoder->base); | |
1349 | struct drm_device *dev = encoder->base.dev; | |
1350 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1351 | struct intel_crtc *intel_crtc = | |
1352 | to_intel_crtc(encoder->base.crtc); | |
1353 | enum dpio_channel ch = vlv_dport_to_channel(dport); | |
1354 | enum pipe pipe = intel_crtc->pipe; | |
1355 | u32 val; | |
1356 | ||
625695f8 VS |
1357 | intel_hdmi_prepare(encoder); |
1358 | ||
9197c88b VS |
1359 | mutex_lock(&dev_priv->dpio_lock); |
1360 | ||
b9e5ac3c VS |
1361 | /* program left/right clock distribution */ |
1362 | if (pipe != PIPE_B) { | |
1363 | val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0); | |
1364 | val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK); | |
1365 | if (ch == DPIO_CH0) | |
1366 | val |= CHV_BUFLEFTENA1_FORCE; | |
1367 | if (ch == DPIO_CH1) | |
1368 | val |= CHV_BUFRIGHTENA1_FORCE; | |
1369 | vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val); | |
1370 | } else { | |
1371 | val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1); | |
1372 | val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK); | |
1373 | if (ch == DPIO_CH0) | |
1374 | val |= CHV_BUFLEFTENA2_FORCE; | |
1375 | if (ch == DPIO_CH1) | |
1376 | val |= CHV_BUFRIGHTENA2_FORCE; | |
1377 | vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val); | |
1378 | } | |
1379 | ||
9197c88b VS |
1380 | /* program clock channel usage */ |
1381 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(ch)); | |
1382 | val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE; | |
1383 | if (pipe != PIPE_B) | |
1384 | val &= ~CHV_PCS_USEDCLKCHANNEL; | |
1385 | else | |
1386 | val |= CHV_PCS_USEDCLKCHANNEL; | |
1387 | vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW8(ch), val); | |
1388 | ||
1389 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW8(ch)); | |
1390 | val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE; | |
1391 | if (pipe != PIPE_B) | |
1392 | val &= ~CHV_PCS_USEDCLKCHANNEL; | |
1393 | else | |
1394 | val |= CHV_PCS_USEDCLKCHANNEL; | |
1395 | vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW8(ch), val); | |
1396 | ||
1397 | /* | |
1398 | * This a a bit weird since generally CL | |
1399 | * matches the pipe, but here we need to | |
1400 | * pick the CL based on the port. | |
1401 | */ | |
1402 | val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW19(ch)); | |
1403 | if (pipe != PIPE_B) | |
1404 | val &= ~CHV_CMN_USEDCLKCHANNEL; | |
1405 | else | |
1406 | val |= CHV_CMN_USEDCLKCHANNEL; | |
1407 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW19(ch), val); | |
1408 | ||
1409 | mutex_unlock(&dev_priv->dpio_lock); | |
1410 | } | |
1411 | ||
9514ac6e | 1412 | static void vlv_hdmi_post_disable(struct intel_encoder *encoder) |
89b667f8 JB |
1413 | { |
1414 | struct intel_digital_port *dport = enc_to_dig_port(&encoder->base); | |
1415 | struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; | |
5e69f97f CML |
1416 | struct intel_crtc *intel_crtc = |
1417 | to_intel_crtc(encoder->base.crtc); | |
e4607fcf | 1418 | enum dpio_channel port = vlv_dport_to_channel(dport); |
5e69f97f | 1419 | int pipe = intel_crtc->pipe; |
89b667f8 JB |
1420 | |
1421 | /* Reset lanes to avoid HDMI flicker (VLV w/a) */ | |
1422 | mutex_lock(&dev_priv->dpio_lock); | |
ab3c759a CML |
1423 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port), 0x00000000); |
1424 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port), 0x00e00060); | |
89b667f8 JB |
1425 | mutex_unlock(&dev_priv->dpio_lock); |
1426 | } | |
1427 | ||
580d3811 VS |
1428 | static void chv_hdmi_post_disable(struct intel_encoder *encoder) |
1429 | { | |
1430 | struct intel_digital_port *dport = enc_to_dig_port(&encoder->base); | |
1431 | struct drm_device *dev = encoder->base.dev; | |
1432 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1433 | struct intel_crtc *intel_crtc = | |
1434 | to_intel_crtc(encoder->base.crtc); | |
1435 | enum dpio_channel ch = vlv_dport_to_channel(dport); | |
1436 | enum pipe pipe = intel_crtc->pipe; | |
1437 | u32 val; | |
1438 | ||
1439 | mutex_lock(&dev_priv->dpio_lock); | |
1440 | ||
1441 | /* Propagate soft reset to data lane reset */ | |
97fd4d5c | 1442 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch)); |
d2152b25 | 1443 | val |= CHV_PCS_REQ_SOFTRESET_EN; |
97fd4d5c | 1444 | vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val); |
d2152b25 | 1445 | |
97fd4d5c VS |
1446 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch)); |
1447 | val |= CHV_PCS_REQ_SOFTRESET_EN; | |
1448 | vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val); | |
1449 | ||
1450 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch)); | |
1451 | val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET); | |
1452 | vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val); | |
1453 | ||
1454 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch)); | |
580d3811 | 1455 | val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET); |
97fd4d5c | 1456 | vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val); |
580d3811 VS |
1457 | |
1458 | mutex_unlock(&dev_priv->dpio_lock); | |
1459 | } | |
1460 | ||
e4a1d846 CML |
1461 | static void chv_hdmi_pre_enable(struct intel_encoder *encoder) |
1462 | { | |
1463 | struct intel_digital_port *dport = enc_to_dig_port(&encoder->base); | |
b4eb1564 | 1464 | struct intel_hdmi *intel_hdmi = &dport->hdmi; |
e4a1d846 CML |
1465 | struct drm_device *dev = encoder->base.dev; |
1466 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1467 | struct intel_crtc *intel_crtc = | |
1468 | to_intel_crtc(encoder->base.crtc); | |
b4eb1564 | 1469 | struct drm_display_mode *adjusted_mode = |
6e3c9717 | 1470 | &intel_crtc->config->base.adjusted_mode; |
e4a1d846 CML |
1471 | enum dpio_channel ch = vlv_dport_to_channel(dport); |
1472 | int pipe = intel_crtc->pipe; | |
1473 | int data, i; | |
1474 | u32 val; | |
1475 | ||
e4a1d846 | 1476 | mutex_lock(&dev_priv->dpio_lock); |
949c1d43 | 1477 | |
570e2a74 VS |
1478 | /* allow hardware to manage TX FIFO reset source */ |
1479 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch)); | |
1480 | val &= ~DPIO_LANEDESKEW_STRAP_OVRD; | |
1481 | vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val); | |
1482 | ||
1483 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch)); | |
1484 | val &= ~DPIO_LANEDESKEW_STRAP_OVRD; | |
1485 | vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val); | |
1486 | ||
949c1d43 | 1487 | /* Deassert soft data lane reset*/ |
97fd4d5c | 1488 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch)); |
d2152b25 | 1489 | val |= CHV_PCS_REQ_SOFTRESET_EN; |
97fd4d5c VS |
1490 | vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val); |
1491 | ||
1492 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch)); | |
1493 | val |= CHV_PCS_REQ_SOFTRESET_EN; | |
1494 | vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val); | |
1495 | ||
1496 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch)); | |
1497 | val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET); | |
1498 | vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val); | |
d2152b25 | 1499 | |
97fd4d5c | 1500 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch)); |
949c1d43 | 1501 | val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET); |
97fd4d5c | 1502 | vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val); |
949c1d43 VS |
1503 | |
1504 | /* Program Tx latency optimal setting */ | |
e4a1d846 CML |
1505 | for (i = 0; i < 4; i++) { |
1506 | /* Set the latency optimal bit */ | |
1507 | data = (i == 1) ? 0x0 : 0x6; | |
1508 | vlv_dpio_write(dev_priv, pipe, CHV_TX_DW11(ch, i), | |
1509 | data << DPIO_FRC_LATENCY_SHFIT); | |
1510 | ||
1511 | /* Set the upar bit */ | |
1512 | data = (i == 1) ? 0x0 : 0x1; | |
1513 | vlv_dpio_write(dev_priv, pipe, CHV_TX_DW14(ch, i), | |
1514 | data << DPIO_UPAR_SHIFT); | |
1515 | } | |
1516 | ||
1517 | /* Data lane stagger programming */ | |
1518 | /* FIXME: Fix up value only after power analysis */ | |
1519 | ||
1520 | /* Clear calc init */ | |
1966e59e VS |
1521 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch)); |
1522 | val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3); | |
a02ef3c7 VS |
1523 | val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK); |
1524 | val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5; | |
1966e59e VS |
1525 | vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val); |
1526 | ||
1527 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch)); | |
1528 | val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3); | |
a02ef3c7 VS |
1529 | val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK); |
1530 | val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5; | |
1966e59e | 1531 | vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val); |
e4a1d846 | 1532 | |
a02ef3c7 VS |
1533 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW9(ch)); |
1534 | val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK); | |
1535 | val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000; | |
1536 | vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW9(ch), val); | |
1537 | ||
1538 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW9(ch)); | |
1539 | val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK); | |
1540 | val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000; | |
1541 | vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW9(ch), val); | |
1542 | ||
e4a1d846 CML |
1543 | /* FIXME: Program the support xxx V-dB */ |
1544 | /* Use 800mV-0dB */ | |
f72df8db VS |
1545 | for (i = 0; i < 4; i++) { |
1546 | val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW4(ch, i)); | |
1547 | val &= ~DPIO_SWING_DEEMPH9P5_MASK; | |
1548 | val |= 128 << DPIO_SWING_DEEMPH9P5_SHIFT; | |
1549 | vlv_dpio_write(dev_priv, pipe, CHV_TX_DW4(ch, i), val); | |
1550 | } | |
e4a1d846 | 1551 | |
f72df8db VS |
1552 | for (i = 0; i < 4; i++) { |
1553 | val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i)); | |
1fb44505 VS |
1554 | val &= ~DPIO_SWING_MARGIN000_MASK; |
1555 | val |= 102 << DPIO_SWING_MARGIN000_SHIFT; | |
f72df8db VS |
1556 | vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val); |
1557 | } | |
e4a1d846 CML |
1558 | |
1559 | /* Disable unique transition scale */ | |
f72df8db VS |
1560 | for (i = 0; i < 4; i++) { |
1561 | val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i)); | |
1562 | val &= ~DPIO_TX_UNIQ_TRANS_SCALE_EN; | |
1563 | vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val); | |
1564 | } | |
e4a1d846 CML |
1565 | |
1566 | /* Additional steps for 1200mV-0dB */ | |
1567 | #if 0 | |
1568 | val = vlv_dpio_read(dev_priv, pipe, VLV_TX_DW3(ch)); | |
1569 | if (ch) | |
1570 | val |= DPIO_TX_UNIQ_TRANS_SCALE_CH1; | |
1571 | else | |
1572 | val |= DPIO_TX_UNIQ_TRANS_SCALE_CH0; | |
1573 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(ch), val); | |
1574 | ||
1575 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(ch), | |
1576 | vlv_dpio_read(dev_priv, pipe, VLV_TX_DW2(ch)) | | |
1577 | (0x9a << DPIO_UNIQ_TRANS_SCALE_SHIFT)); | |
1578 | #endif | |
1579 | /* Start swing calculation */ | |
1966e59e VS |
1580 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch)); |
1581 | val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3; | |
1582 | vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val); | |
1583 | ||
1584 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch)); | |
1585 | val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3; | |
1586 | vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val); | |
e4a1d846 CML |
1587 | |
1588 | /* LRC Bypass */ | |
1589 | val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW30); | |
1590 | val |= DPIO_LRC_BYPASS; | |
1591 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW30, val); | |
1592 | ||
1593 | mutex_unlock(&dev_priv->dpio_lock); | |
1594 | ||
b4eb1564 | 1595 | intel_hdmi->set_infoframes(&encoder->base, |
6e3c9717 | 1596 | intel_crtc->config->has_hdmi_sink, |
b4eb1564 CT |
1597 | adjusted_mode); |
1598 | ||
e4a1d846 CML |
1599 | intel_enable_hdmi(encoder); |
1600 | ||
1601 | vlv_wait_port_ready(dev_priv, dport); | |
1602 | } | |
1603 | ||
7d57382e EA |
1604 | static void intel_hdmi_destroy(struct drm_connector *connector) |
1605 | { | |
10e972d3 | 1606 | kfree(to_intel_connector(connector)->detect_edid); |
7d57382e | 1607 | drm_connector_cleanup(connector); |
674e2d08 | 1608 | kfree(connector); |
7d57382e EA |
1609 | } |
1610 | ||
7d57382e | 1611 | static const struct drm_connector_funcs intel_hdmi_connector_funcs = { |
5ab432ef | 1612 | .dpms = intel_connector_dpms, |
7d57382e | 1613 | .detect = intel_hdmi_detect, |
953ece69 | 1614 | .force = intel_hdmi_force, |
7d57382e | 1615 | .fill_modes = drm_helper_probe_single_connector_modes, |
55b7d6e8 | 1616 | .set_property = intel_hdmi_set_property, |
7d57382e EA |
1617 | .destroy = intel_hdmi_destroy, |
1618 | }; | |
1619 | ||
1620 | static const struct drm_connector_helper_funcs intel_hdmi_connector_helper_funcs = { | |
1621 | .get_modes = intel_hdmi_get_modes, | |
1622 | .mode_valid = intel_hdmi_mode_valid, | |
df0e9248 | 1623 | .best_encoder = intel_best_encoder, |
7d57382e EA |
1624 | }; |
1625 | ||
7d57382e | 1626 | static const struct drm_encoder_funcs intel_hdmi_enc_funcs = { |
ea5b213a | 1627 | .destroy = intel_encoder_destroy, |
7d57382e EA |
1628 | }; |
1629 | ||
94a11ddc VK |
1630 | static void |
1631 | intel_attach_aspect_ratio_property(struct drm_connector *connector) | |
1632 | { | |
1633 | if (!drm_mode_create_aspect_ratio_property(connector->dev)) | |
1634 | drm_object_attach_property(&connector->base, | |
1635 | connector->dev->mode_config.aspect_ratio_property, | |
1636 | DRM_MODE_PICTURE_ASPECT_NONE); | |
1637 | } | |
1638 | ||
55b7d6e8 CW |
1639 | static void |
1640 | intel_hdmi_add_properties(struct intel_hdmi *intel_hdmi, struct drm_connector *connector) | |
1641 | { | |
3f43c48d | 1642 | intel_attach_force_audio_property(connector); |
e953fd7b | 1643 | intel_attach_broadcast_rgb_property(connector); |
55bc60db | 1644 | intel_hdmi->color_range_auto = true; |
94a11ddc VK |
1645 | intel_attach_aspect_ratio_property(connector); |
1646 | intel_hdmi->aspect_ratio = HDMI_PICTURE_ASPECT_NONE; | |
55b7d6e8 CW |
1647 | } |
1648 | ||
00c09d70 PZ |
1649 | void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port, |
1650 | struct intel_connector *intel_connector) | |
7d57382e | 1651 | { |
b9cb234c PZ |
1652 | struct drm_connector *connector = &intel_connector->base; |
1653 | struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi; | |
1654 | struct intel_encoder *intel_encoder = &intel_dig_port->base; | |
1655 | struct drm_device *dev = intel_encoder->base.dev; | |
7d57382e | 1656 | struct drm_i915_private *dev_priv = dev->dev_private; |
174edf1f | 1657 | enum port port = intel_dig_port->port; |
373a3cf7 | 1658 | |
7d57382e | 1659 | drm_connector_init(dev, connector, &intel_hdmi_connector_funcs, |
8d91104a | 1660 | DRM_MODE_CONNECTOR_HDMIA); |
7d57382e EA |
1661 | drm_connector_helper_add(connector, &intel_hdmi_connector_helper_funcs); |
1662 | ||
c3febcc4 | 1663 | connector->interlace_allowed = 1; |
7d57382e | 1664 | connector->doublescan_allowed = 0; |
573e74ad | 1665 | connector->stereo_allowed = 1; |
66a9278e | 1666 | |
08d644ad DV |
1667 | switch (port) { |
1668 | case PORT_B: | |
f899fc64 | 1669 | intel_hdmi->ddc_bus = GMBUS_PORT_DPB; |
1d843f9d | 1670 | intel_encoder->hpd_pin = HPD_PORT_B; |
08d644ad DV |
1671 | break; |
1672 | case PORT_C: | |
7ceae0a5 | 1673 | intel_hdmi->ddc_bus = GMBUS_PORT_DPC; |
1d843f9d | 1674 | intel_encoder->hpd_pin = HPD_PORT_C; |
08d644ad DV |
1675 | break; |
1676 | case PORT_D: | |
c0c35329 VS |
1677 | if (IS_CHERRYVIEW(dev)) |
1678 | intel_hdmi->ddc_bus = GMBUS_PORT_DPD_CHV; | |
1679 | else | |
1680 | intel_hdmi->ddc_bus = GMBUS_PORT_DPD; | |
1d843f9d | 1681 | intel_encoder->hpd_pin = HPD_PORT_D; |
08d644ad DV |
1682 | break; |
1683 | case PORT_A: | |
1d843f9d | 1684 | intel_encoder->hpd_pin = HPD_PORT_A; |
08d644ad DV |
1685 | /* Internal port only for eDP. */ |
1686 | default: | |
6e4c1677 | 1687 | BUG(); |
f8aed700 | 1688 | } |
7d57382e | 1689 | |
7637bfdb | 1690 | if (IS_VALLEYVIEW(dev)) { |
90b107c8 | 1691 | intel_hdmi->write_infoframe = vlv_write_infoframe; |
687f4d06 | 1692 | intel_hdmi->set_infoframes = vlv_set_infoframes; |
e43823ec | 1693 | intel_hdmi->infoframe_enabled = vlv_infoframe_enabled; |
b98856a8 | 1694 | } else if (IS_G4X(dev)) { |
7637bfdb JB |
1695 | intel_hdmi->write_infoframe = g4x_write_infoframe; |
1696 | intel_hdmi->set_infoframes = g4x_set_infoframes; | |
e43823ec | 1697 | intel_hdmi->infoframe_enabled = g4x_infoframe_enabled; |
22b8bf17 | 1698 | } else if (HAS_DDI(dev)) { |
8c5f5f7c | 1699 | intel_hdmi->write_infoframe = hsw_write_infoframe; |
687f4d06 | 1700 | intel_hdmi->set_infoframes = hsw_set_infoframes; |
e43823ec | 1701 | intel_hdmi->infoframe_enabled = hsw_infoframe_enabled; |
fdf1250a PZ |
1702 | } else if (HAS_PCH_IBX(dev)) { |
1703 | intel_hdmi->write_infoframe = ibx_write_infoframe; | |
687f4d06 | 1704 | intel_hdmi->set_infoframes = ibx_set_infoframes; |
e43823ec | 1705 | intel_hdmi->infoframe_enabled = ibx_infoframe_enabled; |
fdf1250a PZ |
1706 | } else { |
1707 | intel_hdmi->write_infoframe = cpt_write_infoframe; | |
687f4d06 | 1708 | intel_hdmi->set_infoframes = cpt_set_infoframes; |
e43823ec | 1709 | intel_hdmi->infoframe_enabled = cpt_infoframe_enabled; |
64a8fc01 | 1710 | } |
45187ace | 1711 | |
affa9354 | 1712 | if (HAS_DDI(dev)) |
bcbc889b PZ |
1713 | intel_connector->get_hw_state = intel_ddi_connector_get_hw_state; |
1714 | else | |
1715 | intel_connector->get_hw_state = intel_connector_get_hw_state; | |
4932e2c3 | 1716 | intel_connector->unregister = intel_connector_unregister; |
b9cb234c PZ |
1717 | |
1718 | intel_hdmi_add_properties(intel_hdmi, connector); | |
1719 | ||
1720 | intel_connector_attach_encoder(intel_connector, intel_encoder); | |
34ea3d38 | 1721 | drm_connector_register(connector); |
b9cb234c PZ |
1722 | |
1723 | /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written | |
1724 | * 0xd. Failure to do so will result in spurious interrupts being | |
1725 | * generated on the port when a cable is not attached. | |
1726 | */ | |
1727 | if (IS_G4X(dev) && !IS_GM45(dev)) { | |
1728 | u32 temp = I915_READ(PEG_BAND_GAP_DATA); | |
1729 | I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd); | |
1730 | } | |
1731 | } | |
1732 | ||
b242b7f7 | 1733 | void intel_hdmi_init(struct drm_device *dev, int hdmi_reg, enum port port) |
b9cb234c PZ |
1734 | { |
1735 | struct intel_digital_port *intel_dig_port; | |
1736 | struct intel_encoder *intel_encoder; | |
b9cb234c PZ |
1737 | struct intel_connector *intel_connector; |
1738 | ||
b14c5679 | 1739 | intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL); |
b9cb234c PZ |
1740 | if (!intel_dig_port) |
1741 | return; | |
1742 | ||
b14c5679 | 1743 | intel_connector = kzalloc(sizeof(*intel_connector), GFP_KERNEL); |
b9cb234c PZ |
1744 | if (!intel_connector) { |
1745 | kfree(intel_dig_port); | |
1746 | return; | |
1747 | } | |
1748 | ||
1749 | intel_encoder = &intel_dig_port->base; | |
b9cb234c PZ |
1750 | |
1751 | drm_encoder_init(dev, &intel_encoder->base, &intel_hdmi_enc_funcs, | |
1752 | DRM_MODE_ENCODER_TMDS); | |
00c09d70 | 1753 | |
5bfe2ac0 | 1754 | intel_encoder->compute_config = intel_hdmi_compute_config; |
00c09d70 PZ |
1755 | intel_encoder->disable = intel_disable_hdmi; |
1756 | intel_encoder->get_hw_state = intel_hdmi_get_hw_state; | |
045ac3b5 | 1757 | intel_encoder->get_config = intel_hdmi_get_config; |
e4a1d846 | 1758 | if (IS_CHERRYVIEW(dev)) { |
9197c88b | 1759 | intel_encoder->pre_pll_enable = chv_hdmi_pre_pll_enable; |
e4a1d846 CML |
1760 | intel_encoder->pre_enable = chv_hdmi_pre_enable; |
1761 | intel_encoder->enable = vlv_enable_hdmi; | |
580d3811 | 1762 | intel_encoder->post_disable = chv_hdmi_post_disable; |
e4a1d846 | 1763 | } else if (IS_VALLEYVIEW(dev)) { |
9514ac6e CML |
1764 | intel_encoder->pre_pll_enable = vlv_hdmi_pre_pll_enable; |
1765 | intel_encoder->pre_enable = vlv_hdmi_pre_enable; | |
b76cf76b | 1766 | intel_encoder->enable = vlv_enable_hdmi; |
9514ac6e | 1767 | intel_encoder->post_disable = vlv_hdmi_post_disable; |
b76cf76b | 1768 | } else { |
13732ba7 | 1769 | intel_encoder->pre_enable = intel_hdmi_pre_enable; |
b76cf76b | 1770 | intel_encoder->enable = intel_enable_hdmi; |
89b667f8 | 1771 | } |
5ab432ef | 1772 | |
b9cb234c | 1773 | intel_encoder->type = INTEL_OUTPUT_HDMI; |
882ec384 VS |
1774 | if (IS_CHERRYVIEW(dev)) { |
1775 | if (port == PORT_D) | |
1776 | intel_encoder->crtc_mask = 1 << 2; | |
1777 | else | |
1778 | intel_encoder->crtc_mask = (1 << 0) | (1 << 1); | |
1779 | } else { | |
1780 | intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2); | |
1781 | } | |
301ea74a | 1782 | intel_encoder->cloneable = 1 << INTEL_OUTPUT_ANALOG; |
c6f1495d VS |
1783 | /* |
1784 | * BSpec is unclear about HDMI+HDMI cloning on g4x, but it seems | |
1785 | * to work on real hardware. And since g4x can send infoframes to | |
1786 | * only one port anyway, nothing is lost by allowing it. | |
1787 | */ | |
1788 | if (IS_G4X(dev)) | |
1789 | intel_encoder->cloneable |= 1 << INTEL_OUTPUT_HDMI; | |
7d57382e | 1790 | |
174edf1f | 1791 | intel_dig_port->port = port; |
b242b7f7 | 1792 | intel_dig_port->hdmi.hdmi_reg = hdmi_reg; |
b9cb234c | 1793 | intel_dig_port->dp.output_reg = 0; |
55b7d6e8 | 1794 | |
b9cb234c | 1795 | intel_hdmi_init_connector(intel_dig_port, intel_connector); |
7d57382e | 1796 | } |