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7d57382e EA |
1 | /* |
2 | * Copyright 2006 Dave Airlie <airlied@linux.ie> | |
3 | * Copyright © 2006-2009 Intel Corporation | |
4 | * | |
5 | * Permission is hereby granted, free of charge, to any person obtaining a | |
6 | * copy of this software and associated documentation files (the "Software"), | |
7 | * to deal in the Software without restriction, including without limitation | |
8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
9 | * and/or sell copies of the Software, and to permit persons to whom the | |
10 | * Software is furnished to do so, subject to the following conditions: | |
11 | * | |
12 | * The above copyright notice and this permission notice (including the next | |
13 | * paragraph) shall be included in all copies or substantial portions of the | |
14 | * Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
21 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
22 | * DEALINGS IN THE SOFTWARE. | |
23 | * | |
24 | * Authors: | |
25 | * Eric Anholt <eric@anholt.net> | |
26 | * Jesse Barnes <jesse.barnes@intel.com> | |
27 | */ | |
28 | ||
29 | #include <linux/i2c.h> | |
5a0e3ad6 | 30 | #include <linux/slab.h> |
7d57382e | 31 | #include <linux/delay.h> |
178f736a | 32 | #include <linux/hdmi.h> |
760285e7 DH |
33 | #include <drm/drmP.h> |
34 | #include <drm/drm_crtc.h> | |
35 | #include <drm/drm_edid.h> | |
7d57382e | 36 | #include "intel_drv.h" |
760285e7 | 37 | #include <drm/i915_drm.h> |
7d57382e EA |
38 | #include "i915_drv.h" |
39 | ||
30add22d PZ |
40 | static struct drm_device *intel_hdmi_to_dev(struct intel_hdmi *intel_hdmi) |
41 | { | |
da63a9f2 | 42 | return hdmi_to_dig_port(intel_hdmi)->base.base.dev; |
30add22d PZ |
43 | } |
44 | ||
afba0188 DV |
45 | static void |
46 | assert_hdmi_port_disabled(struct intel_hdmi *intel_hdmi) | |
47 | { | |
30add22d | 48 | struct drm_device *dev = intel_hdmi_to_dev(intel_hdmi); |
afba0188 DV |
49 | struct drm_i915_private *dev_priv = dev->dev_private; |
50 | uint32_t enabled_bits; | |
51 | ||
affa9354 | 52 | enabled_bits = HAS_DDI(dev) ? DDI_BUF_CTL_ENABLE : SDVO_ENABLE; |
afba0188 | 53 | |
b242b7f7 | 54 | WARN(I915_READ(intel_hdmi->hdmi_reg) & enabled_bits, |
afba0188 DV |
55 | "HDMI port enabled, expecting disabled\n"); |
56 | } | |
57 | ||
f5bbfca3 | 58 | struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder) |
ea5b213a | 59 | { |
da63a9f2 PZ |
60 | struct intel_digital_port *intel_dig_port = |
61 | container_of(encoder, struct intel_digital_port, base.base); | |
62 | return &intel_dig_port->hdmi; | |
ea5b213a CW |
63 | } |
64 | ||
df0e9248 CW |
65 | static struct intel_hdmi *intel_attached_hdmi(struct drm_connector *connector) |
66 | { | |
da63a9f2 | 67 | return enc_to_intel_hdmi(&intel_attached_encoder(connector)->base); |
df0e9248 CW |
68 | } |
69 | ||
178f736a | 70 | static u32 g4x_infoframe_index(enum hdmi_infoframe_type type) |
3c17fe4b | 71 | { |
178f736a DL |
72 | switch (type) { |
73 | case HDMI_INFOFRAME_TYPE_AVI: | |
ed517fbb | 74 | return VIDEO_DIP_SELECT_AVI; |
178f736a | 75 | case HDMI_INFOFRAME_TYPE_SPD: |
ed517fbb | 76 | return VIDEO_DIP_SELECT_SPD; |
c8bb75af LD |
77 | case HDMI_INFOFRAME_TYPE_VENDOR: |
78 | return VIDEO_DIP_SELECT_VENDOR; | |
45187ace | 79 | default: |
178f736a | 80 | DRM_DEBUG_DRIVER("unknown info frame type %d\n", type); |
ed517fbb | 81 | return 0; |
45187ace | 82 | } |
45187ace JB |
83 | } |
84 | ||
178f736a | 85 | static u32 g4x_infoframe_enable(enum hdmi_infoframe_type type) |
45187ace | 86 | { |
178f736a DL |
87 | switch (type) { |
88 | case HDMI_INFOFRAME_TYPE_AVI: | |
ed517fbb | 89 | return VIDEO_DIP_ENABLE_AVI; |
178f736a | 90 | case HDMI_INFOFRAME_TYPE_SPD: |
ed517fbb | 91 | return VIDEO_DIP_ENABLE_SPD; |
c8bb75af LD |
92 | case HDMI_INFOFRAME_TYPE_VENDOR: |
93 | return VIDEO_DIP_ENABLE_VENDOR; | |
fa193ff7 | 94 | default: |
178f736a | 95 | DRM_DEBUG_DRIVER("unknown info frame type %d\n", type); |
ed517fbb | 96 | return 0; |
fa193ff7 | 97 | } |
fa193ff7 PZ |
98 | } |
99 | ||
178f736a | 100 | static u32 hsw_infoframe_enable(enum hdmi_infoframe_type type) |
2da8af54 | 101 | { |
178f736a DL |
102 | switch (type) { |
103 | case HDMI_INFOFRAME_TYPE_AVI: | |
2da8af54 | 104 | return VIDEO_DIP_ENABLE_AVI_HSW; |
178f736a | 105 | case HDMI_INFOFRAME_TYPE_SPD: |
2da8af54 | 106 | return VIDEO_DIP_ENABLE_SPD_HSW; |
c8bb75af LD |
107 | case HDMI_INFOFRAME_TYPE_VENDOR: |
108 | return VIDEO_DIP_ENABLE_VS_HSW; | |
2da8af54 | 109 | default: |
178f736a | 110 | DRM_DEBUG_DRIVER("unknown info frame type %d\n", type); |
2da8af54 PZ |
111 | return 0; |
112 | } | |
113 | } | |
114 | ||
178f736a | 115 | static u32 hsw_infoframe_data_reg(enum hdmi_infoframe_type type, |
a57c774a AK |
116 | enum transcoder cpu_transcoder, |
117 | struct drm_i915_private *dev_priv) | |
2da8af54 | 118 | { |
178f736a DL |
119 | switch (type) { |
120 | case HDMI_INFOFRAME_TYPE_AVI: | |
7d9bcebe | 121 | return HSW_TVIDEO_DIP_AVI_DATA(cpu_transcoder); |
178f736a | 122 | case HDMI_INFOFRAME_TYPE_SPD: |
7d9bcebe | 123 | return HSW_TVIDEO_DIP_SPD_DATA(cpu_transcoder); |
c8bb75af LD |
124 | case HDMI_INFOFRAME_TYPE_VENDOR: |
125 | return HSW_TVIDEO_DIP_VS_DATA(cpu_transcoder); | |
2da8af54 | 126 | default: |
178f736a | 127 | DRM_DEBUG_DRIVER("unknown info frame type %d\n", type); |
2da8af54 PZ |
128 | return 0; |
129 | } | |
130 | } | |
131 | ||
a3da1df7 | 132 | static void g4x_write_infoframe(struct drm_encoder *encoder, |
178f736a | 133 | enum hdmi_infoframe_type type, |
fff63867 | 134 | const void *frame, ssize_t len) |
45187ace | 135 | { |
fff63867 | 136 | const uint32_t *data = frame; |
3c17fe4b DH |
137 | struct drm_device *dev = encoder->dev; |
138 | struct drm_i915_private *dev_priv = dev->dev_private; | |
22509ec8 | 139 | u32 val = I915_READ(VIDEO_DIP_CTL); |
178f736a | 140 | int i; |
3c17fe4b | 141 | |
822974ae PZ |
142 | WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n"); |
143 | ||
1d4f85ac | 144 | val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ |
178f736a | 145 | val |= g4x_infoframe_index(type); |
22509ec8 | 146 | |
178f736a | 147 | val &= ~g4x_infoframe_enable(type); |
45187ace | 148 | |
22509ec8 | 149 | I915_WRITE(VIDEO_DIP_CTL, val); |
3c17fe4b | 150 | |
9d9740f0 | 151 | mmiowb(); |
45187ace | 152 | for (i = 0; i < len; i += 4) { |
3c17fe4b DH |
153 | I915_WRITE(VIDEO_DIP_DATA, *data); |
154 | data++; | |
155 | } | |
adf00b26 PZ |
156 | /* Write every possible data byte to force correct ECC calculation. */ |
157 | for (; i < VIDEO_DIP_DATA_SIZE; i += 4) | |
158 | I915_WRITE(VIDEO_DIP_DATA, 0); | |
9d9740f0 | 159 | mmiowb(); |
3c17fe4b | 160 | |
178f736a | 161 | val |= g4x_infoframe_enable(type); |
60c5ea2d | 162 | val &= ~VIDEO_DIP_FREQ_MASK; |
4b24c933 | 163 | val |= VIDEO_DIP_FREQ_VSYNC; |
45187ace | 164 | |
22509ec8 | 165 | I915_WRITE(VIDEO_DIP_CTL, val); |
9d9740f0 | 166 | POSTING_READ(VIDEO_DIP_CTL); |
3c17fe4b DH |
167 | } |
168 | ||
fdf1250a | 169 | static void ibx_write_infoframe(struct drm_encoder *encoder, |
178f736a | 170 | enum hdmi_infoframe_type type, |
fff63867 | 171 | const void *frame, ssize_t len) |
fdf1250a | 172 | { |
fff63867 | 173 | const uint32_t *data = frame; |
fdf1250a PZ |
174 | struct drm_device *dev = encoder->dev; |
175 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ed517fbb | 176 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); |
178f736a | 177 | int i, reg = TVIDEO_DIP_CTL(intel_crtc->pipe); |
fdf1250a PZ |
178 | u32 val = I915_READ(reg); |
179 | ||
822974ae PZ |
180 | WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n"); |
181 | ||
fdf1250a | 182 | val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ |
178f736a | 183 | val |= g4x_infoframe_index(type); |
fdf1250a | 184 | |
178f736a | 185 | val &= ~g4x_infoframe_enable(type); |
fdf1250a PZ |
186 | |
187 | I915_WRITE(reg, val); | |
188 | ||
9d9740f0 | 189 | mmiowb(); |
fdf1250a PZ |
190 | for (i = 0; i < len; i += 4) { |
191 | I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data); | |
192 | data++; | |
193 | } | |
adf00b26 PZ |
194 | /* Write every possible data byte to force correct ECC calculation. */ |
195 | for (; i < VIDEO_DIP_DATA_SIZE; i += 4) | |
196 | I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0); | |
9d9740f0 | 197 | mmiowb(); |
fdf1250a | 198 | |
178f736a | 199 | val |= g4x_infoframe_enable(type); |
fdf1250a | 200 | val &= ~VIDEO_DIP_FREQ_MASK; |
4b24c933 | 201 | val |= VIDEO_DIP_FREQ_VSYNC; |
fdf1250a PZ |
202 | |
203 | I915_WRITE(reg, val); | |
9d9740f0 | 204 | POSTING_READ(reg); |
fdf1250a PZ |
205 | } |
206 | ||
207 | static void cpt_write_infoframe(struct drm_encoder *encoder, | |
178f736a | 208 | enum hdmi_infoframe_type type, |
fff63867 | 209 | const void *frame, ssize_t len) |
b055c8f3 | 210 | { |
fff63867 | 211 | const uint32_t *data = frame; |
b055c8f3 JB |
212 | struct drm_device *dev = encoder->dev; |
213 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ed517fbb | 214 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); |
178f736a | 215 | int i, reg = TVIDEO_DIP_CTL(intel_crtc->pipe); |
22509ec8 | 216 | u32 val = I915_READ(reg); |
b055c8f3 | 217 | |
822974ae PZ |
218 | WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n"); |
219 | ||
64a8fc01 | 220 | val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ |
178f736a | 221 | val |= g4x_infoframe_index(type); |
45187ace | 222 | |
ecb97851 PZ |
223 | /* The DIP control register spec says that we need to update the AVI |
224 | * infoframe without clearing its enable bit */ | |
178f736a DL |
225 | if (type != HDMI_INFOFRAME_TYPE_AVI) |
226 | val &= ~g4x_infoframe_enable(type); | |
ecb97851 | 227 | |
22509ec8 | 228 | I915_WRITE(reg, val); |
45187ace | 229 | |
9d9740f0 | 230 | mmiowb(); |
45187ace | 231 | for (i = 0; i < len; i += 4) { |
b055c8f3 JB |
232 | I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data); |
233 | data++; | |
234 | } | |
adf00b26 PZ |
235 | /* Write every possible data byte to force correct ECC calculation. */ |
236 | for (; i < VIDEO_DIP_DATA_SIZE; i += 4) | |
237 | I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0); | |
9d9740f0 | 238 | mmiowb(); |
b055c8f3 | 239 | |
178f736a | 240 | val |= g4x_infoframe_enable(type); |
60c5ea2d | 241 | val &= ~VIDEO_DIP_FREQ_MASK; |
4b24c933 | 242 | val |= VIDEO_DIP_FREQ_VSYNC; |
45187ace | 243 | |
22509ec8 | 244 | I915_WRITE(reg, val); |
9d9740f0 | 245 | POSTING_READ(reg); |
45187ace | 246 | } |
90b107c8 SK |
247 | |
248 | static void vlv_write_infoframe(struct drm_encoder *encoder, | |
178f736a | 249 | enum hdmi_infoframe_type type, |
fff63867 | 250 | const void *frame, ssize_t len) |
90b107c8 | 251 | { |
fff63867 | 252 | const uint32_t *data = frame; |
90b107c8 SK |
253 | struct drm_device *dev = encoder->dev; |
254 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ed517fbb | 255 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); |
178f736a | 256 | int i, reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe); |
22509ec8 | 257 | u32 val = I915_READ(reg); |
90b107c8 | 258 | |
822974ae PZ |
259 | WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n"); |
260 | ||
90b107c8 | 261 | val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ |
178f736a | 262 | val |= g4x_infoframe_index(type); |
22509ec8 | 263 | |
178f736a | 264 | val &= ~g4x_infoframe_enable(type); |
90b107c8 | 265 | |
22509ec8 | 266 | I915_WRITE(reg, val); |
90b107c8 | 267 | |
9d9740f0 | 268 | mmiowb(); |
90b107c8 SK |
269 | for (i = 0; i < len; i += 4) { |
270 | I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), *data); | |
271 | data++; | |
272 | } | |
adf00b26 PZ |
273 | /* Write every possible data byte to force correct ECC calculation. */ |
274 | for (; i < VIDEO_DIP_DATA_SIZE; i += 4) | |
275 | I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), 0); | |
9d9740f0 | 276 | mmiowb(); |
90b107c8 | 277 | |
178f736a | 278 | val |= g4x_infoframe_enable(type); |
60c5ea2d | 279 | val &= ~VIDEO_DIP_FREQ_MASK; |
4b24c933 | 280 | val |= VIDEO_DIP_FREQ_VSYNC; |
90b107c8 | 281 | |
22509ec8 | 282 | I915_WRITE(reg, val); |
9d9740f0 | 283 | POSTING_READ(reg); |
90b107c8 SK |
284 | } |
285 | ||
8c5f5f7c | 286 | static void hsw_write_infoframe(struct drm_encoder *encoder, |
178f736a | 287 | enum hdmi_infoframe_type type, |
fff63867 | 288 | const void *frame, ssize_t len) |
8c5f5f7c | 289 | { |
fff63867 | 290 | const uint32_t *data = frame; |
2da8af54 PZ |
291 | struct drm_device *dev = encoder->dev; |
292 | struct drm_i915_private *dev_priv = dev->dev_private; | |
293 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); | |
3b117c8f | 294 | u32 ctl_reg = HSW_TVIDEO_DIP_CTL(intel_crtc->config.cpu_transcoder); |
178f736a DL |
295 | u32 data_reg; |
296 | int i; | |
2da8af54 | 297 | u32 val = I915_READ(ctl_reg); |
8c5f5f7c | 298 | |
178f736a | 299 | data_reg = hsw_infoframe_data_reg(type, |
a57c774a AK |
300 | intel_crtc->config.cpu_transcoder, |
301 | dev_priv); | |
2da8af54 PZ |
302 | if (data_reg == 0) |
303 | return; | |
304 | ||
178f736a | 305 | val &= ~hsw_infoframe_enable(type); |
2da8af54 PZ |
306 | I915_WRITE(ctl_reg, val); |
307 | ||
9d9740f0 | 308 | mmiowb(); |
2da8af54 PZ |
309 | for (i = 0; i < len; i += 4) { |
310 | I915_WRITE(data_reg + i, *data); | |
311 | data++; | |
312 | } | |
adf00b26 PZ |
313 | /* Write every possible data byte to force correct ECC calculation. */ |
314 | for (; i < VIDEO_DIP_DATA_SIZE; i += 4) | |
315 | I915_WRITE(data_reg + i, 0); | |
9d9740f0 | 316 | mmiowb(); |
8c5f5f7c | 317 | |
178f736a | 318 | val |= hsw_infoframe_enable(type); |
2da8af54 | 319 | I915_WRITE(ctl_reg, val); |
9d9740f0 | 320 | POSTING_READ(ctl_reg); |
8c5f5f7c ED |
321 | } |
322 | ||
5adaea79 DL |
323 | /* |
324 | * The data we write to the DIP data buffer registers is 1 byte bigger than the | |
325 | * HDMI infoframe size because of an ECC/reserved byte at position 3 (starting | |
326 | * at 0). It's also a byte used by DisplayPort so the same DIP registers can be | |
327 | * used for both technologies. | |
328 | * | |
329 | * DW0: Reserved/ECC/DP | HB2 | HB1 | HB0 | |
330 | * DW1: DB3 | DB2 | DB1 | DB0 | |
331 | * DW2: DB7 | DB6 | DB5 | DB4 | |
332 | * DW3: ... | |
333 | * | |
334 | * (HB is Header Byte, DB is Data Byte) | |
335 | * | |
336 | * The hdmi pack() functions don't know about that hardware specific hole so we | |
337 | * trick them by giving an offset into the buffer and moving back the header | |
338 | * bytes by one. | |
339 | */ | |
9198ee5b DL |
340 | static void intel_write_infoframe(struct drm_encoder *encoder, |
341 | union hdmi_infoframe *frame) | |
45187ace JB |
342 | { |
343 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); | |
5adaea79 DL |
344 | uint8_t buffer[VIDEO_DIP_DATA_SIZE]; |
345 | ssize_t len; | |
45187ace | 346 | |
5adaea79 DL |
347 | /* see comment above for the reason for this offset */ |
348 | len = hdmi_infoframe_pack(frame, buffer + 1, sizeof(buffer) - 1); | |
349 | if (len < 0) | |
350 | return; | |
351 | ||
352 | /* Insert the 'hole' (see big comment above) at position 3 */ | |
353 | buffer[0] = buffer[1]; | |
354 | buffer[1] = buffer[2]; | |
355 | buffer[2] = buffer[3]; | |
356 | buffer[3] = 0; | |
357 | len++; | |
45187ace | 358 | |
5adaea79 | 359 | intel_hdmi->write_infoframe(encoder, frame->any.type, buffer, len); |
45187ace JB |
360 | } |
361 | ||
687f4d06 | 362 | static void intel_hdmi_set_avi_infoframe(struct drm_encoder *encoder, |
c846b619 | 363 | struct drm_display_mode *adjusted_mode) |
45187ace | 364 | { |
abedc077 | 365 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); |
50f3b016 | 366 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); |
5adaea79 DL |
367 | union hdmi_infoframe frame; |
368 | int ret; | |
45187ace | 369 | |
5adaea79 DL |
370 | ret = drm_hdmi_avi_infoframe_from_display_mode(&frame.avi, |
371 | adjusted_mode); | |
372 | if (ret < 0) { | |
373 | DRM_ERROR("couldn't fill AVI infoframe\n"); | |
374 | return; | |
375 | } | |
c846b619 | 376 | |
abedc077 | 377 | if (intel_hdmi->rgb_quant_range_selectable) { |
50f3b016 | 378 | if (intel_crtc->config.limited_color_range) |
5adaea79 DL |
379 | frame.avi.quantization_range = |
380 | HDMI_QUANTIZATION_RANGE_LIMITED; | |
abedc077 | 381 | else |
5adaea79 DL |
382 | frame.avi.quantization_range = |
383 | HDMI_QUANTIZATION_RANGE_FULL; | |
abedc077 VS |
384 | } |
385 | ||
9198ee5b | 386 | intel_write_infoframe(encoder, &frame); |
b055c8f3 JB |
387 | } |
388 | ||
687f4d06 | 389 | static void intel_hdmi_set_spd_infoframe(struct drm_encoder *encoder) |
c0864cb3 | 390 | { |
5adaea79 DL |
391 | union hdmi_infoframe frame; |
392 | int ret; | |
393 | ||
394 | ret = hdmi_spd_infoframe_init(&frame.spd, "Intel", "Integrated gfx"); | |
395 | if (ret < 0) { | |
396 | DRM_ERROR("couldn't fill SPD infoframe\n"); | |
397 | return; | |
398 | } | |
c0864cb3 | 399 | |
5adaea79 | 400 | frame.spd.sdi = HDMI_SPD_SDI_PC; |
c0864cb3 | 401 | |
9198ee5b | 402 | intel_write_infoframe(encoder, &frame); |
c0864cb3 JB |
403 | } |
404 | ||
c8bb75af LD |
405 | static void |
406 | intel_hdmi_set_hdmi_infoframe(struct drm_encoder *encoder, | |
407 | struct drm_display_mode *adjusted_mode) | |
408 | { | |
409 | union hdmi_infoframe frame; | |
410 | int ret; | |
411 | ||
412 | ret = drm_hdmi_vendor_infoframe_from_display_mode(&frame.vendor.hdmi, | |
413 | adjusted_mode); | |
414 | if (ret < 0) | |
415 | return; | |
416 | ||
417 | intel_write_infoframe(encoder, &frame); | |
418 | } | |
419 | ||
687f4d06 PZ |
420 | static void g4x_set_infoframes(struct drm_encoder *encoder, |
421 | struct drm_display_mode *adjusted_mode) | |
422 | { | |
0c14c7f9 | 423 | struct drm_i915_private *dev_priv = encoder->dev->dev_private; |
69fde0a6 VS |
424 | struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); |
425 | struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi; | |
0c14c7f9 PZ |
426 | u32 reg = VIDEO_DIP_CTL; |
427 | u32 val = I915_READ(reg); | |
822cdc52 | 428 | u32 port = VIDEO_DIP_PORT(intel_dig_port->port); |
0c14c7f9 | 429 | |
afba0188 DV |
430 | assert_hdmi_port_disabled(intel_hdmi); |
431 | ||
0c14c7f9 PZ |
432 | /* If the registers were not initialized yet, they might be zeroes, |
433 | * which means we're selecting the AVI DIP and we're setting its | |
434 | * frequency to once. This seems to really confuse the HW and make | |
435 | * things stop working (the register spec says the AVI always needs to | |
436 | * be sent every VSync). So here we avoid writing to the register more | |
437 | * than we need and also explicitly select the AVI DIP and explicitly | |
438 | * set its frequency to every VSync. Avoiding to write it twice seems to | |
439 | * be enough to solve the problem, but being defensive shouldn't hurt us | |
440 | * either. */ | |
441 | val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; | |
442 | ||
443 | if (!intel_hdmi->has_hdmi_sink) { | |
444 | if (!(val & VIDEO_DIP_ENABLE)) | |
445 | return; | |
446 | val &= ~VIDEO_DIP_ENABLE; | |
447 | I915_WRITE(reg, val); | |
9d9740f0 | 448 | POSTING_READ(reg); |
0c14c7f9 PZ |
449 | return; |
450 | } | |
451 | ||
72b78c9d PZ |
452 | if (port != (val & VIDEO_DIP_PORT_MASK)) { |
453 | if (val & VIDEO_DIP_ENABLE) { | |
454 | val &= ~VIDEO_DIP_ENABLE; | |
455 | I915_WRITE(reg, val); | |
9d9740f0 | 456 | POSTING_READ(reg); |
72b78c9d PZ |
457 | } |
458 | val &= ~VIDEO_DIP_PORT_MASK; | |
459 | val |= port; | |
460 | } | |
461 | ||
822974ae | 462 | val |= VIDEO_DIP_ENABLE; |
0dd87d20 | 463 | val &= ~VIDEO_DIP_ENABLE_VENDOR; |
822974ae | 464 | |
f278d972 | 465 | I915_WRITE(reg, val); |
9d9740f0 | 466 | POSTING_READ(reg); |
f278d972 | 467 | |
687f4d06 PZ |
468 | intel_hdmi_set_avi_infoframe(encoder, adjusted_mode); |
469 | intel_hdmi_set_spd_infoframe(encoder); | |
c8bb75af | 470 | intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode); |
687f4d06 PZ |
471 | } |
472 | ||
473 | static void ibx_set_infoframes(struct drm_encoder *encoder, | |
474 | struct drm_display_mode *adjusted_mode) | |
475 | { | |
0c14c7f9 PZ |
476 | struct drm_i915_private *dev_priv = encoder->dev->dev_private; |
477 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); | |
69fde0a6 VS |
478 | struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); |
479 | struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi; | |
0c14c7f9 PZ |
480 | u32 reg = TVIDEO_DIP_CTL(intel_crtc->pipe); |
481 | u32 val = I915_READ(reg); | |
822cdc52 | 482 | u32 port = VIDEO_DIP_PORT(intel_dig_port->port); |
0c14c7f9 | 483 | |
afba0188 DV |
484 | assert_hdmi_port_disabled(intel_hdmi); |
485 | ||
0c14c7f9 PZ |
486 | /* See the big comment in g4x_set_infoframes() */ |
487 | val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; | |
488 | ||
489 | if (!intel_hdmi->has_hdmi_sink) { | |
490 | if (!(val & VIDEO_DIP_ENABLE)) | |
491 | return; | |
492 | val &= ~VIDEO_DIP_ENABLE; | |
493 | I915_WRITE(reg, val); | |
9d9740f0 | 494 | POSTING_READ(reg); |
0c14c7f9 PZ |
495 | return; |
496 | } | |
497 | ||
72b78c9d PZ |
498 | if (port != (val & VIDEO_DIP_PORT_MASK)) { |
499 | if (val & VIDEO_DIP_ENABLE) { | |
500 | val &= ~VIDEO_DIP_ENABLE; | |
501 | I915_WRITE(reg, val); | |
9d9740f0 | 502 | POSTING_READ(reg); |
72b78c9d PZ |
503 | } |
504 | val &= ~VIDEO_DIP_PORT_MASK; | |
505 | val |= port; | |
506 | } | |
507 | ||
822974ae | 508 | val |= VIDEO_DIP_ENABLE; |
0dd87d20 PZ |
509 | val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | |
510 | VIDEO_DIP_ENABLE_GCP); | |
822974ae | 511 | |
f278d972 | 512 | I915_WRITE(reg, val); |
9d9740f0 | 513 | POSTING_READ(reg); |
f278d972 | 514 | |
687f4d06 PZ |
515 | intel_hdmi_set_avi_infoframe(encoder, adjusted_mode); |
516 | intel_hdmi_set_spd_infoframe(encoder); | |
c8bb75af | 517 | intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode); |
687f4d06 PZ |
518 | } |
519 | ||
520 | static void cpt_set_infoframes(struct drm_encoder *encoder, | |
521 | struct drm_display_mode *adjusted_mode) | |
522 | { | |
0c14c7f9 PZ |
523 | struct drm_i915_private *dev_priv = encoder->dev->dev_private; |
524 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); | |
525 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); | |
526 | u32 reg = TVIDEO_DIP_CTL(intel_crtc->pipe); | |
527 | u32 val = I915_READ(reg); | |
528 | ||
afba0188 DV |
529 | assert_hdmi_port_disabled(intel_hdmi); |
530 | ||
0c14c7f9 PZ |
531 | /* See the big comment in g4x_set_infoframes() */ |
532 | val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; | |
533 | ||
534 | if (!intel_hdmi->has_hdmi_sink) { | |
535 | if (!(val & VIDEO_DIP_ENABLE)) | |
536 | return; | |
537 | val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI); | |
538 | I915_WRITE(reg, val); | |
9d9740f0 | 539 | POSTING_READ(reg); |
0c14c7f9 PZ |
540 | return; |
541 | } | |
542 | ||
822974ae PZ |
543 | /* Set both together, unset both together: see the spec. */ |
544 | val |= VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI; | |
0dd87d20 PZ |
545 | val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | |
546 | VIDEO_DIP_ENABLE_GCP); | |
822974ae PZ |
547 | |
548 | I915_WRITE(reg, val); | |
9d9740f0 | 549 | POSTING_READ(reg); |
822974ae | 550 | |
687f4d06 PZ |
551 | intel_hdmi_set_avi_infoframe(encoder, adjusted_mode); |
552 | intel_hdmi_set_spd_infoframe(encoder); | |
c8bb75af | 553 | intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode); |
687f4d06 PZ |
554 | } |
555 | ||
556 | static void vlv_set_infoframes(struct drm_encoder *encoder, | |
557 | struct drm_display_mode *adjusted_mode) | |
558 | { | |
0c14c7f9 | 559 | struct drm_i915_private *dev_priv = encoder->dev->dev_private; |
6a2b8021 | 560 | struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); |
0c14c7f9 PZ |
561 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); |
562 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); | |
563 | u32 reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe); | |
564 | u32 val = I915_READ(reg); | |
6a2b8021 | 565 | u32 port = VIDEO_DIP_PORT(intel_dig_port->port); |
0c14c7f9 | 566 | |
afba0188 DV |
567 | assert_hdmi_port_disabled(intel_hdmi); |
568 | ||
0c14c7f9 PZ |
569 | /* See the big comment in g4x_set_infoframes() */ |
570 | val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; | |
571 | ||
572 | if (!intel_hdmi->has_hdmi_sink) { | |
573 | if (!(val & VIDEO_DIP_ENABLE)) | |
574 | return; | |
575 | val &= ~VIDEO_DIP_ENABLE; | |
576 | I915_WRITE(reg, val); | |
9d9740f0 | 577 | POSTING_READ(reg); |
0c14c7f9 PZ |
578 | return; |
579 | } | |
580 | ||
6a2b8021 JB |
581 | if (port != (val & VIDEO_DIP_PORT_MASK)) { |
582 | if (val & VIDEO_DIP_ENABLE) { | |
583 | val &= ~VIDEO_DIP_ENABLE; | |
584 | I915_WRITE(reg, val); | |
585 | POSTING_READ(reg); | |
586 | } | |
587 | val &= ~VIDEO_DIP_PORT_MASK; | |
588 | val |= port; | |
589 | } | |
590 | ||
822974ae | 591 | val |= VIDEO_DIP_ENABLE; |
4d47dfb8 JB |
592 | val &= ~(VIDEO_DIP_ENABLE_AVI | VIDEO_DIP_ENABLE_VENDOR | |
593 | VIDEO_DIP_ENABLE_GAMUT | VIDEO_DIP_ENABLE_GCP); | |
822974ae PZ |
594 | |
595 | I915_WRITE(reg, val); | |
9d9740f0 | 596 | POSTING_READ(reg); |
822974ae | 597 | |
687f4d06 PZ |
598 | intel_hdmi_set_avi_infoframe(encoder, adjusted_mode); |
599 | intel_hdmi_set_spd_infoframe(encoder); | |
c8bb75af | 600 | intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode); |
687f4d06 PZ |
601 | } |
602 | ||
603 | static void hsw_set_infoframes(struct drm_encoder *encoder, | |
604 | struct drm_display_mode *adjusted_mode) | |
605 | { | |
0c14c7f9 PZ |
606 | struct drm_i915_private *dev_priv = encoder->dev->dev_private; |
607 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); | |
608 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); | |
3b117c8f | 609 | u32 reg = HSW_TVIDEO_DIP_CTL(intel_crtc->config.cpu_transcoder); |
0dd87d20 | 610 | u32 val = I915_READ(reg); |
0c14c7f9 | 611 | |
afba0188 DV |
612 | assert_hdmi_port_disabled(intel_hdmi); |
613 | ||
0c14c7f9 PZ |
614 | if (!intel_hdmi->has_hdmi_sink) { |
615 | I915_WRITE(reg, 0); | |
9d9740f0 | 616 | POSTING_READ(reg); |
0c14c7f9 PZ |
617 | return; |
618 | } | |
619 | ||
0dd87d20 PZ |
620 | val &= ~(VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_GCP_HSW | |
621 | VIDEO_DIP_ENABLE_VS_HSW | VIDEO_DIP_ENABLE_GMP_HSW); | |
622 | ||
623 | I915_WRITE(reg, val); | |
9d9740f0 | 624 | POSTING_READ(reg); |
0dd87d20 | 625 | |
687f4d06 PZ |
626 | intel_hdmi_set_avi_infoframe(encoder, adjusted_mode); |
627 | intel_hdmi_set_spd_infoframe(encoder); | |
c8bb75af | 628 | intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode); |
687f4d06 PZ |
629 | } |
630 | ||
c59423a3 | 631 | static void intel_hdmi_mode_set(struct intel_encoder *encoder) |
7d57382e | 632 | { |
c59423a3 | 633 | struct drm_device *dev = encoder->base.dev; |
7d57382e | 634 | struct drm_i915_private *dev_priv = dev->dev_private; |
c59423a3 DV |
635 | struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); |
636 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); | |
637 | struct drm_display_mode *adjusted_mode = &crtc->config.adjusted_mode; | |
b242b7f7 | 638 | u32 hdmi_val; |
7d57382e | 639 | |
b242b7f7 | 640 | hdmi_val = SDVO_ENCODING_HDMI; |
2af2c490 | 641 | if (!HAS_PCH_SPLIT(dev)) |
b242b7f7 | 642 | hdmi_val |= intel_hdmi->color_range; |
b599c0bc | 643 | if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) |
b242b7f7 | 644 | hdmi_val |= SDVO_VSYNC_ACTIVE_HIGH; |
b599c0bc | 645 | if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) |
b242b7f7 | 646 | hdmi_val |= SDVO_HSYNC_ACTIVE_HIGH; |
7d57382e | 647 | |
c59423a3 | 648 | if (crtc->config.pipe_bpp > 24) |
4f3a8bc7 | 649 | hdmi_val |= HDMI_COLOR_FORMAT_12bpc; |
020f6704 | 650 | else |
4f3a8bc7 | 651 | hdmi_val |= SDVO_COLOR_FORMAT_8bpc; |
020f6704 | 652 | |
759c85e7 JB |
653 | if (intel_hdmi->has_hdmi_sink && |
654 | (HAS_PCH_CPT(dev) || IS_VALLEYVIEW(dev))) | |
dc0fa718 | 655 | hdmi_val |= HDMI_MODE_SELECT_HDMI; |
2e3d6006 | 656 | |
3c17fe4b | 657 | if (intel_hdmi->has_audio) { |
e0dac65e | 658 | DRM_DEBUG_DRIVER("Enabling HDMI audio on pipe %c\n", |
c59423a3 | 659 | pipe_name(crtc->pipe)); |
b242b7f7 | 660 | hdmi_val |= SDVO_AUDIO_ENABLE; |
dc0fa718 | 661 | hdmi_val |= HDMI_MODE_SELECT_HDMI; |
c59423a3 | 662 | intel_write_eld(&encoder->base, adjusted_mode); |
3c17fe4b | 663 | } |
7d57382e | 664 | |
75770564 | 665 | if (HAS_PCH_CPT(dev)) |
c59423a3 | 666 | hdmi_val |= SDVO_PIPE_SEL_CPT(crtc->pipe); |
dc0fa718 | 667 | else |
c59423a3 | 668 | hdmi_val |= SDVO_PIPE_SEL(crtc->pipe); |
7d57382e | 669 | |
b242b7f7 PZ |
670 | I915_WRITE(intel_hdmi->hdmi_reg, hdmi_val); |
671 | POSTING_READ(intel_hdmi->hdmi_reg); | |
7d57382e EA |
672 | } |
673 | ||
85234cdc DV |
674 | static bool intel_hdmi_get_hw_state(struct intel_encoder *encoder, |
675 | enum pipe *pipe) | |
7d57382e | 676 | { |
85234cdc | 677 | struct drm_device *dev = encoder->base.dev; |
7d57382e | 678 | struct drm_i915_private *dev_priv = dev->dev_private; |
85234cdc | 679 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); |
6d129bea | 680 | enum intel_display_power_domain power_domain; |
85234cdc DV |
681 | u32 tmp; |
682 | ||
6d129bea ID |
683 | power_domain = intel_display_port_power_domain(encoder); |
684 | if (!intel_display_power_enabled(dev_priv, power_domain)) | |
685 | return false; | |
686 | ||
b242b7f7 | 687 | tmp = I915_READ(intel_hdmi->hdmi_reg); |
85234cdc DV |
688 | |
689 | if (!(tmp & SDVO_ENABLE)) | |
690 | return false; | |
691 | ||
692 | if (HAS_PCH_CPT(dev)) | |
693 | *pipe = PORT_TO_PIPE_CPT(tmp); | |
694 | else | |
695 | *pipe = PORT_TO_PIPE(tmp); | |
696 | ||
697 | return true; | |
698 | } | |
699 | ||
045ac3b5 JB |
700 | static void intel_hdmi_get_config(struct intel_encoder *encoder, |
701 | struct intel_crtc_config *pipe_config) | |
702 | { | |
703 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); | |
704 | struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; | |
705 | u32 tmp, flags = 0; | |
18442d08 | 706 | int dotclock; |
045ac3b5 JB |
707 | |
708 | tmp = I915_READ(intel_hdmi->hdmi_reg); | |
709 | ||
710 | if (tmp & SDVO_HSYNC_ACTIVE_HIGH) | |
711 | flags |= DRM_MODE_FLAG_PHSYNC; | |
712 | else | |
713 | flags |= DRM_MODE_FLAG_NHSYNC; | |
714 | ||
715 | if (tmp & SDVO_VSYNC_ACTIVE_HIGH) | |
716 | flags |= DRM_MODE_FLAG_PVSYNC; | |
717 | else | |
718 | flags |= DRM_MODE_FLAG_NVSYNC; | |
719 | ||
720 | pipe_config->adjusted_mode.flags |= flags; | |
18442d08 VS |
721 | |
722 | if ((tmp & SDVO_COLOR_FORMAT_MASK) == HDMI_COLOR_FORMAT_12bpc) | |
723 | dotclock = pipe_config->port_clock * 2 / 3; | |
724 | else | |
725 | dotclock = pipe_config->port_clock; | |
726 | ||
727 | if (HAS_PCH_SPLIT(dev_priv->dev)) | |
728 | ironlake_check_encoder_dotclock(pipe_config, dotclock); | |
729 | ||
241bfc38 | 730 | pipe_config->adjusted_mode.crtc_clock = dotclock; |
045ac3b5 JB |
731 | } |
732 | ||
5ab432ef | 733 | static void intel_enable_hdmi(struct intel_encoder *encoder) |
7d57382e | 734 | { |
5ab432ef | 735 | struct drm_device *dev = encoder->base.dev; |
7d57382e | 736 | struct drm_i915_private *dev_priv = dev->dev_private; |
dc0fa718 | 737 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); |
5ab432ef | 738 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); |
7d57382e | 739 | u32 temp; |
2deed761 WF |
740 | u32 enable_bits = SDVO_ENABLE; |
741 | ||
742 | if (intel_hdmi->has_audio) | |
743 | enable_bits |= SDVO_AUDIO_ENABLE; | |
7d57382e | 744 | |
b242b7f7 | 745 | temp = I915_READ(intel_hdmi->hdmi_reg); |
d8a2d0e0 | 746 | |
7a87c289 | 747 | /* HW workaround for IBX, we need to move the port to transcoder A |
dc0fa718 PZ |
748 | * before disabling it, so restore the transcoder select bit here. */ |
749 | if (HAS_PCH_IBX(dev)) | |
750 | enable_bits |= SDVO_PIPE_SEL(intel_crtc->pipe); | |
7a87c289 | 751 | |
d8a2d0e0 ZW |
752 | /* HW workaround, need to toggle enable bit off and on for 12bpc, but |
753 | * we do this anyway which shows more stable in testing. | |
754 | */ | |
c619eed4 | 755 | if (HAS_PCH_SPLIT(dev)) { |
b242b7f7 PZ |
756 | I915_WRITE(intel_hdmi->hdmi_reg, temp & ~SDVO_ENABLE); |
757 | POSTING_READ(intel_hdmi->hdmi_reg); | |
d8a2d0e0 ZW |
758 | } |
759 | ||
5ab432ef DV |
760 | temp |= enable_bits; |
761 | ||
b242b7f7 PZ |
762 | I915_WRITE(intel_hdmi->hdmi_reg, temp); |
763 | POSTING_READ(intel_hdmi->hdmi_reg); | |
5ab432ef DV |
764 | |
765 | /* HW workaround, need to write this twice for issue that may result | |
766 | * in first write getting masked. | |
767 | */ | |
768 | if (HAS_PCH_SPLIT(dev)) { | |
b242b7f7 PZ |
769 | I915_WRITE(intel_hdmi->hdmi_reg, temp); |
770 | POSTING_READ(intel_hdmi->hdmi_reg); | |
7d57382e | 771 | } |
b76cf76b | 772 | } |
89b667f8 | 773 | |
b76cf76b JN |
774 | static void vlv_enable_hdmi(struct intel_encoder *encoder) |
775 | { | |
5ab432ef DV |
776 | } |
777 | ||
778 | static void intel_disable_hdmi(struct intel_encoder *encoder) | |
779 | { | |
780 | struct drm_device *dev = encoder->base.dev; | |
781 | struct drm_i915_private *dev_priv = dev->dev_private; | |
782 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); | |
783 | u32 temp; | |
3cce574f | 784 | u32 enable_bits = SDVO_ENABLE | SDVO_AUDIO_ENABLE; |
5ab432ef | 785 | |
b242b7f7 | 786 | temp = I915_READ(intel_hdmi->hdmi_reg); |
5ab432ef DV |
787 | |
788 | /* HW workaround for IBX, we need to move the port to transcoder A | |
789 | * before disabling it. */ | |
790 | if (HAS_PCH_IBX(dev)) { | |
791 | struct drm_crtc *crtc = encoder->base.crtc; | |
792 | int pipe = crtc ? to_intel_crtc(crtc)->pipe : -1; | |
793 | ||
794 | if (temp & SDVO_PIPE_B_SELECT) { | |
795 | temp &= ~SDVO_PIPE_B_SELECT; | |
b242b7f7 PZ |
796 | I915_WRITE(intel_hdmi->hdmi_reg, temp); |
797 | POSTING_READ(intel_hdmi->hdmi_reg); | |
5ab432ef DV |
798 | |
799 | /* Again we need to write this twice. */ | |
b242b7f7 PZ |
800 | I915_WRITE(intel_hdmi->hdmi_reg, temp); |
801 | POSTING_READ(intel_hdmi->hdmi_reg); | |
5ab432ef DV |
802 | |
803 | /* Transcoder selection bits only update | |
804 | * effectively on vblank. */ | |
805 | if (crtc) | |
806 | intel_wait_for_vblank(dev, pipe); | |
807 | else | |
808 | msleep(50); | |
809 | } | |
7d57382e | 810 | } |
d8a2d0e0 | 811 | |
5ab432ef DV |
812 | /* HW workaround, need to toggle enable bit off and on for 12bpc, but |
813 | * we do this anyway which shows more stable in testing. | |
814 | */ | |
815 | if (HAS_PCH_SPLIT(dev)) { | |
b242b7f7 PZ |
816 | I915_WRITE(intel_hdmi->hdmi_reg, temp & ~SDVO_ENABLE); |
817 | POSTING_READ(intel_hdmi->hdmi_reg); | |
5ab432ef DV |
818 | } |
819 | ||
820 | temp &= ~enable_bits; | |
d8a2d0e0 | 821 | |
b242b7f7 PZ |
822 | I915_WRITE(intel_hdmi->hdmi_reg, temp); |
823 | POSTING_READ(intel_hdmi->hdmi_reg); | |
d8a2d0e0 ZW |
824 | |
825 | /* HW workaround, need to write this twice for issue that may result | |
826 | * in first write getting masked. | |
827 | */ | |
c619eed4 | 828 | if (HAS_PCH_SPLIT(dev)) { |
b242b7f7 PZ |
829 | I915_WRITE(intel_hdmi->hdmi_reg, temp); |
830 | POSTING_READ(intel_hdmi->hdmi_reg); | |
d8a2d0e0 | 831 | } |
7d57382e EA |
832 | } |
833 | ||
40478455 | 834 | static int hdmi_portclock_limit(struct intel_hdmi *hdmi, bool respect_dvi_limit) |
7d148ef5 DV |
835 | { |
836 | struct drm_device *dev = intel_hdmi_to_dev(hdmi); | |
837 | ||
40478455 | 838 | if ((respect_dvi_limit && !hdmi->has_hdmi_sink) || IS_G4X(dev)) |
7d148ef5 | 839 | return 165000; |
e3c33578 | 840 | else if (IS_HASWELL(dev) || INTEL_INFO(dev)->gen >= 8) |
7d148ef5 DV |
841 | return 300000; |
842 | else | |
843 | return 225000; | |
844 | } | |
845 | ||
c19de8eb DL |
846 | static enum drm_mode_status |
847 | intel_hdmi_mode_valid(struct drm_connector *connector, | |
848 | struct drm_display_mode *mode) | |
7d57382e | 849 | { |
40478455 VS |
850 | if (mode->clock > hdmi_portclock_limit(intel_attached_hdmi(connector), |
851 | true)) | |
7d57382e EA |
852 | return MODE_CLOCK_HIGH; |
853 | if (mode->clock < 20000) | |
5cbba41d | 854 | return MODE_CLOCK_LOW; |
7d57382e EA |
855 | |
856 | if (mode->flags & DRM_MODE_FLAG_DBLSCAN) | |
857 | return MODE_NO_DBLESCAN; | |
858 | ||
859 | return MODE_OK; | |
860 | } | |
861 | ||
71800632 VS |
862 | static bool hdmi_12bpc_possible(struct intel_crtc *crtc) |
863 | { | |
864 | struct drm_device *dev = crtc->base.dev; | |
865 | struct intel_encoder *encoder; | |
866 | int count = 0, count_hdmi = 0; | |
867 | ||
868 | if (!HAS_PCH_SPLIT(dev)) | |
869 | return false; | |
870 | ||
871 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) { | |
872 | if (encoder->new_crtc != crtc) | |
873 | continue; | |
874 | ||
875 | count_hdmi += encoder->type == INTEL_OUTPUT_HDMI; | |
876 | count++; | |
877 | } | |
878 | ||
879 | /* | |
880 | * HDMI 12bpc affects the clocks, so it's only possible | |
881 | * when not cloning with other encoder types. | |
882 | */ | |
883 | return count_hdmi > 0 && count_hdmi == count; | |
884 | } | |
885 | ||
5bfe2ac0 DV |
886 | bool intel_hdmi_compute_config(struct intel_encoder *encoder, |
887 | struct intel_crtc_config *pipe_config) | |
7d57382e | 888 | { |
5bfe2ac0 DV |
889 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); |
890 | struct drm_device *dev = encoder->base.dev; | |
891 | struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode; | |
241bfc38 | 892 | int clock_12bpc = pipe_config->adjusted_mode.crtc_clock * 3 / 2; |
40478455 | 893 | int portclock_limit = hdmi_portclock_limit(intel_hdmi, false); |
e29c22c0 | 894 | int desired_bpp; |
3685a8f3 | 895 | |
55bc60db VS |
896 | if (intel_hdmi->color_range_auto) { |
897 | /* See CEA-861-E - 5.1 Default Encoding Parameters */ | |
898 | if (intel_hdmi->has_hdmi_sink && | |
18316c8c | 899 | drm_match_cea_mode(adjusted_mode) > 1) |
4f3a8bc7 | 900 | intel_hdmi->color_range = HDMI_COLOR_RANGE_16_235; |
55bc60db VS |
901 | else |
902 | intel_hdmi->color_range = 0; | |
903 | } | |
904 | ||
3685a8f3 | 905 | if (intel_hdmi->color_range) |
50f3b016 | 906 | pipe_config->limited_color_range = true; |
3685a8f3 | 907 | |
5bfe2ac0 DV |
908 | if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev)) |
909 | pipe_config->has_pch_encoder = true; | |
910 | ||
4e53c2e0 DV |
911 | /* |
912 | * HDMI is either 12 or 8, so if the display lets 10bpc sneak | |
913 | * through, clamp it down. Note that g4x/vlv don't support 12bpc hdmi | |
325b9d04 DV |
914 | * outputs. We also need to check that the higher clock still fits |
915 | * within limits. | |
4e53c2e0 | 916 | */ |
6375b768 | 917 | if (pipe_config->pipe_bpp > 8*3 && intel_hdmi->has_hdmi_sink && |
71800632 VS |
918 | clock_12bpc <= portclock_limit && |
919 | hdmi_12bpc_possible(encoder->new_crtc)) { | |
e29c22c0 DV |
920 | DRM_DEBUG_KMS("picking bpc to 12 for HDMI output\n"); |
921 | desired_bpp = 12*3; | |
325b9d04 DV |
922 | |
923 | /* Need to adjust the port link by 1.5x for 12bpc. */ | |
ff9a6750 | 924 | pipe_config->port_clock = clock_12bpc; |
4e53c2e0 | 925 | } else { |
e29c22c0 DV |
926 | DRM_DEBUG_KMS("picking bpc to 8 for HDMI output\n"); |
927 | desired_bpp = 8*3; | |
928 | } | |
929 | ||
930 | if (!pipe_config->bw_constrained) { | |
931 | DRM_DEBUG_KMS("forcing pipe bpc to %i for HDMI\n", desired_bpp); | |
932 | pipe_config->pipe_bpp = desired_bpp; | |
4e53c2e0 DV |
933 | } |
934 | ||
241bfc38 | 935 | if (adjusted_mode->crtc_clock > portclock_limit) { |
325b9d04 DV |
936 | DRM_DEBUG_KMS("too high HDMI clock, rejecting mode\n"); |
937 | return false; | |
938 | } | |
939 | ||
7d57382e EA |
940 | return true; |
941 | } | |
942 | ||
aa93d632 | 943 | static enum drm_connector_status |
930a9e28 | 944 | intel_hdmi_detect(struct drm_connector *connector, bool force) |
9dff6af8 | 945 | { |
b0ea7d37 | 946 | struct drm_device *dev = connector->dev; |
df0e9248 | 947 | struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); |
d63885da PZ |
948 | struct intel_digital_port *intel_dig_port = |
949 | hdmi_to_dig_port(intel_hdmi); | |
950 | struct intel_encoder *intel_encoder = &intel_dig_port->base; | |
b0ea7d37 | 951 | struct drm_i915_private *dev_priv = dev->dev_private; |
f899fc64 | 952 | struct edid *edid; |
671dedd2 | 953 | enum intel_display_power_domain power_domain; |
aa93d632 | 954 | enum drm_connector_status status = connector_status_disconnected; |
9dff6af8 | 955 | |
164c8598 CW |
956 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", |
957 | connector->base.id, drm_get_connector_name(connector)); | |
958 | ||
671dedd2 ID |
959 | power_domain = intel_display_port_power_domain(intel_encoder); |
960 | intel_display_power_get(dev_priv, power_domain); | |
961 | ||
ea5b213a | 962 | intel_hdmi->has_hdmi_sink = false; |
2e3d6006 | 963 | intel_hdmi->has_audio = false; |
abedc077 | 964 | intel_hdmi->rgb_quant_range_selectable = false; |
f899fc64 | 965 | edid = drm_get_edid(connector, |
3bd7d909 DK |
966 | intel_gmbus_get_adapter(dev_priv, |
967 | intel_hdmi->ddc_bus)); | |
2ded9e27 | 968 | |
aa93d632 | 969 | if (edid) { |
be9f1c4f | 970 | if (edid->input & DRM_EDID_INPUT_DIGITAL) { |
aa93d632 | 971 | status = connector_status_connected; |
b1d7e4b4 WF |
972 | if (intel_hdmi->force_audio != HDMI_AUDIO_OFF_DVI) |
973 | intel_hdmi->has_hdmi_sink = | |
974 | drm_detect_hdmi_monitor(edid); | |
2e3d6006 | 975 | intel_hdmi->has_audio = drm_detect_monitor_audio(edid); |
abedc077 VS |
976 | intel_hdmi->rgb_quant_range_selectable = |
977 | drm_rgb_quant_range_selectable(edid); | |
aa93d632 | 978 | } |
aa93d632 | 979 | kfree(edid); |
9dff6af8 | 980 | } |
30ad48b7 | 981 | |
55b7d6e8 | 982 | if (status == connector_status_connected) { |
b1d7e4b4 WF |
983 | if (intel_hdmi->force_audio != HDMI_AUDIO_AUTO) |
984 | intel_hdmi->has_audio = | |
985 | (intel_hdmi->force_audio == HDMI_AUDIO_ON); | |
d63885da | 986 | intel_encoder->type = INTEL_OUTPUT_HDMI; |
55b7d6e8 CW |
987 | } |
988 | ||
671dedd2 ID |
989 | intel_display_power_put(dev_priv, power_domain); |
990 | ||
2ded9e27 | 991 | return status; |
7d57382e EA |
992 | } |
993 | ||
994 | static int intel_hdmi_get_modes(struct drm_connector *connector) | |
995 | { | |
671dedd2 ID |
996 | struct intel_encoder *intel_encoder = intel_attached_encoder(connector); |
997 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&intel_encoder->base); | |
f899fc64 | 998 | struct drm_i915_private *dev_priv = connector->dev->dev_private; |
671dedd2 ID |
999 | enum intel_display_power_domain power_domain; |
1000 | int ret; | |
7d57382e EA |
1001 | |
1002 | /* We should parse the EDID data and find out if it's an HDMI sink so | |
1003 | * we can send audio to it. | |
1004 | */ | |
1005 | ||
671dedd2 ID |
1006 | power_domain = intel_display_port_power_domain(intel_encoder); |
1007 | intel_display_power_get(dev_priv, power_domain); | |
1008 | ||
1009 | ret = intel_ddc_get_modes(connector, | |
3bd7d909 DK |
1010 | intel_gmbus_get_adapter(dev_priv, |
1011 | intel_hdmi->ddc_bus)); | |
671dedd2 ID |
1012 | |
1013 | intel_display_power_put(dev_priv, power_domain); | |
1014 | ||
1015 | return ret; | |
7d57382e EA |
1016 | } |
1017 | ||
1aad7ac0 CW |
1018 | static bool |
1019 | intel_hdmi_detect_audio(struct drm_connector *connector) | |
1020 | { | |
671dedd2 ID |
1021 | struct intel_encoder *intel_encoder = intel_attached_encoder(connector); |
1022 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&intel_encoder->base); | |
1aad7ac0 | 1023 | struct drm_i915_private *dev_priv = connector->dev->dev_private; |
671dedd2 | 1024 | enum intel_display_power_domain power_domain; |
1aad7ac0 CW |
1025 | struct edid *edid; |
1026 | bool has_audio = false; | |
1027 | ||
671dedd2 ID |
1028 | power_domain = intel_display_port_power_domain(intel_encoder); |
1029 | intel_display_power_get(dev_priv, power_domain); | |
1030 | ||
1aad7ac0 | 1031 | edid = drm_get_edid(connector, |
3bd7d909 DK |
1032 | intel_gmbus_get_adapter(dev_priv, |
1033 | intel_hdmi->ddc_bus)); | |
1aad7ac0 CW |
1034 | if (edid) { |
1035 | if (edid->input & DRM_EDID_INPUT_DIGITAL) | |
1036 | has_audio = drm_detect_monitor_audio(edid); | |
1aad7ac0 CW |
1037 | kfree(edid); |
1038 | } | |
1039 | ||
671dedd2 ID |
1040 | intel_display_power_put(dev_priv, power_domain); |
1041 | ||
1aad7ac0 CW |
1042 | return has_audio; |
1043 | } | |
1044 | ||
55b7d6e8 CW |
1045 | static int |
1046 | intel_hdmi_set_property(struct drm_connector *connector, | |
ed517fbb PZ |
1047 | struct drm_property *property, |
1048 | uint64_t val) | |
55b7d6e8 CW |
1049 | { |
1050 | struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); | |
da63a9f2 PZ |
1051 | struct intel_digital_port *intel_dig_port = |
1052 | hdmi_to_dig_port(intel_hdmi); | |
e953fd7b | 1053 | struct drm_i915_private *dev_priv = connector->dev->dev_private; |
55b7d6e8 CW |
1054 | int ret; |
1055 | ||
662595df | 1056 | ret = drm_object_property_set_value(&connector->base, property, val); |
55b7d6e8 CW |
1057 | if (ret) |
1058 | return ret; | |
1059 | ||
3f43c48d | 1060 | if (property == dev_priv->force_audio_property) { |
b1d7e4b4 | 1061 | enum hdmi_force_audio i = val; |
1aad7ac0 CW |
1062 | bool has_audio; |
1063 | ||
1064 | if (i == intel_hdmi->force_audio) | |
55b7d6e8 CW |
1065 | return 0; |
1066 | ||
1aad7ac0 | 1067 | intel_hdmi->force_audio = i; |
55b7d6e8 | 1068 | |
b1d7e4b4 | 1069 | if (i == HDMI_AUDIO_AUTO) |
1aad7ac0 CW |
1070 | has_audio = intel_hdmi_detect_audio(connector); |
1071 | else | |
b1d7e4b4 | 1072 | has_audio = (i == HDMI_AUDIO_ON); |
1aad7ac0 | 1073 | |
b1d7e4b4 WF |
1074 | if (i == HDMI_AUDIO_OFF_DVI) |
1075 | intel_hdmi->has_hdmi_sink = 0; | |
55b7d6e8 | 1076 | |
1aad7ac0 | 1077 | intel_hdmi->has_audio = has_audio; |
55b7d6e8 CW |
1078 | goto done; |
1079 | } | |
1080 | ||
e953fd7b | 1081 | if (property == dev_priv->broadcast_rgb_property) { |
ae4edb80 DV |
1082 | bool old_auto = intel_hdmi->color_range_auto; |
1083 | uint32_t old_range = intel_hdmi->color_range; | |
1084 | ||
55bc60db VS |
1085 | switch (val) { |
1086 | case INTEL_BROADCAST_RGB_AUTO: | |
1087 | intel_hdmi->color_range_auto = true; | |
1088 | break; | |
1089 | case INTEL_BROADCAST_RGB_FULL: | |
1090 | intel_hdmi->color_range_auto = false; | |
1091 | intel_hdmi->color_range = 0; | |
1092 | break; | |
1093 | case INTEL_BROADCAST_RGB_LIMITED: | |
1094 | intel_hdmi->color_range_auto = false; | |
4f3a8bc7 | 1095 | intel_hdmi->color_range = HDMI_COLOR_RANGE_16_235; |
55bc60db VS |
1096 | break; |
1097 | default: | |
1098 | return -EINVAL; | |
1099 | } | |
ae4edb80 DV |
1100 | |
1101 | if (old_auto == intel_hdmi->color_range_auto && | |
1102 | old_range == intel_hdmi->color_range) | |
1103 | return 0; | |
1104 | ||
e953fd7b CW |
1105 | goto done; |
1106 | } | |
1107 | ||
55b7d6e8 CW |
1108 | return -EINVAL; |
1109 | ||
1110 | done: | |
c0c36b94 CW |
1111 | if (intel_dig_port->base.base.crtc) |
1112 | intel_crtc_restore_mode(intel_dig_port->base.base.crtc); | |
55b7d6e8 CW |
1113 | |
1114 | return 0; | |
1115 | } | |
1116 | ||
13732ba7 JB |
1117 | static void intel_hdmi_pre_enable(struct intel_encoder *encoder) |
1118 | { | |
1119 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); | |
1120 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); | |
1121 | struct drm_display_mode *adjusted_mode = | |
1122 | &intel_crtc->config.adjusted_mode; | |
1123 | ||
1124 | intel_hdmi->set_infoframes(&encoder->base, adjusted_mode); | |
1125 | } | |
1126 | ||
9514ac6e | 1127 | static void vlv_hdmi_pre_enable(struct intel_encoder *encoder) |
89b667f8 JB |
1128 | { |
1129 | struct intel_digital_port *dport = enc_to_dig_port(&encoder->base); | |
13732ba7 | 1130 | struct intel_hdmi *intel_hdmi = &dport->hdmi; |
89b667f8 JB |
1131 | struct drm_device *dev = encoder->base.dev; |
1132 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1133 | struct intel_crtc *intel_crtc = | |
1134 | to_intel_crtc(encoder->base.crtc); | |
13732ba7 JB |
1135 | struct drm_display_mode *adjusted_mode = |
1136 | &intel_crtc->config.adjusted_mode; | |
e4607fcf | 1137 | enum dpio_channel port = vlv_dport_to_channel(dport); |
89b667f8 JB |
1138 | int pipe = intel_crtc->pipe; |
1139 | u32 val; | |
1140 | ||
1141 | if (!IS_VALLEYVIEW(dev)) | |
1142 | return; | |
1143 | ||
89b667f8 | 1144 | /* Enable clock channels for this port */ |
0980a60f | 1145 | mutex_lock(&dev_priv->dpio_lock); |
ab3c759a | 1146 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port)); |
89b667f8 JB |
1147 | val = 0; |
1148 | if (pipe) | |
1149 | val |= (1<<21); | |
1150 | else | |
1151 | val &= ~(1<<21); | |
1152 | val |= 0x001000c4; | |
ab3c759a | 1153 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val); |
89b667f8 JB |
1154 | |
1155 | /* HDMI 1.0V-2dB */ | |
ab3c759a CML |
1156 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0); |
1157 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), 0x2b245f5f); | |
1158 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port), 0x5578b83a); | |
1159 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0c782040); | |
1160 | vlv_dpio_write(dev_priv, pipe, VLV_TX3_DW4(port), 0x2b247878); | |
1161 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000); | |
1162 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), 0x00002000); | |
1163 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), DPIO_TX_OCALINIT_EN); | |
89b667f8 JB |
1164 | |
1165 | /* Program lane clock */ | |
ab3c759a CML |
1166 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018); |
1167 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888); | |
0980a60f | 1168 | mutex_unlock(&dev_priv->dpio_lock); |
b76cf76b | 1169 | |
13732ba7 JB |
1170 | intel_hdmi->set_infoframes(&encoder->base, adjusted_mode); |
1171 | ||
b76cf76b JN |
1172 | intel_enable_hdmi(encoder); |
1173 | ||
e4607fcf | 1174 | vlv_wait_port_ready(dev_priv, dport); |
89b667f8 JB |
1175 | } |
1176 | ||
9514ac6e | 1177 | static void vlv_hdmi_pre_pll_enable(struct intel_encoder *encoder) |
89b667f8 JB |
1178 | { |
1179 | struct intel_digital_port *dport = enc_to_dig_port(&encoder->base); | |
1180 | struct drm_device *dev = encoder->base.dev; | |
1181 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5e69f97f CML |
1182 | struct intel_crtc *intel_crtc = |
1183 | to_intel_crtc(encoder->base.crtc); | |
e4607fcf | 1184 | enum dpio_channel port = vlv_dport_to_channel(dport); |
5e69f97f | 1185 | int pipe = intel_crtc->pipe; |
89b667f8 JB |
1186 | |
1187 | if (!IS_VALLEYVIEW(dev)) | |
1188 | return; | |
1189 | ||
89b667f8 | 1190 | /* Program Tx lane resets to default */ |
0980a60f | 1191 | mutex_lock(&dev_priv->dpio_lock); |
ab3c759a | 1192 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port), |
89b667f8 JB |
1193 | DPIO_PCS_TX_LANE2_RESET | |
1194 | DPIO_PCS_TX_LANE1_RESET); | |
ab3c759a | 1195 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port), |
89b667f8 JB |
1196 | DPIO_PCS_CLK_CRI_RXEB_EIOS_EN | |
1197 | DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN | | |
1198 | (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) | | |
1199 | DPIO_PCS_CLK_SOFT_RESET); | |
1200 | ||
1201 | /* Fix up inter-pair skew failure */ | |
ab3c759a CML |
1202 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW12(port), 0x00750f00); |
1203 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW11(port), 0x00001500); | |
1204 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000); | |
1205 | ||
1206 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), 0x00002000); | |
1207 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), DPIO_TX_OCALINIT_EN); | |
0980a60f | 1208 | mutex_unlock(&dev_priv->dpio_lock); |
89b667f8 JB |
1209 | } |
1210 | ||
9514ac6e | 1211 | static void vlv_hdmi_post_disable(struct intel_encoder *encoder) |
89b667f8 JB |
1212 | { |
1213 | struct intel_digital_port *dport = enc_to_dig_port(&encoder->base); | |
1214 | struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; | |
5e69f97f CML |
1215 | struct intel_crtc *intel_crtc = |
1216 | to_intel_crtc(encoder->base.crtc); | |
e4607fcf | 1217 | enum dpio_channel port = vlv_dport_to_channel(dport); |
5e69f97f | 1218 | int pipe = intel_crtc->pipe; |
89b667f8 JB |
1219 | |
1220 | /* Reset lanes to avoid HDMI flicker (VLV w/a) */ | |
1221 | mutex_lock(&dev_priv->dpio_lock); | |
ab3c759a CML |
1222 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port), 0x00000000); |
1223 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port), 0x00e00060); | |
89b667f8 JB |
1224 | mutex_unlock(&dev_priv->dpio_lock); |
1225 | } | |
1226 | ||
7d57382e EA |
1227 | static void intel_hdmi_destroy(struct drm_connector *connector) |
1228 | { | |
7d57382e | 1229 | drm_connector_cleanup(connector); |
674e2d08 | 1230 | kfree(connector); |
7d57382e EA |
1231 | } |
1232 | ||
7d57382e | 1233 | static const struct drm_connector_funcs intel_hdmi_connector_funcs = { |
5ab432ef | 1234 | .dpms = intel_connector_dpms, |
7d57382e EA |
1235 | .detect = intel_hdmi_detect, |
1236 | .fill_modes = drm_helper_probe_single_connector_modes, | |
55b7d6e8 | 1237 | .set_property = intel_hdmi_set_property, |
7d57382e EA |
1238 | .destroy = intel_hdmi_destroy, |
1239 | }; | |
1240 | ||
1241 | static const struct drm_connector_helper_funcs intel_hdmi_connector_helper_funcs = { | |
1242 | .get_modes = intel_hdmi_get_modes, | |
1243 | .mode_valid = intel_hdmi_mode_valid, | |
df0e9248 | 1244 | .best_encoder = intel_best_encoder, |
7d57382e EA |
1245 | }; |
1246 | ||
7d57382e | 1247 | static const struct drm_encoder_funcs intel_hdmi_enc_funcs = { |
ea5b213a | 1248 | .destroy = intel_encoder_destroy, |
7d57382e EA |
1249 | }; |
1250 | ||
55b7d6e8 CW |
1251 | static void |
1252 | intel_hdmi_add_properties(struct intel_hdmi *intel_hdmi, struct drm_connector *connector) | |
1253 | { | |
3f43c48d | 1254 | intel_attach_force_audio_property(connector); |
e953fd7b | 1255 | intel_attach_broadcast_rgb_property(connector); |
55bc60db | 1256 | intel_hdmi->color_range_auto = true; |
55b7d6e8 CW |
1257 | } |
1258 | ||
00c09d70 PZ |
1259 | void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port, |
1260 | struct intel_connector *intel_connector) | |
7d57382e | 1261 | { |
b9cb234c PZ |
1262 | struct drm_connector *connector = &intel_connector->base; |
1263 | struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi; | |
1264 | struct intel_encoder *intel_encoder = &intel_dig_port->base; | |
1265 | struct drm_device *dev = intel_encoder->base.dev; | |
7d57382e | 1266 | struct drm_i915_private *dev_priv = dev->dev_private; |
174edf1f | 1267 | enum port port = intel_dig_port->port; |
373a3cf7 | 1268 | |
7d57382e | 1269 | drm_connector_init(dev, connector, &intel_hdmi_connector_funcs, |
8d91104a | 1270 | DRM_MODE_CONNECTOR_HDMIA); |
7d57382e EA |
1271 | drm_connector_helper_add(connector, &intel_hdmi_connector_helper_funcs); |
1272 | ||
c3febcc4 | 1273 | connector->interlace_allowed = 1; |
7d57382e | 1274 | connector->doublescan_allowed = 0; |
573e74ad | 1275 | connector->stereo_allowed = 1; |
66a9278e | 1276 | |
08d644ad DV |
1277 | switch (port) { |
1278 | case PORT_B: | |
f899fc64 | 1279 | intel_hdmi->ddc_bus = GMBUS_PORT_DPB; |
1d843f9d | 1280 | intel_encoder->hpd_pin = HPD_PORT_B; |
08d644ad DV |
1281 | break; |
1282 | case PORT_C: | |
7ceae0a5 | 1283 | intel_hdmi->ddc_bus = GMBUS_PORT_DPC; |
1d843f9d | 1284 | intel_encoder->hpd_pin = HPD_PORT_C; |
08d644ad DV |
1285 | break; |
1286 | case PORT_D: | |
7ceae0a5 | 1287 | intel_hdmi->ddc_bus = GMBUS_PORT_DPD; |
1d843f9d | 1288 | intel_encoder->hpd_pin = HPD_PORT_D; |
08d644ad DV |
1289 | break; |
1290 | case PORT_A: | |
1d843f9d | 1291 | intel_encoder->hpd_pin = HPD_PORT_A; |
08d644ad DV |
1292 | /* Internal port only for eDP. */ |
1293 | default: | |
6e4c1677 | 1294 | BUG(); |
f8aed700 | 1295 | } |
7d57382e | 1296 | |
7637bfdb | 1297 | if (IS_VALLEYVIEW(dev)) { |
90b107c8 | 1298 | intel_hdmi->write_infoframe = vlv_write_infoframe; |
687f4d06 | 1299 | intel_hdmi->set_infoframes = vlv_set_infoframes; |
7637bfdb JB |
1300 | } else if (!HAS_PCH_SPLIT(dev)) { |
1301 | intel_hdmi->write_infoframe = g4x_write_infoframe; | |
1302 | intel_hdmi->set_infoframes = g4x_set_infoframes; | |
22b8bf17 | 1303 | } else if (HAS_DDI(dev)) { |
8c5f5f7c | 1304 | intel_hdmi->write_infoframe = hsw_write_infoframe; |
687f4d06 | 1305 | intel_hdmi->set_infoframes = hsw_set_infoframes; |
fdf1250a PZ |
1306 | } else if (HAS_PCH_IBX(dev)) { |
1307 | intel_hdmi->write_infoframe = ibx_write_infoframe; | |
687f4d06 | 1308 | intel_hdmi->set_infoframes = ibx_set_infoframes; |
fdf1250a PZ |
1309 | } else { |
1310 | intel_hdmi->write_infoframe = cpt_write_infoframe; | |
687f4d06 | 1311 | intel_hdmi->set_infoframes = cpt_set_infoframes; |
64a8fc01 | 1312 | } |
45187ace | 1313 | |
affa9354 | 1314 | if (HAS_DDI(dev)) |
bcbc889b PZ |
1315 | intel_connector->get_hw_state = intel_ddi_connector_get_hw_state; |
1316 | else | |
1317 | intel_connector->get_hw_state = intel_connector_get_hw_state; | |
4932e2c3 | 1318 | intel_connector->unregister = intel_connector_unregister; |
b9cb234c PZ |
1319 | |
1320 | intel_hdmi_add_properties(intel_hdmi, connector); | |
1321 | ||
1322 | intel_connector_attach_encoder(intel_connector, intel_encoder); | |
1323 | drm_sysfs_connector_add(connector); | |
1324 | ||
1325 | /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written | |
1326 | * 0xd. Failure to do so will result in spurious interrupts being | |
1327 | * generated on the port when a cable is not attached. | |
1328 | */ | |
1329 | if (IS_G4X(dev) && !IS_GM45(dev)) { | |
1330 | u32 temp = I915_READ(PEG_BAND_GAP_DATA); | |
1331 | I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd); | |
1332 | } | |
1333 | } | |
1334 | ||
b242b7f7 | 1335 | void intel_hdmi_init(struct drm_device *dev, int hdmi_reg, enum port port) |
b9cb234c PZ |
1336 | { |
1337 | struct intel_digital_port *intel_dig_port; | |
1338 | struct intel_encoder *intel_encoder; | |
b9cb234c PZ |
1339 | struct intel_connector *intel_connector; |
1340 | ||
b14c5679 | 1341 | intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL); |
b9cb234c PZ |
1342 | if (!intel_dig_port) |
1343 | return; | |
1344 | ||
b14c5679 | 1345 | intel_connector = kzalloc(sizeof(*intel_connector), GFP_KERNEL); |
b9cb234c PZ |
1346 | if (!intel_connector) { |
1347 | kfree(intel_dig_port); | |
1348 | return; | |
1349 | } | |
1350 | ||
1351 | intel_encoder = &intel_dig_port->base; | |
b9cb234c PZ |
1352 | |
1353 | drm_encoder_init(dev, &intel_encoder->base, &intel_hdmi_enc_funcs, | |
1354 | DRM_MODE_ENCODER_TMDS); | |
00c09d70 | 1355 | |
5bfe2ac0 | 1356 | intel_encoder->compute_config = intel_hdmi_compute_config; |
c59423a3 | 1357 | intel_encoder->mode_set = intel_hdmi_mode_set; |
00c09d70 PZ |
1358 | intel_encoder->disable = intel_disable_hdmi; |
1359 | intel_encoder->get_hw_state = intel_hdmi_get_hw_state; | |
045ac3b5 | 1360 | intel_encoder->get_config = intel_hdmi_get_config; |
89b667f8 | 1361 | if (IS_VALLEYVIEW(dev)) { |
9514ac6e CML |
1362 | intel_encoder->pre_pll_enable = vlv_hdmi_pre_pll_enable; |
1363 | intel_encoder->pre_enable = vlv_hdmi_pre_enable; | |
b76cf76b | 1364 | intel_encoder->enable = vlv_enable_hdmi; |
9514ac6e | 1365 | intel_encoder->post_disable = vlv_hdmi_post_disable; |
b76cf76b | 1366 | } else { |
13732ba7 | 1367 | intel_encoder->pre_enable = intel_hdmi_pre_enable; |
b76cf76b | 1368 | intel_encoder->enable = intel_enable_hdmi; |
89b667f8 | 1369 | } |
5ab432ef | 1370 | |
b9cb234c PZ |
1371 | intel_encoder->type = INTEL_OUTPUT_HDMI; |
1372 | intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2); | |
301ea74a | 1373 | intel_encoder->cloneable = 1 << INTEL_OUTPUT_ANALOG; |
c6f1495d VS |
1374 | /* |
1375 | * BSpec is unclear about HDMI+HDMI cloning on g4x, but it seems | |
1376 | * to work on real hardware. And since g4x can send infoframes to | |
1377 | * only one port anyway, nothing is lost by allowing it. | |
1378 | */ | |
1379 | if (IS_G4X(dev)) | |
1380 | intel_encoder->cloneable |= 1 << INTEL_OUTPUT_HDMI; | |
7d57382e | 1381 | |
174edf1f | 1382 | intel_dig_port->port = port; |
b242b7f7 | 1383 | intel_dig_port->hdmi.hdmi_reg = hdmi_reg; |
b9cb234c | 1384 | intel_dig_port->dp.output_reg = 0; |
55b7d6e8 | 1385 | |
b9cb234c | 1386 | intel_hdmi_init_connector(intel_dig_port, intel_connector); |
7d57382e | 1387 | } |