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7d57382e EA |
1 | /* |
2 | * Copyright 2006 Dave Airlie <airlied@linux.ie> | |
3 | * Copyright © 2006-2009 Intel Corporation | |
4 | * | |
5 | * Permission is hereby granted, free of charge, to any person obtaining a | |
6 | * copy of this software and associated documentation files (the "Software"), | |
7 | * to deal in the Software without restriction, including without limitation | |
8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
9 | * and/or sell copies of the Software, and to permit persons to whom the | |
10 | * Software is furnished to do so, subject to the following conditions: | |
11 | * | |
12 | * The above copyright notice and this permission notice (including the next | |
13 | * paragraph) shall be included in all copies or substantial portions of the | |
14 | * Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
21 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
22 | * DEALINGS IN THE SOFTWARE. | |
23 | * | |
24 | * Authors: | |
25 | * Eric Anholt <eric@anholt.net> | |
26 | * Jesse Barnes <jesse.barnes@intel.com> | |
27 | */ | |
28 | ||
29 | #include <linux/i2c.h> | |
5a0e3ad6 | 30 | #include <linux/slab.h> |
7d57382e | 31 | #include <linux/delay.h> |
178f736a | 32 | #include <linux/hdmi.h> |
760285e7 DH |
33 | #include <drm/drmP.h> |
34 | #include <drm/drm_crtc.h> | |
35 | #include <drm/drm_edid.h> | |
7d57382e | 36 | #include "intel_drv.h" |
760285e7 | 37 | #include <drm/i915_drm.h> |
7d57382e EA |
38 | #include "i915_drv.h" |
39 | ||
30add22d PZ |
40 | static struct drm_device *intel_hdmi_to_dev(struct intel_hdmi *intel_hdmi) |
41 | { | |
da63a9f2 | 42 | return hdmi_to_dig_port(intel_hdmi)->base.base.dev; |
30add22d PZ |
43 | } |
44 | ||
afba0188 DV |
45 | static void |
46 | assert_hdmi_port_disabled(struct intel_hdmi *intel_hdmi) | |
47 | { | |
30add22d | 48 | struct drm_device *dev = intel_hdmi_to_dev(intel_hdmi); |
afba0188 DV |
49 | struct drm_i915_private *dev_priv = dev->dev_private; |
50 | uint32_t enabled_bits; | |
51 | ||
affa9354 | 52 | enabled_bits = HAS_DDI(dev) ? DDI_BUF_CTL_ENABLE : SDVO_ENABLE; |
afba0188 | 53 | |
b242b7f7 | 54 | WARN(I915_READ(intel_hdmi->hdmi_reg) & enabled_bits, |
afba0188 DV |
55 | "HDMI port enabled, expecting disabled\n"); |
56 | } | |
57 | ||
f5bbfca3 | 58 | struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder) |
ea5b213a | 59 | { |
da63a9f2 PZ |
60 | struct intel_digital_port *intel_dig_port = |
61 | container_of(encoder, struct intel_digital_port, base.base); | |
62 | return &intel_dig_port->hdmi; | |
ea5b213a CW |
63 | } |
64 | ||
df0e9248 CW |
65 | static struct intel_hdmi *intel_attached_hdmi(struct drm_connector *connector) |
66 | { | |
da63a9f2 | 67 | return enc_to_intel_hdmi(&intel_attached_encoder(connector)->base); |
df0e9248 CW |
68 | } |
69 | ||
178f736a | 70 | static u32 g4x_infoframe_index(enum hdmi_infoframe_type type) |
3c17fe4b | 71 | { |
178f736a DL |
72 | switch (type) { |
73 | case HDMI_INFOFRAME_TYPE_AVI: | |
ed517fbb | 74 | return VIDEO_DIP_SELECT_AVI; |
178f736a | 75 | case HDMI_INFOFRAME_TYPE_SPD: |
ed517fbb | 76 | return VIDEO_DIP_SELECT_SPD; |
c8bb75af LD |
77 | case HDMI_INFOFRAME_TYPE_VENDOR: |
78 | return VIDEO_DIP_SELECT_VENDOR; | |
45187ace | 79 | default: |
178f736a | 80 | DRM_DEBUG_DRIVER("unknown info frame type %d\n", type); |
ed517fbb | 81 | return 0; |
45187ace | 82 | } |
45187ace JB |
83 | } |
84 | ||
178f736a | 85 | static u32 g4x_infoframe_enable(enum hdmi_infoframe_type type) |
45187ace | 86 | { |
178f736a DL |
87 | switch (type) { |
88 | case HDMI_INFOFRAME_TYPE_AVI: | |
ed517fbb | 89 | return VIDEO_DIP_ENABLE_AVI; |
178f736a | 90 | case HDMI_INFOFRAME_TYPE_SPD: |
ed517fbb | 91 | return VIDEO_DIP_ENABLE_SPD; |
c8bb75af LD |
92 | case HDMI_INFOFRAME_TYPE_VENDOR: |
93 | return VIDEO_DIP_ENABLE_VENDOR; | |
fa193ff7 | 94 | default: |
178f736a | 95 | DRM_DEBUG_DRIVER("unknown info frame type %d\n", type); |
ed517fbb | 96 | return 0; |
fa193ff7 | 97 | } |
fa193ff7 PZ |
98 | } |
99 | ||
178f736a | 100 | static u32 hsw_infoframe_enable(enum hdmi_infoframe_type type) |
2da8af54 | 101 | { |
178f736a DL |
102 | switch (type) { |
103 | case HDMI_INFOFRAME_TYPE_AVI: | |
2da8af54 | 104 | return VIDEO_DIP_ENABLE_AVI_HSW; |
178f736a | 105 | case HDMI_INFOFRAME_TYPE_SPD: |
2da8af54 | 106 | return VIDEO_DIP_ENABLE_SPD_HSW; |
c8bb75af LD |
107 | case HDMI_INFOFRAME_TYPE_VENDOR: |
108 | return VIDEO_DIP_ENABLE_VS_HSW; | |
2da8af54 | 109 | default: |
178f736a | 110 | DRM_DEBUG_DRIVER("unknown info frame type %d\n", type); |
2da8af54 PZ |
111 | return 0; |
112 | } | |
113 | } | |
114 | ||
178f736a | 115 | static u32 hsw_infoframe_data_reg(enum hdmi_infoframe_type type, |
a57c774a AK |
116 | enum transcoder cpu_transcoder, |
117 | struct drm_i915_private *dev_priv) | |
2da8af54 | 118 | { |
178f736a DL |
119 | switch (type) { |
120 | case HDMI_INFOFRAME_TYPE_AVI: | |
7d9bcebe | 121 | return HSW_TVIDEO_DIP_AVI_DATA(cpu_transcoder); |
178f736a | 122 | case HDMI_INFOFRAME_TYPE_SPD: |
7d9bcebe | 123 | return HSW_TVIDEO_DIP_SPD_DATA(cpu_transcoder); |
c8bb75af LD |
124 | case HDMI_INFOFRAME_TYPE_VENDOR: |
125 | return HSW_TVIDEO_DIP_VS_DATA(cpu_transcoder); | |
2da8af54 | 126 | default: |
178f736a | 127 | DRM_DEBUG_DRIVER("unknown info frame type %d\n", type); |
2da8af54 PZ |
128 | return 0; |
129 | } | |
130 | } | |
131 | ||
a3da1df7 | 132 | static void g4x_write_infoframe(struct drm_encoder *encoder, |
178f736a | 133 | enum hdmi_infoframe_type type, |
fff63867 | 134 | const void *frame, ssize_t len) |
45187ace | 135 | { |
fff63867 | 136 | const uint32_t *data = frame; |
3c17fe4b DH |
137 | struct drm_device *dev = encoder->dev; |
138 | struct drm_i915_private *dev_priv = dev->dev_private; | |
22509ec8 | 139 | u32 val = I915_READ(VIDEO_DIP_CTL); |
178f736a | 140 | int i; |
3c17fe4b | 141 | |
822974ae PZ |
142 | WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n"); |
143 | ||
1d4f85ac | 144 | val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ |
178f736a | 145 | val |= g4x_infoframe_index(type); |
22509ec8 | 146 | |
178f736a | 147 | val &= ~g4x_infoframe_enable(type); |
45187ace | 148 | |
22509ec8 | 149 | I915_WRITE(VIDEO_DIP_CTL, val); |
3c17fe4b | 150 | |
9d9740f0 | 151 | mmiowb(); |
45187ace | 152 | for (i = 0; i < len; i += 4) { |
3c17fe4b DH |
153 | I915_WRITE(VIDEO_DIP_DATA, *data); |
154 | data++; | |
155 | } | |
adf00b26 PZ |
156 | /* Write every possible data byte to force correct ECC calculation. */ |
157 | for (; i < VIDEO_DIP_DATA_SIZE; i += 4) | |
158 | I915_WRITE(VIDEO_DIP_DATA, 0); | |
9d9740f0 | 159 | mmiowb(); |
3c17fe4b | 160 | |
178f736a | 161 | val |= g4x_infoframe_enable(type); |
60c5ea2d | 162 | val &= ~VIDEO_DIP_FREQ_MASK; |
4b24c933 | 163 | val |= VIDEO_DIP_FREQ_VSYNC; |
45187ace | 164 | |
22509ec8 | 165 | I915_WRITE(VIDEO_DIP_CTL, val); |
9d9740f0 | 166 | POSTING_READ(VIDEO_DIP_CTL); |
3c17fe4b DH |
167 | } |
168 | ||
fdf1250a | 169 | static void ibx_write_infoframe(struct drm_encoder *encoder, |
178f736a | 170 | enum hdmi_infoframe_type type, |
fff63867 | 171 | const void *frame, ssize_t len) |
fdf1250a | 172 | { |
fff63867 | 173 | const uint32_t *data = frame; |
fdf1250a PZ |
174 | struct drm_device *dev = encoder->dev; |
175 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ed517fbb | 176 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); |
178f736a | 177 | int i, reg = TVIDEO_DIP_CTL(intel_crtc->pipe); |
fdf1250a PZ |
178 | u32 val = I915_READ(reg); |
179 | ||
822974ae PZ |
180 | WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n"); |
181 | ||
fdf1250a | 182 | val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ |
178f736a | 183 | val |= g4x_infoframe_index(type); |
fdf1250a | 184 | |
178f736a | 185 | val &= ~g4x_infoframe_enable(type); |
fdf1250a PZ |
186 | |
187 | I915_WRITE(reg, val); | |
188 | ||
9d9740f0 | 189 | mmiowb(); |
fdf1250a PZ |
190 | for (i = 0; i < len; i += 4) { |
191 | I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data); | |
192 | data++; | |
193 | } | |
adf00b26 PZ |
194 | /* Write every possible data byte to force correct ECC calculation. */ |
195 | for (; i < VIDEO_DIP_DATA_SIZE; i += 4) | |
196 | I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0); | |
9d9740f0 | 197 | mmiowb(); |
fdf1250a | 198 | |
178f736a | 199 | val |= g4x_infoframe_enable(type); |
fdf1250a | 200 | val &= ~VIDEO_DIP_FREQ_MASK; |
4b24c933 | 201 | val |= VIDEO_DIP_FREQ_VSYNC; |
fdf1250a PZ |
202 | |
203 | I915_WRITE(reg, val); | |
9d9740f0 | 204 | POSTING_READ(reg); |
fdf1250a PZ |
205 | } |
206 | ||
207 | static void cpt_write_infoframe(struct drm_encoder *encoder, | |
178f736a | 208 | enum hdmi_infoframe_type type, |
fff63867 | 209 | const void *frame, ssize_t len) |
b055c8f3 | 210 | { |
fff63867 | 211 | const uint32_t *data = frame; |
b055c8f3 JB |
212 | struct drm_device *dev = encoder->dev; |
213 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ed517fbb | 214 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); |
178f736a | 215 | int i, reg = TVIDEO_DIP_CTL(intel_crtc->pipe); |
22509ec8 | 216 | u32 val = I915_READ(reg); |
b055c8f3 | 217 | |
822974ae PZ |
218 | WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n"); |
219 | ||
64a8fc01 | 220 | val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ |
178f736a | 221 | val |= g4x_infoframe_index(type); |
45187ace | 222 | |
ecb97851 PZ |
223 | /* The DIP control register spec says that we need to update the AVI |
224 | * infoframe without clearing its enable bit */ | |
178f736a DL |
225 | if (type != HDMI_INFOFRAME_TYPE_AVI) |
226 | val &= ~g4x_infoframe_enable(type); | |
ecb97851 | 227 | |
22509ec8 | 228 | I915_WRITE(reg, val); |
45187ace | 229 | |
9d9740f0 | 230 | mmiowb(); |
45187ace | 231 | for (i = 0; i < len; i += 4) { |
b055c8f3 JB |
232 | I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data); |
233 | data++; | |
234 | } | |
adf00b26 PZ |
235 | /* Write every possible data byte to force correct ECC calculation. */ |
236 | for (; i < VIDEO_DIP_DATA_SIZE; i += 4) | |
237 | I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0); | |
9d9740f0 | 238 | mmiowb(); |
b055c8f3 | 239 | |
178f736a | 240 | val |= g4x_infoframe_enable(type); |
60c5ea2d | 241 | val &= ~VIDEO_DIP_FREQ_MASK; |
4b24c933 | 242 | val |= VIDEO_DIP_FREQ_VSYNC; |
45187ace | 243 | |
22509ec8 | 244 | I915_WRITE(reg, val); |
9d9740f0 | 245 | POSTING_READ(reg); |
45187ace | 246 | } |
90b107c8 SK |
247 | |
248 | static void vlv_write_infoframe(struct drm_encoder *encoder, | |
178f736a | 249 | enum hdmi_infoframe_type type, |
fff63867 | 250 | const void *frame, ssize_t len) |
90b107c8 | 251 | { |
fff63867 | 252 | const uint32_t *data = frame; |
90b107c8 SK |
253 | struct drm_device *dev = encoder->dev; |
254 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ed517fbb | 255 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); |
178f736a | 256 | int i, reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe); |
22509ec8 | 257 | u32 val = I915_READ(reg); |
90b107c8 | 258 | |
822974ae PZ |
259 | WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n"); |
260 | ||
90b107c8 | 261 | val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ |
178f736a | 262 | val |= g4x_infoframe_index(type); |
22509ec8 | 263 | |
178f736a | 264 | val &= ~g4x_infoframe_enable(type); |
90b107c8 | 265 | |
22509ec8 | 266 | I915_WRITE(reg, val); |
90b107c8 | 267 | |
9d9740f0 | 268 | mmiowb(); |
90b107c8 SK |
269 | for (i = 0; i < len; i += 4) { |
270 | I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), *data); | |
271 | data++; | |
272 | } | |
adf00b26 PZ |
273 | /* Write every possible data byte to force correct ECC calculation. */ |
274 | for (; i < VIDEO_DIP_DATA_SIZE; i += 4) | |
275 | I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), 0); | |
9d9740f0 | 276 | mmiowb(); |
90b107c8 | 277 | |
178f736a | 278 | val |= g4x_infoframe_enable(type); |
60c5ea2d | 279 | val &= ~VIDEO_DIP_FREQ_MASK; |
4b24c933 | 280 | val |= VIDEO_DIP_FREQ_VSYNC; |
90b107c8 | 281 | |
22509ec8 | 282 | I915_WRITE(reg, val); |
9d9740f0 | 283 | POSTING_READ(reg); |
90b107c8 SK |
284 | } |
285 | ||
8c5f5f7c | 286 | static void hsw_write_infoframe(struct drm_encoder *encoder, |
178f736a | 287 | enum hdmi_infoframe_type type, |
fff63867 | 288 | const void *frame, ssize_t len) |
8c5f5f7c | 289 | { |
fff63867 | 290 | const uint32_t *data = frame; |
2da8af54 PZ |
291 | struct drm_device *dev = encoder->dev; |
292 | struct drm_i915_private *dev_priv = dev->dev_private; | |
293 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); | |
3b117c8f | 294 | u32 ctl_reg = HSW_TVIDEO_DIP_CTL(intel_crtc->config.cpu_transcoder); |
178f736a DL |
295 | u32 data_reg; |
296 | int i; | |
2da8af54 | 297 | u32 val = I915_READ(ctl_reg); |
8c5f5f7c | 298 | |
178f736a | 299 | data_reg = hsw_infoframe_data_reg(type, |
a57c774a AK |
300 | intel_crtc->config.cpu_transcoder, |
301 | dev_priv); | |
2da8af54 PZ |
302 | if (data_reg == 0) |
303 | return; | |
304 | ||
178f736a | 305 | val &= ~hsw_infoframe_enable(type); |
2da8af54 PZ |
306 | I915_WRITE(ctl_reg, val); |
307 | ||
9d9740f0 | 308 | mmiowb(); |
2da8af54 PZ |
309 | for (i = 0; i < len; i += 4) { |
310 | I915_WRITE(data_reg + i, *data); | |
311 | data++; | |
312 | } | |
adf00b26 PZ |
313 | /* Write every possible data byte to force correct ECC calculation. */ |
314 | for (; i < VIDEO_DIP_DATA_SIZE; i += 4) | |
315 | I915_WRITE(data_reg + i, 0); | |
9d9740f0 | 316 | mmiowb(); |
8c5f5f7c | 317 | |
178f736a | 318 | val |= hsw_infoframe_enable(type); |
2da8af54 | 319 | I915_WRITE(ctl_reg, val); |
9d9740f0 | 320 | POSTING_READ(ctl_reg); |
8c5f5f7c ED |
321 | } |
322 | ||
5adaea79 DL |
323 | /* |
324 | * The data we write to the DIP data buffer registers is 1 byte bigger than the | |
325 | * HDMI infoframe size because of an ECC/reserved byte at position 3 (starting | |
326 | * at 0). It's also a byte used by DisplayPort so the same DIP registers can be | |
327 | * used for both technologies. | |
328 | * | |
329 | * DW0: Reserved/ECC/DP | HB2 | HB1 | HB0 | |
330 | * DW1: DB3 | DB2 | DB1 | DB0 | |
331 | * DW2: DB7 | DB6 | DB5 | DB4 | |
332 | * DW3: ... | |
333 | * | |
334 | * (HB is Header Byte, DB is Data Byte) | |
335 | * | |
336 | * The hdmi pack() functions don't know about that hardware specific hole so we | |
337 | * trick them by giving an offset into the buffer and moving back the header | |
338 | * bytes by one. | |
339 | */ | |
9198ee5b DL |
340 | static void intel_write_infoframe(struct drm_encoder *encoder, |
341 | union hdmi_infoframe *frame) | |
45187ace JB |
342 | { |
343 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); | |
5adaea79 DL |
344 | uint8_t buffer[VIDEO_DIP_DATA_SIZE]; |
345 | ssize_t len; | |
45187ace | 346 | |
5adaea79 DL |
347 | /* see comment above for the reason for this offset */ |
348 | len = hdmi_infoframe_pack(frame, buffer + 1, sizeof(buffer) - 1); | |
349 | if (len < 0) | |
350 | return; | |
351 | ||
352 | /* Insert the 'hole' (see big comment above) at position 3 */ | |
353 | buffer[0] = buffer[1]; | |
354 | buffer[1] = buffer[2]; | |
355 | buffer[2] = buffer[3]; | |
356 | buffer[3] = 0; | |
357 | len++; | |
45187ace | 358 | |
5adaea79 | 359 | intel_hdmi->write_infoframe(encoder, frame->any.type, buffer, len); |
45187ace JB |
360 | } |
361 | ||
687f4d06 | 362 | static void intel_hdmi_set_avi_infoframe(struct drm_encoder *encoder, |
c846b619 | 363 | struct drm_display_mode *adjusted_mode) |
45187ace | 364 | { |
abedc077 | 365 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); |
50f3b016 | 366 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); |
5adaea79 DL |
367 | union hdmi_infoframe frame; |
368 | int ret; | |
45187ace | 369 | |
5adaea79 DL |
370 | ret = drm_hdmi_avi_infoframe_from_display_mode(&frame.avi, |
371 | adjusted_mode); | |
372 | if (ret < 0) { | |
373 | DRM_ERROR("couldn't fill AVI infoframe\n"); | |
374 | return; | |
375 | } | |
c846b619 | 376 | |
abedc077 | 377 | if (intel_hdmi->rgb_quant_range_selectable) { |
50f3b016 | 378 | if (intel_crtc->config.limited_color_range) |
5adaea79 DL |
379 | frame.avi.quantization_range = |
380 | HDMI_QUANTIZATION_RANGE_LIMITED; | |
abedc077 | 381 | else |
5adaea79 DL |
382 | frame.avi.quantization_range = |
383 | HDMI_QUANTIZATION_RANGE_FULL; | |
abedc077 VS |
384 | } |
385 | ||
9198ee5b | 386 | intel_write_infoframe(encoder, &frame); |
b055c8f3 JB |
387 | } |
388 | ||
687f4d06 | 389 | static void intel_hdmi_set_spd_infoframe(struct drm_encoder *encoder) |
c0864cb3 | 390 | { |
5adaea79 DL |
391 | union hdmi_infoframe frame; |
392 | int ret; | |
393 | ||
394 | ret = hdmi_spd_infoframe_init(&frame.spd, "Intel", "Integrated gfx"); | |
395 | if (ret < 0) { | |
396 | DRM_ERROR("couldn't fill SPD infoframe\n"); | |
397 | return; | |
398 | } | |
c0864cb3 | 399 | |
5adaea79 | 400 | frame.spd.sdi = HDMI_SPD_SDI_PC; |
c0864cb3 | 401 | |
9198ee5b | 402 | intel_write_infoframe(encoder, &frame); |
c0864cb3 JB |
403 | } |
404 | ||
c8bb75af LD |
405 | static void |
406 | intel_hdmi_set_hdmi_infoframe(struct drm_encoder *encoder, | |
407 | struct drm_display_mode *adjusted_mode) | |
408 | { | |
409 | union hdmi_infoframe frame; | |
410 | int ret; | |
411 | ||
412 | ret = drm_hdmi_vendor_infoframe_from_display_mode(&frame.vendor.hdmi, | |
413 | adjusted_mode); | |
414 | if (ret < 0) | |
415 | return; | |
416 | ||
417 | intel_write_infoframe(encoder, &frame); | |
418 | } | |
419 | ||
687f4d06 PZ |
420 | static void g4x_set_infoframes(struct drm_encoder *encoder, |
421 | struct drm_display_mode *adjusted_mode) | |
422 | { | |
0c14c7f9 | 423 | struct drm_i915_private *dev_priv = encoder->dev->dev_private; |
69fde0a6 VS |
424 | struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); |
425 | struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi; | |
0c14c7f9 PZ |
426 | u32 reg = VIDEO_DIP_CTL; |
427 | u32 val = I915_READ(reg); | |
822cdc52 | 428 | u32 port = VIDEO_DIP_PORT(intel_dig_port->port); |
0c14c7f9 | 429 | |
afba0188 DV |
430 | assert_hdmi_port_disabled(intel_hdmi); |
431 | ||
0c14c7f9 PZ |
432 | /* If the registers were not initialized yet, they might be zeroes, |
433 | * which means we're selecting the AVI DIP and we're setting its | |
434 | * frequency to once. This seems to really confuse the HW and make | |
435 | * things stop working (the register spec says the AVI always needs to | |
436 | * be sent every VSync). So here we avoid writing to the register more | |
437 | * than we need and also explicitly select the AVI DIP and explicitly | |
438 | * set its frequency to every VSync. Avoiding to write it twice seems to | |
439 | * be enough to solve the problem, but being defensive shouldn't hurt us | |
440 | * either. */ | |
441 | val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; | |
442 | ||
443 | if (!intel_hdmi->has_hdmi_sink) { | |
444 | if (!(val & VIDEO_DIP_ENABLE)) | |
445 | return; | |
446 | val &= ~VIDEO_DIP_ENABLE; | |
447 | I915_WRITE(reg, val); | |
9d9740f0 | 448 | POSTING_READ(reg); |
0c14c7f9 PZ |
449 | return; |
450 | } | |
451 | ||
72b78c9d PZ |
452 | if (port != (val & VIDEO_DIP_PORT_MASK)) { |
453 | if (val & VIDEO_DIP_ENABLE) { | |
454 | val &= ~VIDEO_DIP_ENABLE; | |
455 | I915_WRITE(reg, val); | |
9d9740f0 | 456 | POSTING_READ(reg); |
72b78c9d PZ |
457 | } |
458 | val &= ~VIDEO_DIP_PORT_MASK; | |
459 | val |= port; | |
460 | } | |
461 | ||
822974ae | 462 | val |= VIDEO_DIP_ENABLE; |
0dd87d20 | 463 | val &= ~VIDEO_DIP_ENABLE_VENDOR; |
822974ae | 464 | |
f278d972 | 465 | I915_WRITE(reg, val); |
9d9740f0 | 466 | POSTING_READ(reg); |
f278d972 | 467 | |
687f4d06 PZ |
468 | intel_hdmi_set_avi_infoframe(encoder, adjusted_mode); |
469 | intel_hdmi_set_spd_infoframe(encoder); | |
c8bb75af | 470 | intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode); |
687f4d06 PZ |
471 | } |
472 | ||
473 | static void ibx_set_infoframes(struct drm_encoder *encoder, | |
474 | struct drm_display_mode *adjusted_mode) | |
475 | { | |
0c14c7f9 PZ |
476 | struct drm_i915_private *dev_priv = encoder->dev->dev_private; |
477 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); | |
69fde0a6 VS |
478 | struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); |
479 | struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi; | |
0c14c7f9 PZ |
480 | u32 reg = TVIDEO_DIP_CTL(intel_crtc->pipe); |
481 | u32 val = I915_READ(reg); | |
822cdc52 | 482 | u32 port = VIDEO_DIP_PORT(intel_dig_port->port); |
0c14c7f9 | 483 | |
afba0188 DV |
484 | assert_hdmi_port_disabled(intel_hdmi); |
485 | ||
0c14c7f9 PZ |
486 | /* See the big comment in g4x_set_infoframes() */ |
487 | val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; | |
488 | ||
489 | if (!intel_hdmi->has_hdmi_sink) { | |
490 | if (!(val & VIDEO_DIP_ENABLE)) | |
491 | return; | |
492 | val &= ~VIDEO_DIP_ENABLE; | |
493 | I915_WRITE(reg, val); | |
9d9740f0 | 494 | POSTING_READ(reg); |
0c14c7f9 PZ |
495 | return; |
496 | } | |
497 | ||
72b78c9d PZ |
498 | if (port != (val & VIDEO_DIP_PORT_MASK)) { |
499 | if (val & VIDEO_DIP_ENABLE) { | |
500 | val &= ~VIDEO_DIP_ENABLE; | |
501 | I915_WRITE(reg, val); | |
9d9740f0 | 502 | POSTING_READ(reg); |
72b78c9d PZ |
503 | } |
504 | val &= ~VIDEO_DIP_PORT_MASK; | |
505 | val |= port; | |
506 | } | |
507 | ||
822974ae | 508 | val |= VIDEO_DIP_ENABLE; |
0dd87d20 PZ |
509 | val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | |
510 | VIDEO_DIP_ENABLE_GCP); | |
822974ae | 511 | |
f278d972 | 512 | I915_WRITE(reg, val); |
9d9740f0 | 513 | POSTING_READ(reg); |
f278d972 | 514 | |
687f4d06 PZ |
515 | intel_hdmi_set_avi_infoframe(encoder, adjusted_mode); |
516 | intel_hdmi_set_spd_infoframe(encoder); | |
c8bb75af | 517 | intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode); |
687f4d06 PZ |
518 | } |
519 | ||
520 | static void cpt_set_infoframes(struct drm_encoder *encoder, | |
521 | struct drm_display_mode *adjusted_mode) | |
522 | { | |
0c14c7f9 PZ |
523 | struct drm_i915_private *dev_priv = encoder->dev->dev_private; |
524 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); | |
525 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); | |
526 | u32 reg = TVIDEO_DIP_CTL(intel_crtc->pipe); | |
527 | u32 val = I915_READ(reg); | |
528 | ||
afba0188 DV |
529 | assert_hdmi_port_disabled(intel_hdmi); |
530 | ||
0c14c7f9 PZ |
531 | /* See the big comment in g4x_set_infoframes() */ |
532 | val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; | |
533 | ||
534 | if (!intel_hdmi->has_hdmi_sink) { | |
535 | if (!(val & VIDEO_DIP_ENABLE)) | |
536 | return; | |
537 | val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI); | |
538 | I915_WRITE(reg, val); | |
9d9740f0 | 539 | POSTING_READ(reg); |
0c14c7f9 PZ |
540 | return; |
541 | } | |
542 | ||
822974ae PZ |
543 | /* Set both together, unset both together: see the spec. */ |
544 | val |= VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI; | |
0dd87d20 PZ |
545 | val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | |
546 | VIDEO_DIP_ENABLE_GCP); | |
822974ae PZ |
547 | |
548 | I915_WRITE(reg, val); | |
9d9740f0 | 549 | POSTING_READ(reg); |
822974ae | 550 | |
687f4d06 PZ |
551 | intel_hdmi_set_avi_infoframe(encoder, adjusted_mode); |
552 | intel_hdmi_set_spd_infoframe(encoder); | |
c8bb75af | 553 | intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode); |
687f4d06 PZ |
554 | } |
555 | ||
556 | static void vlv_set_infoframes(struct drm_encoder *encoder, | |
557 | struct drm_display_mode *adjusted_mode) | |
558 | { | |
0c14c7f9 PZ |
559 | struct drm_i915_private *dev_priv = encoder->dev->dev_private; |
560 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); | |
561 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); | |
562 | u32 reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe); | |
563 | u32 val = I915_READ(reg); | |
564 | ||
afba0188 DV |
565 | assert_hdmi_port_disabled(intel_hdmi); |
566 | ||
0c14c7f9 PZ |
567 | /* See the big comment in g4x_set_infoframes() */ |
568 | val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; | |
569 | ||
570 | if (!intel_hdmi->has_hdmi_sink) { | |
571 | if (!(val & VIDEO_DIP_ENABLE)) | |
572 | return; | |
573 | val &= ~VIDEO_DIP_ENABLE; | |
574 | I915_WRITE(reg, val); | |
9d9740f0 | 575 | POSTING_READ(reg); |
0c14c7f9 PZ |
576 | return; |
577 | } | |
578 | ||
822974ae | 579 | val |= VIDEO_DIP_ENABLE; |
0dd87d20 PZ |
580 | val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | |
581 | VIDEO_DIP_ENABLE_GCP); | |
822974ae PZ |
582 | |
583 | I915_WRITE(reg, val); | |
9d9740f0 | 584 | POSTING_READ(reg); |
822974ae | 585 | |
687f4d06 PZ |
586 | intel_hdmi_set_avi_infoframe(encoder, adjusted_mode); |
587 | intel_hdmi_set_spd_infoframe(encoder); | |
c8bb75af | 588 | intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode); |
687f4d06 PZ |
589 | } |
590 | ||
591 | static void hsw_set_infoframes(struct drm_encoder *encoder, | |
592 | struct drm_display_mode *adjusted_mode) | |
593 | { | |
0c14c7f9 PZ |
594 | struct drm_i915_private *dev_priv = encoder->dev->dev_private; |
595 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); | |
596 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); | |
3b117c8f | 597 | u32 reg = HSW_TVIDEO_DIP_CTL(intel_crtc->config.cpu_transcoder); |
0dd87d20 | 598 | u32 val = I915_READ(reg); |
0c14c7f9 | 599 | |
afba0188 DV |
600 | assert_hdmi_port_disabled(intel_hdmi); |
601 | ||
0c14c7f9 PZ |
602 | if (!intel_hdmi->has_hdmi_sink) { |
603 | I915_WRITE(reg, 0); | |
9d9740f0 | 604 | POSTING_READ(reg); |
0c14c7f9 PZ |
605 | return; |
606 | } | |
607 | ||
0dd87d20 PZ |
608 | val &= ~(VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_GCP_HSW | |
609 | VIDEO_DIP_ENABLE_VS_HSW | VIDEO_DIP_ENABLE_GMP_HSW); | |
610 | ||
611 | I915_WRITE(reg, val); | |
9d9740f0 | 612 | POSTING_READ(reg); |
0dd87d20 | 613 | |
687f4d06 PZ |
614 | intel_hdmi_set_avi_infoframe(encoder, adjusted_mode); |
615 | intel_hdmi_set_spd_infoframe(encoder); | |
c8bb75af | 616 | intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode); |
687f4d06 PZ |
617 | } |
618 | ||
c59423a3 | 619 | static void intel_hdmi_mode_set(struct intel_encoder *encoder) |
7d57382e | 620 | { |
c59423a3 | 621 | struct drm_device *dev = encoder->base.dev; |
7d57382e | 622 | struct drm_i915_private *dev_priv = dev->dev_private; |
c59423a3 DV |
623 | struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); |
624 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); | |
625 | struct drm_display_mode *adjusted_mode = &crtc->config.adjusted_mode; | |
b242b7f7 | 626 | u32 hdmi_val; |
7d57382e | 627 | |
b242b7f7 | 628 | hdmi_val = SDVO_ENCODING_HDMI; |
2af2c490 | 629 | if (!HAS_PCH_SPLIT(dev)) |
b242b7f7 | 630 | hdmi_val |= intel_hdmi->color_range; |
b599c0bc | 631 | if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) |
b242b7f7 | 632 | hdmi_val |= SDVO_VSYNC_ACTIVE_HIGH; |
b599c0bc | 633 | if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) |
b242b7f7 | 634 | hdmi_val |= SDVO_HSYNC_ACTIVE_HIGH; |
7d57382e | 635 | |
c59423a3 | 636 | if (crtc->config.pipe_bpp > 24) |
4f3a8bc7 | 637 | hdmi_val |= HDMI_COLOR_FORMAT_12bpc; |
020f6704 | 638 | else |
4f3a8bc7 | 639 | hdmi_val |= SDVO_COLOR_FORMAT_8bpc; |
020f6704 | 640 | |
2e3d6006 ZW |
641 | /* Required on CPT */ |
642 | if (intel_hdmi->has_hdmi_sink && HAS_PCH_CPT(dev)) | |
dc0fa718 | 643 | hdmi_val |= HDMI_MODE_SELECT_HDMI; |
2e3d6006 | 644 | |
3c17fe4b | 645 | if (intel_hdmi->has_audio) { |
e0dac65e | 646 | DRM_DEBUG_DRIVER("Enabling HDMI audio on pipe %c\n", |
c59423a3 | 647 | pipe_name(crtc->pipe)); |
b242b7f7 | 648 | hdmi_val |= SDVO_AUDIO_ENABLE; |
dc0fa718 | 649 | hdmi_val |= HDMI_MODE_SELECT_HDMI; |
c59423a3 | 650 | intel_write_eld(&encoder->base, adjusted_mode); |
3c17fe4b | 651 | } |
7d57382e | 652 | |
75770564 | 653 | if (HAS_PCH_CPT(dev)) |
c59423a3 | 654 | hdmi_val |= SDVO_PIPE_SEL_CPT(crtc->pipe); |
dc0fa718 | 655 | else |
c59423a3 | 656 | hdmi_val |= SDVO_PIPE_SEL(crtc->pipe); |
7d57382e | 657 | |
b242b7f7 PZ |
658 | I915_WRITE(intel_hdmi->hdmi_reg, hdmi_val); |
659 | POSTING_READ(intel_hdmi->hdmi_reg); | |
3c17fe4b | 660 | |
c59423a3 | 661 | intel_hdmi->set_infoframes(&encoder->base, adjusted_mode); |
7d57382e EA |
662 | } |
663 | ||
85234cdc DV |
664 | static bool intel_hdmi_get_hw_state(struct intel_encoder *encoder, |
665 | enum pipe *pipe) | |
7d57382e | 666 | { |
85234cdc | 667 | struct drm_device *dev = encoder->base.dev; |
7d57382e | 668 | struct drm_i915_private *dev_priv = dev->dev_private; |
85234cdc DV |
669 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); |
670 | u32 tmp; | |
671 | ||
b242b7f7 | 672 | tmp = I915_READ(intel_hdmi->hdmi_reg); |
85234cdc DV |
673 | |
674 | if (!(tmp & SDVO_ENABLE)) | |
675 | return false; | |
676 | ||
677 | if (HAS_PCH_CPT(dev)) | |
678 | *pipe = PORT_TO_PIPE_CPT(tmp); | |
679 | else | |
680 | *pipe = PORT_TO_PIPE(tmp); | |
681 | ||
682 | return true; | |
683 | } | |
684 | ||
045ac3b5 JB |
685 | static void intel_hdmi_get_config(struct intel_encoder *encoder, |
686 | struct intel_crtc_config *pipe_config) | |
687 | { | |
688 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); | |
689 | struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; | |
690 | u32 tmp, flags = 0; | |
18442d08 | 691 | int dotclock; |
045ac3b5 JB |
692 | |
693 | tmp = I915_READ(intel_hdmi->hdmi_reg); | |
694 | ||
695 | if (tmp & SDVO_HSYNC_ACTIVE_HIGH) | |
696 | flags |= DRM_MODE_FLAG_PHSYNC; | |
697 | else | |
698 | flags |= DRM_MODE_FLAG_NHSYNC; | |
699 | ||
700 | if (tmp & SDVO_VSYNC_ACTIVE_HIGH) | |
701 | flags |= DRM_MODE_FLAG_PVSYNC; | |
702 | else | |
703 | flags |= DRM_MODE_FLAG_NVSYNC; | |
704 | ||
705 | pipe_config->adjusted_mode.flags |= flags; | |
18442d08 VS |
706 | |
707 | if ((tmp & SDVO_COLOR_FORMAT_MASK) == HDMI_COLOR_FORMAT_12bpc) | |
708 | dotclock = pipe_config->port_clock * 2 / 3; | |
709 | else | |
710 | dotclock = pipe_config->port_clock; | |
711 | ||
712 | if (HAS_PCH_SPLIT(dev_priv->dev)) | |
713 | ironlake_check_encoder_dotclock(pipe_config, dotclock); | |
714 | ||
241bfc38 | 715 | pipe_config->adjusted_mode.crtc_clock = dotclock; |
045ac3b5 JB |
716 | } |
717 | ||
5ab432ef | 718 | static void intel_enable_hdmi(struct intel_encoder *encoder) |
7d57382e | 719 | { |
5ab432ef | 720 | struct drm_device *dev = encoder->base.dev; |
7d57382e | 721 | struct drm_i915_private *dev_priv = dev->dev_private; |
dc0fa718 | 722 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); |
5ab432ef | 723 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); |
7d57382e | 724 | u32 temp; |
2deed761 WF |
725 | u32 enable_bits = SDVO_ENABLE; |
726 | ||
727 | if (intel_hdmi->has_audio) | |
728 | enable_bits |= SDVO_AUDIO_ENABLE; | |
7d57382e | 729 | |
b242b7f7 | 730 | temp = I915_READ(intel_hdmi->hdmi_reg); |
d8a2d0e0 | 731 | |
7a87c289 | 732 | /* HW workaround for IBX, we need to move the port to transcoder A |
dc0fa718 PZ |
733 | * before disabling it, so restore the transcoder select bit here. */ |
734 | if (HAS_PCH_IBX(dev)) | |
735 | enable_bits |= SDVO_PIPE_SEL(intel_crtc->pipe); | |
7a87c289 | 736 | |
d8a2d0e0 ZW |
737 | /* HW workaround, need to toggle enable bit off and on for 12bpc, but |
738 | * we do this anyway which shows more stable in testing. | |
739 | */ | |
c619eed4 | 740 | if (HAS_PCH_SPLIT(dev)) { |
b242b7f7 PZ |
741 | I915_WRITE(intel_hdmi->hdmi_reg, temp & ~SDVO_ENABLE); |
742 | POSTING_READ(intel_hdmi->hdmi_reg); | |
d8a2d0e0 ZW |
743 | } |
744 | ||
5ab432ef DV |
745 | temp |= enable_bits; |
746 | ||
b242b7f7 PZ |
747 | I915_WRITE(intel_hdmi->hdmi_reg, temp); |
748 | POSTING_READ(intel_hdmi->hdmi_reg); | |
5ab432ef DV |
749 | |
750 | /* HW workaround, need to write this twice for issue that may result | |
751 | * in first write getting masked. | |
752 | */ | |
753 | if (HAS_PCH_SPLIT(dev)) { | |
b242b7f7 PZ |
754 | I915_WRITE(intel_hdmi->hdmi_reg, temp); |
755 | POSTING_READ(intel_hdmi->hdmi_reg); | |
7d57382e | 756 | } |
b76cf76b | 757 | } |
89b667f8 | 758 | |
b76cf76b JN |
759 | static void vlv_enable_hdmi(struct intel_encoder *encoder) |
760 | { | |
5ab432ef DV |
761 | } |
762 | ||
763 | static void intel_disable_hdmi(struct intel_encoder *encoder) | |
764 | { | |
765 | struct drm_device *dev = encoder->base.dev; | |
766 | struct drm_i915_private *dev_priv = dev->dev_private; | |
767 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); | |
768 | u32 temp; | |
3cce574f | 769 | u32 enable_bits = SDVO_ENABLE | SDVO_AUDIO_ENABLE; |
5ab432ef | 770 | |
b242b7f7 | 771 | temp = I915_READ(intel_hdmi->hdmi_reg); |
5ab432ef DV |
772 | |
773 | /* HW workaround for IBX, we need to move the port to transcoder A | |
774 | * before disabling it. */ | |
775 | if (HAS_PCH_IBX(dev)) { | |
776 | struct drm_crtc *crtc = encoder->base.crtc; | |
777 | int pipe = crtc ? to_intel_crtc(crtc)->pipe : -1; | |
778 | ||
779 | if (temp & SDVO_PIPE_B_SELECT) { | |
780 | temp &= ~SDVO_PIPE_B_SELECT; | |
b242b7f7 PZ |
781 | I915_WRITE(intel_hdmi->hdmi_reg, temp); |
782 | POSTING_READ(intel_hdmi->hdmi_reg); | |
5ab432ef DV |
783 | |
784 | /* Again we need to write this twice. */ | |
b242b7f7 PZ |
785 | I915_WRITE(intel_hdmi->hdmi_reg, temp); |
786 | POSTING_READ(intel_hdmi->hdmi_reg); | |
5ab432ef DV |
787 | |
788 | /* Transcoder selection bits only update | |
789 | * effectively on vblank. */ | |
790 | if (crtc) | |
791 | intel_wait_for_vblank(dev, pipe); | |
792 | else | |
793 | msleep(50); | |
794 | } | |
7d57382e | 795 | } |
d8a2d0e0 | 796 | |
5ab432ef DV |
797 | /* HW workaround, need to toggle enable bit off and on for 12bpc, but |
798 | * we do this anyway which shows more stable in testing. | |
799 | */ | |
800 | if (HAS_PCH_SPLIT(dev)) { | |
b242b7f7 PZ |
801 | I915_WRITE(intel_hdmi->hdmi_reg, temp & ~SDVO_ENABLE); |
802 | POSTING_READ(intel_hdmi->hdmi_reg); | |
5ab432ef DV |
803 | } |
804 | ||
805 | temp &= ~enable_bits; | |
d8a2d0e0 | 806 | |
b242b7f7 PZ |
807 | I915_WRITE(intel_hdmi->hdmi_reg, temp); |
808 | POSTING_READ(intel_hdmi->hdmi_reg); | |
d8a2d0e0 ZW |
809 | |
810 | /* HW workaround, need to write this twice for issue that may result | |
811 | * in first write getting masked. | |
812 | */ | |
c619eed4 | 813 | if (HAS_PCH_SPLIT(dev)) { |
b242b7f7 PZ |
814 | I915_WRITE(intel_hdmi->hdmi_reg, temp); |
815 | POSTING_READ(intel_hdmi->hdmi_reg); | |
d8a2d0e0 | 816 | } |
7d57382e EA |
817 | } |
818 | ||
7d148ef5 DV |
819 | static int hdmi_portclock_limit(struct intel_hdmi *hdmi) |
820 | { | |
821 | struct drm_device *dev = intel_hdmi_to_dev(hdmi); | |
822 | ||
823 | if (IS_G4X(dev)) | |
824 | return 165000; | |
e3c33578 | 825 | else if (IS_HASWELL(dev) || INTEL_INFO(dev)->gen >= 8) |
7d148ef5 DV |
826 | return 300000; |
827 | else | |
828 | return 225000; | |
829 | } | |
830 | ||
c19de8eb DL |
831 | static enum drm_mode_status |
832 | intel_hdmi_mode_valid(struct drm_connector *connector, | |
833 | struct drm_display_mode *mode) | |
7d57382e | 834 | { |
7d148ef5 | 835 | if (mode->clock > hdmi_portclock_limit(intel_attached_hdmi(connector))) |
7d57382e EA |
836 | return MODE_CLOCK_HIGH; |
837 | if (mode->clock < 20000) | |
5cbba41d | 838 | return MODE_CLOCK_LOW; |
7d57382e EA |
839 | |
840 | if (mode->flags & DRM_MODE_FLAG_DBLSCAN) | |
841 | return MODE_NO_DBLESCAN; | |
842 | ||
843 | return MODE_OK; | |
844 | } | |
845 | ||
5bfe2ac0 DV |
846 | bool intel_hdmi_compute_config(struct intel_encoder *encoder, |
847 | struct intel_crtc_config *pipe_config) | |
7d57382e | 848 | { |
5bfe2ac0 DV |
849 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); |
850 | struct drm_device *dev = encoder->base.dev; | |
851 | struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode; | |
241bfc38 | 852 | int clock_12bpc = pipe_config->adjusted_mode.crtc_clock * 3 / 2; |
7d148ef5 | 853 | int portclock_limit = hdmi_portclock_limit(intel_hdmi); |
e29c22c0 | 854 | int desired_bpp; |
3685a8f3 | 855 | |
55bc60db VS |
856 | if (intel_hdmi->color_range_auto) { |
857 | /* See CEA-861-E - 5.1 Default Encoding Parameters */ | |
858 | if (intel_hdmi->has_hdmi_sink && | |
18316c8c | 859 | drm_match_cea_mode(adjusted_mode) > 1) |
4f3a8bc7 | 860 | intel_hdmi->color_range = HDMI_COLOR_RANGE_16_235; |
55bc60db VS |
861 | else |
862 | intel_hdmi->color_range = 0; | |
863 | } | |
864 | ||
3685a8f3 | 865 | if (intel_hdmi->color_range) |
50f3b016 | 866 | pipe_config->limited_color_range = true; |
3685a8f3 | 867 | |
5bfe2ac0 DV |
868 | if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev)) |
869 | pipe_config->has_pch_encoder = true; | |
870 | ||
4e53c2e0 DV |
871 | /* |
872 | * HDMI is either 12 or 8, so if the display lets 10bpc sneak | |
873 | * through, clamp it down. Note that g4x/vlv don't support 12bpc hdmi | |
325b9d04 DV |
874 | * outputs. We also need to check that the higher clock still fits |
875 | * within limits. | |
4e53c2e0 | 876 | */ |
7d148ef5 | 877 | if (pipe_config->pipe_bpp > 8*3 && clock_12bpc <= portclock_limit |
325b9d04 | 878 | && HAS_PCH_SPLIT(dev)) { |
e29c22c0 DV |
879 | DRM_DEBUG_KMS("picking bpc to 12 for HDMI output\n"); |
880 | desired_bpp = 12*3; | |
325b9d04 DV |
881 | |
882 | /* Need to adjust the port link by 1.5x for 12bpc. */ | |
ff9a6750 | 883 | pipe_config->port_clock = clock_12bpc; |
4e53c2e0 | 884 | } else { |
e29c22c0 DV |
885 | DRM_DEBUG_KMS("picking bpc to 8 for HDMI output\n"); |
886 | desired_bpp = 8*3; | |
887 | } | |
888 | ||
889 | if (!pipe_config->bw_constrained) { | |
890 | DRM_DEBUG_KMS("forcing pipe bpc to %i for HDMI\n", desired_bpp); | |
891 | pipe_config->pipe_bpp = desired_bpp; | |
4e53c2e0 DV |
892 | } |
893 | ||
241bfc38 | 894 | if (adjusted_mode->crtc_clock > portclock_limit) { |
325b9d04 DV |
895 | DRM_DEBUG_KMS("too high HDMI clock, rejecting mode\n"); |
896 | return false; | |
897 | } | |
898 | ||
7d57382e EA |
899 | return true; |
900 | } | |
901 | ||
aa93d632 | 902 | static enum drm_connector_status |
930a9e28 | 903 | intel_hdmi_detect(struct drm_connector *connector, bool force) |
9dff6af8 | 904 | { |
b0ea7d37 | 905 | struct drm_device *dev = connector->dev; |
df0e9248 | 906 | struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); |
d63885da PZ |
907 | struct intel_digital_port *intel_dig_port = |
908 | hdmi_to_dig_port(intel_hdmi); | |
909 | struct intel_encoder *intel_encoder = &intel_dig_port->base; | |
b0ea7d37 | 910 | struct drm_i915_private *dev_priv = dev->dev_private; |
f899fc64 | 911 | struct edid *edid; |
aa93d632 | 912 | enum drm_connector_status status = connector_status_disconnected; |
9dff6af8 | 913 | |
164c8598 CW |
914 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", |
915 | connector->base.id, drm_get_connector_name(connector)); | |
916 | ||
ea5b213a | 917 | intel_hdmi->has_hdmi_sink = false; |
2e3d6006 | 918 | intel_hdmi->has_audio = false; |
abedc077 | 919 | intel_hdmi->rgb_quant_range_selectable = false; |
f899fc64 | 920 | edid = drm_get_edid(connector, |
3bd7d909 DK |
921 | intel_gmbus_get_adapter(dev_priv, |
922 | intel_hdmi->ddc_bus)); | |
2ded9e27 | 923 | |
aa93d632 | 924 | if (edid) { |
be9f1c4f | 925 | if (edid->input & DRM_EDID_INPUT_DIGITAL) { |
aa93d632 | 926 | status = connector_status_connected; |
b1d7e4b4 WF |
927 | if (intel_hdmi->force_audio != HDMI_AUDIO_OFF_DVI) |
928 | intel_hdmi->has_hdmi_sink = | |
929 | drm_detect_hdmi_monitor(edid); | |
2e3d6006 | 930 | intel_hdmi->has_audio = drm_detect_monitor_audio(edid); |
abedc077 VS |
931 | intel_hdmi->rgb_quant_range_selectable = |
932 | drm_rgb_quant_range_selectable(edid); | |
aa93d632 | 933 | } |
aa93d632 | 934 | kfree(edid); |
9dff6af8 | 935 | } |
30ad48b7 | 936 | |
55b7d6e8 | 937 | if (status == connector_status_connected) { |
b1d7e4b4 WF |
938 | if (intel_hdmi->force_audio != HDMI_AUDIO_AUTO) |
939 | intel_hdmi->has_audio = | |
940 | (intel_hdmi->force_audio == HDMI_AUDIO_ON); | |
d63885da | 941 | intel_encoder->type = INTEL_OUTPUT_HDMI; |
55b7d6e8 CW |
942 | } |
943 | ||
2ded9e27 | 944 | return status; |
7d57382e EA |
945 | } |
946 | ||
947 | static int intel_hdmi_get_modes(struct drm_connector *connector) | |
948 | { | |
df0e9248 | 949 | struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); |
f899fc64 | 950 | struct drm_i915_private *dev_priv = connector->dev->dev_private; |
7d57382e EA |
951 | |
952 | /* We should parse the EDID data and find out if it's an HDMI sink so | |
953 | * we can send audio to it. | |
954 | */ | |
955 | ||
f899fc64 | 956 | return intel_ddc_get_modes(connector, |
3bd7d909 DK |
957 | intel_gmbus_get_adapter(dev_priv, |
958 | intel_hdmi->ddc_bus)); | |
7d57382e EA |
959 | } |
960 | ||
1aad7ac0 CW |
961 | static bool |
962 | intel_hdmi_detect_audio(struct drm_connector *connector) | |
963 | { | |
964 | struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); | |
965 | struct drm_i915_private *dev_priv = connector->dev->dev_private; | |
966 | struct edid *edid; | |
967 | bool has_audio = false; | |
968 | ||
969 | edid = drm_get_edid(connector, | |
3bd7d909 DK |
970 | intel_gmbus_get_adapter(dev_priv, |
971 | intel_hdmi->ddc_bus)); | |
1aad7ac0 CW |
972 | if (edid) { |
973 | if (edid->input & DRM_EDID_INPUT_DIGITAL) | |
974 | has_audio = drm_detect_monitor_audio(edid); | |
1aad7ac0 CW |
975 | kfree(edid); |
976 | } | |
977 | ||
978 | return has_audio; | |
979 | } | |
980 | ||
55b7d6e8 CW |
981 | static int |
982 | intel_hdmi_set_property(struct drm_connector *connector, | |
ed517fbb PZ |
983 | struct drm_property *property, |
984 | uint64_t val) | |
55b7d6e8 CW |
985 | { |
986 | struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); | |
da63a9f2 PZ |
987 | struct intel_digital_port *intel_dig_port = |
988 | hdmi_to_dig_port(intel_hdmi); | |
e953fd7b | 989 | struct drm_i915_private *dev_priv = connector->dev->dev_private; |
55b7d6e8 CW |
990 | int ret; |
991 | ||
662595df | 992 | ret = drm_object_property_set_value(&connector->base, property, val); |
55b7d6e8 CW |
993 | if (ret) |
994 | return ret; | |
995 | ||
3f43c48d | 996 | if (property == dev_priv->force_audio_property) { |
b1d7e4b4 | 997 | enum hdmi_force_audio i = val; |
1aad7ac0 CW |
998 | bool has_audio; |
999 | ||
1000 | if (i == intel_hdmi->force_audio) | |
55b7d6e8 CW |
1001 | return 0; |
1002 | ||
1aad7ac0 | 1003 | intel_hdmi->force_audio = i; |
55b7d6e8 | 1004 | |
b1d7e4b4 | 1005 | if (i == HDMI_AUDIO_AUTO) |
1aad7ac0 CW |
1006 | has_audio = intel_hdmi_detect_audio(connector); |
1007 | else | |
b1d7e4b4 | 1008 | has_audio = (i == HDMI_AUDIO_ON); |
1aad7ac0 | 1009 | |
b1d7e4b4 WF |
1010 | if (i == HDMI_AUDIO_OFF_DVI) |
1011 | intel_hdmi->has_hdmi_sink = 0; | |
55b7d6e8 | 1012 | |
1aad7ac0 | 1013 | intel_hdmi->has_audio = has_audio; |
55b7d6e8 CW |
1014 | goto done; |
1015 | } | |
1016 | ||
e953fd7b | 1017 | if (property == dev_priv->broadcast_rgb_property) { |
ae4edb80 DV |
1018 | bool old_auto = intel_hdmi->color_range_auto; |
1019 | uint32_t old_range = intel_hdmi->color_range; | |
1020 | ||
55bc60db VS |
1021 | switch (val) { |
1022 | case INTEL_BROADCAST_RGB_AUTO: | |
1023 | intel_hdmi->color_range_auto = true; | |
1024 | break; | |
1025 | case INTEL_BROADCAST_RGB_FULL: | |
1026 | intel_hdmi->color_range_auto = false; | |
1027 | intel_hdmi->color_range = 0; | |
1028 | break; | |
1029 | case INTEL_BROADCAST_RGB_LIMITED: | |
1030 | intel_hdmi->color_range_auto = false; | |
4f3a8bc7 | 1031 | intel_hdmi->color_range = HDMI_COLOR_RANGE_16_235; |
55bc60db VS |
1032 | break; |
1033 | default: | |
1034 | return -EINVAL; | |
1035 | } | |
ae4edb80 DV |
1036 | |
1037 | if (old_auto == intel_hdmi->color_range_auto && | |
1038 | old_range == intel_hdmi->color_range) | |
1039 | return 0; | |
1040 | ||
e953fd7b CW |
1041 | goto done; |
1042 | } | |
1043 | ||
55b7d6e8 CW |
1044 | return -EINVAL; |
1045 | ||
1046 | done: | |
c0c36b94 CW |
1047 | if (intel_dig_port->base.base.crtc) |
1048 | intel_crtc_restore_mode(intel_dig_port->base.base.crtc); | |
55b7d6e8 CW |
1049 | |
1050 | return 0; | |
1051 | } | |
1052 | ||
9514ac6e | 1053 | static void vlv_hdmi_pre_enable(struct intel_encoder *encoder) |
89b667f8 JB |
1054 | { |
1055 | struct intel_digital_port *dport = enc_to_dig_port(&encoder->base); | |
1056 | struct drm_device *dev = encoder->base.dev; | |
1057 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1058 | struct intel_crtc *intel_crtc = | |
1059 | to_intel_crtc(encoder->base.crtc); | |
e4607fcf | 1060 | enum dpio_channel port = vlv_dport_to_channel(dport); |
89b667f8 JB |
1061 | int pipe = intel_crtc->pipe; |
1062 | u32 val; | |
1063 | ||
1064 | if (!IS_VALLEYVIEW(dev)) | |
1065 | return; | |
1066 | ||
89b667f8 | 1067 | /* Enable clock channels for this port */ |
0980a60f | 1068 | mutex_lock(&dev_priv->dpio_lock); |
ab3c759a | 1069 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port)); |
89b667f8 JB |
1070 | val = 0; |
1071 | if (pipe) | |
1072 | val |= (1<<21); | |
1073 | else | |
1074 | val &= ~(1<<21); | |
1075 | val |= 0x001000c4; | |
ab3c759a | 1076 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val); |
89b667f8 JB |
1077 | |
1078 | /* HDMI 1.0V-2dB */ | |
ab3c759a CML |
1079 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0); |
1080 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), 0x2b245f5f); | |
1081 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port), 0x5578b83a); | |
1082 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0c782040); | |
1083 | vlv_dpio_write(dev_priv, pipe, VLV_TX3_DW4(port), 0x2b247878); | |
1084 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000); | |
1085 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), 0x00002000); | |
1086 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), DPIO_TX_OCALINIT_EN); | |
89b667f8 JB |
1087 | |
1088 | /* Program lane clock */ | |
ab3c759a CML |
1089 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018); |
1090 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888); | |
0980a60f | 1091 | mutex_unlock(&dev_priv->dpio_lock); |
b76cf76b JN |
1092 | |
1093 | intel_enable_hdmi(encoder); | |
1094 | ||
e4607fcf | 1095 | vlv_wait_port_ready(dev_priv, dport); |
89b667f8 JB |
1096 | } |
1097 | ||
9514ac6e | 1098 | static void vlv_hdmi_pre_pll_enable(struct intel_encoder *encoder) |
89b667f8 JB |
1099 | { |
1100 | struct intel_digital_port *dport = enc_to_dig_port(&encoder->base); | |
1101 | struct drm_device *dev = encoder->base.dev; | |
1102 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5e69f97f CML |
1103 | struct intel_crtc *intel_crtc = |
1104 | to_intel_crtc(encoder->base.crtc); | |
e4607fcf | 1105 | enum dpio_channel port = vlv_dport_to_channel(dport); |
5e69f97f | 1106 | int pipe = intel_crtc->pipe; |
89b667f8 JB |
1107 | |
1108 | if (!IS_VALLEYVIEW(dev)) | |
1109 | return; | |
1110 | ||
89b667f8 | 1111 | /* Program Tx lane resets to default */ |
0980a60f | 1112 | mutex_lock(&dev_priv->dpio_lock); |
ab3c759a | 1113 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port), |
89b667f8 JB |
1114 | DPIO_PCS_TX_LANE2_RESET | |
1115 | DPIO_PCS_TX_LANE1_RESET); | |
ab3c759a | 1116 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port), |
89b667f8 JB |
1117 | DPIO_PCS_CLK_CRI_RXEB_EIOS_EN | |
1118 | DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN | | |
1119 | (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) | | |
1120 | DPIO_PCS_CLK_SOFT_RESET); | |
1121 | ||
1122 | /* Fix up inter-pair skew failure */ | |
ab3c759a CML |
1123 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW12(port), 0x00750f00); |
1124 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW11(port), 0x00001500); | |
1125 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000); | |
1126 | ||
1127 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), 0x00002000); | |
1128 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), DPIO_TX_OCALINIT_EN); | |
0980a60f | 1129 | mutex_unlock(&dev_priv->dpio_lock); |
89b667f8 JB |
1130 | } |
1131 | ||
9514ac6e | 1132 | static void vlv_hdmi_post_disable(struct intel_encoder *encoder) |
89b667f8 JB |
1133 | { |
1134 | struct intel_digital_port *dport = enc_to_dig_port(&encoder->base); | |
1135 | struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; | |
5e69f97f CML |
1136 | struct intel_crtc *intel_crtc = |
1137 | to_intel_crtc(encoder->base.crtc); | |
e4607fcf | 1138 | enum dpio_channel port = vlv_dport_to_channel(dport); |
5e69f97f | 1139 | int pipe = intel_crtc->pipe; |
89b667f8 JB |
1140 | |
1141 | /* Reset lanes to avoid HDMI flicker (VLV w/a) */ | |
1142 | mutex_lock(&dev_priv->dpio_lock); | |
ab3c759a CML |
1143 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port), 0x00000000); |
1144 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port), 0x00e00060); | |
89b667f8 JB |
1145 | mutex_unlock(&dev_priv->dpio_lock); |
1146 | } | |
1147 | ||
7d57382e EA |
1148 | static void intel_hdmi_destroy(struct drm_connector *connector) |
1149 | { | |
7d57382e | 1150 | drm_connector_cleanup(connector); |
674e2d08 | 1151 | kfree(connector); |
7d57382e EA |
1152 | } |
1153 | ||
7d57382e | 1154 | static const struct drm_connector_funcs intel_hdmi_connector_funcs = { |
5ab432ef | 1155 | .dpms = intel_connector_dpms, |
7d57382e EA |
1156 | .detect = intel_hdmi_detect, |
1157 | .fill_modes = drm_helper_probe_single_connector_modes, | |
55b7d6e8 | 1158 | .set_property = intel_hdmi_set_property, |
7d57382e EA |
1159 | .destroy = intel_hdmi_destroy, |
1160 | }; | |
1161 | ||
1162 | static const struct drm_connector_helper_funcs intel_hdmi_connector_helper_funcs = { | |
1163 | .get_modes = intel_hdmi_get_modes, | |
1164 | .mode_valid = intel_hdmi_mode_valid, | |
df0e9248 | 1165 | .best_encoder = intel_best_encoder, |
7d57382e EA |
1166 | }; |
1167 | ||
7d57382e | 1168 | static const struct drm_encoder_funcs intel_hdmi_enc_funcs = { |
ea5b213a | 1169 | .destroy = intel_encoder_destroy, |
7d57382e EA |
1170 | }; |
1171 | ||
55b7d6e8 CW |
1172 | static void |
1173 | intel_hdmi_add_properties(struct intel_hdmi *intel_hdmi, struct drm_connector *connector) | |
1174 | { | |
3f43c48d | 1175 | intel_attach_force_audio_property(connector); |
e953fd7b | 1176 | intel_attach_broadcast_rgb_property(connector); |
55bc60db | 1177 | intel_hdmi->color_range_auto = true; |
55b7d6e8 CW |
1178 | } |
1179 | ||
00c09d70 PZ |
1180 | void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port, |
1181 | struct intel_connector *intel_connector) | |
7d57382e | 1182 | { |
b9cb234c PZ |
1183 | struct drm_connector *connector = &intel_connector->base; |
1184 | struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi; | |
1185 | struct intel_encoder *intel_encoder = &intel_dig_port->base; | |
1186 | struct drm_device *dev = intel_encoder->base.dev; | |
7d57382e | 1187 | struct drm_i915_private *dev_priv = dev->dev_private; |
174edf1f | 1188 | enum port port = intel_dig_port->port; |
373a3cf7 | 1189 | |
7d57382e | 1190 | drm_connector_init(dev, connector, &intel_hdmi_connector_funcs, |
8d91104a | 1191 | DRM_MODE_CONNECTOR_HDMIA); |
7d57382e EA |
1192 | drm_connector_helper_add(connector, &intel_hdmi_connector_helper_funcs); |
1193 | ||
c3febcc4 | 1194 | connector->interlace_allowed = 1; |
7d57382e | 1195 | connector->doublescan_allowed = 0; |
573e74ad | 1196 | connector->stereo_allowed = 1; |
66a9278e | 1197 | |
08d644ad DV |
1198 | switch (port) { |
1199 | case PORT_B: | |
f899fc64 | 1200 | intel_hdmi->ddc_bus = GMBUS_PORT_DPB; |
1d843f9d | 1201 | intel_encoder->hpd_pin = HPD_PORT_B; |
08d644ad DV |
1202 | break; |
1203 | case PORT_C: | |
7ceae0a5 | 1204 | intel_hdmi->ddc_bus = GMBUS_PORT_DPC; |
1d843f9d | 1205 | intel_encoder->hpd_pin = HPD_PORT_C; |
08d644ad DV |
1206 | break; |
1207 | case PORT_D: | |
7ceae0a5 | 1208 | intel_hdmi->ddc_bus = GMBUS_PORT_DPD; |
1d843f9d | 1209 | intel_encoder->hpd_pin = HPD_PORT_D; |
08d644ad DV |
1210 | break; |
1211 | case PORT_A: | |
1d843f9d | 1212 | intel_encoder->hpd_pin = HPD_PORT_A; |
08d644ad DV |
1213 | /* Internal port only for eDP. */ |
1214 | default: | |
6e4c1677 | 1215 | BUG(); |
f8aed700 | 1216 | } |
7d57382e | 1217 | |
7637bfdb | 1218 | if (IS_VALLEYVIEW(dev)) { |
90b107c8 | 1219 | intel_hdmi->write_infoframe = vlv_write_infoframe; |
687f4d06 | 1220 | intel_hdmi->set_infoframes = vlv_set_infoframes; |
7637bfdb JB |
1221 | } else if (!HAS_PCH_SPLIT(dev)) { |
1222 | intel_hdmi->write_infoframe = g4x_write_infoframe; | |
1223 | intel_hdmi->set_infoframes = g4x_set_infoframes; | |
22b8bf17 | 1224 | } else if (HAS_DDI(dev)) { |
8c5f5f7c | 1225 | intel_hdmi->write_infoframe = hsw_write_infoframe; |
687f4d06 | 1226 | intel_hdmi->set_infoframes = hsw_set_infoframes; |
fdf1250a PZ |
1227 | } else if (HAS_PCH_IBX(dev)) { |
1228 | intel_hdmi->write_infoframe = ibx_write_infoframe; | |
687f4d06 | 1229 | intel_hdmi->set_infoframes = ibx_set_infoframes; |
fdf1250a PZ |
1230 | } else { |
1231 | intel_hdmi->write_infoframe = cpt_write_infoframe; | |
687f4d06 | 1232 | intel_hdmi->set_infoframes = cpt_set_infoframes; |
64a8fc01 | 1233 | } |
45187ace | 1234 | |
affa9354 | 1235 | if (HAS_DDI(dev)) |
bcbc889b PZ |
1236 | intel_connector->get_hw_state = intel_ddi_connector_get_hw_state; |
1237 | else | |
1238 | intel_connector->get_hw_state = intel_connector_get_hw_state; | |
b9cb234c PZ |
1239 | |
1240 | intel_hdmi_add_properties(intel_hdmi, connector); | |
1241 | ||
1242 | intel_connector_attach_encoder(intel_connector, intel_encoder); | |
1243 | drm_sysfs_connector_add(connector); | |
1244 | ||
1245 | /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written | |
1246 | * 0xd. Failure to do so will result in spurious interrupts being | |
1247 | * generated on the port when a cable is not attached. | |
1248 | */ | |
1249 | if (IS_G4X(dev) && !IS_GM45(dev)) { | |
1250 | u32 temp = I915_READ(PEG_BAND_GAP_DATA); | |
1251 | I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd); | |
1252 | } | |
1253 | } | |
1254 | ||
b242b7f7 | 1255 | void intel_hdmi_init(struct drm_device *dev, int hdmi_reg, enum port port) |
b9cb234c PZ |
1256 | { |
1257 | struct intel_digital_port *intel_dig_port; | |
1258 | struct intel_encoder *intel_encoder; | |
b9cb234c PZ |
1259 | struct intel_connector *intel_connector; |
1260 | ||
b14c5679 | 1261 | intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL); |
b9cb234c PZ |
1262 | if (!intel_dig_port) |
1263 | return; | |
1264 | ||
b14c5679 | 1265 | intel_connector = kzalloc(sizeof(*intel_connector), GFP_KERNEL); |
b9cb234c PZ |
1266 | if (!intel_connector) { |
1267 | kfree(intel_dig_port); | |
1268 | return; | |
1269 | } | |
1270 | ||
1271 | intel_encoder = &intel_dig_port->base; | |
b9cb234c PZ |
1272 | |
1273 | drm_encoder_init(dev, &intel_encoder->base, &intel_hdmi_enc_funcs, | |
1274 | DRM_MODE_ENCODER_TMDS); | |
00c09d70 | 1275 | |
5bfe2ac0 | 1276 | intel_encoder->compute_config = intel_hdmi_compute_config; |
c59423a3 | 1277 | intel_encoder->mode_set = intel_hdmi_mode_set; |
00c09d70 PZ |
1278 | intel_encoder->disable = intel_disable_hdmi; |
1279 | intel_encoder->get_hw_state = intel_hdmi_get_hw_state; | |
045ac3b5 | 1280 | intel_encoder->get_config = intel_hdmi_get_config; |
89b667f8 | 1281 | if (IS_VALLEYVIEW(dev)) { |
9514ac6e CML |
1282 | intel_encoder->pre_pll_enable = vlv_hdmi_pre_pll_enable; |
1283 | intel_encoder->pre_enable = vlv_hdmi_pre_enable; | |
b76cf76b | 1284 | intel_encoder->enable = vlv_enable_hdmi; |
9514ac6e | 1285 | intel_encoder->post_disable = vlv_hdmi_post_disable; |
b76cf76b JN |
1286 | } else { |
1287 | intel_encoder->enable = intel_enable_hdmi; | |
89b667f8 | 1288 | } |
5ab432ef | 1289 | |
b9cb234c PZ |
1290 | intel_encoder->type = INTEL_OUTPUT_HDMI; |
1291 | intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2); | |
1292 | intel_encoder->cloneable = false; | |
7d57382e | 1293 | |
174edf1f | 1294 | intel_dig_port->port = port; |
b242b7f7 | 1295 | intel_dig_port->hdmi.hdmi_reg = hdmi_reg; |
b9cb234c | 1296 | intel_dig_port->dp.output_reg = 0; |
55b7d6e8 | 1297 | |
b9cb234c | 1298 | intel_hdmi_init_connector(intel_dig_port, intel_connector); |
7d57382e | 1299 | } |