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7d57382e EA |
1 | /* |
2 | * Copyright 2006 Dave Airlie <airlied@linux.ie> | |
3 | * Copyright © 2006-2009 Intel Corporation | |
4 | * | |
5 | * Permission is hereby granted, free of charge, to any person obtaining a | |
6 | * copy of this software and associated documentation files (the "Software"), | |
7 | * to deal in the Software without restriction, including without limitation | |
8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
9 | * and/or sell copies of the Software, and to permit persons to whom the | |
10 | * Software is furnished to do so, subject to the following conditions: | |
11 | * | |
12 | * The above copyright notice and this permission notice (including the next | |
13 | * paragraph) shall be included in all copies or substantial portions of the | |
14 | * Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
21 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
22 | * DEALINGS IN THE SOFTWARE. | |
23 | * | |
24 | * Authors: | |
25 | * Eric Anholt <eric@anholt.net> | |
26 | * Jesse Barnes <jesse.barnes@intel.com> | |
27 | */ | |
28 | ||
29 | #include <linux/i2c.h> | |
5a0e3ad6 | 30 | #include <linux/slab.h> |
7d57382e | 31 | #include <linux/delay.h> |
760285e7 DH |
32 | #include <drm/drmP.h> |
33 | #include <drm/drm_crtc.h> | |
34 | #include <drm/drm_edid.h> | |
7d57382e | 35 | #include "intel_drv.h" |
760285e7 | 36 | #include <drm/i915_drm.h> |
7d57382e EA |
37 | #include "i915_drv.h" |
38 | ||
30add22d PZ |
39 | static struct drm_device *intel_hdmi_to_dev(struct intel_hdmi *intel_hdmi) |
40 | { | |
da63a9f2 | 41 | return hdmi_to_dig_port(intel_hdmi)->base.base.dev; |
30add22d PZ |
42 | } |
43 | ||
afba0188 DV |
44 | static void |
45 | assert_hdmi_port_disabled(struct intel_hdmi *intel_hdmi) | |
46 | { | |
30add22d | 47 | struct drm_device *dev = intel_hdmi_to_dev(intel_hdmi); |
afba0188 DV |
48 | struct drm_i915_private *dev_priv = dev->dev_private; |
49 | uint32_t enabled_bits; | |
50 | ||
affa9354 | 51 | enabled_bits = HAS_DDI(dev) ? DDI_BUF_CTL_ENABLE : SDVO_ENABLE; |
afba0188 | 52 | |
b242b7f7 | 53 | WARN(I915_READ(intel_hdmi->hdmi_reg) & enabled_bits, |
afba0188 DV |
54 | "HDMI port enabled, expecting disabled\n"); |
55 | } | |
56 | ||
f5bbfca3 | 57 | struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder) |
ea5b213a | 58 | { |
da63a9f2 PZ |
59 | struct intel_digital_port *intel_dig_port = |
60 | container_of(encoder, struct intel_digital_port, base.base); | |
61 | return &intel_dig_port->hdmi; | |
ea5b213a CW |
62 | } |
63 | ||
df0e9248 CW |
64 | static struct intel_hdmi *intel_attached_hdmi(struct drm_connector *connector) |
65 | { | |
da63a9f2 | 66 | return enc_to_intel_hdmi(&intel_attached_encoder(connector)->base); |
df0e9248 CW |
67 | } |
68 | ||
45187ace | 69 | void intel_dip_infoframe_csum(struct dip_infoframe *frame) |
3c17fe4b | 70 | { |
45187ace | 71 | uint8_t *data = (uint8_t *)frame; |
3c17fe4b DH |
72 | uint8_t sum = 0; |
73 | unsigned i; | |
74 | ||
45187ace JB |
75 | frame->checksum = 0; |
76 | frame->ecc = 0; | |
3c17fe4b | 77 | |
64a8fc01 | 78 | for (i = 0; i < frame->len + DIP_HEADER_SIZE; i++) |
3c17fe4b DH |
79 | sum += data[i]; |
80 | ||
45187ace | 81 | frame->checksum = 0x100 - sum; |
3c17fe4b DH |
82 | } |
83 | ||
bc2481f3 | 84 | static u32 g4x_infoframe_index(struct dip_infoframe *frame) |
3c17fe4b | 85 | { |
45187ace JB |
86 | switch (frame->type) { |
87 | case DIP_TYPE_AVI: | |
ed517fbb | 88 | return VIDEO_DIP_SELECT_AVI; |
45187ace | 89 | case DIP_TYPE_SPD: |
ed517fbb | 90 | return VIDEO_DIP_SELECT_SPD; |
45187ace JB |
91 | default: |
92 | DRM_DEBUG_DRIVER("unknown info frame type %d\n", frame->type); | |
ed517fbb | 93 | return 0; |
45187ace | 94 | } |
45187ace JB |
95 | } |
96 | ||
bc2481f3 | 97 | static u32 g4x_infoframe_enable(struct dip_infoframe *frame) |
45187ace | 98 | { |
45187ace JB |
99 | switch (frame->type) { |
100 | case DIP_TYPE_AVI: | |
ed517fbb | 101 | return VIDEO_DIP_ENABLE_AVI; |
45187ace | 102 | case DIP_TYPE_SPD: |
ed517fbb | 103 | return VIDEO_DIP_ENABLE_SPD; |
fa193ff7 PZ |
104 | default: |
105 | DRM_DEBUG_DRIVER("unknown info frame type %d\n", frame->type); | |
ed517fbb | 106 | return 0; |
fa193ff7 | 107 | } |
fa193ff7 PZ |
108 | } |
109 | ||
2da8af54 PZ |
110 | static u32 hsw_infoframe_enable(struct dip_infoframe *frame) |
111 | { | |
112 | switch (frame->type) { | |
113 | case DIP_TYPE_AVI: | |
114 | return VIDEO_DIP_ENABLE_AVI_HSW; | |
115 | case DIP_TYPE_SPD: | |
116 | return VIDEO_DIP_ENABLE_SPD_HSW; | |
117 | default: | |
118 | DRM_DEBUG_DRIVER("unknown info frame type %d\n", frame->type); | |
119 | return 0; | |
120 | } | |
121 | } | |
122 | ||
7d9bcebe RV |
123 | static u32 hsw_infoframe_data_reg(struct dip_infoframe *frame, |
124 | enum transcoder cpu_transcoder) | |
2da8af54 PZ |
125 | { |
126 | switch (frame->type) { | |
127 | case DIP_TYPE_AVI: | |
7d9bcebe | 128 | return HSW_TVIDEO_DIP_AVI_DATA(cpu_transcoder); |
2da8af54 | 129 | case DIP_TYPE_SPD: |
7d9bcebe | 130 | return HSW_TVIDEO_DIP_SPD_DATA(cpu_transcoder); |
2da8af54 PZ |
131 | default: |
132 | DRM_DEBUG_DRIVER("unknown info frame type %d\n", frame->type); | |
133 | return 0; | |
134 | } | |
135 | } | |
136 | ||
a3da1df7 DV |
137 | static void g4x_write_infoframe(struct drm_encoder *encoder, |
138 | struct dip_infoframe *frame) | |
45187ace JB |
139 | { |
140 | uint32_t *data = (uint32_t *)frame; | |
3c17fe4b DH |
141 | struct drm_device *dev = encoder->dev; |
142 | struct drm_i915_private *dev_priv = dev->dev_private; | |
22509ec8 | 143 | u32 val = I915_READ(VIDEO_DIP_CTL); |
45187ace | 144 | unsigned i, len = DIP_HEADER_SIZE + frame->len; |
3c17fe4b | 145 | |
822974ae PZ |
146 | WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n"); |
147 | ||
1d4f85ac | 148 | val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ |
bc2481f3 | 149 | val |= g4x_infoframe_index(frame); |
22509ec8 | 150 | |
bc2481f3 | 151 | val &= ~g4x_infoframe_enable(frame); |
45187ace | 152 | |
22509ec8 | 153 | I915_WRITE(VIDEO_DIP_CTL, val); |
3c17fe4b | 154 | |
9d9740f0 | 155 | mmiowb(); |
45187ace | 156 | for (i = 0; i < len; i += 4) { |
3c17fe4b DH |
157 | I915_WRITE(VIDEO_DIP_DATA, *data); |
158 | data++; | |
159 | } | |
adf00b26 PZ |
160 | /* Write every possible data byte to force correct ECC calculation. */ |
161 | for (; i < VIDEO_DIP_DATA_SIZE; i += 4) | |
162 | I915_WRITE(VIDEO_DIP_DATA, 0); | |
9d9740f0 | 163 | mmiowb(); |
3c17fe4b | 164 | |
bc2481f3 | 165 | val |= g4x_infoframe_enable(frame); |
60c5ea2d | 166 | val &= ~VIDEO_DIP_FREQ_MASK; |
4b24c933 | 167 | val |= VIDEO_DIP_FREQ_VSYNC; |
45187ace | 168 | |
22509ec8 | 169 | I915_WRITE(VIDEO_DIP_CTL, val); |
9d9740f0 | 170 | POSTING_READ(VIDEO_DIP_CTL); |
3c17fe4b DH |
171 | } |
172 | ||
fdf1250a PZ |
173 | static void ibx_write_infoframe(struct drm_encoder *encoder, |
174 | struct dip_infoframe *frame) | |
175 | { | |
176 | uint32_t *data = (uint32_t *)frame; | |
177 | struct drm_device *dev = encoder->dev; | |
178 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ed517fbb | 179 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); |
fdf1250a PZ |
180 | int reg = TVIDEO_DIP_CTL(intel_crtc->pipe); |
181 | unsigned i, len = DIP_HEADER_SIZE + frame->len; | |
182 | u32 val = I915_READ(reg); | |
183 | ||
822974ae PZ |
184 | WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n"); |
185 | ||
fdf1250a | 186 | val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ |
bc2481f3 | 187 | val |= g4x_infoframe_index(frame); |
fdf1250a | 188 | |
bc2481f3 | 189 | val &= ~g4x_infoframe_enable(frame); |
fdf1250a PZ |
190 | |
191 | I915_WRITE(reg, val); | |
192 | ||
9d9740f0 | 193 | mmiowb(); |
fdf1250a PZ |
194 | for (i = 0; i < len; i += 4) { |
195 | I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data); | |
196 | data++; | |
197 | } | |
adf00b26 PZ |
198 | /* Write every possible data byte to force correct ECC calculation. */ |
199 | for (; i < VIDEO_DIP_DATA_SIZE; i += 4) | |
200 | I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0); | |
9d9740f0 | 201 | mmiowb(); |
fdf1250a | 202 | |
bc2481f3 | 203 | val |= g4x_infoframe_enable(frame); |
fdf1250a | 204 | val &= ~VIDEO_DIP_FREQ_MASK; |
4b24c933 | 205 | val |= VIDEO_DIP_FREQ_VSYNC; |
fdf1250a PZ |
206 | |
207 | I915_WRITE(reg, val); | |
9d9740f0 | 208 | POSTING_READ(reg); |
fdf1250a PZ |
209 | } |
210 | ||
211 | static void cpt_write_infoframe(struct drm_encoder *encoder, | |
212 | struct dip_infoframe *frame) | |
b055c8f3 | 213 | { |
45187ace | 214 | uint32_t *data = (uint32_t *)frame; |
b055c8f3 JB |
215 | struct drm_device *dev = encoder->dev; |
216 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ed517fbb | 217 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); |
b055c8f3 | 218 | int reg = TVIDEO_DIP_CTL(intel_crtc->pipe); |
45187ace | 219 | unsigned i, len = DIP_HEADER_SIZE + frame->len; |
22509ec8 | 220 | u32 val = I915_READ(reg); |
b055c8f3 | 221 | |
822974ae PZ |
222 | WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n"); |
223 | ||
64a8fc01 | 224 | val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ |
bc2481f3 | 225 | val |= g4x_infoframe_index(frame); |
45187ace | 226 | |
ecb97851 PZ |
227 | /* The DIP control register spec says that we need to update the AVI |
228 | * infoframe without clearing its enable bit */ | |
822974ae | 229 | if (frame->type != DIP_TYPE_AVI) |
bc2481f3 | 230 | val &= ~g4x_infoframe_enable(frame); |
ecb97851 | 231 | |
22509ec8 | 232 | I915_WRITE(reg, val); |
45187ace | 233 | |
9d9740f0 | 234 | mmiowb(); |
45187ace | 235 | for (i = 0; i < len; i += 4) { |
b055c8f3 JB |
236 | I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data); |
237 | data++; | |
238 | } | |
adf00b26 PZ |
239 | /* Write every possible data byte to force correct ECC calculation. */ |
240 | for (; i < VIDEO_DIP_DATA_SIZE; i += 4) | |
241 | I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0); | |
9d9740f0 | 242 | mmiowb(); |
b055c8f3 | 243 | |
bc2481f3 | 244 | val |= g4x_infoframe_enable(frame); |
60c5ea2d | 245 | val &= ~VIDEO_DIP_FREQ_MASK; |
4b24c933 | 246 | val |= VIDEO_DIP_FREQ_VSYNC; |
45187ace | 247 | |
22509ec8 | 248 | I915_WRITE(reg, val); |
9d9740f0 | 249 | POSTING_READ(reg); |
45187ace | 250 | } |
90b107c8 SK |
251 | |
252 | static void vlv_write_infoframe(struct drm_encoder *encoder, | |
253 | struct dip_infoframe *frame) | |
254 | { | |
255 | uint32_t *data = (uint32_t *)frame; | |
256 | struct drm_device *dev = encoder->dev; | |
257 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ed517fbb | 258 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); |
90b107c8 SK |
259 | int reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe); |
260 | unsigned i, len = DIP_HEADER_SIZE + frame->len; | |
22509ec8 | 261 | u32 val = I915_READ(reg); |
90b107c8 | 262 | |
822974ae PZ |
263 | WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n"); |
264 | ||
90b107c8 | 265 | val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ |
bc2481f3 | 266 | val |= g4x_infoframe_index(frame); |
22509ec8 | 267 | |
bc2481f3 | 268 | val &= ~g4x_infoframe_enable(frame); |
90b107c8 | 269 | |
22509ec8 | 270 | I915_WRITE(reg, val); |
90b107c8 | 271 | |
9d9740f0 | 272 | mmiowb(); |
90b107c8 SK |
273 | for (i = 0; i < len; i += 4) { |
274 | I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), *data); | |
275 | data++; | |
276 | } | |
adf00b26 PZ |
277 | /* Write every possible data byte to force correct ECC calculation. */ |
278 | for (; i < VIDEO_DIP_DATA_SIZE; i += 4) | |
279 | I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), 0); | |
9d9740f0 | 280 | mmiowb(); |
90b107c8 | 281 | |
bc2481f3 | 282 | val |= g4x_infoframe_enable(frame); |
60c5ea2d | 283 | val &= ~VIDEO_DIP_FREQ_MASK; |
4b24c933 | 284 | val |= VIDEO_DIP_FREQ_VSYNC; |
90b107c8 | 285 | |
22509ec8 | 286 | I915_WRITE(reg, val); |
9d9740f0 | 287 | POSTING_READ(reg); |
90b107c8 SK |
288 | } |
289 | ||
8c5f5f7c | 290 | static void hsw_write_infoframe(struct drm_encoder *encoder, |
ed517fbb | 291 | struct dip_infoframe *frame) |
8c5f5f7c | 292 | { |
2da8af54 PZ |
293 | uint32_t *data = (uint32_t *)frame; |
294 | struct drm_device *dev = encoder->dev; | |
295 | struct drm_i915_private *dev_priv = dev->dev_private; | |
296 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); | |
7d9bcebe RV |
297 | u32 ctl_reg = HSW_TVIDEO_DIP_CTL(intel_crtc->cpu_transcoder); |
298 | u32 data_reg = hsw_infoframe_data_reg(frame, intel_crtc->cpu_transcoder); | |
2da8af54 PZ |
299 | unsigned int i, len = DIP_HEADER_SIZE + frame->len; |
300 | u32 val = I915_READ(ctl_reg); | |
8c5f5f7c | 301 | |
2da8af54 PZ |
302 | if (data_reg == 0) |
303 | return; | |
304 | ||
2da8af54 PZ |
305 | val &= ~hsw_infoframe_enable(frame); |
306 | I915_WRITE(ctl_reg, val); | |
307 | ||
9d9740f0 | 308 | mmiowb(); |
2da8af54 PZ |
309 | for (i = 0; i < len; i += 4) { |
310 | I915_WRITE(data_reg + i, *data); | |
311 | data++; | |
312 | } | |
adf00b26 PZ |
313 | /* Write every possible data byte to force correct ECC calculation. */ |
314 | for (; i < VIDEO_DIP_DATA_SIZE; i += 4) | |
315 | I915_WRITE(data_reg + i, 0); | |
9d9740f0 | 316 | mmiowb(); |
8c5f5f7c | 317 | |
2da8af54 PZ |
318 | val |= hsw_infoframe_enable(frame); |
319 | I915_WRITE(ctl_reg, val); | |
9d9740f0 | 320 | POSTING_READ(ctl_reg); |
8c5f5f7c ED |
321 | } |
322 | ||
45187ace JB |
323 | static void intel_set_infoframe(struct drm_encoder *encoder, |
324 | struct dip_infoframe *frame) | |
325 | { | |
326 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); | |
327 | ||
45187ace JB |
328 | intel_dip_infoframe_csum(frame); |
329 | intel_hdmi->write_infoframe(encoder, frame); | |
330 | } | |
331 | ||
687f4d06 | 332 | static void intel_hdmi_set_avi_infoframe(struct drm_encoder *encoder, |
c846b619 | 333 | struct drm_display_mode *adjusted_mode) |
45187ace | 334 | { |
abedc077 | 335 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); |
45187ace JB |
336 | struct dip_infoframe avi_if = { |
337 | .type = DIP_TYPE_AVI, | |
338 | .ver = DIP_VERSION_AVI, | |
339 | .len = DIP_LEN_AVI, | |
340 | }; | |
341 | ||
c846b619 PZ |
342 | if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK) |
343 | avi_if.body.avi.YQ_CN_PR |= DIP_AVI_PR_2; | |
344 | ||
abedc077 VS |
345 | if (intel_hdmi->rgb_quant_range_selectable) { |
346 | if (adjusted_mode->private_flags & INTEL_MODE_LIMITED_COLOR_RANGE) | |
347 | avi_if.body.avi.ITC_EC_Q_SC |= DIP_AVI_RGB_QUANT_RANGE_LIMITED; | |
348 | else | |
349 | avi_if.body.avi.ITC_EC_Q_SC |= DIP_AVI_RGB_QUANT_RANGE_FULL; | |
350 | } | |
351 | ||
9a69b885 PZ |
352 | avi_if.body.avi.VIC = drm_mode_cea_vic(adjusted_mode); |
353 | ||
45187ace | 354 | intel_set_infoframe(encoder, &avi_if); |
b055c8f3 JB |
355 | } |
356 | ||
687f4d06 | 357 | static void intel_hdmi_set_spd_infoframe(struct drm_encoder *encoder) |
c0864cb3 JB |
358 | { |
359 | struct dip_infoframe spd_if; | |
360 | ||
361 | memset(&spd_if, 0, sizeof(spd_if)); | |
362 | spd_if.type = DIP_TYPE_SPD; | |
363 | spd_if.ver = DIP_VERSION_SPD; | |
364 | spd_if.len = DIP_LEN_SPD; | |
365 | strcpy(spd_if.body.spd.vn, "Intel"); | |
366 | strcpy(spd_if.body.spd.pd, "Integrated gfx"); | |
367 | spd_if.body.spd.sdi = DIP_SPD_PC; | |
368 | ||
369 | intel_set_infoframe(encoder, &spd_if); | |
370 | } | |
371 | ||
687f4d06 PZ |
372 | static void g4x_set_infoframes(struct drm_encoder *encoder, |
373 | struct drm_display_mode *adjusted_mode) | |
374 | { | |
0c14c7f9 | 375 | struct drm_i915_private *dev_priv = encoder->dev->dev_private; |
69fde0a6 VS |
376 | struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); |
377 | struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi; | |
0c14c7f9 PZ |
378 | u32 reg = VIDEO_DIP_CTL; |
379 | u32 val = I915_READ(reg); | |
72b78c9d | 380 | u32 port; |
0c14c7f9 | 381 | |
afba0188 DV |
382 | assert_hdmi_port_disabled(intel_hdmi); |
383 | ||
0c14c7f9 PZ |
384 | /* If the registers were not initialized yet, they might be zeroes, |
385 | * which means we're selecting the AVI DIP and we're setting its | |
386 | * frequency to once. This seems to really confuse the HW and make | |
387 | * things stop working (the register spec says the AVI always needs to | |
388 | * be sent every VSync). So here we avoid writing to the register more | |
389 | * than we need and also explicitly select the AVI DIP and explicitly | |
390 | * set its frequency to every VSync. Avoiding to write it twice seems to | |
391 | * be enough to solve the problem, but being defensive shouldn't hurt us | |
392 | * either. */ | |
393 | val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; | |
394 | ||
395 | if (!intel_hdmi->has_hdmi_sink) { | |
396 | if (!(val & VIDEO_DIP_ENABLE)) | |
397 | return; | |
398 | val &= ~VIDEO_DIP_ENABLE; | |
399 | I915_WRITE(reg, val); | |
9d9740f0 | 400 | POSTING_READ(reg); |
0c14c7f9 PZ |
401 | return; |
402 | } | |
403 | ||
69fde0a6 VS |
404 | switch (intel_dig_port->port) { |
405 | case PORT_B: | |
72b78c9d | 406 | port = VIDEO_DIP_PORT_B; |
f278d972 | 407 | break; |
69fde0a6 | 408 | case PORT_C: |
72b78c9d | 409 | port = VIDEO_DIP_PORT_C; |
f278d972 PZ |
410 | break; |
411 | default: | |
57df2ae9 | 412 | BUG(); |
f278d972 PZ |
413 | return; |
414 | } | |
415 | ||
72b78c9d PZ |
416 | if (port != (val & VIDEO_DIP_PORT_MASK)) { |
417 | if (val & VIDEO_DIP_ENABLE) { | |
418 | val &= ~VIDEO_DIP_ENABLE; | |
419 | I915_WRITE(reg, val); | |
9d9740f0 | 420 | POSTING_READ(reg); |
72b78c9d PZ |
421 | } |
422 | val &= ~VIDEO_DIP_PORT_MASK; | |
423 | val |= port; | |
424 | } | |
425 | ||
822974ae | 426 | val |= VIDEO_DIP_ENABLE; |
0dd87d20 | 427 | val &= ~VIDEO_DIP_ENABLE_VENDOR; |
822974ae | 428 | |
f278d972 | 429 | I915_WRITE(reg, val); |
9d9740f0 | 430 | POSTING_READ(reg); |
f278d972 | 431 | |
687f4d06 PZ |
432 | intel_hdmi_set_avi_infoframe(encoder, adjusted_mode); |
433 | intel_hdmi_set_spd_infoframe(encoder); | |
434 | } | |
435 | ||
436 | static void ibx_set_infoframes(struct drm_encoder *encoder, | |
437 | struct drm_display_mode *adjusted_mode) | |
438 | { | |
0c14c7f9 PZ |
439 | struct drm_i915_private *dev_priv = encoder->dev->dev_private; |
440 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); | |
69fde0a6 VS |
441 | struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); |
442 | struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi; | |
0c14c7f9 PZ |
443 | u32 reg = TVIDEO_DIP_CTL(intel_crtc->pipe); |
444 | u32 val = I915_READ(reg); | |
72b78c9d | 445 | u32 port; |
0c14c7f9 | 446 | |
afba0188 DV |
447 | assert_hdmi_port_disabled(intel_hdmi); |
448 | ||
0c14c7f9 PZ |
449 | /* See the big comment in g4x_set_infoframes() */ |
450 | val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; | |
451 | ||
452 | if (!intel_hdmi->has_hdmi_sink) { | |
453 | if (!(val & VIDEO_DIP_ENABLE)) | |
454 | return; | |
455 | val &= ~VIDEO_DIP_ENABLE; | |
456 | I915_WRITE(reg, val); | |
9d9740f0 | 457 | POSTING_READ(reg); |
0c14c7f9 PZ |
458 | return; |
459 | } | |
460 | ||
69fde0a6 VS |
461 | switch (intel_dig_port->port) { |
462 | case PORT_B: | |
72b78c9d | 463 | port = VIDEO_DIP_PORT_B; |
f278d972 | 464 | break; |
69fde0a6 | 465 | case PORT_C: |
72b78c9d | 466 | port = VIDEO_DIP_PORT_C; |
f278d972 | 467 | break; |
69fde0a6 | 468 | case PORT_D: |
72b78c9d | 469 | port = VIDEO_DIP_PORT_D; |
f278d972 PZ |
470 | break; |
471 | default: | |
57df2ae9 | 472 | BUG(); |
f278d972 PZ |
473 | return; |
474 | } | |
475 | ||
72b78c9d PZ |
476 | if (port != (val & VIDEO_DIP_PORT_MASK)) { |
477 | if (val & VIDEO_DIP_ENABLE) { | |
478 | val &= ~VIDEO_DIP_ENABLE; | |
479 | I915_WRITE(reg, val); | |
9d9740f0 | 480 | POSTING_READ(reg); |
72b78c9d PZ |
481 | } |
482 | val &= ~VIDEO_DIP_PORT_MASK; | |
483 | val |= port; | |
484 | } | |
485 | ||
822974ae | 486 | val |= VIDEO_DIP_ENABLE; |
0dd87d20 PZ |
487 | val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | |
488 | VIDEO_DIP_ENABLE_GCP); | |
822974ae | 489 | |
f278d972 | 490 | I915_WRITE(reg, val); |
9d9740f0 | 491 | POSTING_READ(reg); |
f278d972 | 492 | |
687f4d06 PZ |
493 | intel_hdmi_set_avi_infoframe(encoder, adjusted_mode); |
494 | intel_hdmi_set_spd_infoframe(encoder); | |
495 | } | |
496 | ||
497 | static void cpt_set_infoframes(struct drm_encoder *encoder, | |
498 | struct drm_display_mode *adjusted_mode) | |
499 | { | |
0c14c7f9 PZ |
500 | struct drm_i915_private *dev_priv = encoder->dev->dev_private; |
501 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); | |
502 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); | |
503 | u32 reg = TVIDEO_DIP_CTL(intel_crtc->pipe); | |
504 | u32 val = I915_READ(reg); | |
505 | ||
afba0188 DV |
506 | assert_hdmi_port_disabled(intel_hdmi); |
507 | ||
0c14c7f9 PZ |
508 | /* See the big comment in g4x_set_infoframes() */ |
509 | val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; | |
510 | ||
511 | if (!intel_hdmi->has_hdmi_sink) { | |
512 | if (!(val & VIDEO_DIP_ENABLE)) | |
513 | return; | |
514 | val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI); | |
515 | I915_WRITE(reg, val); | |
9d9740f0 | 516 | POSTING_READ(reg); |
0c14c7f9 PZ |
517 | return; |
518 | } | |
519 | ||
822974ae PZ |
520 | /* Set both together, unset both together: see the spec. */ |
521 | val |= VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI; | |
0dd87d20 PZ |
522 | val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | |
523 | VIDEO_DIP_ENABLE_GCP); | |
822974ae PZ |
524 | |
525 | I915_WRITE(reg, val); | |
9d9740f0 | 526 | POSTING_READ(reg); |
822974ae | 527 | |
687f4d06 PZ |
528 | intel_hdmi_set_avi_infoframe(encoder, adjusted_mode); |
529 | intel_hdmi_set_spd_infoframe(encoder); | |
530 | } | |
531 | ||
532 | static void vlv_set_infoframes(struct drm_encoder *encoder, | |
533 | struct drm_display_mode *adjusted_mode) | |
534 | { | |
0c14c7f9 PZ |
535 | struct drm_i915_private *dev_priv = encoder->dev->dev_private; |
536 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); | |
537 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); | |
538 | u32 reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe); | |
539 | u32 val = I915_READ(reg); | |
540 | ||
afba0188 DV |
541 | assert_hdmi_port_disabled(intel_hdmi); |
542 | ||
0c14c7f9 PZ |
543 | /* See the big comment in g4x_set_infoframes() */ |
544 | val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; | |
545 | ||
546 | if (!intel_hdmi->has_hdmi_sink) { | |
547 | if (!(val & VIDEO_DIP_ENABLE)) | |
548 | return; | |
549 | val &= ~VIDEO_DIP_ENABLE; | |
550 | I915_WRITE(reg, val); | |
9d9740f0 | 551 | POSTING_READ(reg); |
0c14c7f9 PZ |
552 | return; |
553 | } | |
554 | ||
822974ae | 555 | val |= VIDEO_DIP_ENABLE; |
0dd87d20 PZ |
556 | val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | |
557 | VIDEO_DIP_ENABLE_GCP); | |
822974ae PZ |
558 | |
559 | I915_WRITE(reg, val); | |
9d9740f0 | 560 | POSTING_READ(reg); |
822974ae | 561 | |
687f4d06 PZ |
562 | intel_hdmi_set_avi_infoframe(encoder, adjusted_mode); |
563 | intel_hdmi_set_spd_infoframe(encoder); | |
564 | } | |
565 | ||
566 | static void hsw_set_infoframes(struct drm_encoder *encoder, | |
567 | struct drm_display_mode *adjusted_mode) | |
568 | { | |
0c14c7f9 PZ |
569 | struct drm_i915_private *dev_priv = encoder->dev->dev_private; |
570 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); | |
571 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); | |
7d9bcebe | 572 | u32 reg = HSW_TVIDEO_DIP_CTL(intel_crtc->cpu_transcoder); |
0dd87d20 | 573 | u32 val = I915_READ(reg); |
0c14c7f9 | 574 | |
afba0188 DV |
575 | assert_hdmi_port_disabled(intel_hdmi); |
576 | ||
0c14c7f9 PZ |
577 | if (!intel_hdmi->has_hdmi_sink) { |
578 | I915_WRITE(reg, 0); | |
9d9740f0 | 579 | POSTING_READ(reg); |
0c14c7f9 PZ |
580 | return; |
581 | } | |
582 | ||
0dd87d20 PZ |
583 | val &= ~(VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_GCP_HSW | |
584 | VIDEO_DIP_ENABLE_VS_HSW | VIDEO_DIP_ENABLE_GMP_HSW); | |
585 | ||
586 | I915_WRITE(reg, val); | |
9d9740f0 | 587 | POSTING_READ(reg); |
0dd87d20 | 588 | |
687f4d06 PZ |
589 | intel_hdmi_set_avi_infoframe(encoder, adjusted_mode); |
590 | intel_hdmi_set_spd_infoframe(encoder); | |
591 | } | |
592 | ||
7d57382e EA |
593 | static void intel_hdmi_mode_set(struct drm_encoder *encoder, |
594 | struct drm_display_mode *mode, | |
595 | struct drm_display_mode *adjusted_mode) | |
596 | { | |
597 | struct drm_device *dev = encoder->dev; | |
598 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ed517fbb | 599 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); |
ea5b213a | 600 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); |
b242b7f7 | 601 | u32 hdmi_val; |
7d57382e | 602 | |
b242b7f7 | 603 | hdmi_val = SDVO_ENCODING_HDMI; |
5d4fac97 | 604 | if (!HAS_PCH_SPLIT(dev)) |
b242b7f7 | 605 | hdmi_val |= intel_hdmi->color_range; |
b599c0bc | 606 | if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) |
b242b7f7 | 607 | hdmi_val |= SDVO_VSYNC_ACTIVE_HIGH; |
b599c0bc | 608 | if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) |
b242b7f7 | 609 | hdmi_val |= SDVO_HSYNC_ACTIVE_HIGH; |
7d57382e | 610 | |
020f6704 | 611 | if (intel_crtc->bpp > 24) |
b242b7f7 | 612 | hdmi_val |= COLOR_FORMAT_12bpc; |
020f6704 | 613 | else |
b242b7f7 | 614 | hdmi_val |= COLOR_FORMAT_8bpc; |
020f6704 | 615 | |
2e3d6006 ZW |
616 | /* Required on CPT */ |
617 | if (intel_hdmi->has_hdmi_sink && HAS_PCH_CPT(dev)) | |
b242b7f7 | 618 | hdmi_val |= HDMI_MODE_SELECT; |
2e3d6006 | 619 | |
3c17fe4b | 620 | if (intel_hdmi->has_audio) { |
e0dac65e WF |
621 | DRM_DEBUG_DRIVER("Enabling HDMI audio on pipe %c\n", |
622 | pipe_name(intel_crtc->pipe)); | |
b242b7f7 PZ |
623 | hdmi_val |= SDVO_AUDIO_ENABLE; |
624 | hdmi_val |= SDVO_NULL_PACKETS_DURING_VSYNC; | |
e0dac65e | 625 | intel_write_eld(encoder, adjusted_mode); |
3c17fe4b | 626 | } |
7d57382e | 627 | |
75770564 | 628 | if (HAS_PCH_CPT(dev)) |
b242b7f7 | 629 | hdmi_val |= PORT_TRANS_SEL_CPT(intel_crtc->pipe); |
7a87c289 | 630 | else if (intel_crtc->pipe == PIPE_B) |
b242b7f7 | 631 | hdmi_val |= SDVO_PIPE_B_SELECT; |
7d57382e | 632 | |
b242b7f7 PZ |
633 | I915_WRITE(intel_hdmi->hdmi_reg, hdmi_val); |
634 | POSTING_READ(intel_hdmi->hdmi_reg); | |
3c17fe4b | 635 | |
687f4d06 | 636 | intel_hdmi->set_infoframes(encoder, adjusted_mode); |
7d57382e EA |
637 | } |
638 | ||
85234cdc DV |
639 | static bool intel_hdmi_get_hw_state(struct intel_encoder *encoder, |
640 | enum pipe *pipe) | |
7d57382e | 641 | { |
85234cdc | 642 | struct drm_device *dev = encoder->base.dev; |
7d57382e | 643 | struct drm_i915_private *dev_priv = dev->dev_private; |
85234cdc DV |
644 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); |
645 | u32 tmp; | |
646 | ||
b242b7f7 | 647 | tmp = I915_READ(intel_hdmi->hdmi_reg); |
85234cdc DV |
648 | |
649 | if (!(tmp & SDVO_ENABLE)) | |
650 | return false; | |
651 | ||
652 | if (HAS_PCH_CPT(dev)) | |
653 | *pipe = PORT_TO_PIPE_CPT(tmp); | |
654 | else | |
655 | *pipe = PORT_TO_PIPE(tmp); | |
656 | ||
657 | return true; | |
658 | } | |
659 | ||
5ab432ef | 660 | static void intel_enable_hdmi(struct intel_encoder *encoder) |
7d57382e | 661 | { |
5ab432ef | 662 | struct drm_device *dev = encoder->base.dev; |
7d57382e | 663 | struct drm_i915_private *dev_priv = dev->dev_private; |
5ab432ef | 664 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); |
7d57382e | 665 | u32 temp; |
2deed761 WF |
666 | u32 enable_bits = SDVO_ENABLE; |
667 | ||
668 | if (intel_hdmi->has_audio) | |
669 | enable_bits |= SDVO_AUDIO_ENABLE; | |
7d57382e | 670 | |
b242b7f7 | 671 | temp = I915_READ(intel_hdmi->hdmi_reg); |
d8a2d0e0 | 672 | |
7a87c289 DV |
673 | /* HW workaround for IBX, we need to move the port to transcoder A |
674 | * before disabling it. */ | |
675 | if (HAS_PCH_IBX(dev)) { | |
5ab432ef | 676 | struct drm_crtc *crtc = encoder->base.crtc; |
7a87c289 DV |
677 | int pipe = crtc ? to_intel_crtc(crtc)->pipe : -1; |
678 | ||
5ab432ef DV |
679 | /* Restore the transcoder select bit. */ |
680 | if (pipe == PIPE_B) | |
681 | enable_bits |= SDVO_PIPE_B_SELECT; | |
7a87c289 DV |
682 | } |
683 | ||
d8a2d0e0 ZW |
684 | /* HW workaround, need to toggle enable bit off and on for 12bpc, but |
685 | * we do this anyway which shows more stable in testing. | |
686 | */ | |
c619eed4 | 687 | if (HAS_PCH_SPLIT(dev)) { |
b242b7f7 PZ |
688 | I915_WRITE(intel_hdmi->hdmi_reg, temp & ~SDVO_ENABLE); |
689 | POSTING_READ(intel_hdmi->hdmi_reg); | |
d8a2d0e0 ZW |
690 | } |
691 | ||
5ab432ef DV |
692 | temp |= enable_bits; |
693 | ||
b242b7f7 PZ |
694 | I915_WRITE(intel_hdmi->hdmi_reg, temp); |
695 | POSTING_READ(intel_hdmi->hdmi_reg); | |
5ab432ef DV |
696 | |
697 | /* HW workaround, need to write this twice for issue that may result | |
698 | * in first write getting masked. | |
699 | */ | |
700 | if (HAS_PCH_SPLIT(dev)) { | |
b242b7f7 PZ |
701 | I915_WRITE(intel_hdmi->hdmi_reg, temp); |
702 | POSTING_READ(intel_hdmi->hdmi_reg); | |
7d57382e | 703 | } |
5ab432ef DV |
704 | } |
705 | ||
706 | static void intel_disable_hdmi(struct intel_encoder *encoder) | |
707 | { | |
708 | struct drm_device *dev = encoder->base.dev; | |
709 | struct drm_i915_private *dev_priv = dev->dev_private; | |
710 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); | |
711 | u32 temp; | |
3cce574f | 712 | u32 enable_bits = SDVO_ENABLE | SDVO_AUDIO_ENABLE; |
5ab432ef | 713 | |
b242b7f7 | 714 | temp = I915_READ(intel_hdmi->hdmi_reg); |
5ab432ef DV |
715 | |
716 | /* HW workaround for IBX, we need to move the port to transcoder A | |
717 | * before disabling it. */ | |
718 | if (HAS_PCH_IBX(dev)) { | |
719 | struct drm_crtc *crtc = encoder->base.crtc; | |
720 | int pipe = crtc ? to_intel_crtc(crtc)->pipe : -1; | |
721 | ||
722 | if (temp & SDVO_PIPE_B_SELECT) { | |
723 | temp &= ~SDVO_PIPE_B_SELECT; | |
b242b7f7 PZ |
724 | I915_WRITE(intel_hdmi->hdmi_reg, temp); |
725 | POSTING_READ(intel_hdmi->hdmi_reg); | |
5ab432ef DV |
726 | |
727 | /* Again we need to write this twice. */ | |
b242b7f7 PZ |
728 | I915_WRITE(intel_hdmi->hdmi_reg, temp); |
729 | POSTING_READ(intel_hdmi->hdmi_reg); | |
5ab432ef DV |
730 | |
731 | /* Transcoder selection bits only update | |
732 | * effectively on vblank. */ | |
733 | if (crtc) | |
734 | intel_wait_for_vblank(dev, pipe); | |
735 | else | |
736 | msleep(50); | |
737 | } | |
7d57382e | 738 | } |
d8a2d0e0 | 739 | |
5ab432ef DV |
740 | /* HW workaround, need to toggle enable bit off and on for 12bpc, but |
741 | * we do this anyway which shows more stable in testing. | |
742 | */ | |
743 | if (HAS_PCH_SPLIT(dev)) { | |
b242b7f7 PZ |
744 | I915_WRITE(intel_hdmi->hdmi_reg, temp & ~SDVO_ENABLE); |
745 | POSTING_READ(intel_hdmi->hdmi_reg); | |
5ab432ef DV |
746 | } |
747 | ||
748 | temp &= ~enable_bits; | |
d8a2d0e0 | 749 | |
b242b7f7 PZ |
750 | I915_WRITE(intel_hdmi->hdmi_reg, temp); |
751 | POSTING_READ(intel_hdmi->hdmi_reg); | |
d8a2d0e0 ZW |
752 | |
753 | /* HW workaround, need to write this twice for issue that may result | |
754 | * in first write getting masked. | |
755 | */ | |
c619eed4 | 756 | if (HAS_PCH_SPLIT(dev)) { |
b242b7f7 PZ |
757 | I915_WRITE(intel_hdmi->hdmi_reg, temp); |
758 | POSTING_READ(intel_hdmi->hdmi_reg); | |
d8a2d0e0 | 759 | } |
7d57382e EA |
760 | } |
761 | ||
7d57382e EA |
762 | static int intel_hdmi_mode_valid(struct drm_connector *connector, |
763 | struct drm_display_mode *mode) | |
764 | { | |
765 | if (mode->clock > 165000) | |
766 | return MODE_CLOCK_HIGH; | |
767 | if (mode->clock < 20000) | |
5cbba41d | 768 | return MODE_CLOCK_LOW; |
7d57382e EA |
769 | |
770 | if (mode->flags & DRM_MODE_FLAG_DBLSCAN) | |
771 | return MODE_NO_DBLESCAN; | |
772 | ||
773 | return MODE_OK; | |
774 | } | |
775 | ||
00c09d70 PZ |
776 | bool intel_hdmi_mode_fixup(struct drm_encoder *encoder, |
777 | const struct drm_display_mode *mode, | |
778 | struct drm_display_mode *adjusted_mode) | |
7d57382e | 779 | { |
3685a8f3 VS |
780 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); |
781 | ||
55bc60db VS |
782 | if (intel_hdmi->color_range_auto) { |
783 | /* See CEA-861-E - 5.1 Default Encoding Parameters */ | |
784 | if (intel_hdmi->has_hdmi_sink && | |
785 | drm_mode_cea_vic(adjusted_mode) > 1) | |
786 | intel_hdmi->color_range = SDVO_COLOR_RANGE_16_235; | |
787 | else | |
788 | intel_hdmi->color_range = 0; | |
789 | } | |
790 | ||
3685a8f3 VS |
791 | if (intel_hdmi->color_range) |
792 | adjusted_mode->private_flags |= INTEL_MODE_LIMITED_COLOR_RANGE; | |
793 | ||
7d57382e EA |
794 | return true; |
795 | } | |
796 | ||
8ec22b21 CW |
797 | static bool g4x_hdmi_connected(struct intel_hdmi *intel_hdmi) |
798 | { | |
30add22d | 799 | struct drm_device *dev = intel_hdmi_to_dev(intel_hdmi); |
8ec22b21 | 800 | struct drm_i915_private *dev_priv = dev->dev_private; |
69fde0a6 | 801 | struct intel_digital_port *intel_dig_port = hdmi_to_dig_port(intel_hdmi); |
8ec22b21 CW |
802 | uint32_t bit; |
803 | ||
69fde0a6 VS |
804 | switch (intel_dig_port->port) { |
805 | case PORT_B: | |
26739f12 | 806 | bit = PORTB_HOTPLUG_LIVE_STATUS; |
8ec22b21 | 807 | break; |
69fde0a6 | 808 | case PORT_C: |
26739f12 | 809 | bit = PORTC_HOTPLUG_LIVE_STATUS; |
8ec22b21 | 810 | break; |
8ec22b21 CW |
811 | default: |
812 | bit = 0; | |
813 | break; | |
814 | } | |
815 | ||
816 | return I915_READ(PORT_HOTPLUG_STAT) & bit; | |
817 | } | |
818 | ||
aa93d632 | 819 | static enum drm_connector_status |
930a9e28 | 820 | intel_hdmi_detect(struct drm_connector *connector, bool force) |
9dff6af8 | 821 | { |
b0ea7d37 | 822 | struct drm_device *dev = connector->dev; |
df0e9248 | 823 | struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); |
d63885da PZ |
824 | struct intel_digital_port *intel_dig_port = |
825 | hdmi_to_dig_port(intel_hdmi); | |
826 | struct intel_encoder *intel_encoder = &intel_dig_port->base; | |
b0ea7d37 | 827 | struct drm_i915_private *dev_priv = dev->dev_private; |
f899fc64 | 828 | struct edid *edid; |
aa93d632 | 829 | enum drm_connector_status status = connector_status_disconnected; |
9dff6af8 | 830 | |
b0ea7d37 DL |
831 | |
832 | if (IS_G4X(dev) && !g4x_hdmi_connected(intel_hdmi)) | |
8ec22b21 | 833 | return status; |
b0ea7d37 DL |
834 | else if (HAS_PCH_SPLIT(dev) && |
835 | !ibx_digital_port_connected(dev_priv, intel_dig_port)) | |
836 | return status; | |
8ec22b21 | 837 | |
ea5b213a | 838 | intel_hdmi->has_hdmi_sink = false; |
2e3d6006 | 839 | intel_hdmi->has_audio = false; |
abedc077 | 840 | intel_hdmi->rgb_quant_range_selectable = false; |
f899fc64 | 841 | edid = drm_get_edid(connector, |
3bd7d909 DK |
842 | intel_gmbus_get_adapter(dev_priv, |
843 | intel_hdmi->ddc_bus)); | |
2ded9e27 | 844 | |
aa93d632 | 845 | if (edid) { |
be9f1c4f | 846 | if (edid->input & DRM_EDID_INPUT_DIGITAL) { |
aa93d632 | 847 | status = connector_status_connected; |
b1d7e4b4 WF |
848 | if (intel_hdmi->force_audio != HDMI_AUDIO_OFF_DVI) |
849 | intel_hdmi->has_hdmi_sink = | |
850 | drm_detect_hdmi_monitor(edid); | |
2e3d6006 | 851 | intel_hdmi->has_audio = drm_detect_monitor_audio(edid); |
abedc077 VS |
852 | intel_hdmi->rgb_quant_range_selectable = |
853 | drm_rgb_quant_range_selectable(edid); | |
aa93d632 | 854 | } |
aa93d632 | 855 | kfree(edid); |
9dff6af8 | 856 | } |
30ad48b7 | 857 | |
55b7d6e8 | 858 | if (status == connector_status_connected) { |
b1d7e4b4 WF |
859 | if (intel_hdmi->force_audio != HDMI_AUDIO_AUTO) |
860 | intel_hdmi->has_audio = | |
861 | (intel_hdmi->force_audio == HDMI_AUDIO_ON); | |
d63885da | 862 | intel_encoder->type = INTEL_OUTPUT_HDMI; |
55b7d6e8 CW |
863 | } |
864 | ||
2ded9e27 | 865 | return status; |
7d57382e EA |
866 | } |
867 | ||
868 | static int intel_hdmi_get_modes(struct drm_connector *connector) | |
869 | { | |
df0e9248 | 870 | struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); |
f899fc64 | 871 | struct drm_i915_private *dev_priv = connector->dev->dev_private; |
7d57382e EA |
872 | |
873 | /* We should parse the EDID data and find out if it's an HDMI sink so | |
874 | * we can send audio to it. | |
875 | */ | |
876 | ||
f899fc64 | 877 | return intel_ddc_get_modes(connector, |
3bd7d909 DK |
878 | intel_gmbus_get_adapter(dev_priv, |
879 | intel_hdmi->ddc_bus)); | |
7d57382e EA |
880 | } |
881 | ||
1aad7ac0 CW |
882 | static bool |
883 | intel_hdmi_detect_audio(struct drm_connector *connector) | |
884 | { | |
885 | struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); | |
886 | struct drm_i915_private *dev_priv = connector->dev->dev_private; | |
887 | struct edid *edid; | |
888 | bool has_audio = false; | |
889 | ||
890 | edid = drm_get_edid(connector, | |
3bd7d909 DK |
891 | intel_gmbus_get_adapter(dev_priv, |
892 | intel_hdmi->ddc_bus)); | |
1aad7ac0 CW |
893 | if (edid) { |
894 | if (edid->input & DRM_EDID_INPUT_DIGITAL) | |
895 | has_audio = drm_detect_monitor_audio(edid); | |
1aad7ac0 CW |
896 | kfree(edid); |
897 | } | |
898 | ||
899 | return has_audio; | |
900 | } | |
901 | ||
55b7d6e8 CW |
902 | static int |
903 | intel_hdmi_set_property(struct drm_connector *connector, | |
ed517fbb PZ |
904 | struct drm_property *property, |
905 | uint64_t val) | |
55b7d6e8 CW |
906 | { |
907 | struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); | |
da63a9f2 PZ |
908 | struct intel_digital_port *intel_dig_port = |
909 | hdmi_to_dig_port(intel_hdmi); | |
e953fd7b | 910 | struct drm_i915_private *dev_priv = connector->dev->dev_private; |
55b7d6e8 CW |
911 | int ret; |
912 | ||
662595df | 913 | ret = drm_object_property_set_value(&connector->base, property, val); |
55b7d6e8 CW |
914 | if (ret) |
915 | return ret; | |
916 | ||
3f43c48d | 917 | if (property == dev_priv->force_audio_property) { |
b1d7e4b4 | 918 | enum hdmi_force_audio i = val; |
1aad7ac0 CW |
919 | bool has_audio; |
920 | ||
921 | if (i == intel_hdmi->force_audio) | |
55b7d6e8 CW |
922 | return 0; |
923 | ||
1aad7ac0 | 924 | intel_hdmi->force_audio = i; |
55b7d6e8 | 925 | |
b1d7e4b4 | 926 | if (i == HDMI_AUDIO_AUTO) |
1aad7ac0 CW |
927 | has_audio = intel_hdmi_detect_audio(connector); |
928 | else | |
b1d7e4b4 | 929 | has_audio = (i == HDMI_AUDIO_ON); |
1aad7ac0 | 930 | |
b1d7e4b4 WF |
931 | if (i == HDMI_AUDIO_OFF_DVI) |
932 | intel_hdmi->has_hdmi_sink = 0; | |
55b7d6e8 | 933 | |
1aad7ac0 | 934 | intel_hdmi->has_audio = has_audio; |
55b7d6e8 CW |
935 | goto done; |
936 | } | |
937 | ||
e953fd7b | 938 | if (property == dev_priv->broadcast_rgb_property) { |
55bc60db VS |
939 | switch (val) { |
940 | case INTEL_BROADCAST_RGB_AUTO: | |
941 | intel_hdmi->color_range_auto = true; | |
942 | break; | |
943 | case INTEL_BROADCAST_RGB_FULL: | |
944 | intel_hdmi->color_range_auto = false; | |
945 | intel_hdmi->color_range = 0; | |
946 | break; | |
947 | case INTEL_BROADCAST_RGB_LIMITED: | |
948 | intel_hdmi->color_range_auto = false; | |
949 | intel_hdmi->color_range = SDVO_COLOR_RANGE_16_235; | |
950 | break; | |
951 | default: | |
952 | return -EINVAL; | |
953 | } | |
e953fd7b CW |
954 | goto done; |
955 | } | |
956 | ||
55b7d6e8 CW |
957 | return -EINVAL; |
958 | ||
959 | done: | |
c0c36b94 CW |
960 | if (intel_dig_port->base.base.crtc) |
961 | intel_crtc_restore_mode(intel_dig_port->base.base.crtc); | |
55b7d6e8 CW |
962 | |
963 | return 0; | |
964 | } | |
965 | ||
7d57382e EA |
966 | static void intel_hdmi_destroy(struct drm_connector *connector) |
967 | { | |
7d57382e EA |
968 | drm_sysfs_connector_remove(connector); |
969 | drm_connector_cleanup(connector); | |
674e2d08 | 970 | kfree(connector); |
7d57382e EA |
971 | } |
972 | ||
973 | static const struct drm_encoder_helper_funcs intel_hdmi_helper_funcs = { | |
7d57382e | 974 | .mode_fixup = intel_hdmi_mode_fixup, |
7d57382e | 975 | .mode_set = intel_hdmi_mode_set, |
1f703855 | 976 | .disable = intel_encoder_noop, |
7d57382e EA |
977 | }; |
978 | ||
979 | static const struct drm_connector_funcs intel_hdmi_connector_funcs = { | |
5ab432ef | 980 | .dpms = intel_connector_dpms, |
7d57382e EA |
981 | .detect = intel_hdmi_detect, |
982 | .fill_modes = drm_helper_probe_single_connector_modes, | |
55b7d6e8 | 983 | .set_property = intel_hdmi_set_property, |
7d57382e EA |
984 | .destroy = intel_hdmi_destroy, |
985 | }; | |
986 | ||
987 | static const struct drm_connector_helper_funcs intel_hdmi_connector_helper_funcs = { | |
988 | .get_modes = intel_hdmi_get_modes, | |
989 | .mode_valid = intel_hdmi_mode_valid, | |
df0e9248 | 990 | .best_encoder = intel_best_encoder, |
7d57382e EA |
991 | }; |
992 | ||
7d57382e | 993 | static const struct drm_encoder_funcs intel_hdmi_enc_funcs = { |
ea5b213a | 994 | .destroy = intel_encoder_destroy, |
7d57382e EA |
995 | }; |
996 | ||
55b7d6e8 CW |
997 | static void |
998 | intel_hdmi_add_properties(struct intel_hdmi *intel_hdmi, struct drm_connector *connector) | |
999 | { | |
3f43c48d | 1000 | intel_attach_force_audio_property(connector); |
e953fd7b | 1001 | intel_attach_broadcast_rgb_property(connector); |
55bc60db | 1002 | intel_hdmi->color_range_auto = true; |
55b7d6e8 CW |
1003 | } |
1004 | ||
00c09d70 PZ |
1005 | void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port, |
1006 | struct intel_connector *intel_connector) | |
7d57382e | 1007 | { |
b9cb234c PZ |
1008 | struct drm_connector *connector = &intel_connector->base; |
1009 | struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi; | |
1010 | struct intel_encoder *intel_encoder = &intel_dig_port->base; | |
1011 | struct drm_device *dev = intel_encoder->base.dev; | |
7d57382e | 1012 | struct drm_i915_private *dev_priv = dev->dev_private; |
174edf1f | 1013 | enum port port = intel_dig_port->port; |
373a3cf7 | 1014 | |
7d57382e | 1015 | drm_connector_init(dev, connector, &intel_hdmi_connector_funcs, |
8d91104a | 1016 | DRM_MODE_CONNECTOR_HDMIA); |
7d57382e EA |
1017 | drm_connector_helper_add(connector, &intel_hdmi_connector_helper_funcs); |
1018 | ||
eb1f8e4f | 1019 | connector->polled = DRM_CONNECTOR_POLL_HPD; |
c3febcc4 | 1020 | connector->interlace_allowed = 1; |
7d57382e | 1021 | connector->doublescan_allowed = 0; |
66a9278e | 1022 | |
08d644ad DV |
1023 | switch (port) { |
1024 | case PORT_B: | |
f899fc64 | 1025 | intel_hdmi->ddc_bus = GMBUS_PORT_DPB; |
26739f12 | 1026 | dev_priv->hotplug_supported_mask |= PORTB_HOTPLUG_INT_STATUS; |
08d644ad DV |
1027 | break; |
1028 | case PORT_C: | |
7ceae0a5 | 1029 | intel_hdmi->ddc_bus = GMBUS_PORT_DPC; |
26739f12 | 1030 | dev_priv->hotplug_supported_mask |= PORTC_HOTPLUG_INT_STATUS; |
08d644ad DV |
1031 | break; |
1032 | case PORT_D: | |
7ceae0a5 | 1033 | intel_hdmi->ddc_bus = GMBUS_PORT_DPD; |
26739f12 | 1034 | dev_priv->hotplug_supported_mask |= PORTD_HOTPLUG_INT_STATUS; |
08d644ad DV |
1035 | break; |
1036 | case PORT_A: | |
1037 | /* Internal port only for eDP. */ | |
1038 | default: | |
6e4c1677 | 1039 | BUG(); |
f8aed700 | 1040 | } |
7d57382e | 1041 | |
64a8fc01 | 1042 | if (!HAS_PCH_SPLIT(dev)) { |
a3da1df7 | 1043 | intel_hdmi->write_infoframe = g4x_write_infoframe; |
687f4d06 | 1044 | intel_hdmi->set_infoframes = g4x_set_infoframes; |
90b107c8 SK |
1045 | } else if (IS_VALLEYVIEW(dev)) { |
1046 | intel_hdmi->write_infoframe = vlv_write_infoframe; | |
687f4d06 | 1047 | intel_hdmi->set_infoframes = vlv_set_infoframes; |
22b8bf17 | 1048 | } else if (HAS_DDI(dev)) { |
8c5f5f7c | 1049 | intel_hdmi->write_infoframe = hsw_write_infoframe; |
687f4d06 | 1050 | intel_hdmi->set_infoframes = hsw_set_infoframes; |
fdf1250a PZ |
1051 | } else if (HAS_PCH_IBX(dev)) { |
1052 | intel_hdmi->write_infoframe = ibx_write_infoframe; | |
687f4d06 | 1053 | intel_hdmi->set_infoframes = ibx_set_infoframes; |
fdf1250a PZ |
1054 | } else { |
1055 | intel_hdmi->write_infoframe = cpt_write_infoframe; | |
687f4d06 | 1056 | intel_hdmi->set_infoframes = cpt_set_infoframes; |
64a8fc01 | 1057 | } |
45187ace | 1058 | |
affa9354 | 1059 | if (HAS_DDI(dev)) |
bcbc889b PZ |
1060 | intel_connector->get_hw_state = intel_ddi_connector_get_hw_state; |
1061 | else | |
1062 | intel_connector->get_hw_state = intel_connector_get_hw_state; | |
b9cb234c PZ |
1063 | |
1064 | intel_hdmi_add_properties(intel_hdmi, connector); | |
1065 | ||
1066 | intel_connector_attach_encoder(intel_connector, intel_encoder); | |
1067 | drm_sysfs_connector_add(connector); | |
1068 | ||
1069 | /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written | |
1070 | * 0xd. Failure to do so will result in spurious interrupts being | |
1071 | * generated on the port when a cable is not attached. | |
1072 | */ | |
1073 | if (IS_G4X(dev) && !IS_GM45(dev)) { | |
1074 | u32 temp = I915_READ(PEG_BAND_GAP_DATA); | |
1075 | I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd); | |
1076 | } | |
1077 | } | |
1078 | ||
b242b7f7 | 1079 | void intel_hdmi_init(struct drm_device *dev, int hdmi_reg, enum port port) |
b9cb234c PZ |
1080 | { |
1081 | struct intel_digital_port *intel_dig_port; | |
1082 | struct intel_encoder *intel_encoder; | |
1083 | struct drm_encoder *encoder; | |
1084 | struct intel_connector *intel_connector; | |
1085 | ||
1086 | intel_dig_port = kzalloc(sizeof(struct intel_digital_port), GFP_KERNEL); | |
1087 | if (!intel_dig_port) | |
1088 | return; | |
1089 | ||
1090 | intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL); | |
1091 | if (!intel_connector) { | |
1092 | kfree(intel_dig_port); | |
1093 | return; | |
1094 | } | |
1095 | ||
1096 | intel_encoder = &intel_dig_port->base; | |
1097 | encoder = &intel_encoder->base; | |
1098 | ||
1099 | drm_encoder_init(dev, &intel_encoder->base, &intel_hdmi_enc_funcs, | |
1100 | DRM_MODE_ENCODER_TMDS); | |
00c09d70 PZ |
1101 | drm_encoder_helper_add(&intel_encoder->base, &intel_hdmi_helper_funcs); |
1102 | ||
1103 | intel_encoder->enable = intel_enable_hdmi; | |
1104 | intel_encoder->disable = intel_disable_hdmi; | |
1105 | intel_encoder->get_hw_state = intel_hdmi_get_hw_state; | |
5ab432ef | 1106 | |
b9cb234c PZ |
1107 | intel_encoder->type = INTEL_OUTPUT_HDMI; |
1108 | intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2); | |
1109 | intel_encoder->cloneable = false; | |
7d57382e | 1110 | |
174edf1f | 1111 | intel_dig_port->port = port; |
b242b7f7 | 1112 | intel_dig_port->hdmi.hdmi_reg = hdmi_reg; |
b9cb234c | 1113 | intel_dig_port->dp.output_reg = 0; |
55b7d6e8 | 1114 | |
b9cb234c | 1115 | intel_hdmi_init_connector(intel_dig_port, intel_connector); |
7d57382e | 1116 | } |