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7d57382e EA |
1 | /* |
2 | * Copyright 2006 Dave Airlie <airlied@linux.ie> | |
3 | * Copyright © 2006-2009 Intel Corporation | |
4 | * | |
5 | * Permission is hereby granted, free of charge, to any person obtaining a | |
6 | * copy of this software and associated documentation files (the "Software"), | |
7 | * to deal in the Software without restriction, including without limitation | |
8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
9 | * and/or sell copies of the Software, and to permit persons to whom the | |
10 | * Software is furnished to do so, subject to the following conditions: | |
11 | * | |
12 | * The above copyright notice and this permission notice (including the next | |
13 | * paragraph) shall be included in all copies or substantial portions of the | |
14 | * Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
21 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
22 | * DEALINGS IN THE SOFTWARE. | |
23 | * | |
24 | * Authors: | |
25 | * Eric Anholt <eric@anholt.net> | |
26 | * Jesse Barnes <jesse.barnes@intel.com> | |
27 | */ | |
28 | ||
29 | #include <linux/i2c.h> | |
5a0e3ad6 | 30 | #include <linux/slab.h> |
7d57382e | 31 | #include <linux/delay.h> |
178f736a | 32 | #include <linux/hdmi.h> |
760285e7 | 33 | #include <drm/drmP.h> |
c6f95f27 | 34 | #include <drm/drm_atomic_helper.h> |
760285e7 DH |
35 | #include <drm/drm_crtc.h> |
36 | #include <drm/drm_edid.h> | |
7d57382e | 37 | #include "intel_drv.h" |
760285e7 | 38 | #include <drm/i915_drm.h> |
7d57382e EA |
39 | #include "i915_drv.h" |
40 | ||
30add22d PZ |
41 | static struct drm_device *intel_hdmi_to_dev(struct intel_hdmi *intel_hdmi) |
42 | { | |
da63a9f2 | 43 | return hdmi_to_dig_port(intel_hdmi)->base.base.dev; |
30add22d PZ |
44 | } |
45 | ||
afba0188 DV |
46 | static void |
47 | assert_hdmi_port_disabled(struct intel_hdmi *intel_hdmi) | |
48 | { | |
30add22d | 49 | struct drm_device *dev = intel_hdmi_to_dev(intel_hdmi); |
afba0188 DV |
50 | struct drm_i915_private *dev_priv = dev->dev_private; |
51 | uint32_t enabled_bits; | |
52 | ||
affa9354 | 53 | enabled_bits = HAS_DDI(dev) ? DDI_BUF_CTL_ENABLE : SDVO_ENABLE; |
afba0188 | 54 | |
b242b7f7 | 55 | WARN(I915_READ(intel_hdmi->hdmi_reg) & enabled_bits, |
afba0188 DV |
56 | "HDMI port enabled, expecting disabled\n"); |
57 | } | |
58 | ||
f5bbfca3 | 59 | struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder) |
ea5b213a | 60 | { |
da63a9f2 PZ |
61 | struct intel_digital_port *intel_dig_port = |
62 | container_of(encoder, struct intel_digital_port, base.base); | |
63 | return &intel_dig_port->hdmi; | |
ea5b213a CW |
64 | } |
65 | ||
df0e9248 CW |
66 | static struct intel_hdmi *intel_attached_hdmi(struct drm_connector *connector) |
67 | { | |
da63a9f2 | 68 | return enc_to_intel_hdmi(&intel_attached_encoder(connector)->base); |
df0e9248 CW |
69 | } |
70 | ||
178f736a | 71 | static u32 g4x_infoframe_index(enum hdmi_infoframe_type type) |
3c17fe4b | 72 | { |
178f736a DL |
73 | switch (type) { |
74 | case HDMI_INFOFRAME_TYPE_AVI: | |
ed517fbb | 75 | return VIDEO_DIP_SELECT_AVI; |
178f736a | 76 | case HDMI_INFOFRAME_TYPE_SPD: |
ed517fbb | 77 | return VIDEO_DIP_SELECT_SPD; |
c8bb75af LD |
78 | case HDMI_INFOFRAME_TYPE_VENDOR: |
79 | return VIDEO_DIP_SELECT_VENDOR; | |
45187ace | 80 | default: |
178f736a | 81 | DRM_DEBUG_DRIVER("unknown info frame type %d\n", type); |
ed517fbb | 82 | return 0; |
45187ace | 83 | } |
45187ace JB |
84 | } |
85 | ||
178f736a | 86 | static u32 g4x_infoframe_enable(enum hdmi_infoframe_type type) |
45187ace | 87 | { |
178f736a DL |
88 | switch (type) { |
89 | case HDMI_INFOFRAME_TYPE_AVI: | |
ed517fbb | 90 | return VIDEO_DIP_ENABLE_AVI; |
178f736a | 91 | case HDMI_INFOFRAME_TYPE_SPD: |
ed517fbb | 92 | return VIDEO_DIP_ENABLE_SPD; |
c8bb75af LD |
93 | case HDMI_INFOFRAME_TYPE_VENDOR: |
94 | return VIDEO_DIP_ENABLE_VENDOR; | |
fa193ff7 | 95 | default: |
178f736a | 96 | DRM_DEBUG_DRIVER("unknown info frame type %d\n", type); |
ed517fbb | 97 | return 0; |
fa193ff7 | 98 | } |
fa193ff7 PZ |
99 | } |
100 | ||
178f736a | 101 | static u32 hsw_infoframe_enable(enum hdmi_infoframe_type type) |
2da8af54 | 102 | { |
178f736a DL |
103 | switch (type) { |
104 | case HDMI_INFOFRAME_TYPE_AVI: | |
2da8af54 | 105 | return VIDEO_DIP_ENABLE_AVI_HSW; |
178f736a | 106 | case HDMI_INFOFRAME_TYPE_SPD: |
2da8af54 | 107 | return VIDEO_DIP_ENABLE_SPD_HSW; |
c8bb75af LD |
108 | case HDMI_INFOFRAME_TYPE_VENDOR: |
109 | return VIDEO_DIP_ENABLE_VS_HSW; | |
2da8af54 | 110 | default: |
178f736a | 111 | DRM_DEBUG_DRIVER("unknown info frame type %d\n", type); |
2da8af54 PZ |
112 | return 0; |
113 | } | |
114 | } | |
115 | ||
178f736a | 116 | static u32 hsw_infoframe_data_reg(enum hdmi_infoframe_type type, |
a57c774a AK |
117 | enum transcoder cpu_transcoder, |
118 | struct drm_i915_private *dev_priv) | |
2da8af54 | 119 | { |
178f736a DL |
120 | switch (type) { |
121 | case HDMI_INFOFRAME_TYPE_AVI: | |
7d9bcebe | 122 | return HSW_TVIDEO_DIP_AVI_DATA(cpu_transcoder); |
178f736a | 123 | case HDMI_INFOFRAME_TYPE_SPD: |
7d9bcebe | 124 | return HSW_TVIDEO_DIP_SPD_DATA(cpu_transcoder); |
c8bb75af LD |
125 | case HDMI_INFOFRAME_TYPE_VENDOR: |
126 | return HSW_TVIDEO_DIP_VS_DATA(cpu_transcoder); | |
2da8af54 | 127 | default: |
178f736a | 128 | DRM_DEBUG_DRIVER("unknown info frame type %d\n", type); |
2da8af54 PZ |
129 | return 0; |
130 | } | |
131 | } | |
132 | ||
a3da1df7 | 133 | static void g4x_write_infoframe(struct drm_encoder *encoder, |
178f736a | 134 | enum hdmi_infoframe_type type, |
fff63867 | 135 | const void *frame, ssize_t len) |
45187ace | 136 | { |
fff63867 | 137 | const uint32_t *data = frame; |
3c17fe4b DH |
138 | struct drm_device *dev = encoder->dev; |
139 | struct drm_i915_private *dev_priv = dev->dev_private; | |
22509ec8 | 140 | u32 val = I915_READ(VIDEO_DIP_CTL); |
178f736a | 141 | int i; |
3c17fe4b | 142 | |
822974ae PZ |
143 | WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n"); |
144 | ||
1d4f85ac | 145 | val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ |
178f736a | 146 | val |= g4x_infoframe_index(type); |
22509ec8 | 147 | |
178f736a | 148 | val &= ~g4x_infoframe_enable(type); |
45187ace | 149 | |
22509ec8 | 150 | I915_WRITE(VIDEO_DIP_CTL, val); |
3c17fe4b | 151 | |
9d9740f0 | 152 | mmiowb(); |
45187ace | 153 | for (i = 0; i < len; i += 4) { |
3c17fe4b DH |
154 | I915_WRITE(VIDEO_DIP_DATA, *data); |
155 | data++; | |
156 | } | |
adf00b26 PZ |
157 | /* Write every possible data byte to force correct ECC calculation. */ |
158 | for (; i < VIDEO_DIP_DATA_SIZE; i += 4) | |
159 | I915_WRITE(VIDEO_DIP_DATA, 0); | |
9d9740f0 | 160 | mmiowb(); |
3c17fe4b | 161 | |
178f736a | 162 | val |= g4x_infoframe_enable(type); |
60c5ea2d | 163 | val &= ~VIDEO_DIP_FREQ_MASK; |
4b24c933 | 164 | val |= VIDEO_DIP_FREQ_VSYNC; |
45187ace | 165 | |
22509ec8 | 166 | I915_WRITE(VIDEO_DIP_CTL, val); |
9d9740f0 | 167 | POSTING_READ(VIDEO_DIP_CTL); |
3c17fe4b DH |
168 | } |
169 | ||
e43823ec JB |
170 | static bool g4x_infoframe_enabled(struct drm_encoder *encoder) |
171 | { | |
172 | struct drm_device *dev = encoder->dev; | |
173 | struct drm_i915_private *dev_priv = dev->dev_private; | |
89a35ecd | 174 | struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); |
e43823ec JB |
175 | u32 val = I915_READ(VIDEO_DIP_CTL); |
176 | ||
89a35ecd JB |
177 | if (VIDEO_DIP_PORT(intel_dig_port->port) == (val & VIDEO_DIP_PORT_MASK)) |
178 | return val & VIDEO_DIP_ENABLE; | |
179 | ||
180 | return false; | |
e43823ec JB |
181 | } |
182 | ||
fdf1250a | 183 | static void ibx_write_infoframe(struct drm_encoder *encoder, |
178f736a | 184 | enum hdmi_infoframe_type type, |
fff63867 | 185 | const void *frame, ssize_t len) |
fdf1250a | 186 | { |
fff63867 | 187 | const uint32_t *data = frame; |
fdf1250a PZ |
188 | struct drm_device *dev = encoder->dev; |
189 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ed517fbb | 190 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); |
178f736a | 191 | int i, reg = TVIDEO_DIP_CTL(intel_crtc->pipe); |
fdf1250a PZ |
192 | u32 val = I915_READ(reg); |
193 | ||
822974ae PZ |
194 | WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n"); |
195 | ||
fdf1250a | 196 | val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ |
178f736a | 197 | val |= g4x_infoframe_index(type); |
fdf1250a | 198 | |
178f736a | 199 | val &= ~g4x_infoframe_enable(type); |
fdf1250a PZ |
200 | |
201 | I915_WRITE(reg, val); | |
202 | ||
9d9740f0 | 203 | mmiowb(); |
fdf1250a PZ |
204 | for (i = 0; i < len; i += 4) { |
205 | I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data); | |
206 | data++; | |
207 | } | |
adf00b26 PZ |
208 | /* Write every possible data byte to force correct ECC calculation. */ |
209 | for (; i < VIDEO_DIP_DATA_SIZE; i += 4) | |
210 | I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0); | |
9d9740f0 | 211 | mmiowb(); |
fdf1250a | 212 | |
178f736a | 213 | val |= g4x_infoframe_enable(type); |
fdf1250a | 214 | val &= ~VIDEO_DIP_FREQ_MASK; |
4b24c933 | 215 | val |= VIDEO_DIP_FREQ_VSYNC; |
fdf1250a PZ |
216 | |
217 | I915_WRITE(reg, val); | |
9d9740f0 | 218 | POSTING_READ(reg); |
fdf1250a PZ |
219 | } |
220 | ||
e43823ec JB |
221 | static bool ibx_infoframe_enabled(struct drm_encoder *encoder) |
222 | { | |
223 | struct drm_device *dev = encoder->dev; | |
224 | struct drm_i915_private *dev_priv = dev->dev_private; | |
225 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); | |
226 | int reg = TVIDEO_DIP_CTL(intel_crtc->pipe); | |
227 | u32 val = I915_READ(reg); | |
228 | ||
229 | return val & VIDEO_DIP_ENABLE; | |
230 | } | |
231 | ||
fdf1250a | 232 | static void cpt_write_infoframe(struct drm_encoder *encoder, |
178f736a | 233 | enum hdmi_infoframe_type type, |
fff63867 | 234 | const void *frame, ssize_t len) |
b055c8f3 | 235 | { |
fff63867 | 236 | const uint32_t *data = frame; |
b055c8f3 JB |
237 | struct drm_device *dev = encoder->dev; |
238 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ed517fbb | 239 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); |
178f736a | 240 | int i, reg = TVIDEO_DIP_CTL(intel_crtc->pipe); |
22509ec8 | 241 | u32 val = I915_READ(reg); |
b055c8f3 | 242 | |
822974ae PZ |
243 | WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n"); |
244 | ||
64a8fc01 | 245 | val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ |
178f736a | 246 | val |= g4x_infoframe_index(type); |
45187ace | 247 | |
ecb97851 PZ |
248 | /* The DIP control register spec says that we need to update the AVI |
249 | * infoframe without clearing its enable bit */ | |
178f736a DL |
250 | if (type != HDMI_INFOFRAME_TYPE_AVI) |
251 | val &= ~g4x_infoframe_enable(type); | |
ecb97851 | 252 | |
22509ec8 | 253 | I915_WRITE(reg, val); |
45187ace | 254 | |
9d9740f0 | 255 | mmiowb(); |
45187ace | 256 | for (i = 0; i < len; i += 4) { |
b055c8f3 JB |
257 | I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data); |
258 | data++; | |
259 | } | |
adf00b26 PZ |
260 | /* Write every possible data byte to force correct ECC calculation. */ |
261 | for (; i < VIDEO_DIP_DATA_SIZE; i += 4) | |
262 | I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0); | |
9d9740f0 | 263 | mmiowb(); |
b055c8f3 | 264 | |
178f736a | 265 | val |= g4x_infoframe_enable(type); |
60c5ea2d | 266 | val &= ~VIDEO_DIP_FREQ_MASK; |
4b24c933 | 267 | val |= VIDEO_DIP_FREQ_VSYNC; |
45187ace | 268 | |
22509ec8 | 269 | I915_WRITE(reg, val); |
9d9740f0 | 270 | POSTING_READ(reg); |
45187ace | 271 | } |
90b107c8 | 272 | |
e43823ec JB |
273 | static bool cpt_infoframe_enabled(struct drm_encoder *encoder) |
274 | { | |
275 | struct drm_device *dev = encoder->dev; | |
276 | struct drm_i915_private *dev_priv = dev->dev_private; | |
277 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); | |
278 | int reg = TVIDEO_DIP_CTL(intel_crtc->pipe); | |
279 | u32 val = I915_READ(reg); | |
280 | ||
281 | return val & VIDEO_DIP_ENABLE; | |
282 | } | |
283 | ||
90b107c8 | 284 | static void vlv_write_infoframe(struct drm_encoder *encoder, |
178f736a | 285 | enum hdmi_infoframe_type type, |
fff63867 | 286 | const void *frame, ssize_t len) |
90b107c8 | 287 | { |
fff63867 | 288 | const uint32_t *data = frame; |
90b107c8 SK |
289 | struct drm_device *dev = encoder->dev; |
290 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ed517fbb | 291 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); |
178f736a | 292 | int i, reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe); |
22509ec8 | 293 | u32 val = I915_READ(reg); |
90b107c8 | 294 | |
822974ae PZ |
295 | WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n"); |
296 | ||
90b107c8 | 297 | val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ |
178f736a | 298 | val |= g4x_infoframe_index(type); |
22509ec8 | 299 | |
178f736a | 300 | val &= ~g4x_infoframe_enable(type); |
90b107c8 | 301 | |
22509ec8 | 302 | I915_WRITE(reg, val); |
90b107c8 | 303 | |
9d9740f0 | 304 | mmiowb(); |
90b107c8 SK |
305 | for (i = 0; i < len; i += 4) { |
306 | I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), *data); | |
307 | data++; | |
308 | } | |
adf00b26 PZ |
309 | /* Write every possible data byte to force correct ECC calculation. */ |
310 | for (; i < VIDEO_DIP_DATA_SIZE; i += 4) | |
311 | I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), 0); | |
9d9740f0 | 312 | mmiowb(); |
90b107c8 | 313 | |
178f736a | 314 | val |= g4x_infoframe_enable(type); |
60c5ea2d | 315 | val &= ~VIDEO_DIP_FREQ_MASK; |
4b24c933 | 316 | val |= VIDEO_DIP_FREQ_VSYNC; |
90b107c8 | 317 | |
22509ec8 | 318 | I915_WRITE(reg, val); |
9d9740f0 | 319 | POSTING_READ(reg); |
90b107c8 SK |
320 | } |
321 | ||
e43823ec JB |
322 | static bool vlv_infoframe_enabled(struct drm_encoder *encoder) |
323 | { | |
324 | struct drm_device *dev = encoder->dev; | |
325 | struct drm_i915_private *dev_priv = dev->dev_private; | |
326 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); | |
327 | int reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe); | |
328 | u32 val = I915_READ(reg); | |
329 | ||
330 | return val & VIDEO_DIP_ENABLE; | |
331 | } | |
332 | ||
8c5f5f7c | 333 | static void hsw_write_infoframe(struct drm_encoder *encoder, |
178f736a | 334 | enum hdmi_infoframe_type type, |
fff63867 | 335 | const void *frame, ssize_t len) |
8c5f5f7c | 336 | { |
fff63867 | 337 | const uint32_t *data = frame; |
2da8af54 PZ |
338 | struct drm_device *dev = encoder->dev; |
339 | struct drm_i915_private *dev_priv = dev->dev_private; | |
340 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); | |
6e3c9717 | 341 | u32 ctl_reg = HSW_TVIDEO_DIP_CTL(intel_crtc->config->cpu_transcoder); |
178f736a DL |
342 | u32 data_reg; |
343 | int i; | |
2da8af54 | 344 | u32 val = I915_READ(ctl_reg); |
8c5f5f7c | 345 | |
178f736a | 346 | data_reg = hsw_infoframe_data_reg(type, |
6e3c9717 | 347 | intel_crtc->config->cpu_transcoder, |
a57c774a | 348 | dev_priv); |
2da8af54 PZ |
349 | if (data_reg == 0) |
350 | return; | |
351 | ||
178f736a | 352 | val &= ~hsw_infoframe_enable(type); |
2da8af54 PZ |
353 | I915_WRITE(ctl_reg, val); |
354 | ||
9d9740f0 | 355 | mmiowb(); |
2da8af54 PZ |
356 | for (i = 0; i < len; i += 4) { |
357 | I915_WRITE(data_reg + i, *data); | |
358 | data++; | |
359 | } | |
adf00b26 PZ |
360 | /* Write every possible data byte to force correct ECC calculation. */ |
361 | for (; i < VIDEO_DIP_DATA_SIZE; i += 4) | |
362 | I915_WRITE(data_reg + i, 0); | |
9d9740f0 | 363 | mmiowb(); |
8c5f5f7c | 364 | |
178f736a | 365 | val |= hsw_infoframe_enable(type); |
2da8af54 | 366 | I915_WRITE(ctl_reg, val); |
9d9740f0 | 367 | POSTING_READ(ctl_reg); |
8c5f5f7c ED |
368 | } |
369 | ||
e43823ec JB |
370 | static bool hsw_infoframe_enabled(struct drm_encoder *encoder) |
371 | { | |
372 | struct drm_device *dev = encoder->dev; | |
373 | struct drm_i915_private *dev_priv = dev->dev_private; | |
374 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); | |
6e3c9717 | 375 | u32 ctl_reg = HSW_TVIDEO_DIP_CTL(intel_crtc->config->cpu_transcoder); |
e43823ec JB |
376 | u32 val = I915_READ(ctl_reg); |
377 | ||
378 | return val & (VIDEO_DIP_ENABLE_AVI_HSW | VIDEO_DIP_ENABLE_SPD_HSW | | |
379 | VIDEO_DIP_ENABLE_VS_HSW); | |
380 | } | |
381 | ||
5adaea79 DL |
382 | /* |
383 | * The data we write to the DIP data buffer registers is 1 byte bigger than the | |
384 | * HDMI infoframe size because of an ECC/reserved byte at position 3 (starting | |
385 | * at 0). It's also a byte used by DisplayPort so the same DIP registers can be | |
386 | * used for both technologies. | |
387 | * | |
388 | * DW0: Reserved/ECC/DP | HB2 | HB1 | HB0 | |
389 | * DW1: DB3 | DB2 | DB1 | DB0 | |
390 | * DW2: DB7 | DB6 | DB5 | DB4 | |
391 | * DW3: ... | |
392 | * | |
393 | * (HB is Header Byte, DB is Data Byte) | |
394 | * | |
395 | * The hdmi pack() functions don't know about that hardware specific hole so we | |
396 | * trick them by giving an offset into the buffer and moving back the header | |
397 | * bytes by one. | |
398 | */ | |
9198ee5b DL |
399 | static void intel_write_infoframe(struct drm_encoder *encoder, |
400 | union hdmi_infoframe *frame) | |
45187ace JB |
401 | { |
402 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); | |
5adaea79 DL |
403 | uint8_t buffer[VIDEO_DIP_DATA_SIZE]; |
404 | ssize_t len; | |
45187ace | 405 | |
5adaea79 DL |
406 | /* see comment above for the reason for this offset */ |
407 | len = hdmi_infoframe_pack(frame, buffer + 1, sizeof(buffer) - 1); | |
408 | if (len < 0) | |
409 | return; | |
410 | ||
411 | /* Insert the 'hole' (see big comment above) at position 3 */ | |
412 | buffer[0] = buffer[1]; | |
413 | buffer[1] = buffer[2]; | |
414 | buffer[2] = buffer[3]; | |
415 | buffer[3] = 0; | |
416 | len++; | |
45187ace | 417 | |
5adaea79 | 418 | intel_hdmi->write_infoframe(encoder, frame->any.type, buffer, len); |
45187ace JB |
419 | } |
420 | ||
687f4d06 | 421 | static void intel_hdmi_set_avi_infoframe(struct drm_encoder *encoder, |
c846b619 | 422 | struct drm_display_mode *adjusted_mode) |
45187ace | 423 | { |
abedc077 | 424 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); |
50f3b016 | 425 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); |
5adaea79 DL |
426 | union hdmi_infoframe frame; |
427 | int ret; | |
45187ace | 428 | |
94a11ddc VK |
429 | /* Set user selected PAR to incoming mode's member */ |
430 | adjusted_mode->picture_aspect_ratio = intel_hdmi->aspect_ratio; | |
431 | ||
5adaea79 DL |
432 | ret = drm_hdmi_avi_infoframe_from_display_mode(&frame.avi, |
433 | adjusted_mode); | |
434 | if (ret < 0) { | |
435 | DRM_ERROR("couldn't fill AVI infoframe\n"); | |
436 | return; | |
437 | } | |
c846b619 | 438 | |
abedc077 | 439 | if (intel_hdmi->rgb_quant_range_selectable) { |
6e3c9717 | 440 | if (intel_crtc->config->limited_color_range) |
5adaea79 DL |
441 | frame.avi.quantization_range = |
442 | HDMI_QUANTIZATION_RANGE_LIMITED; | |
abedc077 | 443 | else |
5adaea79 DL |
444 | frame.avi.quantization_range = |
445 | HDMI_QUANTIZATION_RANGE_FULL; | |
abedc077 VS |
446 | } |
447 | ||
9198ee5b | 448 | intel_write_infoframe(encoder, &frame); |
b055c8f3 JB |
449 | } |
450 | ||
687f4d06 | 451 | static void intel_hdmi_set_spd_infoframe(struct drm_encoder *encoder) |
c0864cb3 | 452 | { |
5adaea79 DL |
453 | union hdmi_infoframe frame; |
454 | int ret; | |
455 | ||
456 | ret = hdmi_spd_infoframe_init(&frame.spd, "Intel", "Integrated gfx"); | |
457 | if (ret < 0) { | |
458 | DRM_ERROR("couldn't fill SPD infoframe\n"); | |
459 | return; | |
460 | } | |
c0864cb3 | 461 | |
5adaea79 | 462 | frame.spd.sdi = HDMI_SPD_SDI_PC; |
c0864cb3 | 463 | |
9198ee5b | 464 | intel_write_infoframe(encoder, &frame); |
c0864cb3 JB |
465 | } |
466 | ||
c8bb75af LD |
467 | static void |
468 | intel_hdmi_set_hdmi_infoframe(struct drm_encoder *encoder, | |
469 | struct drm_display_mode *adjusted_mode) | |
470 | { | |
471 | union hdmi_infoframe frame; | |
472 | int ret; | |
473 | ||
474 | ret = drm_hdmi_vendor_infoframe_from_display_mode(&frame.vendor.hdmi, | |
475 | adjusted_mode); | |
476 | if (ret < 0) | |
477 | return; | |
478 | ||
479 | intel_write_infoframe(encoder, &frame); | |
480 | } | |
481 | ||
687f4d06 | 482 | static void g4x_set_infoframes(struct drm_encoder *encoder, |
6897b4b5 | 483 | bool enable, |
687f4d06 PZ |
484 | struct drm_display_mode *adjusted_mode) |
485 | { | |
0c14c7f9 | 486 | struct drm_i915_private *dev_priv = encoder->dev->dev_private; |
69fde0a6 VS |
487 | struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); |
488 | struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi; | |
0c14c7f9 PZ |
489 | u32 reg = VIDEO_DIP_CTL; |
490 | u32 val = I915_READ(reg); | |
822cdc52 | 491 | u32 port = VIDEO_DIP_PORT(intel_dig_port->port); |
0c14c7f9 | 492 | |
afba0188 DV |
493 | assert_hdmi_port_disabled(intel_hdmi); |
494 | ||
0c14c7f9 PZ |
495 | /* If the registers were not initialized yet, they might be zeroes, |
496 | * which means we're selecting the AVI DIP and we're setting its | |
497 | * frequency to once. This seems to really confuse the HW and make | |
498 | * things stop working (the register spec says the AVI always needs to | |
499 | * be sent every VSync). So here we avoid writing to the register more | |
500 | * than we need and also explicitly select the AVI DIP and explicitly | |
501 | * set its frequency to every VSync. Avoiding to write it twice seems to | |
502 | * be enough to solve the problem, but being defensive shouldn't hurt us | |
503 | * either. */ | |
504 | val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; | |
505 | ||
6897b4b5 | 506 | if (!enable) { |
0c14c7f9 PZ |
507 | if (!(val & VIDEO_DIP_ENABLE)) |
508 | return; | |
509 | val &= ~VIDEO_DIP_ENABLE; | |
510 | I915_WRITE(reg, val); | |
9d9740f0 | 511 | POSTING_READ(reg); |
0c14c7f9 PZ |
512 | return; |
513 | } | |
514 | ||
72b78c9d PZ |
515 | if (port != (val & VIDEO_DIP_PORT_MASK)) { |
516 | if (val & VIDEO_DIP_ENABLE) { | |
517 | val &= ~VIDEO_DIP_ENABLE; | |
518 | I915_WRITE(reg, val); | |
9d9740f0 | 519 | POSTING_READ(reg); |
72b78c9d PZ |
520 | } |
521 | val &= ~VIDEO_DIP_PORT_MASK; | |
522 | val |= port; | |
523 | } | |
524 | ||
822974ae | 525 | val |= VIDEO_DIP_ENABLE; |
0dd87d20 | 526 | val &= ~VIDEO_DIP_ENABLE_VENDOR; |
822974ae | 527 | |
f278d972 | 528 | I915_WRITE(reg, val); |
9d9740f0 | 529 | POSTING_READ(reg); |
f278d972 | 530 | |
687f4d06 PZ |
531 | intel_hdmi_set_avi_infoframe(encoder, adjusted_mode); |
532 | intel_hdmi_set_spd_infoframe(encoder); | |
c8bb75af | 533 | intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode); |
687f4d06 PZ |
534 | } |
535 | ||
536 | static void ibx_set_infoframes(struct drm_encoder *encoder, | |
6897b4b5 | 537 | bool enable, |
687f4d06 PZ |
538 | struct drm_display_mode *adjusted_mode) |
539 | { | |
0c14c7f9 PZ |
540 | struct drm_i915_private *dev_priv = encoder->dev->dev_private; |
541 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); | |
69fde0a6 VS |
542 | struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); |
543 | struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi; | |
0c14c7f9 PZ |
544 | u32 reg = TVIDEO_DIP_CTL(intel_crtc->pipe); |
545 | u32 val = I915_READ(reg); | |
822cdc52 | 546 | u32 port = VIDEO_DIP_PORT(intel_dig_port->port); |
0c14c7f9 | 547 | |
afba0188 DV |
548 | assert_hdmi_port_disabled(intel_hdmi); |
549 | ||
0c14c7f9 PZ |
550 | /* See the big comment in g4x_set_infoframes() */ |
551 | val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; | |
552 | ||
6897b4b5 | 553 | if (!enable) { |
0c14c7f9 PZ |
554 | if (!(val & VIDEO_DIP_ENABLE)) |
555 | return; | |
556 | val &= ~VIDEO_DIP_ENABLE; | |
557 | I915_WRITE(reg, val); | |
9d9740f0 | 558 | POSTING_READ(reg); |
0c14c7f9 PZ |
559 | return; |
560 | } | |
561 | ||
72b78c9d PZ |
562 | if (port != (val & VIDEO_DIP_PORT_MASK)) { |
563 | if (val & VIDEO_DIP_ENABLE) { | |
564 | val &= ~VIDEO_DIP_ENABLE; | |
565 | I915_WRITE(reg, val); | |
9d9740f0 | 566 | POSTING_READ(reg); |
72b78c9d PZ |
567 | } |
568 | val &= ~VIDEO_DIP_PORT_MASK; | |
569 | val |= port; | |
570 | } | |
571 | ||
822974ae | 572 | val |= VIDEO_DIP_ENABLE; |
0dd87d20 PZ |
573 | val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | |
574 | VIDEO_DIP_ENABLE_GCP); | |
822974ae | 575 | |
f278d972 | 576 | I915_WRITE(reg, val); |
9d9740f0 | 577 | POSTING_READ(reg); |
f278d972 | 578 | |
687f4d06 PZ |
579 | intel_hdmi_set_avi_infoframe(encoder, adjusted_mode); |
580 | intel_hdmi_set_spd_infoframe(encoder); | |
c8bb75af | 581 | intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode); |
687f4d06 PZ |
582 | } |
583 | ||
584 | static void cpt_set_infoframes(struct drm_encoder *encoder, | |
6897b4b5 | 585 | bool enable, |
687f4d06 PZ |
586 | struct drm_display_mode *adjusted_mode) |
587 | { | |
0c14c7f9 PZ |
588 | struct drm_i915_private *dev_priv = encoder->dev->dev_private; |
589 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); | |
590 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); | |
591 | u32 reg = TVIDEO_DIP_CTL(intel_crtc->pipe); | |
592 | u32 val = I915_READ(reg); | |
593 | ||
afba0188 DV |
594 | assert_hdmi_port_disabled(intel_hdmi); |
595 | ||
0c14c7f9 PZ |
596 | /* See the big comment in g4x_set_infoframes() */ |
597 | val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; | |
598 | ||
6897b4b5 | 599 | if (!enable) { |
0c14c7f9 PZ |
600 | if (!(val & VIDEO_DIP_ENABLE)) |
601 | return; | |
602 | val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI); | |
603 | I915_WRITE(reg, val); | |
9d9740f0 | 604 | POSTING_READ(reg); |
0c14c7f9 PZ |
605 | return; |
606 | } | |
607 | ||
822974ae PZ |
608 | /* Set both together, unset both together: see the spec. */ |
609 | val |= VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI; | |
0dd87d20 PZ |
610 | val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | |
611 | VIDEO_DIP_ENABLE_GCP); | |
822974ae PZ |
612 | |
613 | I915_WRITE(reg, val); | |
9d9740f0 | 614 | POSTING_READ(reg); |
822974ae | 615 | |
687f4d06 PZ |
616 | intel_hdmi_set_avi_infoframe(encoder, adjusted_mode); |
617 | intel_hdmi_set_spd_infoframe(encoder); | |
c8bb75af | 618 | intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode); |
687f4d06 PZ |
619 | } |
620 | ||
621 | static void vlv_set_infoframes(struct drm_encoder *encoder, | |
6897b4b5 | 622 | bool enable, |
687f4d06 PZ |
623 | struct drm_display_mode *adjusted_mode) |
624 | { | |
0c14c7f9 | 625 | struct drm_i915_private *dev_priv = encoder->dev->dev_private; |
6a2b8021 | 626 | struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); |
0c14c7f9 PZ |
627 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); |
628 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); | |
629 | u32 reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe); | |
630 | u32 val = I915_READ(reg); | |
6a2b8021 | 631 | u32 port = VIDEO_DIP_PORT(intel_dig_port->port); |
0c14c7f9 | 632 | |
afba0188 DV |
633 | assert_hdmi_port_disabled(intel_hdmi); |
634 | ||
0c14c7f9 PZ |
635 | /* See the big comment in g4x_set_infoframes() */ |
636 | val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; | |
637 | ||
6897b4b5 | 638 | if (!enable) { |
0c14c7f9 PZ |
639 | if (!(val & VIDEO_DIP_ENABLE)) |
640 | return; | |
641 | val &= ~VIDEO_DIP_ENABLE; | |
642 | I915_WRITE(reg, val); | |
9d9740f0 | 643 | POSTING_READ(reg); |
0c14c7f9 PZ |
644 | return; |
645 | } | |
646 | ||
6a2b8021 JB |
647 | if (port != (val & VIDEO_DIP_PORT_MASK)) { |
648 | if (val & VIDEO_DIP_ENABLE) { | |
649 | val &= ~VIDEO_DIP_ENABLE; | |
650 | I915_WRITE(reg, val); | |
651 | POSTING_READ(reg); | |
652 | } | |
653 | val &= ~VIDEO_DIP_PORT_MASK; | |
654 | val |= port; | |
655 | } | |
656 | ||
822974ae | 657 | val |= VIDEO_DIP_ENABLE; |
4d47dfb8 JB |
658 | val &= ~(VIDEO_DIP_ENABLE_AVI | VIDEO_DIP_ENABLE_VENDOR | |
659 | VIDEO_DIP_ENABLE_GAMUT | VIDEO_DIP_ENABLE_GCP); | |
822974ae PZ |
660 | |
661 | I915_WRITE(reg, val); | |
9d9740f0 | 662 | POSTING_READ(reg); |
822974ae | 663 | |
687f4d06 PZ |
664 | intel_hdmi_set_avi_infoframe(encoder, adjusted_mode); |
665 | intel_hdmi_set_spd_infoframe(encoder); | |
c8bb75af | 666 | intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode); |
687f4d06 PZ |
667 | } |
668 | ||
669 | static void hsw_set_infoframes(struct drm_encoder *encoder, | |
6897b4b5 | 670 | bool enable, |
687f4d06 PZ |
671 | struct drm_display_mode *adjusted_mode) |
672 | { | |
0c14c7f9 PZ |
673 | struct drm_i915_private *dev_priv = encoder->dev->dev_private; |
674 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); | |
675 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); | |
6e3c9717 | 676 | u32 reg = HSW_TVIDEO_DIP_CTL(intel_crtc->config->cpu_transcoder); |
0dd87d20 | 677 | u32 val = I915_READ(reg); |
0c14c7f9 | 678 | |
afba0188 DV |
679 | assert_hdmi_port_disabled(intel_hdmi); |
680 | ||
6897b4b5 | 681 | if (!enable) { |
0c14c7f9 | 682 | I915_WRITE(reg, 0); |
9d9740f0 | 683 | POSTING_READ(reg); |
0c14c7f9 PZ |
684 | return; |
685 | } | |
686 | ||
0dd87d20 PZ |
687 | val &= ~(VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_GCP_HSW | |
688 | VIDEO_DIP_ENABLE_VS_HSW | VIDEO_DIP_ENABLE_GMP_HSW); | |
689 | ||
690 | I915_WRITE(reg, val); | |
9d9740f0 | 691 | POSTING_READ(reg); |
0dd87d20 | 692 | |
687f4d06 PZ |
693 | intel_hdmi_set_avi_infoframe(encoder, adjusted_mode); |
694 | intel_hdmi_set_spd_infoframe(encoder); | |
c8bb75af | 695 | intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode); |
687f4d06 PZ |
696 | } |
697 | ||
4cde8a21 | 698 | static void intel_hdmi_prepare(struct intel_encoder *encoder) |
7d57382e | 699 | { |
c59423a3 | 700 | struct drm_device *dev = encoder->base.dev; |
7d57382e | 701 | struct drm_i915_private *dev_priv = dev->dev_private; |
c59423a3 DV |
702 | struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); |
703 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); | |
6e3c9717 | 704 | struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode; |
b242b7f7 | 705 | u32 hdmi_val; |
7d57382e | 706 | |
b242b7f7 | 707 | hdmi_val = SDVO_ENCODING_HDMI; |
2af2c490 | 708 | if (!HAS_PCH_SPLIT(dev)) |
b242b7f7 | 709 | hdmi_val |= intel_hdmi->color_range; |
b599c0bc | 710 | if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) |
b242b7f7 | 711 | hdmi_val |= SDVO_VSYNC_ACTIVE_HIGH; |
b599c0bc | 712 | if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) |
b242b7f7 | 713 | hdmi_val |= SDVO_HSYNC_ACTIVE_HIGH; |
7d57382e | 714 | |
6e3c9717 | 715 | if (crtc->config->pipe_bpp > 24) |
4f3a8bc7 | 716 | hdmi_val |= HDMI_COLOR_FORMAT_12bpc; |
020f6704 | 717 | else |
4f3a8bc7 | 718 | hdmi_val |= SDVO_COLOR_FORMAT_8bpc; |
020f6704 | 719 | |
6e3c9717 | 720 | if (crtc->config->has_hdmi_sink) |
dc0fa718 | 721 | hdmi_val |= HDMI_MODE_SELECT_HDMI; |
2e3d6006 | 722 | |
75770564 | 723 | if (HAS_PCH_CPT(dev)) |
c59423a3 | 724 | hdmi_val |= SDVO_PIPE_SEL_CPT(crtc->pipe); |
44f37d1f CML |
725 | else if (IS_CHERRYVIEW(dev)) |
726 | hdmi_val |= SDVO_PIPE_SEL_CHV(crtc->pipe); | |
dc0fa718 | 727 | else |
c59423a3 | 728 | hdmi_val |= SDVO_PIPE_SEL(crtc->pipe); |
7d57382e | 729 | |
b242b7f7 PZ |
730 | I915_WRITE(intel_hdmi->hdmi_reg, hdmi_val); |
731 | POSTING_READ(intel_hdmi->hdmi_reg); | |
7d57382e EA |
732 | } |
733 | ||
85234cdc DV |
734 | static bool intel_hdmi_get_hw_state(struct intel_encoder *encoder, |
735 | enum pipe *pipe) | |
7d57382e | 736 | { |
85234cdc | 737 | struct drm_device *dev = encoder->base.dev; |
7d57382e | 738 | struct drm_i915_private *dev_priv = dev->dev_private; |
85234cdc | 739 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); |
6d129bea | 740 | enum intel_display_power_domain power_domain; |
85234cdc DV |
741 | u32 tmp; |
742 | ||
6d129bea | 743 | power_domain = intel_display_port_power_domain(encoder); |
f458ebbc | 744 | if (!intel_display_power_is_enabled(dev_priv, power_domain)) |
6d129bea ID |
745 | return false; |
746 | ||
b242b7f7 | 747 | tmp = I915_READ(intel_hdmi->hdmi_reg); |
85234cdc DV |
748 | |
749 | if (!(tmp & SDVO_ENABLE)) | |
750 | return false; | |
751 | ||
752 | if (HAS_PCH_CPT(dev)) | |
753 | *pipe = PORT_TO_PIPE_CPT(tmp); | |
71485e0a VS |
754 | else if (IS_CHERRYVIEW(dev)) |
755 | *pipe = SDVO_PORT_TO_PIPE_CHV(tmp); | |
85234cdc DV |
756 | else |
757 | *pipe = PORT_TO_PIPE(tmp); | |
758 | ||
759 | return true; | |
760 | } | |
761 | ||
045ac3b5 | 762 | static void intel_hdmi_get_config(struct intel_encoder *encoder, |
5cec258b | 763 | struct intel_crtc_state *pipe_config) |
045ac3b5 JB |
764 | { |
765 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); | |
8c875fca VS |
766 | struct drm_device *dev = encoder->base.dev; |
767 | struct drm_i915_private *dev_priv = dev->dev_private; | |
045ac3b5 | 768 | u32 tmp, flags = 0; |
18442d08 | 769 | int dotclock; |
045ac3b5 JB |
770 | |
771 | tmp = I915_READ(intel_hdmi->hdmi_reg); | |
772 | ||
773 | if (tmp & SDVO_HSYNC_ACTIVE_HIGH) | |
774 | flags |= DRM_MODE_FLAG_PHSYNC; | |
775 | else | |
776 | flags |= DRM_MODE_FLAG_NHSYNC; | |
777 | ||
778 | if (tmp & SDVO_VSYNC_ACTIVE_HIGH) | |
779 | flags |= DRM_MODE_FLAG_PVSYNC; | |
780 | else | |
781 | flags |= DRM_MODE_FLAG_NVSYNC; | |
782 | ||
6897b4b5 DV |
783 | if (tmp & HDMI_MODE_SELECT_HDMI) |
784 | pipe_config->has_hdmi_sink = true; | |
785 | ||
e43823ec JB |
786 | if (intel_hdmi->infoframe_enabled(&encoder->base)) |
787 | pipe_config->has_infoframe = true; | |
788 | ||
c84db770 | 789 | if (tmp & SDVO_AUDIO_ENABLE) |
9ed109a7 DV |
790 | pipe_config->has_audio = true; |
791 | ||
8c875fca VS |
792 | if (!HAS_PCH_SPLIT(dev) && |
793 | tmp & HDMI_COLOR_RANGE_16_235) | |
794 | pipe_config->limited_color_range = true; | |
795 | ||
2d112de7 | 796 | pipe_config->base.adjusted_mode.flags |= flags; |
18442d08 VS |
797 | |
798 | if ((tmp & SDVO_COLOR_FORMAT_MASK) == HDMI_COLOR_FORMAT_12bpc) | |
799 | dotclock = pipe_config->port_clock * 2 / 3; | |
800 | else | |
801 | dotclock = pipe_config->port_clock; | |
802 | ||
803 | if (HAS_PCH_SPLIT(dev_priv->dev)) | |
804 | ironlake_check_encoder_dotclock(pipe_config, dotclock); | |
805 | ||
2d112de7 | 806 | pipe_config->base.adjusted_mode.crtc_clock = dotclock; |
045ac3b5 JB |
807 | } |
808 | ||
5ab432ef | 809 | static void intel_enable_hdmi(struct intel_encoder *encoder) |
7d57382e | 810 | { |
5ab432ef | 811 | struct drm_device *dev = encoder->base.dev; |
7d57382e | 812 | struct drm_i915_private *dev_priv = dev->dev_private; |
dc0fa718 | 813 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); |
5ab432ef | 814 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); |
7d57382e | 815 | u32 temp; |
2deed761 WF |
816 | u32 enable_bits = SDVO_ENABLE; |
817 | ||
6e3c9717 | 818 | if (intel_crtc->config->has_audio) |
2deed761 | 819 | enable_bits |= SDVO_AUDIO_ENABLE; |
7d57382e | 820 | |
b242b7f7 | 821 | temp = I915_READ(intel_hdmi->hdmi_reg); |
d8a2d0e0 | 822 | |
7a87c289 | 823 | /* HW workaround for IBX, we need to move the port to transcoder A |
dc0fa718 PZ |
824 | * before disabling it, so restore the transcoder select bit here. */ |
825 | if (HAS_PCH_IBX(dev)) | |
826 | enable_bits |= SDVO_PIPE_SEL(intel_crtc->pipe); | |
7a87c289 | 827 | |
d8a2d0e0 ZW |
828 | /* HW workaround, need to toggle enable bit off and on for 12bpc, but |
829 | * we do this anyway which shows more stable in testing. | |
830 | */ | |
c619eed4 | 831 | if (HAS_PCH_SPLIT(dev)) { |
b242b7f7 PZ |
832 | I915_WRITE(intel_hdmi->hdmi_reg, temp & ~SDVO_ENABLE); |
833 | POSTING_READ(intel_hdmi->hdmi_reg); | |
d8a2d0e0 ZW |
834 | } |
835 | ||
5ab432ef DV |
836 | temp |= enable_bits; |
837 | ||
b242b7f7 PZ |
838 | I915_WRITE(intel_hdmi->hdmi_reg, temp); |
839 | POSTING_READ(intel_hdmi->hdmi_reg); | |
5ab432ef DV |
840 | |
841 | /* HW workaround, need to write this twice for issue that may result | |
842 | * in first write getting masked. | |
843 | */ | |
844 | if (HAS_PCH_SPLIT(dev)) { | |
b242b7f7 PZ |
845 | I915_WRITE(intel_hdmi->hdmi_reg, temp); |
846 | POSTING_READ(intel_hdmi->hdmi_reg); | |
7d57382e | 847 | } |
c1dec79a | 848 | |
6e3c9717 ACO |
849 | if (intel_crtc->config->has_audio) { |
850 | WARN_ON(!intel_crtc->config->has_hdmi_sink); | |
c1dec79a JN |
851 | DRM_DEBUG_DRIVER("Enabling HDMI audio on pipe %c\n", |
852 | pipe_name(intel_crtc->pipe)); | |
853 | intel_audio_codec_enable(encoder); | |
854 | } | |
b76cf76b | 855 | } |
89b667f8 | 856 | |
b76cf76b JN |
857 | static void vlv_enable_hdmi(struct intel_encoder *encoder) |
858 | { | |
5ab432ef DV |
859 | } |
860 | ||
861 | static void intel_disable_hdmi(struct intel_encoder *encoder) | |
862 | { | |
863 | struct drm_device *dev = encoder->base.dev; | |
864 | struct drm_i915_private *dev_priv = dev->dev_private; | |
865 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); | |
495a5bb8 | 866 | struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); |
5ab432ef | 867 | u32 temp; |
3cce574f | 868 | u32 enable_bits = SDVO_ENABLE | SDVO_AUDIO_ENABLE; |
5ab432ef | 869 | |
6e3c9717 | 870 | if (crtc->config->has_audio) |
495a5bb8 JN |
871 | intel_audio_codec_disable(encoder); |
872 | ||
b242b7f7 | 873 | temp = I915_READ(intel_hdmi->hdmi_reg); |
5ab432ef DV |
874 | |
875 | /* HW workaround for IBX, we need to move the port to transcoder A | |
876 | * before disabling it. */ | |
877 | if (HAS_PCH_IBX(dev)) { | |
878 | struct drm_crtc *crtc = encoder->base.crtc; | |
879 | int pipe = crtc ? to_intel_crtc(crtc)->pipe : -1; | |
880 | ||
881 | if (temp & SDVO_PIPE_B_SELECT) { | |
882 | temp &= ~SDVO_PIPE_B_SELECT; | |
b242b7f7 PZ |
883 | I915_WRITE(intel_hdmi->hdmi_reg, temp); |
884 | POSTING_READ(intel_hdmi->hdmi_reg); | |
5ab432ef DV |
885 | |
886 | /* Again we need to write this twice. */ | |
b242b7f7 PZ |
887 | I915_WRITE(intel_hdmi->hdmi_reg, temp); |
888 | POSTING_READ(intel_hdmi->hdmi_reg); | |
5ab432ef DV |
889 | |
890 | /* Transcoder selection bits only update | |
891 | * effectively on vblank. */ | |
892 | if (crtc) | |
893 | intel_wait_for_vblank(dev, pipe); | |
894 | else | |
895 | msleep(50); | |
896 | } | |
7d57382e | 897 | } |
d8a2d0e0 | 898 | |
5ab432ef DV |
899 | /* HW workaround, need to toggle enable bit off and on for 12bpc, but |
900 | * we do this anyway which shows more stable in testing. | |
901 | */ | |
902 | if (HAS_PCH_SPLIT(dev)) { | |
b242b7f7 PZ |
903 | I915_WRITE(intel_hdmi->hdmi_reg, temp & ~SDVO_ENABLE); |
904 | POSTING_READ(intel_hdmi->hdmi_reg); | |
5ab432ef DV |
905 | } |
906 | ||
907 | temp &= ~enable_bits; | |
d8a2d0e0 | 908 | |
b242b7f7 PZ |
909 | I915_WRITE(intel_hdmi->hdmi_reg, temp); |
910 | POSTING_READ(intel_hdmi->hdmi_reg); | |
d8a2d0e0 ZW |
911 | |
912 | /* HW workaround, need to write this twice for issue that may result | |
913 | * in first write getting masked. | |
914 | */ | |
c619eed4 | 915 | if (HAS_PCH_SPLIT(dev)) { |
b242b7f7 PZ |
916 | I915_WRITE(intel_hdmi->hdmi_reg, temp); |
917 | POSTING_READ(intel_hdmi->hdmi_reg); | |
d8a2d0e0 | 918 | } |
7d57382e EA |
919 | } |
920 | ||
40478455 | 921 | static int hdmi_portclock_limit(struct intel_hdmi *hdmi, bool respect_dvi_limit) |
7d148ef5 DV |
922 | { |
923 | struct drm_device *dev = intel_hdmi_to_dev(hdmi); | |
924 | ||
40478455 | 925 | if ((respect_dvi_limit && !hdmi->has_hdmi_sink) || IS_G4X(dev)) |
7d148ef5 | 926 | return 165000; |
e3c33578 | 927 | else if (IS_HASWELL(dev) || INTEL_INFO(dev)->gen >= 8) |
7d148ef5 DV |
928 | return 300000; |
929 | else | |
930 | return 225000; | |
931 | } | |
932 | ||
c19de8eb DL |
933 | static enum drm_mode_status |
934 | intel_hdmi_mode_valid(struct drm_connector *connector, | |
935 | struct drm_display_mode *mode) | |
7d57382e | 936 | { |
697c4078 CT |
937 | int clock = mode->clock; |
938 | ||
939 | if (mode->flags & DRM_MODE_FLAG_DBLCLK) | |
940 | clock *= 2; | |
941 | ||
942 | if (clock > hdmi_portclock_limit(intel_attached_hdmi(connector), | |
943 | true)) | |
7d57382e | 944 | return MODE_CLOCK_HIGH; |
697c4078 | 945 | if (clock < 20000) |
5cbba41d | 946 | return MODE_CLOCK_LOW; |
7d57382e EA |
947 | |
948 | if (mode->flags & DRM_MODE_FLAG_DBLSCAN) | |
949 | return MODE_NO_DBLESCAN; | |
950 | ||
951 | return MODE_OK; | |
952 | } | |
953 | ||
77f06c86 | 954 | static bool hdmi_12bpc_possible(struct intel_crtc_state *crtc_state) |
71800632 | 955 | { |
77f06c86 ACO |
956 | struct drm_device *dev = crtc_state->base.crtc->dev; |
957 | struct drm_atomic_state *state; | |
71800632 | 958 | struct intel_encoder *encoder; |
77f06c86 | 959 | struct drm_connector_state *connector_state; |
71800632 | 960 | int count = 0, count_hdmi = 0; |
77f06c86 | 961 | int i; |
71800632 | 962 | |
f227ae9e | 963 | if (HAS_GMCH_DISPLAY(dev)) |
71800632 VS |
964 | return false; |
965 | ||
77f06c86 ACO |
966 | state = crtc_state->base.state; |
967 | ||
968 | for (i = 0; i < state->num_connector; i++) { | |
969 | if (!state->connectors[i]) | |
71800632 VS |
970 | continue; |
971 | ||
77f06c86 ACO |
972 | connector_state = state->connector_states[i]; |
973 | if (connector_state->crtc != crtc_state->base.crtc) | |
974 | continue; | |
975 | ||
976 | encoder = to_intel_encoder(connector_state->best_encoder); | |
977 | ||
71800632 VS |
978 | count_hdmi += encoder->type == INTEL_OUTPUT_HDMI; |
979 | count++; | |
980 | } | |
981 | ||
982 | /* | |
983 | * HDMI 12bpc affects the clocks, so it's only possible | |
984 | * when not cloning with other encoder types. | |
985 | */ | |
986 | return count_hdmi > 0 && count_hdmi == count; | |
987 | } | |
988 | ||
5bfe2ac0 | 989 | bool intel_hdmi_compute_config(struct intel_encoder *encoder, |
5cec258b | 990 | struct intel_crtc_state *pipe_config) |
7d57382e | 991 | { |
5bfe2ac0 DV |
992 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); |
993 | struct drm_device *dev = encoder->base.dev; | |
2d112de7 ACO |
994 | struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; |
995 | int clock_12bpc = pipe_config->base.adjusted_mode.crtc_clock * 3 / 2; | |
40478455 | 996 | int portclock_limit = hdmi_portclock_limit(intel_hdmi, false); |
e29c22c0 | 997 | int desired_bpp; |
3685a8f3 | 998 | |
6897b4b5 DV |
999 | pipe_config->has_hdmi_sink = intel_hdmi->has_hdmi_sink; |
1000 | ||
e43823ec JB |
1001 | if (pipe_config->has_hdmi_sink) |
1002 | pipe_config->has_infoframe = true; | |
1003 | ||
55bc60db VS |
1004 | if (intel_hdmi->color_range_auto) { |
1005 | /* See CEA-861-E - 5.1 Default Encoding Parameters */ | |
6897b4b5 | 1006 | if (pipe_config->has_hdmi_sink && |
18316c8c | 1007 | drm_match_cea_mode(adjusted_mode) > 1) |
4f3a8bc7 | 1008 | intel_hdmi->color_range = HDMI_COLOR_RANGE_16_235; |
55bc60db VS |
1009 | else |
1010 | intel_hdmi->color_range = 0; | |
1011 | } | |
1012 | ||
697c4078 CT |
1013 | if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK) { |
1014 | pipe_config->pixel_multiplier = 2; | |
1015 | } | |
1016 | ||
3685a8f3 | 1017 | if (intel_hdmi->color_range) |
50f3b016 | 1018 | pipe_config->limited_color_range = true; |
3685a8f3 | 1019 | |
5bfe2ac0 DV |
1020 | if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev)) |
1021 | pipe_config->has_pch_encoder = true; | |
1022 | ||
9ed109a7 DV |
1023 | if (pipe_config->has_hdmi_sink && intel_hdmi->has_audio) |
1024 | pipe_config->has_audio = true; | |
1025 | ||
4e53c2e0 DV |
1026 | /* |
1027 | * HDMI is either 12 or 8, so if the display lets 10bpc sneak | |
1028 | * through, clamp it down. Note that g4x/vlv don't support 12bpc hdmi | |
325b9d04 DV |
1029 | * outputs. We also need to check that the higher clock still fits |
1030 | * within limits. | |
4e53c2e0 | 1031 | */ |
6897b4b5 | 1032 | if (pipe_config->pipe_bpp > 8*3 && pipe_config->has_hdmi_sink && |
71800632 | 1033 | clock_12bpc <= portclock_limit && |
77f06c86 | 1034 | hdmi_12bpc_possible(pipe_config)) { |
e29c22c0 DV |
1035 | DRM_DEBUG_KMS("picking bpc to 12 for HDMI output\n"); |
1036 | desired_bpp = 12*3; | |
325b9d04 DV |
1037 | |
1038 | /* Need to adjust the port link by 1.5x for 12bpc. */ | |
ff9a6750 | 1039 | pipe_config->port_clock = clock_12bpc; |
4e53c2e0 | 1040 | } else { |
e29c22c0 DV |
1041 | DRM_DEBUG_KMS("picking bpc to 8 for HDMI output\n"); |
1042 | desired_bpp = 8*3; | |
1043 | } | |
1044 | ||
1045 | if (!pipe_config->bw_constrained) { | |
1046 | DRM_DEBUG_KMS("forcing pipe bpc to %i for HDMI\n", desired_bpp); | |
1047 | pipe_config->pipe_bpp = desired_bpp; | |
4e53c2e0 DV |
1048 | } |
1049 | ||
241bfc38 | 1050 | if (adjusted_mode->crtc_clock > portclock_limit) { |
325b9d04 DV |
1051 | DRM_DEBUG_KMS("too high HDMI clock, rejecting mode\n"); |
1052 | return false; | |
1053 | } | |
1054 | ||
7d57382e EA |
1055 | return true; |
1056 | } | |
1057 | ||
953ece69 CW |
1058 | static void |
1059 | intel_hdmi_unset_edid(struct drm_connector *connector) | |
9dff6af8 | 1060 | { |
df0e9248 | 1061 | struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); |
9dff6af8 | 1062 | |
953ece69 CW |
1063 | intel_hdmi->has_hdmi_sink = false; |
1064 | intel_hdmi->has_audio = false; | |
1065 | intel_hdmi->rgb_quant_range_selectable = false; | |
1066 | ||
1067 | kfree(to_intel_connector(connector)->detect_edid); | |
1068 | to_intel_connector(connector)->detect_edid = NULL; | |
1069 | } | |
1070 | ||
1071 | static bool | |
1072 | intel_hdmi_set_edid(struct drm_connector *connector) | |
1073 | { | |
1074 | struct drm_i915_private *dev_priv = to_i915(connector->dev); | |
1075 | struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); | |
1076 | struct intel_encoder *intel_encoder = | |
1077 | &hdmi_to_dig_port(intel_hdmi)->base; | |
1078 | enum intel_display_power_domain power_domain; | |
1079 | struct edid *edid; | |
1080 | bool connected = false; | |
164c8598 | 1081 | |
671dedd2 ID |
1082 | power_domain = intel_display_port_power_domain(intel_encoder); |
1083 | intel_display_power_get(dev_priv, power_domain); | |
1084 | ||
f899fc64 | 1085 | edid = drm_get_edid(connector, |
3bd7d909 DK |
1086 | intel_gmbus_get_adapter(dev_priv, |
1087 | intel_hdmi->ddc_bus)); | |
2ded9e27 | 1088 | |
953ece69 | 1089 | intel_display_power_put(dev_priv, power_domain); |
30ad48b7 | 1090 | |
953ece69 CW |
1091 | to_intel_connector(connector)->detect_edid = edid; |
1092 | if (edid && edid->input & DRM_EDID_INPUT_DIGITAL) { | |
1093 | intel_hdmi->rgb_quant_range_selectable = | |
1094 | drm_rgb_quant_range_selectable(edid); | |
1095 | ||
1096 | intel_hdmi->has_audio = drm_detect_monitor_audio(edid); | |
b1d7e4b4 WF |
1097 | if (intel_hdmi->force_audio != HDMI_AUDIO_AUTO) |
1098 | intel_hdmi->has_audio = | |
953ece69 CW |
1099 | intel_hdmi->force_audio == HDMI_AUDIO_ON; |
1100 | ||
1101 | if (intel_hdmi->force_audio != HDMI_AUDIO_OFF_DVI) | |
1102 | intel_hdmi->has_hdmi_sink = | |
1103 | drm_detect_hdmi_monitor(edid); | |
1104 | ||
1105 | connected = true; | |
55b7d6e8 CW |
1106 | } |
1107 | ||
953ece69 CW |
1108 | return connected; |
1109 | } | |
1110 | ||
1111 | static enum drm_connector_status | |
1112 | intel_hdmi_detect(struct drm_connector *connector, bool force) | |
1113 | { | |
1114 | enum drm_connector_status status; | |
1115 | ||
1116 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", | |
1117 | connector->base.id, connector->name); | |
1118 | ||
1119 | intel_hdmi_unset_edid(connector); | |
1120 | ||
1121 | if (intel_hdmi_set_edid(connector)) { | |
1122 | struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); | |
1123 | ||
1124 | hdmi_to_dig_port(intel_hdmi)->base.type = INTEL_OUTPUT_HDMI; | |
1125 | status = connector_status_connected; | |
1126 | } else | |
1127 | status = connector_status_disconnected; | |
671dedd2 | 1128 | |
2ded9e27 | 1129 | return status; |
7d57382e EA |
1130 | } |
1131 | ||
953ece69 CW |
1132 | static void |
1133 | intel_hdmi_force(struct drm_connector *connector) | |
7d57382e | 1134 | { |
953ece69 | 1135 | struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); |
7d57382e | 1136 | |
953ece69 CW |
1137 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", |
1138 | connector->base.id, connector->name); | |
7d57382e | 1139 | |
953ece69 | 1140 | intel_hdmi_unset_edid(connector); |
671dedd2 | 1141 | |
953ece69 CW |
1142 | if (connector->status != connector_status_connected) |
1143 | return; | |
671dedd2 | 1144 | |
953ece69 CW |
1145 | intel_hdmi_set_edid(connector); |
1146 | hdmi_to_dig_port(intel_hdmi)->base.type = INTEL_OUTPUT_HDMI; | |
1147 | } | |
671dedd2 | 1148 | |
953ece69 CW |
1149 | static int intel_hdmi_get_modes(struct drm_connector *connector) |
1150 | { | |
1151 | struct edid *edid; | |
1152 | ||
1153 | edid = to_intel_connector(connector)->detect_edid; | |
1154 | if (edid == NULL) | |
1155 | return 0; | |
671dedd2 | 1156 | |
953ece69 | 1157 | return intel_connector_update_modes(connector, edid); |
7d57382e EA |
1158 | } |
1159 | ||
1aad7ac0 CW |
1160 | static bool |
1161 | intel_hdmi_detect_audio(struct drm_connector *connector) | |
1162 | { | |
1aad7ac0 | 1163 | bool has_audio = false; |
953ece69 | 1164 | struct edid *edid; |
1aad7ac0 | 1165 | |
953ece69 CW |
1166 | edid = to_intel_connector(connector)->detect_edid; |
1167 | if (edid && edid->input & DRM_EDID_INPUT_DIGITAL) | |
1168 | has_audio = drm_detect_monitor_audio(edid); | |
671dedd2 | 1169 | |
1aad7ac0 CW |
1170 | return has_audio; |
1171 | } | |
1172 | ||
55b7d6e8 CW |
1173 | static int |
1174 | intel_hdmi_set_property(struct drm_connector *connector, | |
ed517fbb PZ |
1175 | struct drm_property *property, |
1176 | uint64_t val) | |
55b7d6e8 CW |
1177 | { |
1178 | struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); | |
da63a9f2 PZ |
1179 | struct intel_digital_port *intel_dig_port = |
1180 | hdmi_to_dig_port(intel_hdmi); | |
e953fd7b | 1181 | struct drm_i915_private *dev_priv = connector->dev->dev_private; |
55b7d6e8 CW |
1182 | int ret; |
1183 | ||
662595df | 1184 | ret = drm_object_property_set_value(&connector->base, property, val); |
55b7d6e8 CW |
1185 | if (ret) |
1186 | return ret; | |
1187 | ||
3f43c48d | 1188 | if (property == dev_priv->force_audio_property) { |
b1d7e4b4 | 1189 | enum hdmi_force_audio i = val; |
1aad7ac0 CW |
1190 | bool has_audio; |
1191 | ||
1192 | if (i == intel_hdmi->force_audio) | |
55b7d6e8 CW |
1193 | return 0; |
1194 | ||
1aad7ac0 | 1195 | intel_hdmi->force_audio = i; |
55b7d6e8 | 1196 | |
b1d7e4b4 | 1197 | if (i == HDMI_AUDIO_AUTO) |
1aad7ac0 CW |
1198 | has_audio = intel_hdmi_detect_audio(connector); |
1199 | else | |
b1d7e4b4 | 1200 | has_audio = (i == HDMI_AUDIO_ON); |
1aad7ac0 | 1201 | |
b1d7e4b4 WF |
1202 | if (i == HDMI_AUDIO_OFF_DVI) |
1203 | intel_hdmi->has_hdmi_sink = 0; | |
55b7d6e8 | 1204 | |
1aad7ac0 | 1205 | intel_hdmi->has_audio = has_audio; |
55b7d6e8 CW |
1206 | goto done; |
1207 | } | |
1208 | ||
e953fd7b | 1209 | if (property == dev_priv->broadcast_rgb_property) { |
ae4edb80 DV |
1210 | bool old_auto = intel_hdmi->color_range_auto; |
1211 | uint32_t old_range = intel_hdmi->color_range; | |
1212 | ||
55bc60db VS |
1213 | switch (val) { |
1214 | case INTEL_BROADCAST_RGB_AUTO: | |
1215 | intel_hdmi->color_range_auto = true; | |
1216 | break; | |
1217 | case INTEL_BROADCAST_RGB_FULL: | |
1218 | intel_hdmi->color_range_auto = false; | |
1219 | intel_hdmi->color_range = 0; | |
1220 | break; | |
1221 | case INTEL_BROADCAST_RGB_LIMITED: | |
1222 | intel_hdmi->color_range_auto = false; | |
4f3a8bc7 | 1223 | intel_hdmi->color_range = HDMI_COLOR_RANGE_16_235; |
55bc60db VS |
1224 | break; |
1225 | default: | |
1226 | return -EINVAL; | |
1227 | } | |
ae4edb80 DV |
1228 | |
1229 | if (old_auto == intel_hdmi->color_range_auto && | |
1230 | old_range == intel_hdmi->color_range) | |
1231 | return 0; | |
1232 | ||
e953fd7b CW |
1233 | goto done; |
1234 | } | |
1235 | ||
94a11ddc VK |
1236 | if (property == connector->dev->mode_config.aspect_ratio_property) { |
1237 | switch (val) { | |
1238 | case DRM_MODE_PICTURE_ASPECT_NONE: | |
1239 | intel_hdmi->aspect_ratio = HDMI_PICTURE_ASPECT_NONE; | |
1240 | break; | |
1241 | case DRM_MODE_PICTURE_ASPECT_4_3: | |
1242 | intel_hdmi->aspect_ratio = HDMI_PICTURE_ASPECT_4_3; | |
1243 | break; | |
1244 | case DRM_MODE_PICTURE_ASPECT_16_9: | |
1245 | intel_hdmi->aspect_ratio = HDMI_PICTURE_ASPECT_16_9; | |
1246 | break; | |
1247 | default: | |
1248 | return -EINVAL; | |
1249 | } | |
1250 | goto done; | |
1251 | } | |
1252 | ||
55b7d6e8 CW |
1253 | return -EINVAL; |
1254 | ||
1255 | done: | |
c0c36b94 CW |
1256 | if (intel_dig_port->base.base.crtc) |
1257 | intel_crtc_restore_mode(intel_dig_port->base.base.crtc); | |
55b7d6e8 CW |
1258 | |
1259 | return 0; | |
1260 | } | |
1261 | ||
13732ba7 JB |
1262 | static void intel_hdmi_pre_enable(struct intel_encoder *encoder) |
1263 | { | |
1264 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); | |
1265 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); | |
1266 | struct drm_display_mode *adjusted_mode = | |
6e3c9717 | 1267 | &intel_crtc->config->base.adjusted_mode; |
13732ba7 | 1268 | |
4cde8a21 DV |
1269 | intel_hdmi_prepare(encoder); |
1270 | ||
6897b4b5 | 1271 | intel_hdmi->set_infoframes(&encoder->base, |
6e3c9717 | 1272 | intel_crtc->config->has_hdmi_sink, |
6897b4b5 | 1273 | adjusted_mode); |
13732ba7 JB |
1274 | } |
1275 | ||
9514ac6e | 1276 | static void vlv_hdmi_pre_enable(struct intel_encoder *encoder) |
89b667f8 JB |
1277 | { |
1278 | struct intel_digital_port *dport = enc_to_dig_port(&encoder->base); | |
13732ba7 | 1279 | struct intel_hdmi *intel_hdmi = &dport->hdmi; |
89b667f8 JB |
1280 | struct drm_device *dev = encoder->base.dev; |
1281 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1282 | struct intel_crtc *intel_crtc = | |
1283 | to_intel_crtc(encoder->base.crtc); | |
13732ba7 | 1284 | struct drm_display_mode *adjusted_mode = |
6e3c9717 | 1285 | &intel_crtc->config->base.adjusted_mode; |
e4607fcf | 1286 | enum dpio_channel port = vlv_dport_to_channel(dport); |
89b667f8 JB |
1287 | int pipe = intel_crtc->pipe; |
1288 | u32 val; | |
1289 | ||
89b667f8 | 1290 | /* Enable clock channels for this port */ |
0980a60f | 1291 | mutex_lock(&dev_priv->dpio_lock); |
ab3c759a | 1292 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port)); |
89b667f8 JB |
1293 | val = 0; |
1294 | if (pipe) | |
1295 | val |= (1<<21); | |
1296 | else | |
1297 | val &= ~(1<<21); | |
1298 | val |= 0x001000c4; | |
ab3c759a | 1299 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val); |
89b667f8 JB |
1300 | |
1301 | /* HDMI 1.0V-2dB */ | |
ab3c759a CML |
1302 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0); |
1303 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), 0x2b245f5f); | |
1304 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port), 0x5578b83a); | |
1305 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0c782040); | |
1306 | vlv_dpio_write(dev_priv, pipe, VLV_TX3_DW4(port), 0x2b247878); | |
1307 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000); | |
1308 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), 0x00002000); | |
1309 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), DPIO_TX_OCALINIT_EN); | |
89b667f8 JB |
1310 | |
1311 | /* Program lane clock */ | |
ab3c759a CML |
1312 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018); |
1313 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888); | |
0980a60f | 1314 | mutex_unlock(&dev_priv->dpio_lock); |
b76cf76b | 1315 | |
6897b4b5 | 1316 | intel_hdmi->set_infoframes(&encoder->base, |
6e3c9717 | 1317 | intel_crtc->config->has_hdmi_sink, |
6897b4b5 | 1318 | adjusted_mode); |
13732ba7 | 1319 | |
b76cf76b JN |
1320 | intel_enable_hdmi(encoder); |
1321 | ||
e4607fcf | 1322 | vlv_wait_port_ready(dev_priv, dport); |
89b667f8 JB |
1323 | } |
1324 | ||
9514ac6e | 1325 | static void vlv_hdmi_pre_pll_enable(struct intel_encoder *encoder) |
89b667f8 JB |
1326 | { |
1327 | struct intel_digital_port *dport = enc_to_dig_port(&encoder->base); | |
1328 | struct drm_device *dev = encoder->base.dev; | |
1329 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5e69f97f CML |
1330 | struct intel_crtc *intel_crtc = |
1331 | to_intel_crtc(encoder->base.crtc); | |
e4607fcf | 1332 | enum dpio_channel port = vlv_dport_to_channel(dport); |
5e69f97f | 1333 | int pipe = intel_crtc->pipe; |
89b667f8 | 1334 | |
4cde8a21 DV |
1335 | intel_hdmi_prepare(encoder); |
1336 | ||
89b667f8 | 1337 | /* Program Tx lane resets to default */ |
0980a60f | 1338 | mutex_lock(&dev_priv->dpio_lock); |
ab3c759a | 1339 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port), |
89b667f8 JB |
1340 | DPIO_PCS_TX_LANE2_RESET | |
1341 | DPIO_PCS_TX_LANE1_RESET); | |
ab3c759a | 1342 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port), |
89b667f8 JB |
1343 | DPIO_PCS_CLK_CRI_RXEB_EIOS_EN | |
1344 | DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN | | |
1345 | (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) | | |
1346 | DPIO_PCS_CLK_SOFT_RESET); | |
1347 | ||
1348 | /* Fix up inter-pair skew failure */ | |
ab3c759a CML |
1349 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW12(port), 0x00750f00); |
1350 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW11(port), 0x00001500); | |
1351 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000); | |
1352 | ||
1353 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), 0x00002000); | |
1354 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), DPIO_TX_OCALINIT_EN); | |
0980a60f | 1355 | mutex_unlock(&dev_priv->dpio_lock); |
89b667f8 JB |
1356 | } |
1357 | ||
9197c88b VS |
1358 | static void chv_hdmi_pre_pll_enable(struct intel_encoder *encoder) |
1359 | { | |
1360 | struct intel_digital_port *dport = enc_to_dig_port(&encoder->base); | |
1361 | struct drm_device *dev = encoder->base.dev; | |
1362 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1363 | struct intel_crtc *intel_crtc = | |
1364 | to_intel_crtc(encoder->base.crtc); | |
1365 | enum dpio_channel ch = vlv_dport_to_channel(dport); | |
1366 | enum pipe pipe = intel_crtc->pipe; | |
1367 | u32 val; | |
1368 | ||
625695f8 VS |
1369 | intel_hdmi_prepare(encoder); |
1370 | ||
9197c88b VS |
1371 | mutex_lock(&dev_priv->dpio_lock); |
1372 | ||
b9e5ac3c VS |
1373 | /* program left/right clock distribution */ |
1374 | if (pipe != PIPE_B) { | |
1375 | val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0); | |
1376 | val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK); | |
1377 | if (ch == DPIO_CH0) | |
1378 | val |= CHV_BUFLEFTENA1_FORCE; | |
1379 | if (ch == DPIO_CH1) | |
1380 | val |= CHV_BUFRIGHTENA1_FORCE; | |
1381 | vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val); | |
1382 | } else { | |
1383 | val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1); | |
1384 | val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK); | |
1385 | if (ch == DPIO_CH0) | |
1386 | val |= CHV_BUFLEFTENA2_FORCE; | |
1387 | if (ch == DPIO_CH1) | |
1388 | val |= CHV_BUFRIGHTENA2_FORCE; | |
1389 | vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val); | |
1390 | } | |
1391 | ||
9197c88b VS |
1392 | /* program clock channel usage */ |
1393 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(ch)); | |
1394 | val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE; | |
1395 | if (pipe != PIPE_B) | |
1396 | val &= ~CHV_PCS_USEDCLKCHANNEL; | |
1397 | else | |
1398 | val |= CHV_PCS_USEDCLKCHANNEL; | |
1399 | vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW8(ch), val); | |
1400 | ||
1401 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW8(ch)); | |
1402 | val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE; | |
1403 | if (pipe != PIPE_B) | |
1404 | val &= ~CHV_PCS_USEDCLKCHANNEL; | |
1405 | else | |
1406 | val |= CHV_PCS_USEDCLKCHANNEL; | |
1407 | vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW8(ch), val); | |
1408 | ||
1409 | /* | |
1410 | * This a a bit weird since generally CL | |
1411 | * matches the pipe, but here we need to | |
1412 | * pick the CL based on the port. | |
1413 | */ | |
1414 | val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW19(ch)); | |
1415 | if (pipe != PIPE_B) | |
1416 | val &= ~CHV_CMN_USEDCLKCHANNEL; | |
1417 | else | |
1418 | val |= CHV_CMN_USEDCLKCHANNEL; | |
1419 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW19(ch), val); | |
1420 | ||
1421 | mutex_unlock(&dev_priv->dpio_lock); | |
1422 | } | |
1423 | ||
9514ac6e | 1424 | static void vlv_hdmi_post_disable(struct intel_encoder *encoder) |
89b667f8 JB |
1425 | { |
1426 | struct intel_digital_port *dport = enc_to_dig_port(&encoder->base); | |
1427 | struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; | |
5e69f97f CML |
1428 | struct intel_crtc *intel_crtc = |
1429 | to_intel_crtc(encoder->base.crtc); | |
e4607fcf | 1430 | enum dpio_channel port = vlv_dport_to_channel(dport); |
5e69f97f | 1431 | int pipe = intel_crtc->pipe; |
89b667f8 JB |
1432 | |
1433 | /* Reset lanes to avoid HDMI flicker (VLV w/a) */ | |
1434 | mutex_lock(&dev_priv->dpio_lock); | |
ab3c759a CML |
1435 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port), 0x00000000); |
1436 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port), 0x00e00060); | |
89b667f8 JB |
1437 | mutex_unlock(&dev_priv->dpio_lock); |
1438 | } | |
1439 | ||
580d3811 VS |
1440 | static void chv_hdmi_post_disable(struct intel_encoder *encoder) |
1441 | { | |
1442 | struct intel_digital_port *dport = enc_to_dig_port(&encoder->base); | |
1443 | struct drm_device *dev = encoder->base.dev; | |
1444 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1445 | struct intel_crtc *intel_crtc = | |
1446 | to_intel_crtc(encoder->base.crtc); | |
1447 | enum dpio_channel ch = vlv_dport_to_channel(dport); | |
1448 | enum pipe pipe = intel_crtc->pipe; | |
1449 | u32 val; | |
1450 | ||
1451 | mutex_lock(&dev_priv->dpio_lock); | |
1452 | ||
1453 | /* Propagate soft reset to data lane reset */ | |
97fd4d5c | 1454 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch)); |
d2152b25 | 1455 | val |= CHV_PCS_REQ_SOFTRESET_EN; |
97fd4d5c | 1456 | vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val); |
d2152b25 | 1457 | |
97fd4d5c VS |
1458 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch)); |
1459 | val |= CHV_PCS_REQ_SOFTRESET_EN; | |
1460 | vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val); | |
1461 | ||
1462 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch)); | |
1463 | val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET); | |
1464 | vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val); | |
1465 | ||
1466 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch)); | |
580d3811 | 1467 | val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET); |
97fd4d5c | 1468 | vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val); |
580d3811 VS |
1469 | |
1470 | mutex_unlock(&dev_priv->dpio_lock); | |
1471 | } | |
1472 | ||
e4a1d846 CML |
1473 | static void chv_hdmi_pre_enable(struct intel_encoder *encoder) |
1474 | { | |
1475 | struct intel_digital_port *dport = enc_to_dig_port(&encoder->base); | |
b4eb1564 | 1476 | struct intel_hdmi *intel_hdmi = &dport->hdmi; |
e4a1d846 CML |
1477 | struct drm_device *dev = encoder->base.dev; |
1478 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1479 | struct intel_crtc *intel_crtc = | |
1480 | to_intel_crtc(encoder->base.crtc); | |
b4eb1564 | 1481 | struct drm_display_mode *adjusted_mode = |
6e3c9717 | 1482 | &intel_crtc->config->base.adjusted_mode; |
e4a1d846 CML |
1483 | enum dpio_channel ch = vlv_dport_to_channel(dport); |
1484 | int pipe = intel_crtc->pipe; | |
1485 | int data, i; | |
1486 | u32 val; | |
1487 | ||
e4a1d846 | 1488 | mutex_lock(&dev_priv->dpio_lock); |
949c1d43 | 1489 | |
570e2a74 VS |
1490 | /* allow hardware to manage TX FIFO reset source */ |
1491 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch)); | |
1492 | val &= ~DPIO_LANEDESKEW_STRAP_OVRD; | |
1493 | vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val); | |
1494 | ||
1495 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch)); | |
1496 | val &= ~DPIO_LANEDESKEW_STRAP_OVRD; | |
1497 | vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val); | |
1498 | ||
949c1d43 | 1499 | /* Deassert soft data lane reset*/ |
97fd4d5c | 1500 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch)); |
d2152b25 | 1501 | val |= CHV_PCS_REQ_SOFTRESET_EN; |
97fd4d5c VS |
1502 | vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val); |
1503 | ||
1504 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch)); | |
1505 | val |= CHV_PCS_REQ_SOFTRESET_EN; | |
1506 | vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val); | |
1507 | ||
1508 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch)); | |
1509 | val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET); | |
1510 | vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val); | |
d2152b25 | 1511 | |
97fd4d5c | 1512 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch)); |
949c1d43 | 1513 | val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET); |
97fd4d5c | 1514 | vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val); |
949c1d43 VS |
1515 | |
1516 | /* Program Tx latency optimal setting */ | |
e4a1d846 CML |
1517 | for (i = 0; i < 4; i++) { |
1518 | /* Set the latency optimal bit */ | |
1519 | data = (i == 1) ? 0x0 : 0x6; | |
1520 | vlv_dpio_write(dev_priv, pipe, CHV_TX_DW11(ch, i), | |
1521 | data << DPIO_FRC_LATENCY_SHFIT); | |
1522 | ||
1523 | /* Set the upar bit */ | |
1524 | data = (i == 1) ? 0x0 : 0x1; | |
1525 | vlv_dpio_write(dev_priv, pipe, CHV_TX_DW14(ch, i), | |
1526 | data << DPIO_UPAR_SHIFT); | |
1527 | } | |
1528 | ||
1529 | /* Data lane stagger programming */ | |
1530 | /* FIXME: Fix up value only after power analysis */ | |
1531 | ||
1532 | /* Clear calc init */ | |
1966e59e VS |
1533 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch)); |
1534 | val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3); | |
a02ef3c7 VS |
1535 | val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK); |
1536 | val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5; | |
1966e59e VS |
1537 | vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val); |
1538 | ||
1539 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch)); | |
1540 | val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3); | |
a02ef3c7 VS |
1541 | val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK); |
1542 | val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5; | |
1966e59e | 1543 | vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val); |
e4a1d846 | 1544 | |
a02ef3c7 VS |
1545 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW9(ch)); |
1546 | val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK); | |
1547 | val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000; | |
1548 | vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW9(ch), val); | |
1549 | ||
1550 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW9(ch)); | |
1551 | val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK); | |
1552 | val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000; | |
1553 | vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW9(ch), val); | |
1554 | ||
e4a1d846 CML |
1555 | /* FIXME: Program the support xxx V-dB */ |
1556 | /* Use 800mV-0dB */ | |
f72df8db VS |
1557 | for (i = 0; i < 4; i++) { |
1558 | val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW4(ch, i)); | |
1559 | val &= ~DPIO_SWING_DEEMPH9P5_MASK; | |
1560 | val |= 128 << DPIO_SWING_DEEMPH9P5_SHIFT; | |
1561 | vlv_dpio_write(dev_priv, pipe, CHV_TX_DW4(ch, i), val); | |
1562 | } | |
e4a1d846 | 1563 | |
f72df8db VS |
1564 | for (i = 0; i < 4; i++) { |
1565 | val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i)); | |
1fb44505 VS |
1566 | val &= ~DPIO_SWING_MARGIN000_MASK; |
1567 | val |= 102 << DPIO_SWING_MARGIN000_SHIFT; | |
f72df8db VS |
1568 | vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val); |
1569 | } | |
e4a1d846 CML |
1570 | |
1571 | /* Disable unique transition scale */ | |
f72df8db VS |
1572 | for (i = 0; i < 4; i++) { |
1573 | val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i)); | |
1574 | val &= ~DPIO_TX_UNIQ_TRANS_SCALE_EN; | |
1575 | vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val); | |
1576 | } | |
e4a1d846 CML |
1577 | |
1578 | /* Additional steps for 1200mV-0dB */ | |
1579 | #if 0 | |
1580 | val = vlv_dpio_read(dev_priv, pipe, VLV_TX_DW3(ch)); | |
1581 | if (ch) | |
1582 | val |= DPIO_TX_UNIQ_TRANS_SCALE_CH1; | |
1583 | else | |
1584 | val |= DPIO_TX_UNIQ_TRANS_SCALE_CH0; | |
1585 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(ch), val); | |
1586 | ||
1587 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(ch), | |
1588 | vlv_dpio_read(dev_priv, pipe, VLV_TX_DW2(ch)) | | |
1589 | (0x9a << DPIO_UNIQ_TRANS_SCALE_SHIFT)); | |
1590 | #endif | |
1591 | /* Start swing calculation */ | |
1966e59e VS |
1592 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch)); |
1593 | val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3; | |
1594 | vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val); | |
1595 | ||
1596 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch)); | |
1597 | val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3; | |
1598 | vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val); | |
e4a1d846 CML |
1599 | |
1600 | /* LRC Bypass */ | |
1601 | val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW30); | |
1602 | val |= DPIO_LRC_BYPASS; | |
1603 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW30, val); | |
1604 | ||
1605 | mutex_unlock(&dev_priv->dpio_lock); | |
1606 | ||
b4eb1564 | 1607 | intel_hdmi->set_infoframes(&encoder->base, |
6e3c9717 | 1608 | intel_crtc->config->has_hdmi_sink, |
b4eb1564 CT |
1609 | adjusted_mode); |
1610 | ||
e4a1d846 CML |
1611 | intel_enable_hdmi(encoder); |
1612 | ||
1613 | vlv_wait_port_ready(dev_priv, dport); | |
1614 | } | |
1615 | ||
7d57382e EA |
1616 | static void intel_hdmi_destroy(struct drm_connector *connector) |
1617 | { | |
10e972d3 | 1618 | kfree(to_intel_connector(connector)->detect_edid); |
7d57382e | 1619 | drm_connector_cleanup(connector); |
674e2d08 | 1620 | kfree(connector); |
7d57382e EA |
1621 | } |
1622 | ||
7d57382e | 1623 | static const struct drm_connector_funcs intel_hdmi_connector_funcs = { |
5ab432ef | 1624 | .dpms = intel_connector_dpms, |
7d57382e | 1625 | .detect = intel_hdmi_detect, |
953ece69 | 1626 | .force = intel_hdmi_force, |
7d57382e | 1627 | .fill_modes = drm_helper_probe_single_connector_modes, |
55b7d6e8 | 1628 | .set_property = intel_hdmi_set_property, |
2545e4a6 | 1629 | .atomic_get_property = intel_connector_atomic_get_property, |
7d57382e | 1630 | .destroy = intel_hdmi_destroy, |
c6f95f27 | 1631 | .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, |
98969725 | 1632 | .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, |
7d57382e EA |
1633 | }; |
1634 | ||
1635 | static const struct drm_connector_helper_funcs intel_hdmi_connector_helper_funcs = { | |
1636 | .get_modes = intel_hdmi_get_modes, | |
1637 | .mode_valid = intel_hdmi_mode_valid, | |
df0e9248 | 1638 | .best_encoder = intel_best_encoder, |
7d57382e EA |
1639 | }; |
1640 | ||
7d57382e | 1641 | static const struct drm_encoder_funcs intel_hdmi_enc_funcs = { |
ea5b213a | 1642 | .destroy = intel_encoder_destroy, |
7d57382e EA |
1643 | }; |
1644 | ||
94a11ddc VK |
1645 | static void |
1646 | intel_attach_aspect_ratio_property(struct drm_connector *connector) | |
1647 | { | |
1648 | if (!drm_mode_create_aspect_ratio_property(connector->dev)) | |
1649 | drm_object_attach_property(&connector->base, | |
1650 | connector->dev->mode_config.aspect_ratio_property, | |
1651 | DRM_MODE_PICTURE_ASPECT_NONE); | |
1652 | } | |
1653 | ||
55b7d6e8 CW |
1654 | static void |
1655 | intel_hdmi_add_properties(struct intel_hdmi *intel_hdmi, struct drm_connector *connector) | |
1656 | { | |
3f43c48d | 1657 | intel_attach_force_audio_property(connector); |
e953fd7b | 1658 | intel_attach_broadcast_rgb_property(connector); |
55bc60db | 1659 | intel_hdmi->color_range_auto = true; |
94a11ddc VK |
1660 | intel_attach_aspect_ratio_property(connector); |
1661 | intel_hdmi->aspect_ratio = HDMI_PICTURE_ASPECT_NONE; | |
55b7d6e8 CW |
1662 | } |
1663 | ||
00c09d70 PZ |
1664 | void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port, |
1665 | struct intel_connector *intel_connector) | |
7d57382e | 1666 | { |
b9cb234c PZ |
1667 | struct drm_connector *connector = &intel_connector->base; |
1668 | struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi; | |
1669 | struct intel_encoder *intel_encoder = &intel_dig_port->base; | |
1670 | struct drm_device *dev = intel_encoder->base.dev; | |
7d57382e | 1671 | struct drm_i915_private *dev_priv = dev->dev_private; |
174edf1f | 1672 | enum port port = intel_dig_port->port; |
373a3cf7 | 1673 | |
7d57382e | 1674 | drm_connector_init(dev, connector, &intel_hdmi_connector_funcs, |
8d91104a | 1675 | DRM_MODE_CONNECTOR_HDMIA); |
7d57382e EA |
1676 | drm_connector_helper_add(connector, &intel_hdmi_connector_helper_funcs); |
1677 | ||
c3febcc4 | 1678 | connector->interlace_allowed = 1; |
7d57382e | 1679 | connector->doublescan_allowed = 0; |
573e74ad | 1680 | connector->stereo_allowed = 1; |
66a9278e | 1681 | |
08d644ad DV |
1682 | switch (port) { |
1683 | case PORT_B: | |
988c7015 | 1684 | intel_hdmi->ddc_bus = GMBUS_PIN_DPB; |
1d843f9d | 1685 | intel_encoder->hpd_pin = HPD_PORT_B; |
08d644ad DV |
1686 | break; |
1687 | case PORT_C: | |
988c7015 | 1688 | intel_hdmi->ddc_bus = GMBUS_PIN_DPC; |
1d843f9d | 1689 | intel_encoder->hpd_pin = HPD_PORT_C; |
08d644ad DV |
1690 | break; |
1691 | case PORT_D: | |
c0c35329 | 1692 | if (IS_CHERRYVIEW(dev)) |
988c7015 | 1693 | intel_hdmi->ddc_bus = GMBUS_PIN_DPD_CHV; |
c0c35329 | 1694 | else |
988c7015 | 1695 | intel_hdmi->ddc_bus = GMBUS_PIN_DPD; |
1d843f9d | 1696 | intel_encoder->hpd_pin = HPD_PORT_D; |
08d644ad DV |
1697 | break; |
1698 | case PORT_A: | |
1d843f9d | 1699 | intel_encoder->hpd_pin = HPD_PORT_A; |
08d644ad DV |
1700 | /* Internal port only for eDP. */ |
1701 | default: | |
6e4c1677 | 1702 | BUG(); |
f8aed700 | 1703 | } |
7d57382e | 1704 | |
7637bfdb | 1705 | if (IS_VALLEYVIEW(dev)) { |
90b107c8 | 1706 | intel_hdmi->write_infoframe = vlv_write_infoframe; |
687f4d06 | 1707 | intel_hdmi->set_infoframes = vlv_set_infoframes; |
e43823ec | 1708 | intel_hdmi->infoframe_enabled = vlv_infoframe_enabled; |
b98856a8 | 1709 | } else if (IS_G4X(dev)) { |
7637bfdb JB |
1710 | intel_hdmi->write_infoframe = g4x_write_infoframe; |
1711 | intel_hdmi->set_infoframes = g4x_set_infoframes; | |
e43823ec | 1712 | intel_hdmi->infoframe_enabled = g4x_infoframe_enabled; |
22b8bf17 | 1713 | } else if (HAS_DDI(dev)) { |
8c5f5f7c | 1714 | intel_hdmi->write_infoframe = hsw_write_infoframe; |
687f4d06 | 1715 | intel_hdmi->set_infoframes = hsw_set_infoframes; |
e43823ec | 1716 | intel_hdmi->infoframe_enabled = hsw_infoframe_enabled; |
fdf1250a PZ |
1717 | } else if (HAS_PCH_IBX(dev)) { |
1718 | intel_hdmi->write_infoframe = ibx_write_infoframe; | |
687f4d06 | 1719 | intel_hdmi->set_infoframes = ibx_set_infoframes; |
e43823ec | 1720 | intel_hdmi->infoframe_enabled = ibx_infoframe_enabled; |
fdf1250a PZ |
1721 | } else { |
1722 | intel_hdmi->write_infoframe = cpt_write_infoframe; | |
687f4d06 | 1723 | intel_hdmi->set_infoframes = cpt_set_infoframes; |
e43823ec | 1724 | intel_hdmi->infoframe_enabled = cpt_infoframe_enabled; |
64a8fc01 | 1725 | } |
45187ace | 1726 | |
affa9354 | 1727 | if (HAS_DDI(dev)) |
bcbc889b PZ |
1728 | intel_connector->get_hw_state = intel_ddi_connector_get_hw_state; |
1729 | else | |
1730 | intel_connector->get_hw_state = intel_connector_get_hw_state; | |
4932e2c3 | 1731 | intel_connector->unregister = intel_connector_unregister; |
b9cb234c PZ |
1732 | |
1733 | intel_hdmi_add_properties(intel_hdmi, connector); | |
1734 | ||
1735 | intel_connector_attach_encoder(intel_connector, intel_encoder); | |
34ea3d38 | 1736 | drm_connector_register(connector); |
b9cb234c PZ |
1737 | |
1738 | /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written | |
1739 | * 0xd. Failure to do so will result in spurious interrupts being | |
1740 | * generated on the port when a cable is not attached. | |
1741 | */ | |
1742 | if (IS_G4X(dev) && !IS_GM45(dev)) { | |
1743 | u32 temp = I915_READ(PEG_BAND_GAP_DATA); | |
1744 | I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd); | |
1745 | } | |
1746 | } | |
1747 | ||
b242b7f7 | 1748 | void intel_hdmi_init(struct drm_device *dev, int hdmi_reg, enum port port) |
b9cb234c PZ |
1749 | { |
1750 | struct intel_digital_port *intel_dig_port; | |
1751 | struct intel_encoder *intel_encoder; | |
b9cb234c PZ |
1752 | struct intel_connector *intel_connector; |
1753 | ||
b14c5679 | 1754 | intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL); |
b9cb234c PZ |
1755 | if (!intel_dig_port) |
1756 | return; | |
1757 | ||
9bdbd0b9 | 1758 | intel_connector = intel_connector_alloc(); |
b9cb234c PZ |
1759 | if (!intel_connector) { |
1760 | kfree(intel_dig_port); | |
1761 | return; | |
1762 | } | |
1763 | ||
1764 | intel_encoder = &intel_dig_port->base; | |
b9cb234c PZ |
1765 | |
1766 | drm_encoder_init(dev, &intel_encoder->base, &intel_hdmi_enc_funcs, | |
1767 | DRM_MODE_ENCODER_TMDS); | |
00c09d70 | 1768 | |
5bfe2ac0 | 1769 | intel_encoder->compute_config = intel_hdmi_compute_config; |
00c09d70 PZ |
1770 | intel_encoder->disable = intel_disable_hdmi; |
1771 | intel_encoder->get_hw_state = intel_hdmi_get_hw_state; | |
045ac3b5 | 1772 | intel_encoder->get_config = intel_hdmi_get_config; |
e4a1d846 | 1773 | if (IS_CHERRYVIEW(dev)) { |
9197c88b | 1774 | intel_encoder->pre_pll_enable = chv_hdmi_pre_pll_enable; |
e4a1d846 CML |
1775 | intel_encoder->pre_enable = chv_hdmi_pre_enable; |
1776 | intel_encoder->enable = vlv_enable_hdmi; | |
580d3811 | 1777 | intel_encoder->post_disable = chv_hdmi_post_disable; |
e4a1d846 | 1778 | } else if (IS_VALLEYVIEW(dev)) { |
9514ac6e CML |
1779 | intel_encoder->pre_pll_enable = vlv_hdmi_pre_pll_enable; |
1780 | intel_encoder->pre_enable = vlv_hdmi_pre_enable; | |
b76cf76b | 1781 | intel_encoder->enable = vlv_enable_hdmi; |
9514ac6e | 1782 | intel_encoder->post_disable = vlv_hdmi_post_disable; |
b76cf76b | 1783 | } else { |
13732ba7 | 1784 | intel_encoder->pre_enable = intel_hdmi_pre_enable; |
b76cf76b | 1785 | intel_encoder->enable = intel_enable_hdmi; |
89b667f8 | 1786 | } |
5ab432ef | 1787 | |
b9cb234c | 1788 | intel_encoder->type = INTEL_OUTPUT_HDMI; |
882ec384 VS |
1789 | if (IS_CHERRYVIEW(dev)) { |
1790 | if (port == PORT_D) | |
1791 | intel_encoder->crtc_mask = 1 << 2; | |
1792 | else | |
1793 | intel_encoder->crtc_mask = (1 << 0) | (1 << 1); | |
1794 | } else { | |
1795 | intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2); | |
1796 | } | |
301ea74a | 1797 | intel_encoder->cloneable = 1 << INTEL_OUTPUT_ANALOG; |
c6f1495d VS |
1798 | /* |
1799 | * BSpec is unclear about HDMI+HDMI cloning on g4x, but it seems | |
1800 | * to work on real hardware. And since g4x can send infoframes to | |
1801 | * only one port anyway, nothing is lost by allowing it. | |
1802 | */ | |
1803 | if (IS_G4X(dev)) | |
1804 | intel_encoder->cloneable |= 1 << INTEL_OUTPUT_HDMI; | |
7d57382e | 1805 | |
174edf1f | 1806 | intel_dig_port->port = port; |
b242b7f7 | 1807 | intel_dig_port->hdmi.hdmi_reg = hdmi_reg; |
b9cb234c | 1808 | intel_dig_port->dp.output_reg = 0; |
55b7d6e8 | 1809 | |
b9cb234c | 1810 | intel_hdmi_init_connector(intel_dig_port, intel_connector); |
7d57382e | 1811 | } |