[mirror_ubuntu-eoan-kernel.git] / drivers / gpu / drm / i915 / intel_hdmi.c

/*
 * Copyright 2006 Dave Airlie <airlied@linux.ie>
 * Copyright © 2006-2009 Intel Corporation
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
 * DEALINGS IN THE SOFTWARE.
 *
 * Authors:
 *	Eric Anholt <eric@anholt.net>
 *	Jesse Barnes <jesse.barnes@intel.com>
 */

#include <linux/i2c.h>
#include <linux/slab.h>
#include <linux/delay.h>
#include "drmP.h"
#include "drm.h"
#include "drm_crtc.h"
#include "drm_edid.h"
#include "intel_drv.h"
#include "i915_drm.h"
#include "i915_drv.h"

struct intel_hdmi {
	struct intel_encoder base;
	u32 sdvox_reg;
	int ddc_bus;
	uint32_t color_range;
	bool has_hdmi_sink;
	bool has_audio;
	int force_audio;
};

static struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder)
{
	return container_of(encoder, struct intel_hdmi, base.base);
}

static struct intel_hdmi *intel_attached_hdmi(struct drm_connector *connector)
{
	return container_of(intel_attached_encoder(connector),
			    struct intel_hdmi, base);
}

void intel_dip_infoframe_csum(struct dip_infoframe *avi_if)
{
	uint8_t *data = (uint8_t *)avi_if;
	uint8_t sum = 0;
	unsigned i;

	avi_if->checksum = 0;
	avi_if->ecc = 0;

	for (i = 0; i < sizeof(*avi_if); i++)
		sum += data[i];

	avi_if->checksum = 0x100 - sum;
}

static void intel_hdmi_set_avi_infoframe(struct drm_encoder *encoder)
{
	struct dip_infoframe avi_if = {
		.type = DIP_TYPE_AVI,
		.ver = DIP_VERSION_AVI,
		.len = DIP_LEN_AVI,
	};
	uint32_t *data = (uint32_t *)&avi_if;
	struct drm_device *dev = encoder->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
	u32 port;
	unsigned i;

	if (!intel_hdmi->has_hdmi_sink)
		return;

	/* XXX first guess at handling video port, is this corrent? */
	if (intel_hdmi->sdvox_reg == SDVOB)
		port = VIDEO_DIP_PORT_B;
	else if (intel_hdmi->sdvox_reg == SDVOC)
		port = VIDEO_DIP_PORT_C;
	else
		return;

	I915_WRITE(VIDEO_DIP_CTL, VIDEO_DIP_ENABLE | port |
		   VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC);

	intel_dip_infoframe_csum(&avi_if);
	for (i = 0; i < sizeof(avi_if); i += 4) {
		I915_WRITE(VIDEO_DIP_DATA, *data);
		data++;
	}

	I915_WRITE(VIDEO_DIP_CTL, VIDEO_DIP_ENABLE | port |
		   VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC |
		   VIDEO_DIP_ENABLE_AVI);
}

static void intel_hdmi_mode_set(struct drm_encoder *encoder,
				struct drm_display_mode *mode,
				struct drm_display_mode *adjusted_mode)
{
	struct drm_device *dev = encoder->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct drm_crtc *crtc = encoder->crtc;
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
	struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
	u32 sdvox;

	sdvox = SDVO_ENCODING_HDMI | SDVO_BORDER_ENABLE;
	sdvox |= intel_hdmi->color_range;
	if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
		sdvox |= SDVO_VSYNC_ACTIVE_HIGH;
	if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
		sdvox |= SDVO_HSYNC_ACTIVE_HIGH;

	/* Required on CPT */
	if (intel_hdmi->has_hdmi_sink && HAS_PCH_CPT(dev))
		sdvox |= HDMI_MODE_SELECT;

	if (intel_hdmi->has_audio) {
		sdvox |= SDVO_AUDIO_ENABLE;
		sdvox |= SDVO_NULL_PACKETS_DURING_VSYNC;
	}

	if (intel_crtc->pipe == 1) {
		if (HAS_PCH_CPT(dev))
			sdvox |= PORT_TRANS_B_SEL_CPT;
		else
			sdvox |= SDVO_PIPE_B_SELECT;
	}

	I915_WRITE(intel_hdmi->sdvox_reg, sdvox);
	POSTING_READ(intel_hdmi->sdvox_reg);

	intel_hdmi_set_avi_infoframe(encoder);
}

static void intel_hdmi_dpms(struct drm_encoder *encoder, int mode)
{
	struct drm_device *dev = encoder->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
	u32 temp;

	temp = I915_READ(intel_hdmi->sdvox_reg);

	/* HW workaround, need to toggle enable bit off and on for 12bpc, but
	 * we do this anyway which shows more stable in testing.
	 */
	if (HAS_PCH_SPLIT(dev)) {
		I915_WRITE(intel_hdmi->sdvox_reg, temp & ~SDVO_ENABLE);
		POSTING_READ(intel_hdmi->sdvox_reg);
	}

	if (mode != DRM_MODE_DPMS_ON) {
		temp &= ~SDVO_ENABLE;
	} else {
		temp |= SDVO_ENABLE;
	}

	I915_WRITE(intel_hdmi->sdvox_reg, temp);
	POSTING_READ(intel_hdmi->sdvox_reg);

	/* HW workaround, need to write this twice for issue that may result
	 * in first write getting masked.
	 */
	if (HAS_PCH_SPLIT(dev)) {
		I915_WRITE(intel_hdmi->sdvox_reg, temp);
		POSTING_READ(intel_hdmi->sdvox_reg);
	}
}

static int intel_hdmi_mode_valid(struct drm_connector *connector,
				 struct drm_display_mode *mode)
{
	if (mode->clock > 165000)
		return MODE_CLOCK_HIGH;
	if (mode->clock < 20000)
		return MODE_CLOCK_LOW;

	if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
		return MODE_NO_DBLESCAN;

	return MODE_OK;
}

static bool intel_hdmi_mode_fixup(struct drm_encoder *encoder,
				  struct drm_display_mode *mode,
				  struct drm_display_mode *adjusted_mode)
{
	return true;
}

static enum drm_connector_status
intel_hdmi_detect(struct drm_connector *connector, bool force)
{
	struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
	struct drm_i915_private *dev_priv = connector->dev->dev_private;
	struct edid *edid;
	enum drm_connector_status status = connector_status_disconnected;

	intel_hdmi->has_hdmi_sink = false;
	intel_hdmi->has_audio = false;
	edid = drm_get_edid(connector,
			    &dev_priv->gmbus[intel_hdmi->ddc_bus].adapter);

	if (edid) {
		if (edid->input & DRM_EDID_INPUT_DIGITAL) {
			status = connector_status_connected;
			intel_hdmi->has_hdmi_sink = drm_detect_hdmi_monitor(edid);
			intel_hdmi->has_audio = drm_detect_monitor_audio(edid);
		}
		connector->display_info.raw_edid = NULL;
		kfree(edid);
	}

	if (status == connector_status_connected) {
		if (intel_hdmi->force_audio)
			intel_hdmi->has_audio = intel_hdmi->force_audio > 0;
	}

	return status;
}

static int intel_hdmi_get_modes(struct drm_connector *connector)
{
	struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
	struct drm_i915_private *dev_priv = connector->dev->dev_private;

	/* We should parse the EDID data and find out if it's an HDMI sink so
	 * we can send audio to it.
	 */

	return intel_ddc_get_modes(connector,
				   &dev_priv->gmbus[intel_hdmi->ddc_bus].adapter);
}

static bool
intel_hdmi_detect_audio(struct drm_connector *connector)
{
	struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
	struct drm_i915_private *dev_priv = connector->dev->dev_private;
	struct edid *edid;
	bool has_audio = false;

	edid = drm_get_edid(connector,
			    &dev_priv->gmbus[intel_hdmi->ddc_bus].adapter);
	if (edid) {
		if (edid->input & DRM_EDID_INPUT_DIGITAL)
			has_audio = drm_detect_monitor_audio(edid);

		connector->display_info.raw_edid = NULL;
		kfree(edid);
	}

	return has_audio;
}

static int
intel_hdmi_set_property(struct drm_connector *connector,
		      struct drm_property *property,
		      uint64_t val)
{
	struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
	struct drm_i915_private *dev_priv = connector->dev->dev_private;
	int ret;

	ret = drm_connector_property_set_value(connector, property, val);
	if (ret)
		return ret;

	if (property == dev_priv->force_audio_property) {
		int i = val;
		bool has_audio;

		if (i == intel_hdmi->force_audio)
			return 0;

		intel_hdmi->force_audio = i;

		if (i == 0)
			has_audio = intel_hdmi_detect_audio(connector);
		else
			has_audio = i > 0;

		if (has_audio == intel_hdmi->has_audio)
			return 0;

		intel_hdmi->has_audio = has_audio;
		goto done;
	}

	if (property == dev_priv->broadcast_rgb_property) {
		if (val == !!intel_hdmi->color_range)
			return 0;

		intel_hdmi->color_range = val ? SDVO_COLOR_RANGE_16_235 : 0;
		goto done;
	}

	return -EINVAL;

done:
	if (intel_hdmi->base.base.crtc) {
		struct drm_crtc *crtc = intel_hdmi->base.base.crtc;
		drm_crtc_helper_set_mode(crtc, &crtc->mode,
					 crtc->x, crtc->y,
					 crtc->fb);
	}

	return 0;
}

static void intel_hdmi_destroy(struct drm_connector *connector)
{
	drm_sysfs_connector_remove(connector);
	drm_connector_cleanup(connector);
	kfree(connector);
}

static const struct drm_encoder_helper_funcs intel_hdmi_helper_funcs = {
	.dpms = intel_hdmi_dpms,
	.mode_fixup = intel_hdmi_mode_fixup,
	.prepare = intel_encoder_prepare,
	.mode_set = intel_hdmi_mode_set,
	.commit = intel_encoder_commit,
};

static const struct drm_connector_funcs intel_hdmi_connector_funcs = {
	.dpms = drm_helper_connector_dpms,
	.detect = intel_hdmi_detect,
	.fill_modes = drm_helper_probe_single_connector_modes,
	.set_property = intel_hdmi_set_property,
	.destroy = intel_hdmi_destroy,
};

static const struct drm_connector_helper_funcs intel_hdmi_connector_helper_funcs = {
	.get_modes = intel_hdmi_get_modes,
	.mode_valid = intel_hdmi_mode_valid,
	.best_encoder = intel_best_encoder,
};

static const struct drm_encoder_funcs intel_hdmi_enc_funcs = {
	.destroy = intel_encoder_destroy,
};

static void
intel_hdmi_add_properties(struct intel_hdmi *intel_hdmi, struct drm_connector *connector)
{
	intel_attach_force_audio_property(connector);
	intel_attach_broadcast_rgb_property(connector);
}

void intel_hdmi_init(struct drm_device *dev, int sdvox_reg)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct drm_connector *connector;
	struct intel_encoder *intel_encoder;
	struct intel_connector *intel_connector;
	struct intel_hdmi *intel_hdmi;

	intel_hdmi = kzalloc(sizeof(struct intel_hdmi), GFP_KERNEL);
	if (!intel_hdmi)
		return;

	intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL);
	if (!intel_connector) {
		kfree(intel_hdmi);
		return;
	}

	intel_encoder = &intel_hdmi->base;
	drm_encoder_init(dev, &intel_encoder->base, &intel_hdmi_enc_funcs,
			 DRM_MODE_ENCODER_TMDS);

	connector = &intel_connector->base;
	drm_connector_init(dev, connector, &intel_hdmi_connector_funcs,
			   DRM_MODE_CONNECTOR_HDMIA);
	drm_connector_helper_add(connector, &intel_hdmi_connector_helper_funcs);

	intel_encoder->type = INTEL_OUTPUT_HDMI;

	connector->polled = DRM_CONNECTOR_POLL_HPD;
	connector->interlace_allowed = 0;
	connector->doublescan_allowed = 0;
	intel_encoder->crtc_mask = (1 << 0) | (1 << 1);

	/* Set up the DDC bus. */
	if (sdvox_reg == SDVOB) {
		intel_encoder->clone_mask = (1 << INTEL_HDMIB_CLONE_BIT);
		intel_hdmi->ddc_bus = GMBUS_PORT_DPB;
		dev_priv->hotplug_supported_mask |= HDMIB_HOTPLUG_INT_STATUS;
	} else if (sdvox_reg == SDVOC) {
		intel_encoder->clone_mask = (1 << INTEL_HDMIC_CLONE_BIT);
		intel_hdmi->ddc_bus = GMBUS_PORT_DPC;
		dev_priv->hotplug_supported_mask |= HDMIC_HOTPLUG_INT_STATUS;
	} else if (sdvox_reg == HDMIB) {
		intel_encoder->clone_mask = (1 << INTEL_HDMID_CLONE_BIT);
		intel_hdmi->ddc_bus = GMBUS_PORT_DPB;
		dev_priv->hotplug_supported_mask |= HDMIB_HOTPLUG_INT_STATUS;
	} else if (sdvox_reg == HDMIC) {
		intel_encoder->clone_mask = (1 << INTEL_HDMIE_CLONE_BIT);
		intel_hdmi->ddc_bus = GMBUS_PORT_DPC;
		dev_priv->hotplug_supported_mask |= HDMIC_HOTPLUG_INT_STATUS;
	} else if (sdvox_reg == HDMID) {
		intel_encoder->clone_mask = (1 << INTEL_HDMIF_CLONE_BIT);
		intel_hdmi->ddc_bus = GMBUS_PORT_DPD;
		dev_priv->hotplug_supported_mask |= HDMID_HOTPLUG_INT_STATUS;
	}

	intel_hdmi->sdvox_reg = sdvox_reg;

	drm_encoder_helper_add(&intel_encoder->base, &intel_hdmi_helper_funcs);

	intel_hdmi_add_properties(intel_hdmi, connector);

	intel_connector_attach_encoder(intel_connector, intel_encoder);
	drm_sysfs_connector_add(connector);

	/* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
	 * 0xd.  Failure to do so will result in spurious interrupts being
	 * generated on the port when a cable is not attached.
	 */
	if (IS_G4X(dev) && !IS_GM45(dev)) {
		u32 temp = I915_READ(PEG_BAND_GAP_DATA);
		I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
	}
}
Commit	Line	Data
7d57382e EA	1	/*
	2	* Copyright 2006 Dave Airlie <airlied@linux.ie>
	3	* Copyright © 2006-2009 Intel Corporation
	4	*
	5	* Permission is hereby granted, free of charge, to any person obtaining a
	6	* copy of this software and associated documentation files (the "Software"),
	7	* to deal in the Software without restriction, including without limitation
	8	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	9	* and/or sell copies of the Software, and to permit persons to whom the
	10	* Software is furnished to do so, subject to the following conditions:
	11	*
	12	* The above copyright notice and this permission notice (including the next
	13	* paragraph) shall be included in all copies or substantial portions of the
	14	* Software.
	15	*
	16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	19	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	20	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
	21	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
	22	* DEALINGS IN THE SOFTWARE.
	23	*
	24	* Authors:
	25	* Eric Anholt <eric@anholt.net>
	26	* Jesse Barnes <jesse.barnes@intel.com>
	27	*/
	28
	29	#include <linux/i2c.h>
5a0e3ad6	30	#include <linux/slab.h>
7d57382e EA	31	#include <linux/delay.h>
	32	#include "drmP.h"
	33	#include "drm.h"
	34	#include "drm_crtc.h"
aa93d632	35	#include "drm_edid.h"
7d57382e EA	36	#include "intel_drv.h"
	37	#include "i915_drm.h"
	38	#include "i915_drv.h"
	39
ea5b213a CW	40	struct intel_hdmi {
ea5b213a CW	41	struct intel_encoder base;
7d57382e	42	u32 sdvox_reg;
f899fc64	43	int ddc_bus;
e953fd7b	44	uint32_t color_range;
9dff6af8	45	bool has_hdmi_sink;
2e3d6006	46	bool has_audio;
55b7d6e8	47	int force_audio;
7d57382e EA	48	};
7d57382e EA	49
ea5b213a CW	50	static struct intel_hdmi enc_to_intel_hdmi(struct drm_encoder encoder)
ea5b213a CW	51	{
4ef69c7a	52	return container_of(encoder, struct intel_hdmi, base.base);
ea5b213a CW	53	}
ea5b213a CW	54
df0e9248 CW	55	static struct intel_hdmi intel_attached_hdmi(struct drm_connector connector)
	56	{
	57	return container_of(intel_attached_encoder(connector),
	58	struct intel_hdmi, base);
	59	}
	60
3c17fe4b DH	61	void intel_dip_infoframe_csum(struct dip_infoframe *avi_if)
	62	{
	63	uint8_t data = (uint8_t )avi_if;
	64	uint8_t sum = 0;
	65	unsigned i;
	66
	67	avi_if->checksum = 0;
	68	avi_if->ecc = 0;
	69
	70	for (i = 0; i < sizeof(*avi_if); i++)
	71	sum += data[i];
	72
	73	avi_if->checksum = 0x100 - sum;
	74	}
	75
	76	static void intel_hdmi_set_avi_infoframe(struct drm_encoder *encoder)
	77	{
	78	struct dip_infoframe avi_if = {
	79	.type = DIP_TYPE_AVI,
	80	.ver = DIP_VERSION_AVI,
	81	.len = DIP_LEN_AVI,
	82	};
	83	uint32_t data = (uint32_t )&avi_if;
	84	struct drm_device *dev = encoder->dev;
	85	struct drm_i915_private *dev_priv = dev->dev_private;
	86	struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
	87	u32 port;
	88	unsigned i;
	89
	90	if (!intel_hdmi->has_hdmi_sink)
	91	return;
	92
	93	/* XXX first guess at handling video port, is this corrent? */
	94	if (intel_hdmi->sdvox_reg == SDVOB)
	95	port = VIDEO_DIP_PORT_B;
	96	else if (intel_hdmi->sdvox_reg == SDVOC)
	97	port = VIDEO_DIP_PORT_C;
	98	else
	99	return;
	100
	101	I915_WRITE(VIDEO_DIP_CTL, VIDEO_DIP_ENABLE \| port \|
	102	VIDEO_DIP_SELECT_AVI \| VIDEO_DIP_FREQ_VSYNC);
	103
	104	intel_dip_infoframe_csum(&avi_if);
	105	for (i = 0; i < sizeof(avi_if); i += 4) {
	106	I915_WRITE(VIDEO_DIP_DATA, *data);
	107	data++;
	108	}
	109
	110	I915_WRITE(VIDEO_DIP_CTL, VIDEO_DIP_ENABLE \| port \|
	111	VIDEO_DIP_SELECT_AVI \| VIDEO_DIP_FREQ_VSYNC \|
	112	VIDEO_DIP_ENABLE_AVI);
	113	}
	114
7d57382e EA	115	static void intel_hdmi_mode_set(struct drm_encoder *encoder,
	116	struct drm_display_mode *mode,
	117	struct drm_display_mode *adjusted_mode)
	118	{
	119	struct drm_device *dev = encoder->dev;
	120	struct drm_i915_private *dev_priv = dev->dev_private;
	121	struct drm_crtc *crtc = encoder->crtc;
	122	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ea5b213a	123	struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
7d57382e EA	124	u32 sdvox;
7d57382e EA	125
b599c0bc	126	sdvox = SDVO_ENCODING_HDMI \| SDVO_BORDER_ENABLE;
e953fd7b	127	sdvox \|= intel_hdmi->color_range;
b599c0bc AJ	128	if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
	129	sdvox \|= SDVO_VSYNC_ACTIVE_HIGH;
	130	if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
	131	sdvox \|= SDVO_HSYNC_ACTIVE_HIGH;
7d57382e	132
2e3d6006 ZW	133	/* Required on CPT */
	134	if (intel_hdmi->has_hdmi_sink && HAS_PCH_CPT(dev))
	135	sdvox \|= HDMI_MODE_SELECT;
	136
3c17fe4b	137	if (intel_hdmi->has_audio) {
7d57382e	138	sdvox \|= SDVO_AUDIO_ENABLE;
3c17fe4b DH	139	sdvox \|= SDVO_NULL_PACKETS_DURING_VSYNC;
3c17fe4b DH	140	}
7d57382e	141
0f229062 ZW	142	if (intel_crtc->pipe == 1) {
	143	if (HAS_PCH_CPT(dev))
	144	sdvox \|= PORT_TRANS_B_SEL_CPT;
	145	else
	146	sdvox \|= SDVO_PIPE_B_SELECT;
	147	}
7d57382e	148
ea5b213a CW	149	I915_WRITE(intel_hdmi->sdvox_reg, sdvox);
ea5b213a CW	150	POSTING_READ(intel_hdmi->sdvox_reg);
3c17fe4b DH	151
3c17fe4b DH	152	intel_hdmi_set_avi_infoframe(encoder);
7d57382e EA	153	}
	154
	155	static void intel_hdmi_dpms(struct drm_encoder *encoder, int mode)
	156	{
	157	struct drm_device *dev = encoder->dev;
	158	struct drm_i915_private *dev_priv = dev->dev_private;
ea5b213a	159	struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
7d57382e EA	160	u32 temp;
7d57382e EA	161
ea5b213a	162	temp = I915_READ(intel_hdmi->sdvox_reg);
d8a2d0e0 ZW	163
	164	/* HW workaround, need to toggle enable bit off and on for 12bpc, but
	165	* we do this anyway which shows more stable in testing.
	166	*/
c619eed4	167	if (HAS_PCH_SPLIT(dev)) {
ea5b213a CW	168	I915_WRITE(intel_hdmi->sdvox_reg, temp & ~SDVO_ENABLE);
ea5b213a CW	169	POSTING_READ(intel_hdmi->sdvox_reg);
d8a2d0e0 ZW	170	}
	171
	172	if (mode != DRM_MODE_DPMS_ON) {
	173	temp &= ~SDVO_ENABLE;
7d57382e	174	} else {
d8a2d0e0	175	temp \|= SDVO_ENABLE;
7d57382e	176	}
d8a2d0e0	177
ea5b213a CW	178	I915_WRITE(intel_hdmi->sdvox_reg, temp);
ea5b213a CW	179	POSTING_READ(intel_hdmi->sdvox_reg);
d8a2d0e0 ZW	180
	181	/* HW workaround, need to write this twice for issue that may result
	182	* in first write getting masked.
	183	*/
c619eed4	184	if (HAS_PCH_SPLIT(dev)) {
ea5b213a CW	185	I915_WRITE(intel_hdmi->sdvox_reg, temp);
ea5b213a CW	186	POSTING_READ(intel_hdmi->sdvox_reg);
d8a2d0e0	187	}
7d57382e EA	188	}
7d57382e EA	189
7d57382e EA	190	static int intel_hdmi_mode_valid(struct drm_connector *connector,
	191	struct drm_display_mode *mode)
	192	{
	193	if (mode->clock > 165000)
	194	return MODE_CLOCK_HIGH;
	195	if (mode->clock < 20000)
5cbba41d	196	return MODE_CLOCK_LOW;
7d57382e EA	197
	198	if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
	199	return MODE_NO_DBLESCAN;
	200
	201	return MODE_OK;
	202	}
	203
	204	static bool intel_hdmi_mode_fixup(struct drm_encoder *encoder,
	205	struct drm_display_mode *mode,
	206	struct drm_display_mode *adjusted_mode)
	207	{
	208	return true;
	209	}
	210
aa93d632	211	static enum drm_connector_status
930a9e28	212	intel_hdmi_detect(struct drm_connector *connector, bool force)
9dff6af8	213	{
df0e9248	214	struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
f899fc64 CW	215	struct drm_i915_private *dev_priv = connector->dev->dev_private;
f899fc64 CW	216	struct edid *edid;
aa93d632	217	enum drm_connector_status status = connector_status_disconnected;
9dff6af8	218
ea5b213a	219	intel_hdmi->has_hdmi_sink = false;
2e3d6006	220	intel_hdmi->has_audio = false;
f899fc64 CW	221	edid = drm_get_edid(connector,
f899fc64 CW	222	&dev_priv->gmbus[intel_hdmi->ddc_bus].adapter);
2ded9e27	223
aa93d632	224	if (edid) {
be9f1c4f	225	if (edid->input & DRM_EDID_INPUT_DIGITAL) {
aa93d632	226	status = connector_status_connected;
ea5b213a	227	intel_hdmi->has_hdmi_sink = drm_detect_hdmi_monitor(edid);
2e3d6006	228	intel_hdmi->has_audio = drm_detect_monitor_audio(edid);
aa93d632	229	}
674e2d08	230	connector->display_info.raw_edid = NULL;
aa93d632	231	kfree(edid);
9dff6af8	232	}
30ad48b7	233
55b7d6e8 CW	234	if (status == connector_status_connected) {
	235	if (intel_hdmi->force_audio)
	236	intel_hdmi->has_audio = intel_hdmi->force_audio > 0;
	237	}
	238
2ded9e27	239	return status;
7d57382e EA	240	}
	241
	242	static int intel_hdmi_get_modes(struct drm_connector *connector)
	243	{
df0e9248	244	struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
f899fc64	245	struct drm_i915_private *dev_priv = connector->dev->dev_private;
7d57382e EA	246
	247	/* We should parse the EDID data and find out if it's an HDMI sink so
	248	* we can send audio to it.
	249	*/
	250
f899fc64 CW	251	return intel_ddc_get_modes(connector,
f899fc64 CW	252	&dev_priv->gmbus[intel_hdmi->ddc_bus].adapter);
7d57382e EA	253	}
7d57382e EA	254
1aad7ac0 CW	255	static bool
	256	intel_hdmi_detect_audio(struct drm_connector *connector)
	257	{
	258	struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
	259	struct drm_i915_private *dev_priv = connector->dev->dev_private;
	260	struct edid *edid;
	261	bool has_audio = false;
	262
	263	edid = drm_get_edid(connector,
	264	&dev_priv->gmbus[intel_hdmi->ddc_bus].adapter);
	265	if (edid) {
	266	if (edid->input & DRM_EDID_INPUT_DIGITAL)
	267	has_audio = drm_detect_monitor_audio(edid);
	268
	269	connector->display_info.raw_edid = NULL;
	270	kfree(edid);
	271	}
	272
	273	return has_audio;
	274	}
	275
55b7d6e8 CW	276	static int
	277	intel_hdmi_set_property(struct drm_connector *connector,
	278	struct drm_property *property,
	279	uint64_t val)
	280	{
	281	struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
e953fd7b	282	struct drm_i915_private *dev_priv = connector->dev->dev_private;
55b7d6e8 CW	283	int ret;
	284
	285	ret = drm_connector_property_set_value(connector, property, val);
	286	if (ret)
	287	return ret;
	288
3f43c48d	289	if (property == dev_priv->force_audio_property) {
1aad7ac0 CW	290	int i = val;
	291	bool has_audio;
	292
	293	if (i == intel_hdmi->force_audio)
55b7d6e8 CW	294	return 0;
55b7d6e8 CW	295
1aad7ac0	296	intel_hdmi->force_audio = i;
55b7d6e8	297
1aad7ac0 CW	298	if (i == 0)
	299	has_audio = intel_hdmi_detect_audio(connector);
	300	else
	301	has_audio = i > 0;
	302
	303	if (has_audio == intel_hdmi->has_audio)
55b7d6e8 CW	304	return 0;
55b7d6e8 CW	305
1aad7ac0	306	intel_hdmi->has_audio = has_audio;
55b7d6e8 CW	307	goto done;
	308	}
	309
e953fd7b CW	310	if (property == dev_priv->broadcast_rgb_property) {
	311	if (val == !!intel_hdmi->color_range)
	312	return 0;
	313
	314	intel_hdmi->color_range = val ? SDVO_COLOR_RANGE_16_235 : 0;
	315	goto done;
	316	}
	317
55b7d6e8 CW	318	return -EINVAL;
	319
	320	done:
	321	if (intel_hdmi->base.base.crtc) {
	322	struct drm_crtc *crtc = intel_hdmi->base.base.crtc;
	323	drm_crtc_helper_set_mode(crtc, &crtc->mode,
	324	crtc->x, crtc->y,
	325	crtc->fb);
	326	}
	327
	328	return 0;
	329	}
	330
7d57382e EA	331	static void intel_hdmi_destroy(struct drm_connector *connector)
7d57382e EA	332	{
7d57382e EA	333	drm_sysfs_connector_remove(connector);
7d57382e EA	334	drm_connector_cleanup(connector);
674e2d08	335	kfree(connector);
7d57382e EA	336	}
	337
	338	static const struct drm_encoder_helper_funcs intel_hdmi_helper_funcs = {
	339	.dpms = intel_hdmi_dpms,
	340	.mode_fixup = intel_hdmi_mode_fixup,
	341	.prepare = intel_encoder_prepare,
	342	.mode_set = intel_hdmi_mode_set,
	343	.commit = intel_encoder_commit,
	344	};
	345
	346	static const struct drm_connector_funcs intel_hdmi_connector_funcs = {
c9fb15f6	347	.dpms = drm_helper_connector_dpms,
7d57382e EA	348	.detect = intel_hdmi_detect,
7d57382e EA	349	.fill_modes = drm_helper_probe_single_connector_modes,
55b7d6e8	350	.set_property = intel_hdmi_set_property,
7d57382e EA	351	.destroy = intel_hdmi_destroy,
	352	};
	353
	354	static const struct drm_connector_helper_funcs intel_hdmi_connector_helper_funcs = {
	355	.get_modes = intel_hdmi_get_modes,
	356	.mode_valid = intel_hdmi_mode_valid,
df0e9248	357	.best_encoder = intel_best_encoder,
7d57382e EA	358	};
7d57382e EA	359
7d57382e	360	static const struct drm_encoder_funcs intel_hdmi_enc_funcs = {
ea5b213a	361	.destroy = intel_encoder_destroy,
7d57382e EA	362	};
7d57382e EA	363
55b7d6e8 CW	364	static void
	365	intel_hdmi_add_properties(struct intel_hdmi intel_hdmi, struct drm_connector connector)
	366	{
3f43c48d	367	intel_attach_force_audio_property(connector);
e953fd7b	368	intel_attach_broadcast_rgb_property(connector);
55b7d6e8 CW	369	}
55b7d6e8 CW	370
7d57382e EA	371	void intel_hdmi_init(struct drm_device *dev, int sdvox_reg)
	372	{
	373	struct drm_i915_private *dev_priv = dev->dev_private;
	374	struct drm_connector *connector;
21d40d37	375	struct intel_encoder *intel_encoder;
674e2d08	376	struct intel_connector *intel_connector;
ea5b213a	377	struct intel_hdmi *intel_hdmi;
7d57382e	378
ea5b213a CW	379	intel_hdmi = kzalloc(sizeof(struct intel_hdmi), GFP_KERNEL);
ea5b213a CW	380	if (!intel_hdmi)
7d57382e	381	return;
674e2d08 ZW	382
	383	intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL);
	384	if (!intel_connector) {
ea5b213a	385	kfree(intel_hdmi);
674e2d08 ZW	386	return;
	387	}
	388
ea5b213a	389	intel_encoder = &intel_hdmi->base;
373a3cf7 CW	390	drm_encoder_init(dev, &intel_encoder->base, &intel_hdmi_enc_funcs,
	391	DRM_MODE_ENCODER_TMDS);
	392
674e2d08	393	connector = &intel_connector->base;
7d57382e	394	drm_connector_init(dev, connector, &intel_hdmi_connector_funcs,
8d91104a	395	DRM_MODE_CONNECTOR_HDMIA);
7d57382e EA	396	drm_connector_helper_add(connector, &intel_hdmi_connector_helper_funcs);
7d57382e EA	397
21d40d37	398	intel_encoder->type = INTEL_OUTPUT_HDMI;
7d57382e	399
eb1f8e4f	400	connector->polled = DRM_CONNECTOR_POLL_HPD;
7d57382e EA	401	connector->interlace_allowed = 0;
7d57382e EA	402	connector->doublescan_allowed = 0;
21d40d37	403	intel_encoder->crtc_mask = (1 << 0) \| (1 << 1);
7d57382e EA	404
7d57382e EA	405	/* Set up the DDC bus. */
f8aed700	406	if (sdvox_reg == SDVOB) {
21d40d37	407	intel_encoder->clone_mask = (1 << INTEL_HDMIB_CLONE_BIT);
f899fc64	408	intel_hdmi->ddc_bus = GMBUS_PORT_DPB;
b01f2c3a	409	dev_priv->hotplug_supported_mask \|= HDMIB_HOTPLUG_INT_STATUS;
f8aed700	410	} else if (sdvox_reg == SDVOC) {
21d40d37	411	intel_encoder->clone_mask = (1 << INTEL_HDMIC_CLONE_BIT);
f899fc64	412	intel_hdmi->ddc_bus = GMBUS_PORT_DPC;
b01f2c3a	413	dev_priv->hotplug_supported_mask \|= HDMIC_HOTPLUG_INT_STATUS;
f8aed700	414	} else if (sdvox_reg == HDMIB) {
21d40d37	415	intel_encoder->clone_mask = (1 << INTEL_HDMID_CLONE_BIT);
f899fc64	416	intel_hdmi->ddc_bus = GMBUS_PORT_DPB;
b01f2c3a	417	dev_priv->hotplug_supported_mask \|= HDMIB_HOTPLUG_INT_STATUS;
f8aed700	418	} else if (sdvox_reg == HDMIC) {
21d40d37	419	intel_encoder->clone_mask = (1 << INTEL_HDMIE_CLONE_BIT);
f899fc64	420	intel_hdmi->ddc_bus = GMBUS_PORT_DPC;
b01f2c3a	421	dev_priv->hotplug_supported_mask \|= HDMIC_HOTPLUG_INT_STATUS;
f8aed700	422	} else if (sdvox_reg == HDMID) {
21d40d37	423	intel_encoder->clone_mask = (1 << INTEL_HDMIF_CLONE_BIT);
f899fc64	424	intel_hdmi->ddc_bus = GMBUS_PORT_DPD;
b01f2c3a	425	dev_priv->hotplug_supported_mask \|= HDMID_HOTPLUG_INT_STATUS;
f8aed700	426	}
7d57382e	427
ea5b213a	428	intel_hdmi->sdvox_reg = sdvox_reg;
7d57382e	429
4ef69c7a	430	drm_encoder_helper_add(&intel_encoder->base, &intel_hdmi_helper_funcs);
7d57382e	431
55b7d6e8 CW	432	intel_hdmi_add_properties(intel_hdmi, connector);
55b7d6e8 CW	433
df0e9248	434	intel_connector_attach_encoder(intel_connector, intel_encoder);
7d57382e EA	435	drm_sysfs_connector_add(connector);
	436
	437	/* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
	438	* 0xd. Failure to do so will result in spurious interrupts being
	439	* generated on the port when a cable is not attached.
	440	*/
	441	if (IS_G4X(dev) && !IS_GM45(dev)) {
	442	u32 temp = I915_READ(PEG_BAND_GAP_DATA);
	443	I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) \| 0xd);
	444	}
7d57382e	445	}