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7d57382e EA |
1 | /* |
2 | * Copyright 2006 Dave Airlie <airlied@linux.ie> | |
3 | * Copyright © 2006-2009 Intel Corporation | |
4 | * | |
5 | * Permission is hereby granted, free of charge, to any person obtaining a | |
6 | * copy of this software and associated documentation files (the "Software"), | |
7 | * to deal in the Software without restriction, including without limitation | |
8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
9 | * and/or sell copies of the Software, and to permit persons to whom the | |
10 | * Software is furnished to do so, subject to the following conditions: | |
11 | * | |
12 | * The above copyright notice and this permission notice (including the next | |
13 | * paragraph) shall be included in all copies or substantial portions of the | |
14 | * Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
21 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
22 | * DEALINGS IN THE SOFTWARE. | |
23 | * | |
24 | * Authors: | |
25 | * Eric Anholt <eric@anholt.net> | |
26 | * Jesse Barnes <jesse.barnes@intel.com> | |
27 | */ | |
28 | ||
29 | #include <linux/i2c.h> | |
5a0e3ad6 | 30 | #include <linux/slab.h> |
7d57382e | 31 | #include <linux/delay.h> |
760285e7 DH |
32 | #include <drm/drmP.h> |
33 | #include <drm/drm_crtc.h> | |
34 | #include <drm/drm_edid.h> | |
7d57382e | 35 | #include "intel_drv.h" |
760285e7 | 36 | #include <drm/i915_drm.h> |
7d57382e EA |
37 | #include "i915_drv.h" |
38 | ||
30add22d PZ |
39 | static struct drm_device *intel_hdmi_to_dev(struct intel_hdmi *intel_hdmi) |
40 | { | |
da63a9f2 | 41 | return hdmi_to_dig_port(intel_hdmi)->base.base.dev; |
30add22d PZ |
42 | } |
43 | ||
afba0188 DV |
44 | static void |
45 | assert_hdmi_port_disabled(struct intel_hdmi *intel_hdmi) | |
46 | { | |
30add22d | 47 | struct drm_device *dev = intel_hdmi_to_dev(intel_hdmi); |
afba0188 DV |
48 | struct drm_i915_private *dev_priv = dev->dev_private; |
49 | uint32_t enabled_bits; | |
50 | ||
affa9354 | 51 | enabled_bits = HAS_DDI(dev) ? DDI_BUF_CTL_ENABLE : SDVO_ENABLE; |
afba0188 | 52 | |
b242b7f7 | 53 | WARN(I915_READ(intel_hdmi->hdmi_reg) & enabled_bits, |
afba0188 DV |
54 | "HDMI port enabled, expecting disabled\n"); |
55 | } | |
56 | ||
f5bbfca3 | 57 | struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder) |
ea5b213a | 58 | { |
da63a9f2 PZ |
59 | struct intel_digital_port *intel_dig_port = |
60 | container_of(encoder, struct intel_digital_port, base.base); | |
61 | return &intel_dig_port->hdmi; | |
ea5b213a CW |
62 | } |
63 | ||
df0e9248 CW |
64 | static struct intel_hdmi *intel_attached_hdmi(struct drm_connector *connector) |
65 | { | |
da63a9f2 | 66 | return enc_to_intel_hdmi(&intel_attached_encoder(connector)->base); |
df0e9248 CW |
67 | } |
68 | ||
45187ace | 69 | void intel_dip_infoframe_csum(struct dip_infoframe *frame) |
3c17fe4b | 70 | { |
45187ace | 71 | uint8_t *data = (uint8_t *)frame; |
3c17fe4b DH |
72 | uint8_t sum = 0; |
73 | unsigned i; | |
74 | ||
45187ace JB |
75 | frame->checksum = 0; |
76 | frame->ecc = 0; | |
3c17fe4b | 77 | |
64a8fc01 | 78 | for (i = 0; i < frame->len + DIP_HEADER_SIZE; i++) |
3c17fe4b DH |
79 | sum += data[i]; |
80 | ||
45187ace | 81 | frame->checksum = 0x100 - sum; |
3c17fe4b DH |
82 | } |
83 | ||
bc2481f3 | 84 | static u32 g4x_infoframe_index(struct dip_infoframe *frame) |
3c17fe4b | 85 | { |
45187ace JB |
86 | switch (frame->type) { |
87 | case DIP_TYPE_AVI: | |
ed517fbb | 88 | return VIDEO_DIP_SELECT_AVI; |
45187ace | 89 | case DIP_TYPE_SPD: |
ed517fbb | 90 | return VIDEO_DIP_SELECT_SPD; |
45187ace JB |
91 | default: |
92 | DRM_DEBUG_DRIVER("unknown info frame type %d\n", frame->type); | |
ed517fbb | 93 | return 0; |
45187ace | 94 | } |
45187ace JB |
95 | } |
96 | ||
bc2481f3 | 97 | static u32 g4x_infoframe_enable(struct dip_infoframe *frame) |
45187ace | 98 | { |
45187ace JB |
99 | switch (frame->type) { |
100 | case DIP_TYPE_AVI: | |
ed517fbb | 101 | return VIDEO_DIP_ENABLE_AVI; |
45187ace | 102 | case DIP_TYPE_SPD: |
ed517fbb | 103 | return VIDEO_DIP_ENABLE_SPD; |
fa193ff7 PZ |
104 | default: |
105 | DRM_DEBUG_DRIVER("unknown info frame type %d\n", frame->type); | |
ed517fbb | 106 | return 0; |
fa193ff7 | 107 | } |
fa193ff7 PZ |
108 | } |
109 | ||
2da8af54 PZ |
110 | static u32 hsw_infoframe_enable(struct dip_infoframe *frame) |
111 | { | |
112 | switch (frame->type) { | |
113 | case DIP_TYPE_AVI: | |
114 | return VIDEO_DIP_ENABLE_AVI_HSW; | |
115 | case DIP_TYPE_SPD: | |
116 | return VIDEO_DIP_ENABLE_SPD_HSW; | |
117 | default: | |
118 | DRM_DEBUG_DRIVER("unknown info frame type %d\n", frame->type); | |
119 | return 0; | |
120 | } | |
121 | } | |
122 | ||
7d9bcebe RV |
123 | static u32 hsw_infoframe_data_reg(struct dip_infoframe *frame, |
124 | enum transcoder cpu_transcoder) | |
2da8af54 PZ |
125 | { |
126 | switch (frame->type) { | |
127 | case DIP_TYPE_AVI: | |
7d9bcebe | 128 | return HSW_TVIDEO_DIP_AVI_DATA(cpu_transcoder); |
2da8af54 | 129 | case DIP_TYPE_SPD: |
7d9bcebe | 130 | return HSW_TVIDEO_DIP_SPD_DATA(cpu_transcoder); |
2da8af54 PZ |
131 | default: |
132 | DRM_DEBUG_DRIVER("unknown info frame type %d\n", frame->type); | |
133 | return 0; | |
134 | } | |
135 | } | |
136 | ||
a3da1df7 DV |
137 | static void g4x_write_infoframe(struct drm_encoder *encoder, |
138 | struct dip_infoframe *frame) | |
45187ace JB |
139 | { |
140 | uint32_t *data = (uint32_t *)frame; | |
3c17fe4b DH |
141 | struct drm_device *dev = encoder->dev; |
142 | struct drm_i915_private *dev_priv = dev->dev_private; | |
22509ec8 | 143 | u32 val = I915_READ(VIDEO_DIP_CTL); |
45187ace | 144 | unsigned i, len = DIP_HEADER_SIZE + frame->len; |
3c17fe4b | 145 | |
822974ae PZ |
146 | WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n"); |
147 | ||
1d4f85ac | 148 | val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ |
bc2481f3 | 149 | val |= g4x_infoframe_index(frame); |
22509ec8 | 150 | |
bc2481f3 | 151 | val &= ~g4x_infoframe_enable(frame); |
45187ace | 152 | |
22509ec8 | 153 | I915_WRITE(VIDEO_DIP_CTL, val); |
3c17fe4b | 154 | |
9d9740f0 | 155 | mmiowb(); |
45187ace | 156 | for (i = 0; i < len; i += 4) { |
3c17fe4b DH |
157 | I915_WRITE(VIDEO_DIP_DATA, *data); |
158 | data++; | |
159 | } | |
adf00b26 PZ |
160 | /* Write every possible data byte to force correct ECC calculation. */ |
161 | for (; i < VIDEO_DIP_DATA_SIZE; i += 4) | |
162 | I915_WRITE(VIDEO_DIP_DATA, 0); | |
9d9740f0 | 163 | mmiowb(); |
3c17fe4b | 164 | |
bc2481f3 | 165 | val |= g4x_infoframe_enable(frame); |
60c5ea2d | 166 | val &= ~VIDEO_DIP_FREQ_MASK; |
4b24c933 | 167 | val |= VIDEO_DIP_FREQ_VSYNC; |
45187ace | 168 | |
22509ec8 | 169 | I915_WRITE(VIDEO_DIP_CTL, val); |
9d9740f0 | 170 | POSTING_READ(VIDEO_DIP_CTL); |
3c17fe4b DH |
171 | } |
172 | ||
fdf1250a PZ |
173 | static void ibx_write_infoframe(struct drm_encoder *encoder, |
174 | struct dip_infoframe *frame) | |
175 | { | |
176 | uint32_t *data = (uint32_t *)frame; | |
177 | struct drm_device *dev = encoder->dev; | |
178 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ed517fbb | 179 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); |
fdf1250a PZ |
180 | int reg = TVIDEO_DIP_CTL(intel_crtc->pipe); |
181 | unsigned i, len = DIP_HEADER_SIZE + frame->len; | |
182 | u32 val = I915_READ(reg); | |
183 | ||
822974ae PZ |
184 | WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n"); |
185 | ||
fdf1250a | 186 | val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ |
bc2481f3 | 187 | val |= g4x_infoframe_index(frame); |
fdf1250a | 188 | |
bc2481f3 | 189 | val &= ~g4x_infoframe_enable(frame); |
fdf1250a PZ |
190 | |
191 | I915_WRITE(reg, val); | |
192 | ||
9d9740f0 | 193 | mmiowb(); |
fdf1250a PZ |
194 | for (i = 0; i < len; i += 4) { |
195 | I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data); | |
196 | data++; | |
197 | } | |
adf00b26 PZ |
198 | /* Write every possible data byte to force correct ECC calculation. */ |
199 | for (; i < VIDEO_DIP_DATA_SIZE; i += 4) | |
200 | I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0); | |
9d9740f0 | 201 | mmiowb(); |
fdf1250a | 202 | |
bc2481f3 | 203 | val |= g4x_infoframe_enable(frame); |
fdf1250a | 204 | val &= ~VIDEO_DIP_FREQ_MASK; |
4b24c933 | 205 | val |= VIDEO_DIP_FREQ_VSYNC; |
fdf1250a PZ |
206 | |
207 | I915_WRITE(reg, val); | |
9d9740f0 | 208 | POSTING_READ(reg); |
fdf1250a PZ |
209 | } |
210 | ||
211 | static void cpt_write_infoframe(struct drm_encoder *encoder, | |
212 | struct dip_infoframe *frame) | |
b055c8f3 | 213 | { |
45187ace | 214 | uint32_t *data = (uint32_t *)frame; |
b055c8f3 JB |
215 | struct drm_device *dev = encoder->dev; |
216 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ed517fbb | 217 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); |
b055c8f3 | 218 | int reg = TVIDEO_DIP_CTL(intel_crtc->pipe); |
45187ace | 219 | unsigned i, len = DIP_HEADER_SIZE + frame->len; |
22509ec8 | 220 | u32 val = I915_READ(reg); |
b055c8f3 | 221 | |
822974ae PZ |
222 | WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n"); |
223 | ||
64a8fc01 | 224 | val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ |
bc2481f3 | 225 | val |= g4x_infoframe_index(frame); |
45187ace | 226 | |
ecb97851 PZ |
227 | /* The DIP control register spec says that we need to update the AVI |
228 | * infoframe without clearing its enable bit */ | |
822974ae | 229 | if (frame->type != DIP_TYPE_AVI) |
bc2481f3 | 230 | val &= ~g4x_infoframe_enable(frame); |
ecb97851 | 231 | |
22509ec8 | 232 | I915_WRITE(reg, val); |
45187ace | 233 | |
9d9740f0 | 234 | mmiowb(); |
45187ace | 235 | for (i = 0; i < len; i += 4) { |
b055c8f3 JB |
236 | I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data); |
237 | data++; | |
238 | } | |
adf00b26 PZ |
239 | /* Write every possible data byte to force correct ECC calculation. */ |
240 | for (; i < VIDEO_DIP_DATA_SIZE; i += 4) | |
241 | I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0); | |
9d9740f0 | 242 | mmiowb(); |
b055c8f3 | 243 | |
bc2481f3 | 244 | val |= g4x_infoframe_enable(frame); |
60c5ea2d | 245 | val &= ~VIDEO_DIP_FREQ_MASK; |
4b24c933 | 246 | val |= VIDEO_DIP_FREQ_VSYNC; |
45187ace | 247 | |
22509ec8 | 248 | I915_WRITE(reg, val); |
9d9740f0 | 249 | POSTING_READ(reg); |
45187ace | 250 | } |
90b107c8 SK |
251 | |
252 | static void vlv_write_infoframe(struct drm_encoder *encoder, | |
253 | struct dip_infoframe *frame) | |
254 | { | |
255 | uint32_t *data = (uint32_t *)frame; | |
256 | struct drm_device *dev = encoder->dev; | |
257 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ed517fbb | 258 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); |
90b107c8 SK |
259 | int reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe); |
260 | unsigned i, len = DIP_HEADER_SIZE + frame->len; | |
22509ec8 | 261 | u32 val = I915_READ(reg); |
90b107c8 | 262 | |
822974ae PZ |
263 | WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n"); |
264 | ||
90b107c8 | 265 | val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ |
bc2481f3 | 266 | val |= g4x_infoframe_index(frame); |
22509ec8 | 267 | |
bc2481f3 | 268 | val &= ~g4x_infoframe_enable(frame); |
90b107c8 | 269 | |
22509ec8 | 270 | I915_WRITE(reg, val); |
90b107c8 | 271 | |
9d9740f0 | 272 | mmiowb(); |
90b107c8 SK |
273 | for (i = 0; i < len; i += 4) { |
274 | I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), *data); | |
275 | data++; | |
276 | } | |
adf00b26 PZ |
277 | /* Write every possible data byte to force correct ECC calculation. */ |
278 | for (; i < VIDEO_DIP_DATA_SIZE; i += 4) | |
279 | I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), 0); | |
9d9740f0 | 280 | mmiowb(); |
90b107c8 | 281 | |
bc2481f3 | 282 | val |= g4x_infoframe_enable(frame); |
60c5ea2d | 283 | val &= ~VIDEO_DIP_FREQ_MASK; |
4b24c933 | 284 | val |= VIDEO_DIP_FREQ_VSYNC; |
90b107c8 | 285 | |
22509ec8 | 286 | I915_WRITE(reg, val); |
9d9740f0 | 287 | POSTING_READ(reg); |
90b107c8 SK |
288 | } |
289 | ||
8c5f5f7c | 290 | static void hsw_write_infoframe(struct drm_encoder *encoder, |
ed517fbb | 291 | struct dip_infoframe *frame) |
8c5f5f7c | 292 | { |
2da8af54 PZ |
293 | uint32_t *data = (uint32_t *)frame; |
294 | struct drm_device *dev = encoder->dev; | |
295 | struct drm_i915_private *dev_priv = dev->dev_private; | |
296 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); | |
3b117c8f DV |
297 | u32 ctl_reg = HSW_TVIDEO_DIP_CTL(intel_crtc->config.cpu_transcoder); |
298 | u32 data_reg = hsw_infoframe_data_reg(frame, intel_crtc->config.cpu_transcoder); | |
2da8af54 PZ |
299 | unsigned int i, len = DIP_HEADER_SIZE + frame->len; |
300 | u32 val = I915_READ(ctl_reg); | |
8c5f5f7c | 301 | |
2da8af54 PZ |
302 | if (data_reg == 0) |
303 | return; | |
304 | ||
2da8af54 PZ |
305 | val &= ~hsw_infoframe_enable(frame); |
306 | I915_WRITE(ctl_reg, val); | |
307 | ||
9d9740f0 | 308 | mmiowb(); |
2da8af54 PZ |
309 | for (i = 0; i < len; i += 4) { |
310 | I915_WRITE(data_reg + i, *data); | |
311 | data++; | |
312 | } | |
adf00b26 PZ |
313 | /* Write every possible data byte to force correct ECC calculation. */ |
314 | for (; i < VIDEO_DIP_DATA_SIZE; i += 4) | |
315 | I915_WRITE(data_reg + i, 0); | |
9d9740f0 | 316 | mmiowb(); |
8c5f5f7c | 317 | |
2da8af54 PZ |
318 | val |= hsw_infoframe_enable(frame); |
319 | I915_WRITE(ctl_reg, val); | |
9d9740f0 | 320 | POSTING_READ(ctl_reg); |
8c5f5f7c ED |
321 | } |
322 | ||
45187ace JB |
323 | static void intel_set_infoframe(struct drm_encoder *encoder, |
324 | struct dip_infoframe *frame) | |
325 | { | |
326 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); | |
327 | ||
45187ace JB |
328 | intel_dip_infoframe_csum(frame); |
329 | intel_hdmi->write_infoframe(encoder, frame); | |
330 | } | |
331 | ||
687f4d06 | 332 | static void intel_hdmi_set_avi_infoframe(struct drm_encoder *encoder, |
c846b619 | 333 | struct drm_display_mode *adjusted_mode) |
45187ace | 334 | { |
abedc077 | 335 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); |
50f3b016 | 336 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); |
45187ace JB |
337 | struct dip_infoframe avi_if = { |
338 | .type = DIP_TYPE_AVI, | |
339 | .ver = DIP_VERSION_AVI, | |
340 | .len = DIP_LEN_AVI, | |
341 | }; | |
342 | ||
c846b619 PZ |
343 | if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK) |
344 | avi_if.body.avi.YQ_CN_PR |= DIP_AVI_PR_2; | |
345 | ||
abedc077 | 346 | if (intel_hdmi->rgb_quant_range_selectable) { |
50f3b016 | 347 | if (intel_crtc->config.limited_color_range) |
abedc077 VS |
348 | avi_if.body.avi.ITC_EC_Q_SC |= DIP_AVI_RGB_QUANT_RANGE_LIMITED; |
349 | else | |
350 | avi_if.body.avi.ITC_EC_Q_SC |= DIP_AVI_RGB_QUANT_RANGE_FULL; | |
351 | } | |
352 | ||
18316c8c | 353 | avi_if.body.avi.VIC = drm_match_cea_mode(adjusted_mode); |
9a69b885 | 354 | |
45187ace | 355 | intel_set_infoframe(encoder, &avi_if); |
b055c8f3 JB |
356 | } |
357 | ||
687f4d06 | 358 | static void intel_hdmi_set_spd_infoframe(struct drm_encoder *encoder) |
c0864cb3 JB |
359 | { |
360 | struct dip_infoframe spd_if; | |
361 | ||
362 | memset(&spd_if, 0, sizeof(spd_if)); | |
363 | spd_if.type = DIP_TYPE_SPD; | |
364 | spd_if.ver = DIP_VERSION_SPD; | |
365 | spd_if.len = DIP_LEN_SPD; | |
366 | strcpy(spd_if.body.spd.vn, "Intel"); | |
367 | strcpy(spd_if.body.spd.pd, "Integrated gfx"); | |
368 | spd_if.body.spd.sdi = DIP_SPD_PC; | |
369 | ||
370 | intel_set_infoframe(encoder, &spd_if); | |
371 | } | |
372 | ||
687f4d06 PZ |
373 | static void g4x_set_infoframes(struct drm_encoder *encoder, |
374 | struct drm_display_mode *adjusted_mode) | |
375 | { | |
0c14c7f9 | 376 | struct drm_i915_private *dev_priv = encoder->dev->dev_private; |
69fde0a6 VS |
377 | struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); |
378 | struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi; | |
0c14c7f9 PZ |
379 | u32 reg = VIDEO_DIP_CTL; |
380 | u32 val = I915_READ(reg); | |
72b78c9d | 381 | u32 port; |
0c14c7f9 | 382 | |
afba0188 DV |
383 | assert_hdmi_port_disabled(intel_hdmi); |
384 | ||
0c14c7f9 PZ |
385 | /* If the registers were not initialized yet, they might be zeroes, |
386 | * which means we're selecting the AVI DIP and we're setting its | |
387 | * frequency to once. This seems to really confuse the HW and make | |
388 | * things stop working (the register spec says the AVI always needs to | |
389 | * be sent every VSync). So here we avoid writing to the register more | |
390 | * than we need and also explicitly select the AVI DIP and explicitly | |
391 | * set its frequency to every VSync. Avoiding to write it twice seems to | |
392 | * be enough to solve the problem, but being defensive shouldn't hurt us | |
393 | * either. */ | |
394 | val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; | |
395 | ||
396 | if (!intel_hdmi->has_hdmi_sink) { | |
397 | if (!(val & VIDEO_DIP_ENABLE)) | |
398 | return; | |
399 | val &= ~VIDEO_DIP_ENABLE; | |
400 | I915_WRITE(reg, val); | |
9d9740f0 | 401 | POSTING_READ(reg); |
0c14c7f9 PZ |
402 | return; |
403 | } | |
404 | ||
69fde0a6 VS |
405 | switch (intel_dig_port->port) { |
406 | case PORT_B: | |
72b78c9d | 407 | port = VIDEO_DIP_PORT_B; |
f278d972 | 408 | break; |
69fde0a6 | 409 | case PORT_C: |
72b78c9d | 410 | port = VIDEO_DIP_PORT_C; |
f278d972 PZ |
411 | break; |
412 | default: | |
57df2ae9 | 413 | BUG(); |
f278d972 PZ |
414 | return; |
415 | } | |
416 | ||
72b78c9d PZ |
417 | if (port != (val & VIDEO_DIP_PORT_MASK)) { |
418 | if (val & VIDEO_DIP_ENABLE) { | |
419 | val &= ~VIDEO_DIP_ENABLE; | |
420 | I915_WRITE(reg, val); | |
9d9740f0 | 421 | POSTING_READ(reg); |
72b78c9d PZ |
422 | } |
423 | val &= ~VIDEO_DIP_PORT_MASK; | |
424 | val |= port; | |
425 | } | |
426 | ||
822974ae | 427 | val |= VIDEO_DIP_ENABLE; |
0dd87d20 | 428 | val &= ~VIDEO_DIP_ENABLE_VENDOR; |
822974ae | 429 | |
f278d972 | 430 | I915_WRITE(reg, val); |
9d9740f0 | 431 | POSTING_READ(reg); |
f278d972 | 432 | |
687f4d06 PZ |
433 | intel_hdmi_set_avi_infoframe(encoder, adjusted_mode); |
434 | intel_hdmi_set_spd_infoframe(encoder); | |
435 | } | |
436 | ||
437 | static void ibx_set_infoframes(struct drm_encoder *encoder, | |
438 | struct drm_display_mode *adjusted_mode) | |
439 | { | |
0c14c7f9 PZ |
440 | struct drm_i915_private *dev_priv = encoder->dev->dev_private; |
441 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); | |
69fde0a6 VS |
442 | struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); |
443 | struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi; | |
0c14c7f9 PZ |
444 | u32 reg = TVIDEO_DIP_CTL(intel_crtc->pipe); |
445 | u32 val = I915_READ(reg); | |
72b78c9d | 446 | u32 port; |
0c14c7f9 | 447 | |
afba0188 DV |
448 | assert_hdmi_port_disabled(intel_hdmi); |
449 | ||
0c14c7f9 PZ |
450 | /* See the big comment in g4x_set_infoframes() */ |
451 | val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; | |
452 | ||
453 | if (!intel_hdmi->has_hdmi_sink) { | |
454 | if (!(val & VIDEO_DIP_ENABLE)) | |
455 | return; | |
456 | val &= ~VIDEO_DIP_ENABLE; | |
457 | I915_WRITE(reg, val); | |
9d9740f0 | 458 | POSTING_READ(reg); |
0c14c7f9 PZ |
459 | return; |
460 | } | |
461 | ||
69fde0a6 VS |
462 | switch (intel_dig_port->port) { |
463 | case PORT_B: | |
72b78c9d | 464 | port = VIDEO_DIP_PORT_B; |
f278d972 | 465 | break; |
69fde0a6 | 466 | case PORT_C: |
72b78c9d | 467 | port = VIDEO_DIP_PORT_C; |
f278d972 | 468 | break; |
69fde0a6 | 469 | case PORT_D: |
72b78c9d | 470 | port = VIDEO_DIP_PORT_D; |
f278d972 PZ |
471 | break; |
472 | default: | |
57df2ae9 | 473 | BUG(); |
f278d972 PZ |
474 | return; |
475 | } | |
476 | ||
72b78c9d PZ |
477 | if (port != (val & VIDEO_DIP_PORT_MASK)) { |
478 | if (val & VIDEO_DIP_ENABLE) { | |
479 | val &= ~VIDEO_DIP_ENABLE; | |
480 | I915_WRITE(reg, val); | |
9d9740f0 | 481 | POSTING_READ(reg); |
72b78c9d PZ |
482 | } |
483 | val &= ~VIDEO_DIP_PORT_MASK; | |
484 | val |= port; | |
485 | } | |
486 | ||
822974ae | 487 | val |= VIDEO_DIP_ENABLE; |
0dd87d20 PZ |
488 | val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | |
489 | VIDEO_DIP_ENABLE_GCP); | |
822974ae | 490 | |
f278d972 | 491 | I915_WRITE(reg, val); |
9d9740f0 | 492 | POSTING_READ(reg); |
f278d972 | 493 | |
687f4d06 PZ |
494 | intel_hdmi_set_avi_infoframe(encoder, adjusted_mode); |
495 | intel_hdmi_set_spd_infoframe(encoder); | |
496 | } | |
497 | ||
498 | static void cpt_set_infoframes(struct drm_encoder *encoder, | |
499 | struct drm_display_mode *adjusted_mode) | |
500 | { | |
0c14c7f9 PZ |
501 | struct drm_i915_private *dev_priv = encoder->dev->dev_private; |
502 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); | |
503 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); | |
504 | u32 reg = TVIDEO_DIP_CTL(intel_crtc->pipe); | |
505 | u32 val = I915_READ(reg); | |
506 | ||
afba0188 DV |
507 | assert_hdmi_port_disabled(intel_hdmi); |
508 | ||
0c14c7f9 PZ |
509 | /* See the big comment in g4x_set_infoframes() */ |
510 | val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; | |
511 | ||
512 | if (!intel_hdmi->has_hdmi_sink) { | |
513 | if (!(val & VIDEO_DIP_ENABLE)) | |
514 | return; | |
515 | val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI); | |
516 | I915_WRITE(reg, val); | |
9d9740f0 | 517 | POSTING_READ(reg); |
0c14c7f9 PZ |
518 | return; |
519 | } | |
520 | ||
822974ae PZ |
521 | /* Set both together, unset both together: see the spec. */ |
522 | val |= VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI; | |
0dd87d20 PZ |
523 | val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | |
524 | VIDEO_DIP_ENABLE_GCP); | |
822974ae PZ |
525 | |
526 | I915_WRITE(reg, val); | |
9d9740f0 | 527 | POSTING_READ(reg); |
822974ae | 528 | |
687f4d06 PZ |
529 | intel_hdmi_set_avi_infoframe(encoder, adjusted_mode); |
530 | intel_hdmi_set_spd_infoframe(encoder); | |
531 | } | |
532 | ||
533 | static void vlv_set_infoframes(struct drm_encoder *encoder, | |
534 | struct drm_display_mode *adjusted_mode) | |
535 | { | |
0c14c7f9 PZ |
536 | struct drm_i915_private *dev_priv = encoder->dev->dev_private; |
537 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); | |
538 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); | |
539 | u32 reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe); | |
540 | u32 val = I915_READ(reg); | |
541 | ||
afba0188 DV |
542 | assert_hdmi_port_disabled(intel_hdmi); |
543 | ||
0c14c7f9 PZ |
544 | /* See the big comment in g4x_set_infoframes() */ |
545 | val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; | |
546 | ||
547 | if (!intel_hdmi->has_hdmi_sink) { | |
548 | if (!(val & VIDEO_DIP_ENABLE)) | |
549 | return; | |
550 | val &= ~VIDEO_DIP_ENABLE; | |
551 | I915_WRITE(reg, val); | |
9d9740f0 | 552 | POSTING_READ(reg); |
0c14c7f9 PZ |
553 | return; |
554 | } | |
555 | ||
822974ae | 556 | val |= VIDEO_DIP_ENABLE; |
0dd87d20 PZ |
557 | val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | |
558 | VIDEO_DIP_ENABLE_GCP); | |
822974ae PZ |
559 | |
560 | I915_WRITE(reg, val); | |
9d9740f0 | 561 | POSTING_READ(reg); |
822974ae | 562 | |
687f4d06 PZ |
563 | intel_hdmi_set_avi_infoframe(encoder, adjusted_mode); |
564 | intel_hdmi_set_spd_infoframe(encoder); | |
565 | } | |
566 | ||
567 | static void hsw_set_infoframes(struct drm_encoder *encoder, | |
568 | struct drm_display_mode *adjusted_mode) | |
569 | { | |
0c14c7f9 PZ |
570 | struct drm_i915_private *dev_priv = encoder->dev->dev_private; |
571 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); | |
572 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); | |
3b117c8f | 573 | u32 reg = HSW_TVIDEO_DIP_CTL(intel_crtc->config.cpu_transcoder); |
0dd87d20 | 574 | u32 val = I915_READ(reg); |
0c14c7f9 | 575 | |
afba0188 DV |
576 | assert_hdmi_port_disabled(intel_hdmi); |
577 | ||
0c14c7f9 PZ |
578 | if (!intel_hdmi->has_hdmi_sink) { |
579 | I915_WRITE(reg, 0); | |
9d9740f0 | 580 | POSTING_READ(reg); |
0c14c7f9 PZ |
581 | return; |
582 | } | |
583 | ||
0dd87d20 PZ |
584 | val &= ~(VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_GCP_HSW | |
585 | VIDEO_DIP_ENABLE_VS_HSW | VIDEO_DIP_ENABLE_GMP_HSW); | |
586 | ||
587 | I915_WRITE(reg, val); | |
9d9740f0 | 588 | POSTING_READ(reg); |
0dd87d20 | 589 | |
687f4d06 PZ |
590 | intel_hdmi_set_avi_infoframe(encoder, adjusted_mode); |
591 | intel_hdmi_set_spd_infoframe(encoder); | |
592 | } | |
593 | ||
7d57382e EA |
594 | static void intel_hdmi_mode_set(struct drm_encoder *encoder, |
595 | struct drm_display_mode *mode, | |
596 | struct drm_display_mode *adjusted_mode) | |
597 | { | |
598 | struct drm_device *dev = encoder->dev; | |
599 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ed517fbb | 600 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); |
ea5b213a | 601 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); |
b242b7f7 | 602 | u32 hdmi_val; |
7d57382e | 603 | |
b242b7f7 | 604 | hdmi_val = SDVO_ENCODING_HDMI; |
2af2c490 | 605 | if (!HAS_PCH_SPLIT(dev)) |
b242b7f7 | 606 | hdmi_val |= intel_hdmi->color_range; |
b599c0bc | 607 | if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) |
b242b7f7 | 608 | hdmi_val |= SDVO_VSYNC_ACTIVE_HIGH; |
b599c0bc | 609 | if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) |
b242b7f7 | 610 | hdmi_val |= SDVO_HSYNC_ACTIVE_HIGH; |
7d57382e | 611 | |
965e0c48 | 612 | if (intel_crtc->config.pipe_bpp > 24) |
4f3a8bc7 | 613 | hdmi_val |= HDMI_COLOR_FORMAT_12bpc; |
020f6704 | 614 | else |
4f3a8bc7 | 615 | hdmi_val |= SDVO_COLOR_FORMAT_8bpc; |
020f6704 | 616 | |
2e3d6006 ZW |
617 | /* Required on CPT */ |
618 | if (intel_hdmi->has_hdmi_sink && HAS_PCH_CPT(dev)) | |
dc0fa718 | 619 | hdmi_val |= HDMI_MODE_SELECT_HDMI; |
2e3d6006 | 620 | |
3c17fe4b | 621 | if (intel_hdmi->has_audio) { |
e0dac65e WF |
622 | DRM_DEBUG_DRIVER("Enabling HDMI audio on pipe %c\n", |
623 | pipe_name(intel_crtc->pipe)); | |
b242b7f7 | 624 | hdmi_val |= SDVO_AUDIO_ENABLE; |
dc0fa718 | 625 | hdmi_val |= HDMI_MODE_SELECT_HDMI; |
e0dac65e | 626 | intel_write_eld(encoder, adjusted_mode); |
3c17fe4b | 627 | } |
7d57382e | 628 | |
75770564 | 629 | if (HAS_PCH_CPT(dev)) |
dc0fa718 PZ |
630 | hdmi_val |= SDVO_PIPE_SEL_CPT(intel_crtc->pipe); |
631 | else | |
632 | hdmi_val |= SDVO_PIPE_SEL(intel_crtc->pipe); | |
7d57382e | 633 | |
b242b7f7 PZ |
634 | I915_WRITE(intel_hdmi->hdmi_reg, hdmi_val); |
635 | POSTING_READ(intel_hdmi->hdmi_reg); | |
3c17fe4b | 636 | |
687f4d06 | 637 | intel_hdmi->set_infoframes(encoder, adjusted_mode); |
7d57382e EA |
638 | } |
639 | ||
85234cdc DV |
640 | static bool intel_hdmi_get_hw_state(struct intel_encoder *encoder, |
641 | enum pipe *pipe) | |
7d57382e | 642 | { |
85234cdc | 643 | struct drm_device *dev = encoder->base.dev; |
7d57382e | 644 | struct drm_i915_private *dev_priv = dev->dev_private; |
85234cdc DV |
645 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); |
646 | u32 tmp; | |
647 | ||
b242b7f7 | 648 | tmp = I915_READ(intel_hdmi->hdmi_reg); |
85234cdc DV |
649 | |
650 | if (!(tmp & SDVO_ENABLE)) | |
651 | return false; | |
652 | ||
653 | if (HAS_PCH_CPT(dev)) | |
654 | *pipe = PORT_TO_PIPE_CPT(tmp); | |
655 | else | |
656 | *pipe = PORT_TO_PIPE(tmp); | |
657 | ||
658 | return true; | |
659 | } | |
660 | ||
045ac3b5 JB |
661 | static void intel_hdmi_get_config(struct intel_encoder *encoder, |
662 | struct intel_crtc_config *pipe_config) | |
663 | { | |
664 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); | |
665 | struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; | |
666 | u32 tmp, flags = 0; | |
667 | ||
668 | tmp = I915_READ(intel_hdmi->hdmi_reg); | |
669 | ||
670 | if (tmp & SDVO_HSYNC_ACTIVE_HIGH) | |
671 | flags |= DRM_MODE_FLAG_PHSYNC; | |
672 | else | |
673 | flags |= DRM_MODE_FLAG_NHSYNC; | |
674 | ||
675 | if (tmp & SDVO_VSYNC_ACTIVE_HIGH) | |
676 | flags |= DRM_MODE_FLAG_PVSYNC; | |
677 | else | |
678 | flags |= DRM_MODE_FLAG_NVSYNC; | |
679 | ||
680 | pipe_config->adjusted_mode.flags |= flags; | |
681 | } | |
682 | ||
5ab432ef | 683 | static void intel_enable_hdmi(struct intel_encoder *encoder) |
7d57382e | 684 | { |
5ab432ef | 685 | struct drm_device *dev = encoder->base.dev; |
7d57382e | 686 | struct drm_i915_private *dev_priv = dev->dev_private; |
dc0fa718 | 687 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); |
5ab432ef | 688 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); |
7d57382e | 689 | u32 temp; |
2deed761 WF |
690 | u32 enable_bits = SDVO_ENABLE; |
691 | ||
692 | if (intel_hdmi->has_audio) | |
693 | enable_bits |= SDVO_AUDIO_ENABLE; | |
7d57382e | 694 | |
b242b7f7 | 695 | temp = I915_READ(intel_hdmi->hdmi_reg); |
d8a2d0e0 | 696 | |
7a87c289 | 697 | /* HW workaround for IBX, we need to move the port to transcoder A |
dc0fa718 PZ |
698 | * before disabling it, so restore the transcoder select bit here. */ |
699 | if (HAS_PCH_IBX(dev)) | |
700 | enable_bits |= SDVO_PIPE_SEL(intel_crtc->pipe); | |
7a87c289 | 701 | |
d8a2d0e0 ZW |
702 | /* HW workaround, need to toggle enable bit off and on for 12bpc, but |
703 | * we do this anyway which shows more stable in testing. | |
704 | */ | |
c619eed4 | 705 | if (HAS_PCH_SPLIT(dev)) { |
b242b7f7 PZ |
706 | I915_WRITE(intel_hdmi->hdmi_reg, temp & ~SDVO_ENABLE); |
707 | POSTING_READ(intel_hdmi->hdmi_reg); | |
d8a2d0e0 ZW |
708 | } |
709 | ||
5ab432ef DV |
710 | temp |= enable_bits; |
711 | ||
b242b7f7 PZ |
712 | I915_WRITE(intel_hdmi->hdmi_reg, temp); |
713 | POSTING_READ(intel_hdmi->hdmi_reg); | |
5ab432ef DV |
714 | |
715 | /* HW workaround, need to write this twice for issue that may result | |
716 | * in first write getting masked. | |
717 | */ | |
718 | if (HAS_PCH_SPLIT(dev)) { | |
b242b7f7 PZ |
719 | I915_WRITE(intel_hdmi->hdmi_reg, temp); |
720 | POSTING_READ(intel_hdmi->hdmi_reg); | |
7d57382e | 721 | } |
89b667f8 JB |
722 | |
723 | if (IS_VALLEYVIEW(dev)) { | |
724 | struct intel_digital_port *dport = | |
725 | enc_to_dig_port(&encoder->base); | |
726 | int channel = vlv_dport_to_channel(dport); | |
727 | ||
728 | vlv_wait_port_ready(dev_priv, channel); | |
729 | } | |
5ab432ef DV |
730 | } |
731 | ||
732 | static void intel_disable_hdmi(struct intel_encoder *encoder) | |
733 | { | |
734 | struct drm_device *dev = encoder->base.dev; | |
735 | struct drm_i915_private *dev_priv = dev->dev_private; | |
736 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); | |
737 | u32 temp; | |
3cce574f | 738 | u32 enable_bits = SDVO_ENABLE | SDVO_AUDIO_ENABLE; |
5ab432ef | 739 | |
b242b7f7 | 740 | temp = I915_READ(intel_hdmi->hdmi_reg); |
5ab432ef DV |
741 | |
742 | /* HW workaround for IBX, we need to move the port to transcoder A | |
743 | * before disabling it. */ | |
744 | if (HAS_PCH_IBX(dev)) { | |
745 | struct drm_crtc *crtc = encoder->base.crtc; | |
746 | int pipe = crtc ? to_intel_crtc(crtc)->pipe : -1; | |
747 | ||
748 | if (temp & SDVO_PIPE_B_SELECT) { | |
749 | temp &= ~SDVO_PIPE_B_SELECT; | |
b242b7f7 PZ |
750 | I915_WRITE(intel_hdmi->hdmi_reg, temp); |
751 | POSTING_READ(intel_hdmi->hdmi_reg); | |
5ab432ef DV |
752 | |
753 | /* Again we need to write this twice. */ | |
b242b7f7 PZ |
754 | I915_WRITE(intel_hdmi->hdmi_reg, temp); |
755 | POSTING_READ(intel_hdmi->hdmi_reg); | |
5ab432ef DV |
756 | |
757 | /* Transcoder selection bits only update | |
758 | * effectively on vblank. */ | |
759 | if (crtc) | |
760 | intel_wait_for_vblank(dev, pipe); | |
761 | else | |
762 | msleep(50); | |
763 | } | |
7d57382e | 764 | } |
d8a2d0e0 | 765 | |
5ab432ef DV |
766 | /* HW workaround, need to toggle enable bit off and on for 12bpc, but |
767 | * we do this anyway which shows more stable in testing. | |
768 | */ | |
769 | if (HAS_PCH_SPLIT(dev)) { | |
b242b7f7 PZ |
770 | I915_WRITE(intel_hdmi->hdmi_reg, temp & ~SDVO_ENABLE); |
771 | POSTING_READ(intel_hdmi->hdmi_reg); | |
5ab432ef DV |
772 | } |
773 | ||
774 | temp &= ~enable_bits; | |
d8a2d0e0 | 775 | |
b242b7f7 PZ |
776 | I915_WRITE(intel_hdmi->hdmi_reg, temp); |
777 | POSTING_READ(intel_hdmi->hdmi_reg); | |
d8a2d0e0 ZW |
778 | |
779 | /* HW workaround, need to write this twice for issue that may result | |
780 | * in first write getting masked. | |
781 | */ | |
c619eed4 | 782 | if (HAS_PCH_SPLIT(dev)) { |
b242b7f7 PZ |
783 | I915_WRITE(intel_hdmi->hdmi_reg, temp); |
784 | POSTING_READ(intel_hdmi->hdmi_reg); | |
d8a2d0e0 | 785 | } |
7d57382e EA |
786 | } |
787 | ||
7d57382e EA |
788 | static int intel_hdmi_mode_valid(struct drm_connector *connector, |
789 | struct drm_display_mode *mode) | |
790 | { | |
791 | if (mode->clock > 165000) | |
792 | return MODE_CLOCK_HIGH; | |
793 | if (mode->clock < 20000) | |
5cbba41d | 794 | return MODE_CLOCK_LOW; |
7d57382e EA |
795 | |
796 | if (mode->flags & DRM_MODE_FLAG_DBLSCAN) | |
797 | return MODE_NO_DBLESCAN; | |
798 | ||
799 | return MODE_OK; | |
800 | } | |
801 | ||
5bfe2ac0 DV |
802 | bool intel_hdmi_compute_config(struct intel_encoder *encoder, |
803 | struct intel_crtc_config *pipe_config) | |
7d57382e | 804 | { |
5bfe2ac0 DV |
805 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); |
806 | struct drm_device *dev = encoder->base.dev; | |
807 | struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode; | |
325b9d04 | 808 | int clock_12bpc = pipe_config->requested_mode.clock * 3 / 2; |
e29c22c0 | 809 | int desired_bpp; |
3685a8f3 | 810 | |
55bc60db VS |
811 | if (intel_hdmi->color_range_auto) { |
812 | /* See CEA-861-E - 5.1 Default Encoding Parameters */ | |
813 | if (intel_hdmi->has_hdmi_sink && | |
18316c8c | 814 | drm_match_cea_mode(adjusted_mode) > 1) |
4f3a8bc7 | 815 | intel_hdmi->color_range = HDMI_COLOR_RANGE_16_235; |
55bc60db VS |
816 | else |
817 | intel_hdmi->color_range = 0; | |
818 | } | |
819 | ||
3685a8f3 | 820 | if (intel_hdmi->color_range) |
50f3b016 | 821 | pipe_config->limited_color_range = true; |
3685a8f3 | 822 | |
5bfe2ac0 DV |
823 | if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev)) |
824 | pipe_config->has_pch_encoder = true; | |
825 | ||
4e53c2e0 DV |
826 | /* |
827 | * HDMI is either 12 or 8, so if the display lets 10bpc sneak | |
828 | * through, clamp it down. Note that g4x/vlv don't support 12bpc hdmi | |
325b9d04 DV |
829 | * outputs. We also need to check that the higher clock still fits |
830 | * within limits. | |
4e53c2e0 | 831 | */ |
325b9d04 DV |
832 | if (pipe_config->pipe_bpp > 8*3 && clock_12bpc <= 225000 |
833 | && HAS_PCH_SPLIT(dev)) { | |
e29c22c0 DV |
834 | DRM_DEBUG_KMS("picking bpc to 12 for HDMI output\n"); |
835 | desired_bpp = 12*3; | |
325b9d04 DV |
836 | |
837 | /* Need to adjust the port link by 1.5x for 12bpc. */ | |
ff9a6750 | 838 | pipe_config->port_clock = clock_12bpc; |
4e53c2e0 | 839 | } else { |
e29c22c0 DV |
840 | DRM_DEBUG_KMS("picking bpc to 8 for HDMI output\n"); |
841 | desired_bpp = 8*3; | |
842 | } | |
843 | ||
844 | if (!pipe_config->bw_constrained) { | |
845 | DRM_DEBUG_KMS("forcing pipe bpc to %i for HDMI\n", desired_bpp); | |
846 | pipe_config->pipe_bpp = desired_bpp; | |
4e53c2e0 DV |
847 | } |
848 | ||
325b9d04 DV |
849 | if (adjusted_mode->clock > 225000) { |
850 | DRM_DEBUG_KMS("too high HDMI clock, rejecting mode\n"); | |
851 | return false; | |
852 | } | |
853 | ||
7d57382e EA |
854 | return true; |
855 | } | |
856 | ||
aa93d632 | 857 | static enum drm_connector_status |
930a9e28 | 858 | intel_hdmi_detect(struct drm_connector *connector, bool force) |
9dff6af8 | 859 | { |
b0ea7d37 | 860 | struct drm_device *dev = connector->dev; |
df0e9248 | 861 | struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); |
d63885da PZ |
862 | struct intel_digital_port *intel_dig_port = |
863 | hdmi_to_dig_port(intel_hdmi); | |
864 | struct intel_encoder *intel_encoder = &intel_dig_port->base; | |
b0ea7d37 | 865 | struct drm_i915_private *dev_priv = dev->dev_private; |
f899fc64 | 866 | struct edid *edid; |
aa93d632 | 867 | enum drm_connector_status status = connector_status_disconnected; |
9dff6af8 | 868 | |
ea5b213a | 869 | intel_hdmi->has_hdmi_sink = false; |
2e3d6006 | 870 | intel_hdmi->has_audio = false; |
abedc077 | 871 | intel_hdmi->rgb_quant_range_selectable = false; |
f899fc64 | 872 | edid = drm_get_edid(connector, |
3bd7d909 DK |
873 | intel_gmbus_get_adapter(dev_priv, |
874 | intel_hdmi->ddc_bus)); | |
2ded9e27 | 875 | |
aa93d632 | 876 | if (edid) { |
be9f1c4f | 877 | if (edid->input & DRM_EDID_INPUT_DIGITAL) { |
aa93d632 | 878 | status = connector_status_connected; |
b1d7e4b4 WF |
879 | if (intel_hdmi->force_audio != HDMI_AUDIO_OFF_DVI) |
880 | intel_hdmi->has_hdmi_sink = | |
881 | drm_detect_hdmi_monitor(edid); | |
2e3d6006 | 882 | intel_hdmi->has_audio = drm_detect_monitor_audio(edid); |
abedc077 VS |
883 | intel_hdmi->rgb_quant_range_selectable = |
884 | drm_rgb_quant_range_selectable(edid); | |
aa93d632 | 885 | } |
aa93d632 | 886 | kfree(edid); |
9dff6af8 | 887 | } |
30ad48b7 | 888 | |
55b7d6e8 | 889 | if (status == connector_status_connected) { |
b1d7e4b4 WF |
890 | if (intel_hdmi->force_audio != HDMI_AUDIO_AUTO) |
891 | intel_hdmi->has_audio = | |
892 | (intel_hdmi->force_audio == HDMI_AUDIO_ON); | |
d63885da | 893 | intel_encoder->type = INTEL_OUTPUT_HDMI; |
55b7d6e8 CW |
894 | } |
895 | ||
2ded9e27 | 896 | return status; |
7d57382e EA |
897 | } |
898 | ||
899 | static int intel_hdmi_get_modes(struct drm_connector *connector) | |
900 | { | |
df0e9248 | 901 | struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); |
f899fc64 | 902 | struct drm_i915_private *dev_priv = connector->dev->dev_private; |
7d57382e EA |
903 | |
904 | /* We should parse the EDID data and find out if it's an HDMI sink so | |
905 | * we can send audio to it. | |
906 | */ | |
907 | ||
f899fc64 | 908 | return intel_ddc_get_modes(connector, |
3bd7d909 DK |
909 | intel_gmbus_get_adapter(dev_priv, |
910 | intel_hdmi->ddc_bus)); | |
7d57382e EA |
911 | } |
912 | ||
1aad7ac0 CW |
913 | static bool |
914 | intel_hdmi_detect_audio(struct drm_connector *connector) | |
915 | { | |
916 | struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); | |
917 | struct drm_i915_private *dev_priv = connector->dev->dev_private; | |
918 | struct edid *edid; | |
919 | bool has_audio = false; | |
920 | ||
921 | edid = drm_get_edid(connector, | |
3bd7d909 DK |
922 | intel_gmbus_get_adapter(dev_priv, |
923 | intel_hdmi->ddc_bus)); | |
1aad7ac0 CW |
924 | if (edid) { |
925 | if (edid->input & DRM_EDID_INPUT_DIGITAL) | |
926 | has_audio = drm_detect_monitor_audio(edid); | |
1aad7ac0 CW |
927 | kfree(edid); |
928 | } | |
929 | ||
930 | return has_audio; | |
931 | } | |
932 | ||
55b7d6e8 CW |
933 | static int |
934 | intel_hdmi_set_property(struct drm_connector *connector, | |
ed517fbb PZ |
935 | struct drm_property *property, |
936 | uint64_t val) | |
55b7d6e8 CW |
937 | { |
938 | struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); | |
da63a9f2 PZ |
939 | struct intel_digital_port *intel_dig_port = |
940 | hdmi_to_dig_port(intel_hdmi); | |
e953fd7b | 941 | struct drm_i915_private *dev_priv = connector->dev->dev_private; |
55b7d6e8 CW |
942 | int ret; |
943 | ||
662595df | 944 | ret = drm_object_property_set_value(&connector->base, property, val); |
55b7d6e8 CW |
945 | if (ret) |
946 | return ret; | |
947 | ||
3f43c48d | 948 | if (property == dev_priv->force_audio_property) { |
b1d7e4b4 | 949 | enum hdmi_force_audio i = val; |
1aad7ac0 CW |
950 | bool has_audio; |
951 | ||
952 | if (i == intel_hdmi->force_audio) | |
55b7d6e8 CW |
953 | return 0; |
954 | ||
1aad7ac0 | 955 | intel_hdmi->force_audio = i; |
55b7d6e8 | 956 | |
b1d7e4b4 | 957 | if (i == HDMI_AUDIO_AUTO) |
1aad7ac0 CW |
958 | has_audio = intel_hdmi_detect_audio(connector); |
959 | else | |
b1d7e4b4 | 960 | has_audio = (i == HDMI_AUDIO_ON); |
1aad7ac0 | 961 | |
b1d7e4b4 WF |
962 | if (i == HDMI_AUDIO_OFF_DVI) |
963 | intel_hdmi->has_hdmi_sink = 0; | |
55b7d6e8 | 964 | |
1aad7ac0 | 965 | intel_hdmi->has_audio = has_audio; |
55b7d6e8 CW |
966 | goto done; |
967 | } | |
968 | ||
e953fd7b | 969 | if (property == dev_priv->broadcast_rgb_property) { |
ae4edb80 DV |
970 | bool old_auto = intel_hdmi->color_range_auto; |
971 | uint32_t old_range = intel_hdmi->color_range; | |
972 | ||
55bc60db VS |
973 | switch (val) { |
974 | case INTEL_BROADCAST_RGB_AUTO: | |
975 | intel_hdmi->color_range_auto = true; | |
976 | break; | |
977 | case INTEL_BROADCAST_RGB_FULL: | |
978 | intel_hdmi->color_range_auto = false; | |
979 | intel_hdmi->color_range = 0; | |
980 | break; | |
981 | case INTEL_BROADCAST_RGB_LIMITED: | |
982 | intel_hdmi->color_range_auto = false; | |
4f3a8bc7 | 983 | intel_hdmi->color_range = HDMI_COLOR_RANGE_16_235; |
55bc60db VS |
984 | break; |
985 | default: | |
986 | return -EINVAL; | |
987 | } | |
ae4edb80 DV |
988 | |
989 | if (old_auto == intel_hdmi->color_range_auto && | |
990 | old_range == intel_hdmi->color_range) | |
991 | return 0; | |
992 | ||
e953fd7b CW |
993 | goto done; |
994 | } | |
995 | ||
55b7d6e8 CW |
996 | return -EINVAL; |
997 | ||
998 | done: | |
c0c36b94 CW |
999 | if (intel_dig_port->base.base.crtc) |
1000 | intel_crtc_restore_mode(intel_dig_port->base.base.crtc); | |
55b7d6e8 CW |
1001 | |
1002 | return 0; | |
1003 | } | |
1004 | ||
89b667f8 JB |
1005 | static void intel_hdmi_pre_enable(struct intel_encoder *encoder) |
1006 | { | |
1007 | struct intel_digital_port *dport = enc_to_dig_port(&encoder->base); | |
1008 | struct drm_device *dev = encoder->base.dev; | |
1009 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1010 | struct intel_crtc *intel_crtc = | |
1011 | to_intel_crtc(encoder->base.crtc); | |
1012 | int port = vlv_dport_to_channel(dport); | |
1013 | int pipe = intel_crtc->pipe; | |
1014 | u32 val; | |
1015 | ||
1016 | if (!IS_VALLEYVIEW(dev)) | |
1017 | return; | |
1018 | ||
89b667f8 | 1019 | /* Enable clock channels for this port */ |
ae99258f | 1020 | val = vlv_dpio_read(dev_priv, DPIO_DATA_LANE_A(port)); |
89b667f8 JB |
1021 | val = 0; |
1022 | if (pipe) | |
1023 | val |= (1<<21); | |
1024 | else | |
1025 | val &= ~(1<<21); | |
1026 | val |= 0x001000c4; | |
ae99258f | 1027 | vlv_dpio_write(dev_priv, DPIO_DATA_CHANNEL(port), val); |
89b667f8 JB |
1028 | |
1029 | /* HDMI 1.0V-2dB */ | |
ae99258f JN |
1030 | vlv_dpio_write(dev_priv, DPIO_TX_OCALINIT(port), 0); |
1031 | vlv_dpio_write(dev_priv, DPIO_TX_SWING_CTL4(port), | |
89b667f8 | 1032 | 0x2b245f5f); |
ae99258f | 1033 | vlv_dpio_write(dev_priv, DPIO_TX_SWING_CTL2(port), |
89b667f8 | 1034 | 0x5578b83a); |
ae99258f | 1035 | vlv_dpio_write(dev_priv, DPIO_TX_SWING_CTL3(port), |
89b667f8 | 1036 | 0x0c782040); |
ae99258f | 1037 | vlv_dpio_write(dev_priv, DPIO_TX3_SWING_CTL4(port), |
89b667f8 | 1038 | 0x2b247878); |
ae99258f JN |
1039 | vlv_dpio_write(dev_priv, DPIO_PCS_STAGGER0(port), 0x00030000); |
1040 | vlv_dpio_write(dev_priv, DPIO_PCS_CTL_OVER1(port), | |
89b667f8 | 1041 | 0x00002000); |
ae99258f | 1042 | vlv_dpio_write(dev_priv, DPIO_TX_OCALINIT(port), |
89b667f8 JB |
1043 | DPIO_TX_OCALINIT_EN); |
1044 | ||
1045 | /* Program lane clock */ | |
ae99258f | 1046 | vlv_dpio_write(dev_priv, DPIO_PCS_CLOCKBUF0(port), |
89b667f8 | 1047 | 0x00760018); |
ae99258f | 1048 | vlv_dpio_write(dev_priv, DPIO_PCS_CLOCKBUF8(port), |
89b667f8 JB |
1049 | 0x00400888); |
1050 | } | |
1051 | ||
1052 | static void intel_hdmi_pre_pll_enable(struct intel_encoder *encoder) | |
1053 | { | |
1054 | struct intel_digital_port *dport = enc_to_dig_port(&encoder->base); | |
1055 | struct drm_device *dev = encoder->base.dev; | |
1056 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1057 | int port = vlv_dport_to_channel(dport); | |
1058 | ||
1059 | if (!IS_VALLEYVIEW(dev)) | |
1060 | return; | |
1061 | ||
89b667f8 | 1062 | /* Program Tx lane resets to default */ |
ae99258f | 1063 | vlv_dpio_write(dev_priv, DPIO_PCS_TX(port), |
89b667f8 JB |
1064 | DPIO_PCS_TX_LANE2_RESET | |
1065 | DPIO_PCS_TX_LANE1_RESET); | |
ae99258f | 1066 | vlv_dpio_write(dev_priv, DPIO_PCS_CLK(port), |
89b667f8 JB |
1067 | DPIO_PCS_CLK_CRI_RXEB_EIOS_EN | |
1068 | DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN | | |
1069 | (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) | | |
1070 | DPIO_PCS_CLK_SOFT_RESET); | |
1071 | ||
1072 | /* Fix up inter-pair skew failure */ | |
ae99258f JN |
1073 | vlv_dpio_write(dev_priv, DPIO_PCS_STAGGER1(port), 0x00750f00); |
1074 | vlv_dpio_write(dev_priv, DPIO_TX_CTL(port), 0x00001500); | |
1075 | vlv_dpio_write(dev_priv, DPIO_TX_LANE(port), 0x40400000); | |
89b667f8 | 1076 | |
ae99258f | 1077 | vlv_dpio_write(dev_priv, DPIO_PCS_CTL_OVER1(port), |
89b667f8 | 1078 | 0x00002000); |
ae99258f | 1079 | vlv_dpio_write(dev_priv, DPIO_TX_OCALINIT(port), |
89b667f8 JB |
1080 | DPIO_TX_OCALINIT_EN); |
1081 | } | |
1082 | ||
1083 | static void intel_hdmi_post_disable(struct intel_encoder *encoder) | |
1084 | { | |
1085 | struct intel_digital_port *dport = enc_to_dig_port(&encoder->base); | |
1086 | struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; | |
1087 | int port = vlv_dport_to_channel(dport); | |
1088 | ||
1089 | /* Reset lanes to avoid HDMI flicker (VLV w/a) */ | |
1090 | mutex_lock(&dev_priv->dpio_lock); | |
ae99258f JN |
1091 | vlv_dpio_write(dev_priv, DPIO_PCS_TX(port), 0x00000000); |
1092 | vlv_dpio_write(dev_priv, DPIO_PCS_CLK(port), 0x00e00060); | |
89b667f8 JB |
1093 | mutex_unlock(&dev_priv->dpio_lock); |
1094 | } | |
1095 | ||
7d57382e EA |
1096 | static void intel_hdmi_destroy(struct drm_connector *connector) |
1097 | { | |
7d57382e EA |
1098 | drm_sysfs_connector_remove(connector); |
1099 | drm_connector_cleanup(connector); | |
674e2d08 | 1100 | kfree(connector); |
7d57382e EA |
1101 | } |
1102 | ||
1103 | static const struct drm_encoder_helper_funcs intel_hdmi_helper_funcs = { | |
7d57382e | 1104 | .mode_set = intel_hdmi_mode_set, |
7d57382e EA |
1105 | }; |
1106 | ||
1107 | static const struct drm_connector_funcs intel_hdmi_connector_funcs = { | |
5ab432ef | 1108 | .dpms = intel_connector_dpms, |
7d57382e EA |
1109 | .detect = intel_hdmi_detect, |
1110 | .fill_modes = drm_helper_probe_single_connector_modes, | |
55b7d6e8 | 1111 | .set_property = intel_hdmi_set_property, |
7d57382e EA |
1112 | .destroy = intel_hdmi_destroy, |
1113 | }; | |
1114 | ||
1115 | static const struct drm_connector_helper_funcs intel_hdmi_connector_helper_funcs = { | |
1116 | .get_modes = intel_hdmi_get_modes, | |
1117 | .mode_valid = intel_hdmi_mode_valid, | |
df0e9248 | 1118 | .best_encoder = intel_best_encoder, |
7d57382e EA |
1119 | }; |
1120 | ||
7d57382e | 1121 | static const struct drm_encoder_funcs intel_hdmi_enc_funcs = { |
ea5b213a | 1122 | .destroy = intel_encoder_destroy, |
7d57382e EA |
1123 | }; |
1124 | ||
55b7d6e8 CW |
1125 | static void |
1126 | intel_hdmi_add_properties(struct intel_hdmi *intel_hdmi, struct drm_connector *connector) | |
1127 | { | |
3f43c48d | 1128 | intel_attach_force_audio_property(connector); |
e953fd7b | 1129 | intel_attach_broadcast_rgb_property(connector); |
55bc60db | 1130 | intel_hdmi->color_range_auto = true; |
55b7d6e8 CW |
1131 | } |
1132 | ||
00c09d70 PZ |
1133 | void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port, |
1134 | struct intel_connector *intel_connector) | |
7d57382e | 1135 | { |
b9cb234c PZ |
1136 | struct drm_connector *connector = &intel_connector->base; |
1137 | struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi; | |
1138 | struct intel_encoder *intel_encoder = &intel_dig_port->base; | |
1139 | struct drm_device *dev = intel_encoder->base.dev; | |
7d57382e | 1140 | struct drm_i915_private *dev_priv = dev->dev_private; |
174edf1f | 1141 | enum port port = intel_dig_port->port; |
373a3cf7 | 1142 | |
7d57382e | 1143 | drm_connector_init(dev, connector, &intel_hdmi_connector_funcs, |
8d91104a | 1144 | DRM_MODE_CONNECTOR_HDMIA); |
7d57382e EA |
1145 | drm_connector_helper_add(connector, &intel_hdmi_connector_helper_funcs); |
1146 | ||
c3febcc4 | 1147 | connector->interlace_allowed = 1; |
7d57382e | 1148 | connector->doublescan_allowed = 0; |
66a9278e | 1149 | |
08d644ad DV |
1150 | switch (port) { |
1151 | case PORT_B: | |
f899fc64 | 1152 | intel_hdmi->ddc_bus = GMBUS_PORT_DPB; |
1d843f9d | 1153 | intel_encoder->hpd_pin = HPD_PORT_B; |
08d644ad DV |
1154 | break; |
1155 | case PORT_C: | |
7ceae0a5 | 1156 | intel_hdmi->ddc_bus = GMBUS_PORT_DPC; |
1d843f9d | 1157 | intel_encoder->hpd_pin = HPD_PORT_C; |
08d644ad DV |
1158 | break; |
1159 | case PORT_D: | |
7ceae0a5 | 1160 | intel_hdmi->ddc_bus = GMBUS_PORT_DPD; |
1d843f9d | 1161 | intel_encoder->hpd_pin = HPD_PORT_D; |
08d644ad DV |
1162 | break; |
1163 | case PORT_A: | |
1d843f9d | 1164 | intel_encoder->hpd_pin = HPD_PORT_A; |
08d644ad DV |
1165 | /* Internal port only for eDP. */ |
1166 | default: | |
6e4c1677 | 1167 | BUG(); |
f8aed700 | 1168 | } |
7d57382e | 1169 | |
7637bfdb | 1170 | if (IS_VALLEYVIEW(dev)) { |
90b107c8 | 1171 | intel_hdmi->write_infoframe = vlv_write_infoframe; |
687f4d06 | 1172 | intel_hdmi->set_infoframes = vlv_set_infoframes; |
7637bfdb JB |
1173 | } else if (!HAS_PCH_SPLIT(dev)) { |
1174 | intel_hdmi->write_infoframe = g4x_write_infoframe; | |
1175 | intel_hdmi->set_infoframes = g4x_set_infoframes; | |
22b8bf17 | 1176 | } else if (HAS_DDI(dev)) { |
8c5f5f7c | 1177 | intel_hdmi->write_infoframe = hsw_write_infoframe; |
687f4d06 | 1178 | intel_hdmi->set_infoframes = hsw_set_infoframes; |
fdf1250a PZ |
1179 | } else if (HAS_PCH_IBX(dev)) { |
1180 | intel_hdmi->write_infoframe = ibx_write_infoframe; | |
687f4d06 | 1181 | intel_hdmi->set_infoframes = ibx_set_infoframes; |
fdf1250a PZ |
1182 | } else { |
1183 | intel_hdmi->write_infoframe = cpt_write_infoframe; | |
687f4d06 | 1184 | intel_hdmi->set_infoframes = cpt_set_infoframes; |
64a8fc01 | 1185 | } |
45187ace | 1186 | |
affa9354 | 1187 | if (HAS_DDI(dev)) |
bcbc889b PZ |
1188 | intel_connector->get_hw_state = intel_ddi_connector_get_hw_state; |
1189 | else | |
1190 | intel_connector->get_hw_state = intel_connector_get_hw_state; | |
b9cb234c PZ |
1191 | |
1192 | intel_hdmi_add_properties(intel_hdmi, connector); | |
1193 | ||
1194 | intel_connector_attach_encoder(intel_connector, intel_encoder); | |
1195 | drm_sysfs_connector_add(connector); | |
1196 | ||
1197 | /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written | |
1198 | * 0xd. Failure to do so will result in spurious interrupts being | |
1199 | * generated on the port when a cable is not attached. | |
1200 | */ | |
1201 | if (IS_G4X(dev) && !IS_GM45(dev)) { | |
1202 | u32 temp = I915_READ(PEG_BAND_GAP_DATA); | |
1203 | I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd); | |
1204 | } | |
1205 | } | |
1206 | ||
b242b7f7 | 1207 | void intel_hdmi_init(struct drm_device *dev, int hdmi_reg, enum port port) |
b9cb234c PZ |
1208 | { |
1209 | struct intel_digital_port *intel_dig_port; | |
1210 | struct intel_encoder *intel_encoder; | |
1211 | struct drm_encoder *encoder; | |
1212 | struct intel_connector *intel_connector; | |
1213 | ||
1214 | intel_dig_port = kzalloc(sizeof(struct intel_digital_port), GFP_KERNEL); | |
1215 | if (!intel_dig_port) | |
1216 | return; | |
1217 | ||
1218 | intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL); | |
1219 | if (!intel_connector) { | |
1220 | kfree(intel_dig_port); | |
1221 | return; | |
1222 | } | |
1223 | ||
1224 | intel_encoder = &intel_dig_port->base; | |
1225 | encoder = &intel_encoder->base; | |
1226 | ||
1227 | drm_encoder_init(dev, &intel_encoder->base, &intel_hdmi_enc_funcs, | |
1228 | DRM_MODE_ENCODER_TMDS); | |
00c09d70 PZ |
1229 | drm_encoder_helper_add(&intel_encoder->base, &intel_hdmi_helper_funcs); |
1230 | ||
5bfe2ac0 | 1231 | intel_encoder->compute_config = intel_hdmi_compute_config; |
00c09d70 PZ |
1232 | intel_encoder->enable = intel_enable_hdmi; |
1233 | intel_encoder->disable = intel_disable_hdmi; | |
1234 | intel_encoder->get_hw_state = intel_hdmi_get_hw_state; | |
045ac3b5 | 1235 | intel_encoder->get_config = intel_hdmi_get_config; |
89b667f8 JB |
1236 | if (IS_VALLEYVIEW(dev)) { |
1237 | intel_encoder->pre_enable = intel_hdmi_pre_enable; | |
1238 | intel_encoder->pre_pll_enable = intel_hdmi_pre_pll_enable; | |
1239 | intel_encoder->post_disable = intel_hdmi_post_disable; | |
1240 | } | |
5ab432ef | 1241 | |
b9cb234c PZ |
1242 | intel_encoder->type = INTEL_OUTPUT_HDMI; |
1243 | intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2); | |
1244 | intel_encoder->cloneable = false; | |
7d57382e | 1245 | |
174edf1f | 1246 | intel_dig_port->port = port; |
b242b7f7 | 1247 | intel_dig_port->hdmi.hdmi_reg = hdmi_reg; |
b9cb234c | 1248 | intel_dig_port->dp.output_reg = 0; |
55b7d6e8 | 1249 | |
b9cb234c | 1250 | intel_hdmi_init_connector(intel_dig_port, intel_connector); |
7d57382e | 1251 | } |