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7d57382e EA |
1 | /* |
2 | * Copyright 2006 Dave Airlie <airlied@linux.ie> | |
3 | * Copyright © 2006-2009 Intel Corporation | |
4 | * | |
5 | * Permission is hereby granted, free of charge, to any person obtaining a | |
6 | * copy of this software and associated documentation files (the "Software"), | |
7 | * to deal in the Software without restriction, including without limitation | |
8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
9 | * and/or sell copies of the Software, and to permit persons to whom the | |
10 | * Software is furnished to do so, subject to the following conditions: | |
11 | * | |
12 | * The above copyright notice and this permission notice (including the next | |
13 | * paragraph) shall be included in all copies or substantial portions of the | |
14 | * Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
21 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
22 | * DEALINGS IN THE SOFTWARE. | |
23 | * | |
24 | * Authors: | |
25 | * Eric Anholt <eric@anholt.net> | |
26 | * Jesse Barnes <jesse.barnes@intel.com> | |
27 | */ | |
28 | ||
29 | #include <linux/i2c.h> | |
5a0e3ad6 | 30 | #include <linux/slab.h> |
7d57382e | 31 | #include <linux/delay.h> |
178f736a | 32 | #include <linux/hdmi.h> |
760285e7 DH |
33 | #include <drm/drmP.h> |
34 | #include <drm/drm_crtc.h> | |
35 | #include <drm/drm_edid.h> | |
7d57382e | 36 | #include "intel_drv.h" |
760285e7 | 37 | #include <drm/i915_drm.h> |
7d57382e EA |
38 | #include "i915_drv.h" |
39 | ||
30add22d PZ |
40 | static struct drm_device *intel_hdmi_to_dev(struct intel_hdmi *intel_hdmi) |
41 | { | |
da63a9f2 | 42 | return hdmi_to_dig_port(intel_hdmi)->base.base.dev; |
30add22d PZ |
43 | } |
44 | ||
afba0188 DV |
45 | static void |
46 | assert_hdmi_port_disabled(struct intel_hdmi *intel_hdmi) | |
47 | { | |
30add22d | 48 | struct drm_device *dev = intel_hdmi_to_dev(intel_hdmi); |
afba0188 DV |
49 | struct drm_i915_private *dev_priv = dev->dev_private; |
50 | uint32_t enabled_bits; | |
51 | ||
affa9354 | 52 | enabled_bits = HAS_DDI(dev) ? DDI_BUF_CTL_ENABLE : SDVO_ENABLE; |
afba0188 | 53 | |
b242b7f7 | 54 | WARN(I915_READ(intel_hdmi->hdmi_reg) & enabled_bits, |
afba0188 DV |
55 | "HDMI port enabled, expecting disabled\n"); |
56 | } | |
57 | ||
f5bbfca3 | 58 | struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder) |
ea5b213a | 59 | { |
da63a9f2 PZ |
60 | struct intel_digital_port *intel_dig_port = |
61 | container_of(encoder, struct intel_digital_port, base.base); | |
62 | return &intel_dig_port->hdmi; | |
ea5b213a CW |
63 | } |
64 | ||
df0e9248 CW |
65 | static struct intel_hdmi *intel_attached_hdmi(struct drm_connector *connector) |
66 | { | |
da63a9f2 | 67 | return enc_to_intel_hdmi(&intel_attached_encoder(connector)->base); |
df0e9248 CW |
68 | } |
69 | ||
178f736a | 70 | static u32 g4x_infoframe_index(enum hdmi_infoframe_type type) |
3c17fe4b | 71 | { |
178f736a DL |
72 | switch (type) { |
73 | case HDMI_INFOFRAME_TYPE_AVI: | |
ed517fbb | 74 | return VIDEO_DIP_SELECT_AVI; |
178f736a | 75 | case HDMI_INFOFRAME_TYPE_SPD: |
ed517fbb | 76 | return VIDEO_DIP_SELECT_SPD; |
c8bb75af LD |
77 | case HDMI_INFOFRAME_TYPE_VENDOR: |
78 | return VIDEO_DIP_SELECT_VENDOR; | |
45187ace | 79 | default: |
178f736a | 80 | DRM_DEBUG_DRIVER("unknown info frame type %d\n", type); |
ed517fbb | 81 | return 0; |
45187ace | 82 | } |
45187ace JB |
83 | } |
84 | ||
178f736a | 85 | static u32 g4x_infoframe_enable(enum hdmi_infoframe_type type) |
45187ace | 86 | { |
178f736a DL |
87 | switch (type) { |
88 | case HDMI_INFOFRAME_TYPE_AVI: | |
ed517fbb | 89 | return VIDEO_DIP_ENABLE_AVI; |
178f736a | 90 | case HDMI_INFOFRAME_TYPE_SPD: |
ed517fbb | 91 | return VIDEO_DIP_ENABLE_SPD; |
c8bb75af LD |
92 | case HDMI_INFOFRAME_TYPE_VENDOR: |
93 | return VIDEO_DIP_ENABLE_VENDOR; | |
fa193ff7 | 94 | default: |
178f736a | 95 | DRM_DEBUG_DRIVER("unknown info frame type %d\n", type); |
ed517fbb | 96 | return 0; |
fa193ff7 | 97 | } |
fa193ff7 PZ |
98 | } |
99 | ||
178f736a | 100 | static u32 hsw_infoframe_enable(enum hdmi_infoframe_type type) |
2da8af54 | 101 | { |
178f736a DL |
102 | switch (type) { |
103 | case HDMI_INFOFRAME_TYPE_AVI: | |
2da8af54 | 104 | return VIDEO_DIP_ENABLE_AVI_HSW; |
178f736a | 105 | case HDMI_INFOFRAME_TYPE_SPD: |
2da8af54 | 106 | return VIDEO_DIP_ENABLE_SPD_HSW; |
c8bb75af LD |
107 | case HDMI_INFOFRAME_TYPE_VENDOR: |
108 | return VIDEO_DIP_ENABLE_VS_HSW; | |
2da8af54 | 109 | default: |
178f736a | 110 | DRM_DEBUG_DRIVER("unknown info frame type %d\n", type); |
2da8af54 PZ |
111 | return 0; |
112 | } | |
113 | } | |
114 | ||
178f736a | 115 | static u32 hsw_infoframe_data_reg(enum hdmi_infoframe_type type, |
a57c774a AK |
116 | enum transcoder cpu_transcoder, |
117 | struct drm_i915_private *dev_priv) | |
2da8af54 | 118 | { |
178f736a DL |
119 | switch (type) { |
120 | case HDMI_INFOFRAME_TYPE_AVI: | |
7d9bcebe | 121 | return HSW_TVIDEO_DIP_AVI_DATA(cpu_transcoder); |
178f736a | 122 | case HDMI_INFOFRAME_TYPE_SPD: |
7d9bcebe | 123 | return HSW_TVIDEO_DIP_SPD_DATA(cpu_transcoder); |
c8bb75af LD |
124 | case HDMI_INFOFRAME_TYPE_VENDOR: |
125 | return HSW_TVIDEO_DIP_VS_DATA(cpu_transcoder); | |
2da8af54 | 126 | default: |
178f736a | 127 | DRM_DEBUG_DRIVER("unknown info frame type %d\n", type); |
2da8af54 PZ |
128 | return 0; |
129 | } | |
130 | } | |
131 | ||
a3da1df7 | 132 | static void g4x_write_infoframe(struct drm_encoder *encoder, |
178f736a | 133 | enum hdmi_infoframe_type type, |
fff63867 | 134 | const void *frame, ssize_t len) |
45187ace | 135 | { |
fff63867 | 136 | const uint32_t *data = frame; |
3c17fe4b DH |
137 | struct drm_device *dev = encoder->dev; |
138 | struct drm_i915_private *dev_priv = dev->dev_private; | |
22509ec8 | 139 | u32 val = I915_READ(VIDEO_DIP_CTL); |
178f736a | 140 | int i; |
3c17fe4b | 141 | |
822974ae PZ |
142 | WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n"); |
143 | ||
1d4f85ac | 144 | val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ |
178f736a | 145 | val |= g4x_infoframe_index(type); |
22509ec8 | 146 | |
178f736a | 147 | val &= ~g4x_infoframe_enable(type); |
45187ace | 148 | |
22509ec8 | 149 | I915_WRITE(VIDEO_DIP_CTL, val); |
3c17fe4b | 150 | |
9d9740f0 | 151 | mmiowb(); |
45187ace | 152 | for (i = 0; i < len; i += 4) { |
3c17fe4b DH |
153 | I915_WRITE(VIDEO_DIP_DATA, *data); |
154 | data++; | |
155 | } | |
adf00b26 PZ |
156 | /* Write every possible data byte to force correct ECC calculation. */ |
157 | for (; i < VIDEO_DIP_DATA_SIZE; i += 4) | |
158 | I915_WRITE(VIDEO_DIP_DATA, 0); | |
9d9740f0 | 159 | mmiowb(); |
3c17fe4b | 160 | |
178f736a | 161 | val |= g4x_infoframe_enable(type); |
60c5ea2d | 162 | val &= ~VIDEO_DIP_FREQ_MASK; |
4b24c933 | 163 | val |= VIDEO_DIP_FREQ_VSYNC; |
45187ace | 164 | |
22509ec8 | 165 | I915_WRITE(VIDEO_DIP_CTL, val); |
9d9740f0 | 166 | POSTING_READ(VIDEO_DIP_CTL); |
3c17fe4b DH |
167 | } |
168 | ||
e43823ec JB |
169 | static bool g4x_infoframe_enabled(struct drm_encoder *encoder) |
170 | { | |
171 | struct drm_device *dev = encoder->dev; | |
172 | struct drm_i915_private *dev_priv = dev->dev_private; | |
173 | u32 val = I915_READ(VIDEO_DIP_CTL); | |
174 | ||
175 | return val & VIDEO_DIP_ENABLE; | |
176 | } | |
177 | ||
fdf1250a | 178 | static void ibx_write_infoframe(struct drm_encoder *encoder, |
178f736a | 179 | enum hdmi_infoframe_type type, |
fff63867 | 180 | const void *frame, ssize_t len) |
fdf1250a | 181 | { |
fff63867 | 182 | const uint32_t *data = frame; |
fdf1250a PZ |
183 | struct drm_device *dev = encoder->dev; |
184 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ed517fbb | 185 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); |
178f736a | 186 | int i, reg = TVIDEO_DIP_CTL(intel_crtc->pipe); |
fdf1250a PZ |
187 | u32 val = I915_READ(reg); |
188 | ||
822974ae PZ |
189 | WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n"); |
190 | ||
fdf1250a | 191 | val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ |
178f736a | 192 | val |= g4x_infoframe_index(type); |
fdf1250a | 193 | |
178f736a | 194 | val &= ~g4x_infoframe_enable(type); |
fdf1250a PZ |
195 | |
196 | I915_WRITE(reg, val); | |
197 | ||
9d9740f0 | 198 | mmiowb(); |
fdf1250a PZ |
199 | for (i = 0; i < len; i += 4) { |
200 | I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data); | |
201 | data++; | |
202 | } | |
adf00b26 PZ |
203 | /* Write every possible data byte to force correct ECC calculation. */ |
204 | for (; i < VIDEO_DIP_DATA_SIZE; i += 4) | |
205 | I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0); | |
9d9740f0 | 206 | mmiowb(); |
fdf1250a | 207 | |
178f736a | 208 | val |= g4x_infoframe_enable(type); |
fdf1250a | 209 | val &= ~VIDEO_DIP_FREQ_MASK; |
4b24c933 | 210 | val |= VIDEO_DIP_FREQ_VSYNC; |
fdf1250a PZ |
211 | |
212 | I915_WRITE(reg, val); | |
9d9740f0 | 213 | POSTING_READ(reg); |
fdf1250a PZ |
214 | } |
215 | ||
e43823ec JB |
216 | static bool ibx_infoframe_enabled(struct drm_encoder *encoder) |
217 | { | |
218 | struct drm_device *dev = encoder->dev; | |
219 | struct drm_i915_private *dev_priv = dev->dev_private; | |
220 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); | |
221 | int reg = TVIDEO_DIP_CTL(intel_crtc->pipe); | |
222 | u32 val = I915_READ(reg); | |
223 | ||
224 | return val & VIDEO_DIP_ENABLE; | |
225 | } | |
226 | ||
fdf1250a | 227 | static void cpt_write_infoframe(struct drm_encoder *encoder, |
178f736a | 228 | enum hdmi_infoframe_type type, |
fff63867 | 229 | const void *frame, ssize_t len) |
b055c8f3 | 230 | { |
fff63867 | 231 | const uint32_t *data = frame; |
b055c8f3 JB |
232 | struct drm_device *dev = encoder->dev; |
233 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ed517fbb | 234 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); |
178f736a | 235 | int i, reg = TVIDEO_DIP_CTL(intel_crtc->pipe); |
22509ec8 | 236 | u32 val = I915_READ(reg); |
b055c8f3 | 237 | |
822974ae PZ |
238 | WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n"); |
239 | ||
64a8fc01 | 240 | val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ |
178f736a | 241 | val |= g4x_infoframe_index(type); |
45187ace | 242 | |
ecb97851 PZ |
243 | /* The DIP control register spec says that we need to update the AVI |
244 | * infoframe without clearing its enable bit */ | |
178f736a DL |
245 | if (type != HDMI_INFOFRAME_TYPE_AVI) |
246 | val &= ~g4x_infoframe_enable(type); | |
ecb97851 | 247 | |
22509ec8 | 248 | I915_WRITE(reg, val); |
45187ace | 249 | |
9d9740f0 | 250 | mmiowb(); |
45187ace | 251 | for (i = 0; i < len; i += 4) { |
b055c8f3 JB |
252 | I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data); |
253 | data++; | |
254 | } | |
adf00b26 PZ |
255 | /* Write every possible data byte to force correct ECC calculation. */ |
256 | for (; i < VIDEO_DIP_DATA_SIZE; i += 4) | |
257 | I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0); | |
9d9740f0 | 258 | mmiowb(); |
b055c8f3 | 259 | |
178f736a | 260 | val |= g4x_infoframe_enable(type); |
60c5ea2d | 261 | val &= ~VIDEO_DIP_FREQ_MASK; |
4b24c933 | 262 | val |= VIDEO_DIP_FREQ_VSYNC; |
45187ace | 263 | |
22509ec8 | 264 | I915_WRITE(reg, val); |
9d9740f0 | 265 | POSTING_READ(reg); |
45187ace | 266 | } |
90b107c8 | 267 | |
e43823ec JB |
268 | static bool cpt_infoframe_enabled(struct drm_encoder *encoder) |
269 | { | |
270 | struct drm_device *dev = encoder->dev; | |
271 | struct drm_i915_private *dev_priv = dev->dev_private; | |
272 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); | |
273 | int reg = TVIDEO_DIP_CTL(intel_crtc->pipe); | |
274 | u32 val = I915_READ(reg); | |
275 | ||
276 | return val & VIDEO_DIP_ENABLE; | |
277 | } | |
278 | ||
90b107c8 | 279 | static void vlv_write_infoframe(struct drm_encoder *encoder, |
178f736a | 280 | enum hdmi_infoframe_type type, |
fff63867 | 281 | const void *frame, ssize_t len) |
90b107c8 | 282 | { |
fff63867 | 283 | const uint32_t *data = frame; |
90b107c8 SK |
284 | struct drm_device *dev = encoder->dev; |
285 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ed517fbb | 286 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); |
178f736a | 287 | int i, reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe); |
22509ec8 | 288 | u32 val = I915_READ(reg); |
90b107c8 | 289 | |
822974ae PZ |
290 | WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n"); |
291 | ||
90b107c8 | 292 | val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ |
178f736a | 293 | val |= g4x_infoframe_index(type); |
22509ec8 | 294 | |
178f736a | 295 | val &= ~g4x_infoframe_enable(type); |
90b107c8 | 296 | |
22509ec8 | 297 | I915_WRITE(reg, val); |
90b107c8 | 298 | |
9d9740f0 | 299 | mmiowb(); |
90b107c8 SK |
300 | for (i = 0; i < len; i += 4) { |
301 | I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), *data); | |
302 | data++; | |
303 | } | |
adf00b26 PZ |
304 | /* Write every possible data byte to force correct ECC calculation. */ |
305 | for (; i < VIDEO_DIP_DATA_SIZE; i += 4) | |
306 | I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), 0); | |
9d9740f0 | 307 | mmiowb(); |
90b107c8 | 308 | |
178f736a | 309 | val |= g4x_infoframe_enable(type); |
60c5ea2d | 310 | val &= ~VIDEO_DIP_FREQ_MASK; |
4b24c933 | 311 | val |= VIDEO_DIP_FREQ_VSYNC; |
90b107c8 | 312 | |
22509ec8 | 313 | I915_WRITE(reg, val); |
9d9740f0 | 314 | POSTING_READ(reg); |
90b107c8 SK |
315 | } |
316 | ||
e43823ec JB |
317 | static bool vlv_infoframe_enabled(struct drm_encoder *encoder) |
318 | { | |
319 | struct drm_device *dev = encoder->dev; | |
320 | struct drm_i915_private *dev_priv = dev->dev_private; | |
321 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); | |
322 | int reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe); | |
323 | u32 val = I915_READ(reg); | |
324 | ||
325 | return val & VIDEO_DIP_ENABLE; | |
326 | } | |
327 | ||
8c5f5f7c | 328 | static void hsw_write_infoframe(struct drm_encoder *encoder, |
178f736a | 329 | enum hdmi_infoframe_type type, |
fff63867 | 330 | const void *frame, ssize_t len) |
8c5f5f7c | 331 | { |
fff63867 | 332 | const uint32_t *data = frame; |
2da8af54 PZ |
333 | struct drm_device *dev = encoder->dev; |
334 | struct drm_i915_private *dev_priv = dev->dev_private; | |
335 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); | |
3b117c8f | 336 | u32 ctl_reg = HSW_TVIDEO_DIP_CTL(intel_crtc->config.cpu_transcoder); |
178f736a DL |
337 | u32 data_reg; |
338 | int i; | |
2da8af54 | 339 | u32 val = I915_READ(ctl_reg); |
8c5f5f7c | 340 | |
178f736a | 341 | data_reg = hsw_infoframe_data_reg(type, |
a57c774a AK |
342 | intel_crtc->config.cpu_transcoder, |
343 | dev_priv); | |
2da8af54 PZ |
344 | if (data_reg == 0) |
345 | return; | |
346 | ||
178f736a | 347 | val &= ~hsw_infoframe_enable(type); |
2da8af54 PZ |
348 | I915_WRITE(ctl_reg, val); |
349 | ||
9d9740f0 | 350 | mmiowb(); |
2da8af54 PZ |
351 | for (i = 0; i < len; i += 4) { |
352 | I915_WRITE(data_reg + i, *data); | |
353 | data++; | |
354 | } | |
adf00b26 PZ |
355 | /* Write every possible data byte to force correct ECC calculation. */ |
356 | for (; i < VIDEO_DIP_DATA_SIZE; i += 4) | |
357 | I915_WRITE(data_reg + i, 0); | |
9d9740f0 | 358 | mmiowb(); |
8c5f5f7c | 359 | |
178f736a | 360 | val |= hsw_infoframe_enable(type); |
2da8af54 | 361 | I915_WRITE(ctl_reg, val); |
9d9740f0 | 362 | POSTING_READ(ctl_reg); |
8c5f5f7c ED |
363 | } |
364 | ||
e43823ec JB |
365 | static bool hsw_infoframe_enabled(struct drm_encoder *encoder) |
366 | { | |
367 | struct drm_device *dev = encoder->dev; | |
368 | struct drm_i915_private *dev_priv = dev->dev_private; | |
369 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); | |
370 | u32 ctl_reg = HSW_TVIDEO_DIP_CTL(intel_crtc->config.cpu_transcoder); | |
371 | u32 val = I915_READ(ctl_reg); | |
372 | ||
373 | return val & (VIDEO_DIP_ENABLE_AVI_HSW | VIDEO_DIP_ENABLE_SPD_HSW | | |
374 | VIDEO_DIP_ENABLE_VS_HSW); | |
375 | } | |
376 | ||
5adaea79 DL |
377 | /* |
378 | * The data we write to the DIP data buffer registers is 1 byte bigger than the | |
379 | * HDMI infoframe size because of an ECC/reserved byte at position 3 (starting | |
380 | * at 0). It's also a byte used by DisplayPort so the same DIP registers can be | |
381 | * used for both technologies. | |
382 | * | |
383 | * DW0: Reserved/ECC/DP | HB2 | HB1 | HB0 | |
384 | * DW1: DB3 | DB2 | DB1 | DB0 | |
385 | * DW2: DB7 | DB6 | DB5 | DB4 | |
386 | * DW3: ... | |
387 | * | |
388 | * (HB is Header Byte, DB is Data Byte) | |
389 | * | |
390 | * The hdmi pack() functions don't know about that hardware specific hole so we | |
391 | * trick them by giving an offset into the buffer and moving back the header | |
392 | * bytes by one. | |
393 | */ | |
9198ee5b DL |
394 | static void intel_write_infoframe(struct drm_encoder *encoder, |
395 | union hdmi_infoframe *frame) | |
45187ace JB |
396 | { |
397 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); | |
5adaea79 DL |
398 | uint8_t buffer[VIDEO_DIP_DATA_SIZE]; |
399 | ssize_t len; | |
45187ace | 400 | |
5adaea79 DL |
401 | /* see comment above for the reason for this offset */ |
402 | len = hdmi_infoframe_pack(frame, buffer + 1, sizeof(buffer) - 1); | |
403 | if (len < 0) | |
404 | return; | |
405 | ||
406 | /* Insert the 'hole' (see big comment above) at position 3 */ | |
407 | buffer[0] = buffer[1]; | |
408 | buffer[1] = buffer[2]; | |
409 | buffer[2] = buffer[3]; | |
410 | buffer[3] = 0; | |
411 | len++; | |
45187ace | 412 | |
5adaea79 | 413 | intel_hdmi->write_infoframe(encoder, frame->any.type, buffer, len); |
45187ace JB |
414 | } |
415 | ||
687f4d06 | 416 | static void intel_hdmi_set_avi_infoframe(struct drm_encoder *encoder, |
c846b619 | 417 | struct drm_display_mode *adjusted_mode) |
45187ace | 418 | { |
abedc077 | 419 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); |
50f3b016 | 420 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); |
5adaea79 DL |
421 | union hdmi_infoframe frame; |
422 | int ret; | |
45187ace | 423 | |
94a11ddc VK |
424 | /* Set user selected PAR to incoming mode's member */ |
425 | adjusted_mode->picture_aspect_ratio = intel_hdmi->aspect_ratio; | |
426 | ||
5adaea79 DL |
427 | ret = drm_hdmi_avi_infoframe_from_display_mode(&frame.avi, |
428 | adjusted_mode); | |
429 | if (ret < 0) { | |
430 | DRM_ERROR("couldn't fill AVI infoframe\n"); | |
431 | return; | |
432 | } | |
c846b619 | 433 | |
abedc077 | 434 | if (intel_hdmi->rgb_quant_range_selectable) { |
50f3b016 | 435 | if (intel_crtc->config.limited_color_range) |
5adaea79 DL |
436 | frame.avi.quantization_range = |
437 | HDMI_QUANTIZATION_RANGE_LIMITED; | |
abedc077 | 438 | else |
5adaea79 DL |
439 | frame.avi.quantization_range = |
440 | HDMI_QUANTIZATION_RANGE_FULL; | |
abedc077 VS |
441 | } |
442 | ||
9198ee5b | 443 | intel_write_infoframe(encoder, &frame); |
b055c8f3 JB |
444 | } |
445 | ||
687f4d06 | 446 | static void intel_hdmi_set_spd_infoframe(struct drm_encoder *encoder) |
c0864cb3 | 447 | { |
5adaea79 DL |
448 | union hdmi_infoframe frame; |
449 | int ret; | |
450 | ||
451 | ret = hdmi_spd_infoframe_init(&frame.spd, "Intel", "Integrated gfx"); | |
452 | if (ret < 0) { | |
453 | DRM_ERROR("couldn't fill SPD infoframe\n"); | |
454 | return; | |
455 | } | |
c0864cb3 | 456 | |
5adaea79 | 457 | frame.spd.sdi = HDMI_SPD_SDI_PC; |
c0864cb3 | 458 | |
9198ee5b | 459 | intel_write_infoframe(encoder, &frame); |
c0864cb3 JB |
460 | } |
461 | ||
c8bb75af LD |
462 | static void |
463 | intel_hdmi_set_hdmi_infoframe(struct drm_encoder *encoder, | |
464 | struct drm_display_mode *adjusted_mode) | |
465 | { | |
466 | union hdmi_infoframe frame; | |
467 | int ret; | |
468 | ||
469 | ret = drm_hdmi_vendor_infoframe_from_display_mode(&frame.vendor.hdmi, | |
470 | adjusted_mode); | |
471 | if (ret < 0) | |
472 | return; | |
473 | ||
474 | intel_write_infoframe(encoder, &frame); | |
475 | } | |
476 | ||
687f4d06 | 477 | static void g4x_set_infoframes(struct drm_encoder *encoder, |
6897b4b5 | 478 | bool enable, |
687f4d06 PZ |
479 | struct drm_display_mode *adjusted_mode) |
480 | { | |
0c14c7f9 | 481 | struct drm_i915_private *dev_priv = encoder->dev->dev_private; |
69fde0a6 VS |
482 | struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); |
483 | struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi; | |
0c14c7f9 PZ |
484 | u32 reg = VIDEO_DIP_CTL; |
485 | u32 val = I915_READ(reg); | |
822cdc52 | 486 | u32 port = VIDEO_DIP_PORT(intel_dig_port->port); |
0c14c7f9 | 487 | |
afba0188 DV |
488 | assert_hdmi_port_disabled(intel_hdmi); |
489 | ||
0c14c7f9 PZ |
490 | /* If the registers were not initialized yet, they might be zeroes, |
491 | * which means we're selecting the AVI DIP and we're setting its | |
492 | * frequency to once. This seems to really confuse the HW and make | |
493 | * things stop working (the register spec says the AVI always needs to | |
494 | * be sent every VSync). So here we avoid writing to the register more | |
495 | * than we need and also explicitly select the AVI DIP and explicitly | |
496 | * set its frequency to every VSync. Avoiding to write it twice seems to | |
497 | * be enough to solve the problem, but being defensive shouldn't hurt us | |
498 | * either. */ | |
499 | val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; | |
500 | ||
6897b4b5 | 501 | if (!enable) { |
0c14c7f9 PZ |
502 | if (!(val & VIDEO_DIP_ENABLE)) |
503 | return; | |
504 | val &= ~VIDEO_DIP_ENABLE; | |
505 | I915_WRITE(reg, val); | |
9d9740f0 | 506 | POSTING_READ(reg); |
0c14c7f9 PZ |
507 | return; |
508 | } | |
509 | ||
72b78c9d PZ |
510 | if (port != (val & VIDEO_DIP_PORT_MASK)) { |
511 | if (val & VIDEO_DIP_ENABLE) { | |
512 | val &= ~VIDEO_DIP_ENABLE; | |
513 | I915_WRITE(reg, val); | |
9d9740f0 | 514 | POSTING_READ(reg); |
72b78c9d PZ |
515 | } |
516 | val &= ~VIDEO_DIP_PORT_MASK; | |
517 | val |= port; | |
518 | } | |
519 | ||
822974ae | 520 | val |= VIDEO_DIP_ENABLE; |
0dd87d20 | 521 | val &= ~VIDEO_DIP_ENABLE_VENDOR; |
822974ae | 522 | |
f278d972 | 523 | I915_WRITE(reg, val); |
9d9740f0 | 524 | POSTING_READ(reg); |
f278d972 | 525 | |
687f4d06 PZ |
526 | intel_hdmi_set_avi_infoframe(encoder, adjusted_mode); |
527 | intel_hdmi_set_spd_infoframe(encoder); | |
c8bb75af | 528 | intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode); |
687f4d06 PZ |
529 | } |
530 | ||
531 | static void ibx_set_infoframes(struct drm_encoder *encoder, | |
6897b4b5 | 532 | bool enable, |
687f4d06 PZ |
533 | struct drm_display_mode *adjusted_mode) |
534 | { | |
0c14c7f9 PZ |
535 | struct drm_i915_private *dev_priv = encoder->dev->dev_private; |
536 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); | |
69fde0a6 VS |
537 | struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); |
538 | struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi; | |
0c14c7f9 PZ |
539 | u32 reg = TVIDEO_DIP_CTL(intel_crtc->pipe); |
540 | u32 val = I915_READ(reg); | |
822cdc52 | 541 | u32 port = VIDEO_DIP_PORT(intel_dig_port->port); |
0c14c7f9 | 542 | |
afba0188 DV |
543 | assert_hdmi_port_disabled(intel_hdmi); |
544 | ||
0c14c7f9 PZ |
545 | /* See the big comment in g4x_set_infoframes() */ |
546 | val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; | |
547 | ||
6897b4b5 | 548 | if (!enable) { |
0c14c7f9 PZ |
549 | if (!(val & VIDEO_DIP_ENABLE)) |
550 | return; | |
551 | val &= ~VIDEO_DIP_ENABLE; | |
552 | I915_WRITE(reg, val); | |
9d9740f0 | 553 | POSTING_READ(reg); |
0c14c7f9 PZ |
554 | return; |
555 | } | |
556 | ||
72b78c9d PZ |
557 | if (port != (val & VIDEO_DIP_PORT_MASK)) { |
558 | if (val & VIDEO_DIP_ENABLE) { | |
559 | val &= ~VIDEO_DIP_ENABLE; | |
560 | I915_WRITE(reg, val); | |
9d9740f0 | 561 | POSTING_READ(reg); |
72b78c9d PZ |
562 | } |
563 | val &= ~VIDEO_DIP_PORT_MASK; | |
564 | val |= port; | |
565 | } | |
566 | ||
822974ae | 567 | val |= VIDEO_DIP_ENABLE; |
0dd87d20 PZ |
568 | val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | |
569 | VIDEO_DIP_ENABLE_GCP); | |
822974ae | 570 | |
f278d972 | 571 | I915_WRITE(reg, val); |
9d9740f0 | 572 | POSTING_READ(reg); |
f278d972 | 573 | |
687f4d06 PZ |
574 | intel_hdmi_set_avi_infoframe(encoder, adjusted_mode); |
575 | intel_hdmi_set_spd_infoframe(encoder); | |
c8bb75af | 576 | intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode); |
687f4d06 PZ |
577 | } |
578 | ||
579 | static void cpt_set_infoframes(struct drm_encoder *encoder, | |
6897b4b5 | 580 | bool enable, |
687f4d06 PZ |
581 | struct drm_display_mode *adjusted_mode) |
582 | { | |
0c14c7f9 PZ |
583 | struct drm_i915_private *dev_priv = encoder->dev->dev_private; |
584 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); | |
585 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); | |
586 | u32 reg = TVIDEO_DIP_CTL(intel_crtc->pipe); | |
587 | u32 val = I915_READ(reg); | |
588 | ||
afba0188 DV |
589 | assert_hdmi_port_disabled(intel_hdmi); |
590 | ||
0c14c7f9 PZ |
591 | /* See the big comment in g4x_set_infoframes() */ |
592 | val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; | |
593 | ||
6897b4b5 | 594 | if (!enable) { |
0c14c7f9 PZ |
595 | if (!(val & VIDEO_DIP_ENABLE)) |
596 | return; | |
597 | val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI); | |
598 | I915_WRITE(reg, val); | |
9d9740f0 | 599 | POSTING_READ(reg); |
0c14c7f9 PZ |
600 | return; |
601 | } | |
602 | ||
822974ae PZ |
603 | /* Set both together, unset both together: see the spec. */ |
604 | val |= VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI; | |
0dd87d20 PZ |
605 | val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | |
606 | VIDEO_DIP_ENABLE_GCP); | |
822974ae PZ |
607 | |
608 | I915_WRITE(reg, val); | |
9d9740f0 | 609 | POSTING_READ(reg); |
822974ae | 610 | |
687f4d06 PZ |
611 | intel_hdmi_set_avi_infoframe(encoder, adjusted_mode); |
612 | intel_hdmi_set_spd_infoframe(encoder); | |
c8bb75af | 613 | intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode); |
687f4d06 PZ |
614 | } |
615 | ||
616 | static void vlv_set_infoframes(struct drm_encoder *encoder, | |
6897b4b5 | 617 | bool enable, |
687f4d06 PZ |
618 | struct drm_display_mode *adjusted_mode) |
619 | { | |
0c14c7f9 | 620 | struct drm_i915_private *dev_priv = encoder->dev->dev_private; |
6a2b8021 | 621 | struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); |
0c14c7f9 PZ |
622 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); |
623 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); | |
624 | u32 reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe); | |
625 | u32 val = I915_READ(reg); | |
6a2b8021 | 626 | u32 port = VIDEO_DIP_PORT(intel_dig_port->port); |
0c14c7f9 | 627 | |
afba0188 DV |
628 | assert_hdmi_port_disabled(intel_hdmi); |
629 | ||
0c14c7f9 PZ |
630 | /* See the big comment in g4x_set_infoframes() */ |
631 | val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; | |
632 | ||
6897b4b5 | 633 | if (!enable) { |
0c14c7f9 PZ |
634 | if (!(val & VIDEO_DIP_ENABLE)) |
635 | return; | |
636 | val &= ~VIDEO_DIP_ENABLE; | |
637 | I915_WRITE(reg, val); | |
9d9740f0 | 638 | POSTING_READ(reg); |
0c14c7f9 PZ |
639 | return; |
640 | } | |
641 | ||
6a2b8021 JB |
642 | if (port != (val & VIDEO_DIP_PORT_MASK)) { |
643 | if (val & VIDEO_DIP_ENABLE) { | |
644 | val &= ~VIDEO_DIP_ENABLE; | |
645 | I915_WRITE(reg, val); | |
646 | POSTING_READ(reg); | |
647 | } | |
648 | val &= ~VIDEO_DIP_PORT_MASK; | |
649 | val |= port; | |
650 | } | |
651 | ||
822974ae | 652 | val |= VIDEO_DIP_ENABLE; |
4d47dfb8 JB |
653 | val &= ~(VIDEO_DIP_ENABLE_AVI | VIDEO_DIP_ENABLE_VENDOR | |
654 | VIDEO_DIP_ENABLE_GAMUT | VIDEO_DIP_ENABLE_GCP); | |
822974ae PZ |
655 | |
656 | I915_WRITE(reg, val); | |
9d9740f0 | 657 | POSTING_READ(reg); |
822974ae | 658 | |
687f4d06 PZ |
659 | intel_hdmi_set_avi_infoframe(encoder, adjusted_mode); |
660 | intel_hdmi_set_spd_infoframe(encoder); | |
c8bb75af | 661 | intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode); |
687f4d06 PZ |
662 | } |
663 | ||
664 | static void hsw_set_infoframes(struct drm_encoder *encoder, | |
6897b4b5 | 665 | bool enable, |
687f4d06 PZ |
666 | struct drm_display_mode *adjusted_mode) |
667 | { | |
0c14c7f9 PZ |
668 | struct drm_i915_private *dev_priv = encoder->dev->dev_private; |
669 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); | |
670 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); | |
3b117c8f | 671 | u32 reg = HSW_TVIDEO_DIP_CTL(intel_crtc->config.cpu_transcoder); |
0dd87d20 | 672 | u32 val = I915_READ(reg); |
0c14c7f9 | 673 | |
afba0188 DV |
674 | assert_hdmi_port_disabled(intel_hdmi); |
675 | ||
6897b4b5 | 676 | if (!enable) { |
0c14c7f9 | 677 | I915_WRITE(reg, 0); |
9d9740f0 | 678 | POSTING_READ(reg); |
0c14c7f9 PZ |
679 | return; |
680 | } | |
681 | ||
0dd87d20 PZ |
682 | val &= ~(VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_GCP_HSW | |
683 | VIDEO_DIP_ENABLE_VS_HSW | VIDEO_DIP_ENABLE_GMP_HSW); | |
684 | ||
685 | I915_WRITE(reg, val); | |
9d9740f0 | 686 | POSTING_READ(reg); |
0dd87d20 | 687 | |
687f4d06 PZ |
688 | intel_hdmi_set_avi_infoframe(encoder, adjusted_mode); |
689 | intel_hdmi_set_spd_infoframe(encoder); | |
c8bb75af | 690 | intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode); |
687f4d06 PZ |
691 | } |
692 | ||
4cde8a21 | 693 | static void intel_hdmi_prepare(struct intel_encoder *encoder) |
7d57382e | 694 | { |
c59423a3 | 695 | struct drm_device *dev = encoder->base.dev; |
7d57382e | 696 | struct drm_i915_private *dev_priv = dev->dev_private; |
c59423a3 DV |
697 | struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); |
698 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); | |
699 | struct drm_display_mode *adjusted_mode = &crtc->config.adjusted_mode; | |
b242b7f7 | 700 | u32 hdmi_val; |
7d57382e | 701 | |
b242b7f7 | 702 | hdmi_val = SDVO_ENCODING_HDMI; |
2af2c490 | 703 | if (!HAS_PCH_SPLIT(dev)) |
b242b7f7 | 704 | hdmi_val |= intel_hdmi->color_range; |
b599c0bc | 705 | if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) |
b242b7f7 | 706 | hdmi_val |= SDVO_VSYNC_ACTIVE_HIGH; |
b599c0bc | 707 | if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) |
b242b7f7 | 708 | hdmi_val |= SDVO_HSYNC_ACTIVE_HIGH; |
7d57382e | 709 | |
c59423a3 | 710 | if (crtc->config.pipe_bpp > 24) |
4f3a8bc7 | 711 | hdmi_val |= HDMI_COLOR_FORMAT_12bpc; |
020f6704 | 712 | else |
4f3a8bc7 | 713 | hdmi_val |= SDVO_COLOR_FORMAT_8bpc; |
020f6704 | 714 | |
6897b4b5 | 715 | if (crtc->config.has_hdmi_sink) |
dc0fa718 | 716 | hdmi_val |= HDMI_MODE_SELECT_HDMI; |
2e3d6006 | 717 | |
75770564 | 718 | if (HAS_PCH_CPT(dev)) |
c59423a3 | 719 | hdmi_val |= SDVO_PIPE_SEL_CPT(crtc->pipe); |
44f37d1f CML |
720 | else if (IS_CHERRYVIEW(dev)) |
721 | hdmi_val |= SDVO_PIPE_SEL_CHV(crtc->pipe); | |
dc0fa718 | 722 | else |
c59423a3 | 723 | hdmi_val |= SDVO_PIPE_SEL(crtc->pipe); |
7d57382e | 724 | |
b242b7f7 PZ |
725 | I915_WRITE(intel_hdmi->hdmi_reg, hdmi_val); |
726 | POSTING_READ(intel_hdmi->hdmi_reg); | |
7d57382e EA |
727 | } |
728 | ||
85234cdc DV |
729 | static bool intel_hdmi_get_hw_state(struct intel_encoder *encoder, |
730 | enum pipe *pipe) | |
7d57382e | 731 | { |
85234cdc | 732 | struct drm_device *dev = encoder->base.dev; |
7d57382e | 733 | struct drm_i915_private *dev_priv = dev->dev_private; |
85234cdc | 734 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); |
6d129bea | 735 | enum intel_display_power_domain power_domain; |
85234cdc DV |
736 | u32 tmp; |
737 | ||
6d129bea | 738 | power_domain = intel_display_port_power_domain(encoder); |
f458ebbc | 739 | if (!intel_display_power_is_enabled(dev_priv, power_domain)) |
6d129bea ID |
740 | return false; |
741 | ||
b242b7f7 | 742 | tmp = I915_READ(intel_hdmi->hdmi_reg); |
85234cdc DV |
743 | |
744 | if (!(tmp & SDVO_ENABLE)) | |
745 | return false; | |
746 | ||
747 | if (HAS_PCH_CPT(dev)) | |
748 | *pipe = PORT_TO_PIPE_CPT(tmp); | |
71485e0a VS |
749 | else if (IS_CHERRYVIEW(dev)) |
750 | *pipe = SDVO_PORT_TO_PIPE_CHV(tmp); | |
85234cdc DV |
751 | else |
752 | *pipe = PORT_TO_PIPE(tmp); | |
753 | ||
754 | return true; | |
755 | } | |
756 | ||
045ac3b5 JB |
757 | static void intel_hdmi_get_config(struct intel_encoder *encoder, |
758 | struct intel_crtc_config *pipe_config) | |
759 | { | |
760 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); | |
8c875fca VS |
761 | struct drm_device *dev = encoder->base.dev; |
762 | struct drm_i915_private *dev_priv = dev->dev_private; | |
045ac3b5 | 763 | u32 tmp, flags = 0; |
18442d08 | 764 | int dotclock; |
045ac3b5 JB |
765 | |
766 | tmp = I915_READ(intel_hdmi->hdmi_reg); | |
767 | ||
768 | if (tmp & SDVO_HSYNC_ACTIVE_HIGH) | |
769 | flags |= DRM_MODE_FLAG_PHSYNC; | |
770 | else | |
771 | flags |= DRM_MODE_FLAG_NHSYNC; | |
772 | ||
773 | if (tmp & SDVO_VSYNC_ACTIVE_HIGH) | |
774 | flags |= DRM_MODE_FLAG_PVSYNC; | |
775 | else | |
776 | flags |= DRM_MODE_FLAG_NVSYNC; | |
777 | ||
6897b4b5 DV |
778 | if (tmp & HDMI_MODE_SELECT_HDMI) |
779 | pipe_config->has_hdmi_sink = true; | |
780 | ||
e43823ec JB |
781 | if (intel_hdmi->infoframe_enabled(&encoder->base)) |
782 | pipe_config->has_infoframe = true; | |
783 | ||
c84db770 | 784 | if (tmp & SDVO_AUDIO_ENABLE) |
9ed109a7 DV |
785 | pipe_config->has_audio = true; |
786 | ||
8c875fca VS |
787 | if (!HAS_PCH_SPLIT(dev) && |
788 | tmp & HDMI_COLOR_RANGE_16_235) | |
789 | pipe_config->limited_color_range = true; | |
790 | ||
045ac3b5 | 791 | pipe_config->adjusted_mode.flags |= flags; |
18442d08 VS |
792 | |
793 | if ((tmp & SDVO_COLOR_FORMAT_MASK) == HDMI_COLOR_FORMAT_12bpc) | |
794 | dotclock = pipe_config->port_clock * 2 / 3; | |
795 | else | |
796 | dotclock = pipe_config->port_clock; | |
797 | ||
798 | if (HAS_PCH_SPLIT(dev_priv->dev)) | |
799 | ironlake_check_encoder_dotclock(pipe_config, dotclock); | |
800 | ||
241bfc38 | 801 | pipe_config->adjusted_mode.crtc_clock = dotclock; |
045ac3b5 JB |
802 | } |
803 | ||
5ab432ef | 804 | static void intel_enable_hdmi(struct intel_encoder *encoder) |
7d57382e | 805 | { |
5ab432ef | 806 | struct drm_device *dev = encoder->base.dev; |
7d57382e | 807 | struct drm_i915_private *dev_priv = dev->dev_private; |
dc0fa718 | 808 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); |
5ab432ef | 809 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); |
7d57382e | 810 | u32 temp; |
2deed761 WF |
811 | u32 enable_bits = SDVO_ENABLE; |
812 | ||
9ed109a7 | 813 | if (intel_crtc->config.has_audio) |
2deed761 | 814 | enable_bits |= SDVO_AUDIO_ENABLE; |
7d57382e | 815 | |
b242b7f7 | 816 | temp = I915_READ(intel_hdmi->hdmi_reg); |
d8a2d0e0 | 817 | |
7a87c289 | 818 | /* HW workaround for IBX, we need to move the port to transcoder A |
dc0fa718 PZ |
819 | * before disabling it, so restore the transcoder select bit here. */ |
820 | if (HAS_PCH_IBX(dev)) | |
821 | enable_bits |= SDVO_PIPE_SEL(intel_crtc->pipe); | |
7a87c289 | 822 | |
d8a2d0e0 ZW |
823 | /* HW workaround, need to toggle enable bit off and on for 12bpc, but |
824 | * we do this anyway which shows more stable in testing. | |
825 | */ | |
c619eed4 | 826 | if (HAS_PCH_SPLIT(dev)) { |
b242b7f7 PZ |
827 | I915_WRITE(intel_hdmi->hdmi_reg, temp & ~SDVO_ENABLE); |
828 | POSTING_READ(intel_hdmi->hdmi_reg); | |
d8a2d0e0 ZW |
829 | } |
830 | ||
5ab432ef DV |
831 | temp |= enable_bits; |
832 | ||
b242b7f7 PZ |
833 | I915_WRITE(intel_hdmi->hdmi_reg, temp); |
834 | POSTING_READ(intel_hdmi->hdmi_reg); | |
5ab432ef DV |
835 | |
836 | /* HW workaround, need to write this twice for issue that may result | |
837 | * in first write getting masked. | |
838 | */ | |
839 | if (HAS_PCH_SPLIT(dev)) { | |
b242b7f7 PZ |
840 | I915_WRITE(intel_hdmi->hdmi_reg, temp); |
841 | POSTING_READ(intel_hdmi->hdmi_reg); | |
7d57382e | 842 | } |
c1dec79a JN |
843 | |
844 | if (intel_crtc->config.has_audio) { | |
845 | WARN_ON(!intel_crtc->config.has_hdmi_sink); | |
846 | DRM_DEBUG_DRIVER("Enabling HDMI audio on pipe %c\n", | |
847 | pipe_name(intel_crtc->pipe)); | |
848 | intel_audio_codec_enable(encoder); | |
849 | } | |
b76cf76b | 850 | } |
89b667f8 | 851 | |
b76cf76b JN |
852 | static void vlv_enable_hdmi(struct intel_encoder *encoder) |
853 | { | |
5ab432ef DV |
854 | } |
855 | ||
856 | static void intel_disable_hdmi(struct intel_encoder *encoder) | |
857 | { | |
858 | struct drm_device *dev = encoder->base.dev; | |
859 | struct drm_i915_private *dev_priv = dev->dev_private; | |
860 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); | |
495a5bb8 | 861 | struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); |
5ab432ef | 862 | u32 temp; |
3cce574f | 863 | u32 enable_bits = SDVO_ENABLE | SDVO_AUDIO_ENABLE; |
5ab432ef | 864 | |
495a5bb8 JN |
865 | if (crtc->config.has_audio) |
866 | intel_audio_codec_disable(encoder); | |
867 | ||
b242b7f7 | 868 | temp = I915_READ(intel_hdmi->hdmi_reg); |
5ab432ef DV |
869 | |
870 | /* HW workaround for IBX, we need to move the port to transcoder A | |
871 | * before disabling it. */ | |
872 | if (HAS_PCH_IBX(dev)) { | |
873 | struct drm_crtc *crtc = encoder->base.crtc; | |
874 | int pipe = crtc ? to_intel_crtc(crtc)->pipe : -1; | |
875 | ||
876 | if (temp & SDVO_PIPE_B_SELECT) { | |
877 | temp &= ~SDVO_PIPE_B_SELECT; | |
b242b7f7 PZ |
878 | I915_WRITE(intel_hdmi->hdmi_reg, temp); |
879 | POSTING_READ(intel_hdmi->hdmi_reg); | |
5ab432ef DV |
880 | |
881 | /* Again we need to write this twice. */ | |
b242b7f7 PZ |
882 | I915_WRITE(intel_hdmi->hdmi_reg, temp); |
883 | POSTING_READ(intel_hdmi->hdmi_reg); | |
5ab432ef DV |
884 | |
885 | /* Transcoder selection bits only update | |
886 | * effectively on vblank. */ | |
887 | if (crtc) | |
888 | intel_wait_for_vblank(dev, pipe); | |
889 | else | |
890 | msleep(50); | |
891 | } | |
7d57382e | 892 | } |
d8a2d0e0 | 893 | |
5ab432ef DV |
894 | /* HW workaround, need to toggle enable bit off and on for 12bpc, but |
895 | * we do this anyway which shows more stable in testing. | |
896 | */ | |
897 | if (HAS_PCH_SPLIT(dev)) { | |
b242b7f7 PZ |
898 | I915_WRITE(intel_hdmi->hdmi_reg, temp & ~SDVO_ENABLE); |
899 | POSTING_READ(intel_hdmi->hdmi_reg); | |
5ab432ef DV |
900 | } |
901 | ||
902 | temp &= ~enable_bits; | |
d8a2d0e0 | 903 | |
b242b7f7 PZ |
904 | I915_WRITE(intel_hdmi->hdmi_reg, temp); |
905 | POSTING_READ(intel_hdmi->hdmi_reg); | |
d8a2d0e0 ZW |
906 | |
907 | /* HW workaround, need to write this twice for issue that may result | |
908 | * in first write getting masked. | |
909 | */ | |
c619eed4 | 910 | if (HAS_PCH_SPLIT(dev)) { |
b242b7f7 PZ |
911 | I915_WRITE(intel_hdmi->hdmi_reg, temp); |
912 | POSTING_READ(intel_hdmi->hdmi_reg); | |
d8a2d0e0 | 913 | } |
7d57382e EA |
914 | } |
915 | ||
40478455 | 916 | static int hdmi_portclock_limit(struct intel_hdmi *hdmi, bool respect_dvi_limit) |
7d148ef5 DV |
917 | { |
918 | struct drm_device *dev = intel_hdmi_to_dev(hdmi); | |
919 | ||
40478455 | 920 | if ((respect_dvi_limit && !hdmi->has_hdmi_sink) || IS_G4X(dev)) |
7d148ef5 | 921 | return 165000; |
e3c33578 | 922 | else if (IS_HASWELL(dev) || INTEL_INFO(dev)->gen >= 8) |
7d148ef5 DV |
923 | return 300000; |
924 | else | |
925 | return 225000; | |
926 | } | |
927 | ||
c19de8eb DL |
928 | static enum drm_mode_status |
929 | intel_hdmi_mode_valid(struct drm_connector *connector, | |
930 | struct drm_display_mode *mode) | |
7d57382e | 931 | { |
697c4078 CT |
932 | int clock = mode->clock; |
933 | ||
934 | if (mode->flags & DRM_MODE_FLAG_DBLCLK) | |
935 | clock *= 2; | |
936 | ||
937 | if (clock > hdmi_portclock_limit(intel_attached_hdmi(connector), | |
938 | true)) | |
7d57382e | 939 | return MODE_CLOCK_HIGH; |
697c4078 | 940 | if (clock < 20000) |
5cbba41d | 941 | return MODE_CLOCK_LOW; |
7d57382e EA |
942 | |
943 | if (mode->flags & DRM_MODE_FLAG_DBLSCAN) | |
944 | return MODE_NO_DBLESCAN; | |
945 | ||
946 | return MODE_OK; | |
947 | } | |
948 | ||
71800632 VS |
949 | static bool hdmi_12bpc_possible(struct intel_crtc *crtc) |
950 | { | |
951 | struct drm_device *dev = crtc->base.dev; | |
952 | struct intel_encoder *encoder; | |
953 | int count = 0, count_hdmi = 0; | |
954 | ||
f227ae9e | 955 | if (HAS_GMCH_DISPLAY(dev)) |
71800632 VS |
956 | return false; |
957 | ||
b2784e15 | 958 | for_each_intel_encoder(dev, encoder) { |
71800632 VS |
959 | if (encoder->new_crtc != crtc) |
960 | continue; | |
961 | ||
962 | count_hdmi += encoder->type == INTEL_OUTPUT_HDMI; | |
963 | count++; | |
964 | } | |
965 | ||
966 | /* | |
967 | * HDMI 12bpc affects the clocks, so it's only possible | |
968 | * when not cloning with other encoder types. | |
969 | */ | |
970 | return count_hdmi > 0 && count_hdmi == count; | |
971 | } | |
972 | ||
5bfe2ac0 DV |
973 | bool intel_hdmi_compute_config(struct intel_encoder *encoder, |
974 | struct intel_crtc_config *pipe_config) | |
7d57382e | 975 | { |
5bfe2ac0 DV |
976 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); |
977 | struct drm_device *dev = encoder->base.dev; | |
978 | struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode; | |
241bfc38 | 979 | int clock_12bpc = pipe_config->adjusted_mode.crtc_clock * 3 / 2; |
40478455 | 980 | int portclock_limit = hdmi_portclock_limit(intel_hdmi, false); |
e29c22c0 | 981 | int desired_bpp; |
3685a8f3 | 982 | |
6897b4b5 DV |
983 | pipe_config->has_hdmi_sink = intel_hdmi->has_hdmi_sink; |
984 | ||
e43823ec JB |
985 | if (pipe_config->has_hdmi_sink) |
986 | pipe_config->has_infoframe = true; | |
987 | ||
55bc60db VS |
988 | if (intel_hdmi->color_range_auto) { |
989 | /* See CEA-861-E - 5.1 Default Encoding Parameters */ | |
6897b4b5 | 990 | if (pipe_config->has_hdmi_sink && |
18316c8c | 991 | drm_match_cea_mode(adjusted_mode) > 1) |
4f3a8bc7 | 992 | intel_hdmi->color_range = HDMI_COLOR_RANGE_16_235; |
55bc60db VS |
993 | else |
994 | intel_hdmi->color_range = 0; | |
995 | } | |
996 | ||
697c4078 CT |
997 | if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK) { |
998 | pipe_config->pixel_multiplier = 2; | |
999 | } | |
1000 | ||
3685a8f3 | 1001 | if (intel_hdmi->color_range) |
50f3b016 | 1002 | pipe_config->limited_color_range = true; |
3685a8f3 | 1003 | |
5bfe2ac0 DV |
1004 | if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev)) |
1005 | pipe_config->has_pch_encoder = true; | |
1006 | ||
9ed109a7 DV |
1007 | if (pipe_config->has_hdmi_sink && intel_hdmi->has_audio) |
1008 | pipe_config->has_audio = true; | |
1009 | ||
4e53c2e0 DV |
1010 | /* |
1011 | * HDMI is either 12 or 8, so if the display lets 10bpc sneak | |
1012 | * through, clamp it down. Note that g4x/vlv don't support 12bpc hdmi | |
325b9d04 DV |
1013 | * outputs. We also need to check that the higher clock still fits |
1014 | * within limits. | |
4e53c2e0 | 1015 | */ |
6897b4b5 | 1016 | if (pipe_config->pipe_bpp > 8*3 && pipe_config->has_hdmi_sink && |
71800632 VS |
1017 | clock_12bpc <= portclock_limit && |
1018 | hdmi_12bpc_possible(encoder->new_crtc)) { | |
e29c22c0 DV |
1019 | DRM_DEBUG_KMS("picking bpc to 12 for HDMI output\n"); |
1020 | desired_bpp = 12*3; | |
325b9d04 DV |
1021 | |
1022 | /* Need to adjust the port link by 1.5x for 12bpc. */ | |
ff9a6750 | 1023 | pipe_config->port_clock = clock_12bpc; |
4e53c2e0 | 1024 | } else { |
e29c22c0 DV |
1025 | DRM_DEBUG_KMS("picking bpc to 8 for HDMI output\n"); |
1026 | desired_bpp = 8*3; | |
1027 | } | |
1028 | ||
1029 | if (!pipe_config->bw_constrained) { | |
1030 | DRM_DEBUG_KMS("forcing pipe bpc to %i for HDMI\n", desired_bpp); | |
1031 | pipe_config->pipe_bpp = desired_bpp; | |
4e53c2e0 DV |
1032 | } |
1033 | ||
241bfc38 | 1034 | if (adjusted_mode->crtc_clock > portclock_limit) { |
325b9d04 DV |
1035 | DRM_DEBUG_KMS("too high HDMI clock, rejecting mode\n"); |
1036 | return false; | |
1037 | } | |
1038 | ||
7d57382e EA |
1039 | return true; |
1040 | } | |
1041 | ||
953ece69 CW |
1042 | static void |
1043 | intel_hdmi_unset_edid(struct drm_connector *connector) | |
9dff6af8 | 1044 | { |
df0e9248 | 1045 | struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); |
9dff6af8 | 1046 | |
953ece69 CW |
1047 | intel_hdmi->has_hdmi_sink = false; |
1048 | intel_hdmi->has_audio = false; | |
1049 | intel_hdmi->rgb_quant_range_selectable = false; | |
1050 | ||
1051 | kfree(to_intel_connector(connector)->detect_edid); | |
1052 | to_intel_connector(connector)->detect_edid = NULL; | |
1053 | } | |
1054 | ||
1055 | static bool | |
1056 | intel_hdmi_set_edid(struct drm_connector *connector) | |
1057 | { | |
1058 | struct drm_i915_private *dev_priv = to_i915(connector->dev); | |
1059 | struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); | |
1060 | struct intel_encoder *intel_encoder = | |
1061 | &hdmi_to_dig_port(intel_hdmi)->base; | |
1062 | enum intel_display_power_domain power_domain; | |
1063 | struct edid *edid; | |
1064 | bool connected = false; | |
164c8598 | 1065 | |
671dedd2 ID |
1066 | power_domain = intel_display_port_power_domain(intel_encoder); |
1067 | intel_display_power_get(dev_priv, power_domain); | |
1068 | ||
f899fc64 | 1069 | edid = drm_get_edid(connector, |
3bd7d909 DK |
1070 | intel_gmbus_get_adapter(dev_priv, |
1071 | intel_hdmi->ddc_bus)); | |
2ded9e27 | 1072 | |
953ece69 | 1073 | intel_display_power_put(dev_priv, power_domain); |
30ad48b7 | 1074 | |
953ece69 CW |
1075 | to_intel_connector(connector)->detect_edid = edid; |
1076 | if (edid && edid->input & DRM_EDID_INPUT_DIGITAL) { | |
1077 | intel_hdmi->rgb_quant_range_selectable = | |
1078 | drm_rgb_quant_range_selectable(edid); | |
1079 | ||
1080 | intel_hdmi->has_audio = drm_detect_monitor_audio(edid); | |
b1d7e4b4 WF |
1081 | if (intel_hdmi->force_audio != HDMI_AUDIO_AUTO) |
1082 | intel_hdmi->has_audio = | |
953ece69 CW |
1083 | intel_hdmi->force_audio == HDMI_AUDIO_ON; |
1084 | ||
1085 | if (intel_hdmi->force_audio != HDMI_AUDIO_OFF_DVI) | |
1086 | intel_hdmi->has_hdmi_sink = | |
1087 | drm_detect_hdmi_monitor(edid); | |
1088 | ||
1089 | connected = true; | |
55b7d6e8 CW |
1090 | } |
1091 | ||
953ece69 CW |
1092 | return connected; |
1093 | } | |
1094 | ||
1095 | static enum drm_connector_status | |
1096 | intel_hdmi_detect(struct drm_connector *connector, bool force) | |
1097 | { | |
1098 | enum drm_connector_status status; | |
1099 | ||
1100 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", | |
1101 | connector->base.id, connector->name); | |
1102 | ||
1103 | intel_hdmi_unset_edid(connector); | |
1104 | ||
1105 | if (intel_hdmi_set_edid(connector)) { | |
1106 | struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); | |
1107 | ||
1108 | hdmi_to_dig_port(intel_hdmi)->base.type = INTEL_OUTPUT_HDMI; | |
1109 | status = connector_status_connected; | |
1110 | } else | |
1111 | status = connector_status_disconnected; | |
671dedd2 | 1112 | |
2ded9e27 | 1113 | return status; |
7d57382e EA |
1114 | } |
1115 | ||
953ece69 CW |
1116 | static void |
1117 | intel_hdmi_force(struct drm_connector *connector) | |
7d57382e | 1118 | { |
953ece69 | 1119 | struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); |
7d57382e | 1120 | |
953ece69 CW |
1121 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", |
1122 | connector->base.id, connector->name); | |
7d57382e | 1123 | |
953ece69 | 1124 | intel_hdmi_unset_edid(connector); |
671dedd2 | 1125 | |
953ece69 CW |
1126 | if (connector->status != connector_status_connected) |
1127 | return; | |
671dedd2 | 1128 | |
953ece69 CW |
1129 | intel_hdmi_set_edid(connector); |
1130 | hdmi_to_dig_port(intel_hdmi)->base.type = INTEL_OUTPUT_HDMI; | |
1131 | } | |
671dedd2 | 1132 | |
953ece69 CW |
1133 | static int intel_hdmi_get_modes(struct drm_connector *connector) |
1134 | { | |
1135 | struct edid *edid; | |
1136 | ||
1137 | edid = to_intel_connector(connector)->detect_edid; | |
1138 | if (edid == NULL) | |
1139 | return 0; | |
671dedd2 | 1140 | |
953ece69 | 1141 | return intel_connector_update_modes(connector, edid); |
7d57382e EA |
1142 | } |
1143 | ||
1aad7ac0 CW |
1144 | static bool |
1145 | intel_hdmi_detect_audio(struct drm_connector *connector) | |
1146 | { | |
1aad7ac0 | 1147 | bool has_audio = false; |
953ece69 | 1148 | struct edid *edid; |
1aad7ac0 | 1149 | |
953ece69 CW |
1150 | edid = to_intel_connector(connector)->detect_edid; |
1151 | if (edid && edid->input & DRM_EDID_INPUT_DIGITAL) | |
1152 | has_audio = drm_detect_monitor_audio(edid); | |
671dedd2 | 1153 | |
1aad7ac0 CW |
1154 | return has_audio; |
1155 | } | |
1156 | ||
55b7d6e8 CW |
1157 | static int |
1158 | intel_hdmi_set_property(struct drm_connector *connector, | |
ed517fbb PZ |
1159 | struct drm_property *property, |
1160 | uint64_t val) | |
55b7d6e8 CW |
1161 | { |
1162 | struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); | |
da63a9f2 PZ |
1163 | struct intel_digital_port *intel_dig_port = |
1164 | hdmi_to_dig_port(intel_hdmi); | |
e953fd7b | 1165 | struct drm_i915_private *dev_priv = connector->dev->dev_private; |
55b7d6e8 CW |
1166 | int ret; |
1167 | ||
662595df | 1168 | ret = drm_object_property_set_value(&connector->base, property, val); |
55b7d6e8 CW |
1169 | if (ret) |
1170 | return ret; | |
1171 | ||
3f43c48d | 1172 | if (property == dev_priv->force_audio_property) { |
b1d7e4b4 | 1173 | enum hdmi_force_audio i = val; |
1aad7ac0 CW |
1174 | bool has_audio; |
1175 | ||
1176 | if (i == intel_hdmi->force_audio) | |
55b7d6e8 CW |
1177 | return 0; |
1178 | ||
1aad7ac0 | 1179 | intel_hdmi->force_audio = i; |
55b7d6e8 | 1180 | |
b1d7e4b4 | 1181 | if (i == HDMI_AUDIO_AUTO) |
1aad7ac0 CW |
1182 | has_audio = intel_hdmi_detect_audio(connector); |
1183 | else | |
b1d7e4b4 | 1184 | has_audio = (i == HDMI_AUDIO_ON); |
1aad7ac0 | 1185 | |
b1d7e4b4 WF |
1186 | if (i == HDMI_AUDIO_OFF_DVI) |
1187 | intel_hdmi->has_hdmi_sink = 0; | |
55b7d6e8 | 1188 | |
1aad7ac0 | 1189 | intel_hdmi->has_audio = has_audio; |
55b7d6e8 CW |
1190 | goto done; |
1191 | } | |
1192 | ||
e953fd7b | 1193 | if (property == dev_priv->broadcast_rgb_property) { |
ae4edb80 DV |
1194 | bool old_auto = intel_hdmi->color_range_auto; |
1195 | uint32_t old_range = intel_hdmi->color_range; | |
1196 | ||
55bc60db VS |
1197 | switch (val) { |
1198 | case INTEL_BROADCAST_RGB_AUTO: | |
1199 | intel_hdmi->color_range_auto = true; | |
1200 | break; | |
1201 | case INTEL_BROADCAST_RGB_FULL: | |
1202 | intel_hdmi->color_range_auto = false; | |
1203 | intel_hdmi->color_range = 0; | |
1204 | break; | |
1205 | case INTEL_BROADCAST_RGB_LIMITED: | |
1206 | intel_hdmi->color_range_auto = false; | |
4f3a8bc7 | 1207 | intel_hdmi->color_range = HDMI_COLOR_RANGE_16_235; |
55bc60db VS |
1208 | break; |
1209 | default: | |
1210 | return -EINVAL; | |
1211 | } | |
ae4edb80 DV |
1212 | |
1213 | if (old_auto == intel_hdmi->color_range_auto && | |
1214 | old_range == intel_hdmi->color_range) | |
1215 | return 0; | |
1216 | ||
e953fd7b CW |
1217 | goto done; |
1218 | } | |
1219 | ||
94a11ddc VK |
1220 | if (property == connector->dev->mode_config.aspect_ratio_property) { |
1221 | switch (val) { | |
1222 | case DRM_MODE_PICTURE_ASPECT_NONE: | |
1223 | intel_hdmi->aspect_ratio = HDMI_PICTURE_ASPECT_NONE; | |
1224 | break; | |
1225 | case DRM_MODE_PICTURE_ASPECT_4_3: | |
1226 | intel_hdmi->aspect_ratio = HDMI_PICTURE_ASPECT_4_3; | |
1227 | break; | |
1228 | case DRM_MODE_PICTURE_ASPECT_16_9: | |
1229 | intel_hdmi->aspect_ratio = HDMI_PICTURE_ASPECT_16_9; | |
1230 | break; | |
1231 | default: | |
1232 | return -EINVAL; | |
1233 | } | |
1234 | goto done; | |
1235 | } | |
1236 | ||
55b7d6e8 CW |
1237 | return -EINVAL; |
1238 | ||
1239 | done: | |
c0c36b94 CW |
1240 | if (intel_dig_port->base.base.crtc) |
1241 | intel_crtc_restore_mode(intel_dig_port->base.base.crtc); | |
55b7d6e8 CW |
1242 | |
1243 | return 0; | |
1244 | } | |
1245 | ||
13732ba7 JB |
1246 | static void intel_hdmi_pre_enable(struct intel_encoder *encoder) |
1247 | { | |
1248 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); | |
1249 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); | |
1250 | struct drm_display_mode *adjusted_mode = | |
1251 | &intel_crtc->config.adjusted_mode; | |
1252 | ||
4cde8a21 DV |
1253 | intel_hdmi_prepare(encoder); |
1254 | ||
6897b4b5 DV |
1255 | intel_hdmi->set_infoframes(&encoder->base, |
1256 | intel_crtc->config.has_hdmi_sink, | |
1257 | adjusted_mode); | |
13732ba7 JB |
1258 | } |
1259 | ||
9514ac6e | 1260 | static void vlv_hdmi_pre_enable(struct intel_encoder *encoder) |
89b667f8 JB |
1261 | { |
1262 | struct intel_digital_port *dport = enc_to_dig_port(&encoder->base); | |
13732ba7 | 1263 | struct intel_hdmi *intel_hdmi = &dport->hdmi; |
89b667f8 JB |
1264 | struct drm_device *dev = encoder->base.dev; |
1265 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1266 | struct intel_crtc *intel_crtc = | |
1267 | to_intel_crtc(encoder->base.crtc); | |
13732ba7 JB |
1268 | struct drm_display_mode *adjusted_mode = |
1269 | &intel_crtc->config.adjusted_mode; | |
e4607fcf | 1270 | enum dpio_channel port = vlv_dport_to_channel(dport); |
89b667f8 JB |
1271 | int pipe = intel_crtc->pipe; |
1272 | u32 val; | |
1273 | ||
89b667f8 | 1274 | /* Enable clock channels for this port */ |
0980a60f | 1275 | mutex_lock(&dev_priv->dpio_lock); |
ab3c759a | 1276 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port)); |
89b667f8 JB |
1277 | val = 0; |
1278 | if (pipe) | |
1279 | val |= (1<<21); | |
1280 | else | |
1281 | val &= ~(1<<21); | |
1282 | val |= 0x001000c4; | |
ab3c759a | 1283 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val); |
89b667f8 JB |
1284 | |
1285 | /* HDMI 1.0V-2dB */ | |
ab3c759a CML |
1286 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0); |
1287 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), 0x2b245f5f); | |
1288 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port), 0x5578b83a); | |
1289 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0c782040); | |
1290 | vlv_dpio_write(dev_priv, pipe, VLV_TX3_DW4(port), 0x2b247878); | |
1291 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000); | |
1292 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), 0x00002000); | |
1293 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), DPIO_TX_OCALINIT_EN); | |
89b667f8 JB |
1294 | |
1295 | /* Program lane clock */ | |
ab3c759a CML |
1296 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018); |
1297 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888); | |
0980a60f | 1298 | mutex_unlock(&dev_priv->dpio_lock); |
b76cf76b | 1299 | |
6897b4b5 DV |
1300 | intel_hdmi->set_infoframes(&encoder->base, |
1301 | intel_crtc->config.has_hdmi_sink, | |
1302 | adjusted_mode); | |
13732ba7 | 1303 | |
b76cf76b JN |
1304 | intel_enable_hdmi(encoder); |
1305 | ||
e4607fcf | 1306 | vlv_wait_port_ready(dev_priv, dport); |
89b667f8 JB |
1307 | } |
1308 | ||
9514ac6e | 1309 | static void vlv_hdmi_pre_pll_enable(struct intel_encoder *encoder) |
89b667f8 JB |
1310 | { |
1311 | struct intel_digital_port *dport = enc_to_dig_port(&encoder->base); | |
1312 | struct drm_device *dev = encoder->base.dev; | |
1313 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5e69f97f CML |
1314 | struct intel_crtc *intel_crtc = |
1315 | to_intel_crtc(encoder->base.crtc); | |
e4607fcf | 1316 | enum dpio_channel port = vlv_dport_to_channel(dport); |
5e69f97f | 1317 | int pipe = intel_crtc->pipe; |
89b667f8 | 1318 | |
4cde8a21 DV |
1319 | intel_hdmi_prepare(encoder); |
1320 | ||
89b667f8 | 1321 | /* Program Tx lane resets to default */ |
0980a60f | 1322 | mutex_lock(&dev_priv->dpio_lock); |
ab3c759a | 1323 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port), |
89b667f8 JB |
1324 | DPIO_PCS_TX_LANE2_RESET | |
1325 | DPIO_PCS_TX_LANE1_RESET); | |
ab3c759a | 1326 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port), |
89b667f8 JB |
1327 | DPIO_PCS_CLK_CRI_RXEB_EIOS_EN | |
1328 | DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN | | |
1329 | (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) | | |
1330 | DPIO_PCS_CLK_SOFT_RESET); | |
1331 | ||
1332 | /* Fix up inter-pair skew failure */ | |
ab3c759a CML |
1333 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW12(port), 0x00750f00); |
1334 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW11(port), 0x00001500); | |
1335 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000); | |
1336 | ||
1337 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), 0x00002000); | |
1338 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), DPIO_TX_OCALINIT_EN); | |
0980a60f | 1339 | mutex_unlock(&dev_priv->dpio_lock); |
89b667f8 JB |
1340 | } |
1341 | ||
9197c88b VS |
1342 | static void chv_hdmi_pre_pll_enable(struct intel_encoder *encoder) |
1343 | { | |
1344 | struct intel_digital_port *dport = enc_to_dig_port(&encoder->base); | |
1345 | struct drm_device *dev = encoder->base.dev; | |
1346 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1347 | struct intel_crtc *intel_crtc = | |
1348 | to_intel_crtc(encoder->base.crtc); | |
1349 | enum dpio_channel ch = vlv_dport_to_channel(dport); | |
1350 | enum pipe pipe = intel_crtc->pipe; | |
1351 | u32 val; | |
1352 | ||
625695f8 VS |
1353 | intel_hdmi_prepare(encoder); |
1354 | ||
9197c88b VS |
1355 | mutex_lock(&dev_priv->dpio_lock); |
1356 | ||
b9e5ac3c VS |
1357 | /* program left/right clock distribution */ |
1358 | if (pipe != PIPE_B) { | |
1359 | val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0); | |
1360 | val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK); | |
1361 | if (ch == DPIO_CH0) | |
1362 | val |= CHV_BUFLEFTENA1_FORCE; | |
1363 | if (ch == DPIO_CH1) | |
1364 | val |= CHV_BUFRIGHTENA1_FORCE; | |
1365 | vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val); | |
1366 | } else { | |
1367 | val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1); | |
1368 | val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK); | |
1369 | if (ch == DPIO_CH0) | |
1370 | val |= CHV_BUFLEFTENA2_FORCE; | |
1371 | if (ch == DPIO_CH1) | |
1372 | val |= CHV_BUFRIGHTENA2_FORCE; | |
1373 | vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val); | |
1374 | } | |
1375 | ||
9197c88b VS |
1376 | /* program clock channel usage */ |
1377 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(ch)); | |
1378 | val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE; | |
1379 | if (pipe != PIPE_B) | |
1380 | val &= ~CHV_PCS_USEDCLKCHANNEL; | |
1381 | else | |
1382 | val |= CHV_PCS_USEDCLKCHANNEL; | |
1383 | vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW8(ch), val); | |
1384 | ||
1385 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW8(ch)); | |
1386 | val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE; | |
1387 | if (pipe != PIPE_B) | |
1388 | val &= ~CHV_PCS_USEDCLKCHANNEL; | |
1389 | else | |
1390 | val |= CHV_PCS_USEDCLKCHANNEL; | |
1391 | vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW8(ch), val); | |
1392 | ||
1393 | /* | |
1394 | * This a a bit weird since generally CL | |
1395 | * matches the pipe, but here we need to | |
1396 | * pick the CL based on the port. | |
1397 | */ | |
1398 | val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW19(ch)); | |
1399 | if (pipe != PIPE_B) | |
1400 | val &= ~CHV_CMN_USEDCLKCHANNEL; | |
1401 | else | |
1402 | val |= CHV_CMN_USEDCLKCHANNEL; | |
1403 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW19(ch), val); | |
1404 | ||
1405 | mutex_unlock(&dev_priv->dpio_lock); | |
1406 | } | |
1407 | ||
9514ac6e | 1408 | static void vlv_hdmi_post_disable(struct intel_encoder *encoder) |
89b667f8 JB |
1409 | { |
1410 | struct intel_digital_port *dport = enc_to_dig_port(&encoder->base); | |
1411 | struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; | |
5e69f97f CML |
1412 | struct intel_crtc *intel_crtc = |
1413 | to_intel_crtc(encoder->base.crtc); | |
e4607fcf | 1414 | enum dpio_channel port = vlv_dport_to_channel(dport); |
5e69f97f | 1415 | int pipe = intel_crtc->pipe; |
89b667f8 JB |
1416 | |
1417 | /* Reset lanes to avoid HDMI flicker (VLV w/a) */ | |
1418 | mutex_lock(&dev_priv->dpio_lock); | |
ab3c759a CML |
1419 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port), 0x00000000); |
1420 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port), 0x00e00060); | |
89b667f8 JB |
1421 | mutex_unlock(&dev_priv->dpio_lock); |
1422 | } | |
1423 | ||
580d3811 VS |
1424 | static void chv_hdmi_post_disable(struct intel_encoder *encoder) |
1425 | { | |
1426 | struct intel_digital_port *dport = enc_to_dig_port(&encoder->base); | |
1427 | struct drm_device *dev = encoder->base.dev; | |
1428 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1429 | struct intel_crtc *intel_crtc = | |
1430 | to_intel_crtc(encoder->base.crtc); | |
1431 | enum dpio_channel ch = vlv_dport_to_channel(dport); | |
1432 | enum pipe pipe = intel_crtc->pipe; | |
1433 | u32 val; | |
1434 | ||
1435 | mutex_lock(&dev_priv->dpio_lock); | |
1436 | ||
1437 | /* Propagate soft reset to data lane reset */ | |
97fd4d5c | 1438 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch)); |
d2152b25 | 1439 | val |= CHV_PCS_REQ_SOFTRESET_EN; |
97fd4d5c | 1440 | vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val); |
d2152b25 | 1441 | |
97fd4d5c VS |
1442 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch)); |
1443 | val |= CHV_PCS_REQ_SOFTRESET_EN; | |
1444 | vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val); | |
1445 | ||
1446 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch)); | |
1447 | val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET); | |
1448 | vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val); | |
1449 | ||
1450 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch)); | |
580d3811 | 1451 | val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET); |
97fd4d5c | 1452 | vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val); |
580d3811 VS |
1453 | |
1454 | mutex_unlock(&dev_priv->dpio_lock); | |
1455 | } | |
1456 | ||
e4a1d846 CML |
1457 | static void chv_hdmi_pre_enable(struct intel_encoder *encoder) |
1458 | { | |
1459 | struct intel_digital_port *dport = enc_to_dig_port(&encoder->base); | |
1460 | struct drm_device *dev = encoder->base.dev; | |
1461 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1462 | struct intel_crtc *intel_crtc = | |
1463 | to_intel_crtc(encoder->base.crtc); | |
1464 | enum dpio_channel ch = vlv_dport_to_channel(dport); | |
1465 | int pipe = intel_crtc->pipe; | |
1466 | int data, i; | |
1467 | u32 val; | |
1468 | ||
e4a1d846 | 1469 | mutex_lock(&dev_priv->dpio_lock); |
949c1d43 | 1470 | |
570e2a74 VS |
1471 | /* allow hardware to manage TX FIFO reset source */ |
1472 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch)); | |
1473 | val &= ~DPIO_LANEDESKEW_STRAP_OVRD; | |
1474 | vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val); | |
1475 | ||
1476 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch)); | |
1477 | val &= ~DPIO_LANEDESKEW_STRAP_OVRD; | |
1478 | vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val); | |
1479 | ||
949c1d43 | 1480 | /* Deassert soft data lane reset*/ |
97fd4d5c | 1481 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch)); |
d2152b25 | 1482 | val |= CHV_PCS_REQ_SOFTRESET_EN; |
97fd4d5c VS |
1483 | vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val); |
1484 | ||
1485 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch)); | |
1486 | val |= CHV_PCS_REQ_SOFTRESET_EN; | |
1487 | vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val); | |
1488 | ||
1489 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch)); | |
1490 | val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET); | |
1491 | vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val); | |
d2152b25 | 1492 | |
97fd4d5c | 1493 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch)); |
949c1d43 | 1494 | val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET); |
97fd4d5c | 1495 | vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val); |
949c1d43 VS |
1496 | |
1497 | /* Program Tx latency optimal setting */ | |
e4a1d846 CML |
1498 | for (i = 0; i < 4; i++) { |
1499 | /* Set the latency optimal bit */ | |
1500 | data = (i == 1) ? 0x0 : 0x6; | |
1501 | vlv_dpio_write(dev_priv, pipe, CHV_TX_DW11(ch, i), | |
1502 | data << DPIO_FRC_LATENCY_SHFIT); | |
1503 | ||
1504 | /* Set the upar bit */ | |
1505 | data = (i == 1) ? 0x0 : 0x1; | |
1506 | vlv_dpio_write(dev_priv, pipe, CHV_TX_DW14(ch, i), | |
1507 | data << DPIO_UPAR_SHIFT); | |
1508 | } | |
1509 | ||
1510 | /* Data lane stagger programming */ | |
1511 | /* FIXME: Fix up value only after power analysis */ | |
1512 | ||
1513 | /* Clear calc init */ | |
1966e59e VS |
1514 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch)); |
1515 | val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3); | |
a02ef3c7 VS |
1516 | val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK); |
1517 | val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5; | |
1966e59e VS |
1518 | vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val); |
1519 | ||
1520 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch)); | |
1521 | val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3); | |
a02ef3c7 VS |
1522 | val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK); |
1523 | val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5; | |
1966e59e | 1524 | vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val); |
e4a1d846 | 1525 | |
a02ef3c7 VS |
1526 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW9(ch)); |
1527 | val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK); | |
1528 | val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000; | |
1529 | vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW9(ch), val); | |
1530 | ||
1531 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW9(ch)); | |
1532 | val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK); | |
1533 | val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000; | |
1534 | vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW9(ch), val); | |
1535 | ||
e4a1d846 CML |
1536 | /* FIXME: Program the support xxx V-dB */ |
1537 | /* Use 800mV-0dB */ | |
f72df8db VS |
1538 | for (i = 0; i < 4; i++) { |
1539 | val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW4(ch, i)); | |
1540 | val &= ~DPIO_SWING_DEEMPH9P5_MASK; | |
1541 | val |= 128 << DPIO_SWING_DEEMPH9P5_SHIFT; | |
1542 | vlv_dpio_write(dev_priv, pipe, CHV_TX_DW4(ch, i), val); | |
1543 | } | |
e4a1d846 | 1544 | |
f72df8db VS |
1545 | for (i = 0; i < 4; i++) { |
1546 | val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i)); | |
1fb44505 VS |
1547 | val &= ~DPIO_SWING_MARGIN000_MASK; |
1548 | val |= 102 << DPIO_SWING_MARGIN000_SHIFT; | |
f72df8db VS |
1549 | vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val); |
1550 | } | |
e4a1d846 CML |
1551 | |
1552 | /* Disable unique transition scale */ | |
f72df8db VS |
1553 | for (i = 0; i < 4; i++) { |
1554 | val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i)); | |
1555 | val &= ~DPIO_TX_UNIQ_TRANS_SCALE_EN; | |
1556 | vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val); | |
1557 | } | |
e4a1d846 CML |
1558 | |
1559 | /* Additional steps for 1200mV-0dB */ | |
1560 | #if 0 | |
1561 | val = vlv_dpio_read(dev_priv, pipe, VLV_TX_DW3(ch)); | |
1562 | if (ch) | |
1563 | val |= DPIO_TX_UNIQ_TRANS_SCALE_CH1; | |
1564 | else | |
1565 | val |= DPIO_TX_UNIQ_TRANS_SCALE_CH0; | |
1566 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(ch), val); | |
1567 | ||
1568 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(ch), | |
1569 | vlv_dpio_read(dev_priv, pipe, VLV_TX_DW2(ch)) | | |
1570 | (0x9a << DPIO_UNIQ_TRANS_SCALE_SHIFT)); | |
1571 | #endif | |
1572 | /* Start swing calculation */ | |
1966e59e VS |
1573 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch)); |
1574 | val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3; | |
1575 | vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val); | |
1576 | ||
1577 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch)); | |
1578 | val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3; | |
1579 | vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val); | |
e4a1d846 CML |
1580 | |
1581 | /* LRC Bypass */ | |
1582 | val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW30); | |
1583 | val |= DPIO_LRC_BYPASS; | |
1584 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW30, val); | |
1585 | ||
1586 | mutex_unlock(&dev_priv->dpio_lock); | |
1587 | ||
1588 | intel_enable_hdmi(encoder); | |
1589 | ||
1590 | vlv_wait_port_ready(dev_priv, dport); | |
1591 | } | |
1592 | ||
7d57382e EA |
1593 | static void intel_hdmi_destroy(struct drm_connector *connector) |
1594 | { | |
10e972d3 | 1595 | kfree(to_intel_connector(connector)->detect_edid); |
7d57382e | 1596 | drm_connector_cleanup(connector); |
674e2d08 | 1597 | kfree(connector); |
7d57382e EA |
1598 | } |
1599 | ||
7d57382e | 1600 | static const struct drm_connector_funcs intel_hdmi_connector_funcs = { |
5ab432ef | 1601 | .dpms = intel_connector_dpms, |
7d57382e | 1602 | .detect = intel_hdmi_detect, |
953ece69 | 1603 | .force = intel_hdmi_force, |
7d57382e | 1604 | .fill_modes = drm_helper_probe_single_connector_modes, |
55b7d6e8 | 1605 | .set_property = intel_hdmi_set_property, |
7d57382e EA |
1606 | .destroy = intel_hdmi_destroy, |
1607 | }; | |
1608 | ||
1609 | static const struct drm_connector_helper_funcs intel_hdmi_connector_helper_funcs = { | |
1610 | .get_modes = intel_hdmi_get_modes, | |
1611 | .mode_valid = intel_hdmi_mode_valid, | |
df0e9248 | 1612 | .best_encoder = intel_best_encoder, |
7d57382e EA |
1613 | }; |
1614 | ||
7d57382e | 1615 | static const struct drm_encoder_funcs intel_hdmi_enc_funcs = { |
ea5b213a | 1616 | .destroy = intel_encoder_destroy, |
7d57382e EA |
1617 | }; |
1618 | ||
94a11ddc VK |
1619 | static void |
1620 | intel_attach_aspect_ratio_property(struct drm_connector *connector) | |
1621 | { | |
1622 | if (!drm_mode_create_aspect_ratio_property(connector->dev)) | |
1623 | drm_object_attach_property(&connector->base, | |
1624 | connector->dev->mode_config.aspect_ratio_property, | |
1625 | DRM_MODE_PICTURE_ASPECT_NONE); | |
1626 | } | |
1627 | ||
55b7d6e8 CW |
1628 | static void |
1629 | intel_hdmi_add_properties(struct intel_hdmi *intel_hdmi, struct drm_connector *connector) | |
1630 | { | |
3f43c48d | 1631 | intel_attach_force_audio_property(connector); |
e953fd7b | 1632 | intel_attach_broadcast_rgb_property(connector); |
55bc60db | 1633 | intel_hdmi->color_range_auto = true; |
94a11ddc VK |
1634 | intel_attach_aspect_ratio_property(connector); |
1635 | intel_hdmi->aspect_ratio = HDMI_PICTURE_ASPECT_NONE; | |
55b7d6e8 CW |
1636 | } |
1637 | ||
00c09d70 PZ |
1638 | void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port, |
1639 | struct intel_connector *intel_connector) | |
7d57382e | 1640 | { |
b9cb234c PZ |
1641 | struct drm_connector *connector = &intel_connector->base; |
1642 | struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi; | |
1643 | struct intel_encoder *intel_encoder = &intel_dig_port->base; | |
1644 | struct drm_device *dev = intel_encoder->base.dev; | |
7d57382e | 1645 | struct drm_i915_private *dev_priv = dev->dev_private; |
174edf1f | 1646 | enum port port = intel_dig_port->port; |
373a3cf7 | 1647 | |
7d57382e | 1648 | drm_connector_init(dev, connector, &intel_hdmi_connector_funcs, |
8d91104a | 1649 | DRM_MODE_CONNECTOR_HDMIA); |
7d57382e EA |
1650 | drm_connector_helper_add(connector, &intel_hdmi_connector_helper_funcs); |
1651 | ||
c3febcc4 | 1652 | connector->interlace_allowed = 1; |
7d57382e | 1653 | connector->doublescan_allowed = 0; |
573e74ad | 1654 | connector->stereo_allowed = 1; |
66a9278e | 1655 | |
08d644ad DV |
1656 | switch (port) { |
1657 | case PORT_B: | |
f899fc64 | 1658 | intel_hdmi->ddc_bus = GMBUS_PORT_DPB; |
1d843f9d | 1659 | intel_encoder->hpd_pin = HPD_PORT_B; |
08d644ad DV |
1660 | break; |
1661 | case PORT_C: | |
7ceae0a5 | 1662 | intel_hdmi->ddc_bus = GMBUS_PORT_DPC; |
1d843f9d | 1663 | intel_encoder->hpd_pin = HPD_PORT_C; |
08d644ad DV |
1664 | break; |
1665 | case PORT_D: | |
c0c35329 VS |
1666 | if (IS_CHERRYVIEW(dev)) |
1667 | intel_hdmi->ddc_bus = GMBUS_PORT_DPD_CHV; | |
1668 | else | |
1669 | intel_hdmi->ddc_bus = GMBUS_PORT_DPD; | |
1d843f9d | 1670 | intel_encoder->hpd_pin = HPD_PORT_D; |
08d644ad DV |
1671 | break; |
1672 | case PORT_A: | |
1d843f9d | 1673 | intel_encoder->hpd_pin = HPD_PORT_A; |
08d644ad DV |
1674 | /* Internal port only for eDP. */ |
1675 | default: | |
6e4c1677 | 1676 | BUG(); |
f8aed700 | 1677 | } |
7d57382e | 1678 | |
7637bfdb | 1679 | if (IS_VALLEYVIEW(dev)) { |
90b107c8 | 1680 | intel_hdmi->write_infoframe = vlv_write_infoframe; |
687f4d06 | 1681 | intel_hdmi->set_infoframes = vlv_set_infoframes; |
e43823ec | 1682 | intel_hdmi->infoframe_enabled = vlv_infoframe_enabled; |
b98856a8 | 1683 | } else if (IS_G4X(dev)) { |
7637bfdb JB |
1684 | intel_hdmi->write_infoframe = g4x_write_infoframe; |
1685 | intel_hdmi->set_infoframes = g4x_set_infoframes; | |
e43823ec | 1686 | intel_hdmi->infoframe_enabled = g4x_infoframe_enabled; |
22b8bf17 | 1687 | } else if (HAS_DDI(dev)) { |
8c5f5f7c | 1688 | intel_hdmi->write_infoframe = hsw_write_infoframe; |
687f4d06 | 1689 | intel_hdmi->set_infoframes = hsw_set_infoframes; |
e43823ec | 1690 | intel_hdmi->infoframe_enabled = hsw_infoframe_enabled; |
fdf1250a PZ |
1691 | } else if (HAS_PCH_IBX(dev)) { |
1692 | intel_hdmi->write_infoframe = ibx_write_infoframe; | |
687f4d06 | 1693 | intel_hdmi->set_infoframes = ibx_set_infoframes; |
e43823ec | 1694 | intel_hdmi->infoframe_enabled = ibx_infoframe_enabled; |
fdf1250a PZ |
1695 | } else { |
1696 | intel_hdmi->write_infoframe = cpt_write_infoframe; | |
687f4d06 | 1697 | intel_hdmi->set_infoframes = cpt_set_infoframes; |
e43823ec | 1698 | intel_hdmi->infoframe_enabled = cpt_infoframe_enabled; |
64a8fc01 | 1699 | } |
45187ace | 1700 | |
affa9354 | 1701 | if (HAS_DDI(dev)) |
bcbc889b PZ |
1702 | intel_connector->get_hw_state = intel_ddi_connector_get_hw_state; |
1703 | else | |
1704 | intel_connector->get_hw_state = intel_connector_get_hw_state; | |
4932e2c3 | 1705 | intel_connector->unregister = intel_connector_unregister; |
b9cb234c PZ |
1706 | |
1707 | intel_hdmi_add_properties(intel_hdmi, connector); | |
1708 | ||
1709 | intel_connector_attach_encoder(intel_connector, intel_encoder); | |
34ea3d38 | 1710 | drm_connector_register(connector); |
b9cb234c PZ |
1711 | |
1712 | /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written | |
1713 | * 0xd. Failure to do so will result in spurious interrupts being | |
1714 | * generated on the port when a cable is not attached. | |
1715 | */ | |
1716 | if (IS_G4X(dev) && !IS_GM45(dev)) { | |
1717 | u32 temp = I915_READ(PEG_BAND_GAP_DATA); | |
1718 | I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd); | |
1719 | } | |
1720 | } | |
1721 | ||
b242b7f7 | 1722 | void intel_hdmi_init(struct drm_device *dev, int hdmi_reg, enum port port) |
b9cb234c PZ |
1723 | { |
1724 | struct intel_digital_port *intel_dig_port; | |
1725 | struct intel_encoder *intel_encoder; | |
b9cb234c PZ |
1726 | struct intel_connector *intel_connector; |
1727 | ||
b14c5679 | 1728 | intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL); |
b9cb234c PZ |
1729 | if (!intel_dig_port) |
1730 | return; | |
1731 | ||
b14c5679 | 1732 | intel_connector = kzalloc(sizeof(*intel_connector), GFP_KERNEL); |
b9cb234c PZ |
1733 | if (!intel_connector) { |
1734 | kfree(intel_dig_port); | |
1735 | return; | |
1736 | } | |
1737 | ||
1738 | intel_encoder = &intel_dig_port->base; | |
b9cb234c PZ |
1739 | |
1740 | drm_encoder_init(dev, &intel_encoder->base, &intel_hdmi_enc_funcs, | |
1741 | DRM_MODE_ENCODER_TMDS); | |
00c09d70 | 1742 | |
5bfe2ac0 | 1743 | intel_encoder->compute_config = intel_hdmi_compute_config; |
00c09d70 PZ |
1744 | intel_encoder->disable = intel_disable_hdmi; |
1745 | intel_encoder->get_hw_state = intel_hdmi_get_hw_state; | |
045ac3b5 | 1746 | intel_encoder->get_config = intel_hdmi_get_config; |
e4a1d846 | 1747 | if (IS_CHERRYVIEW(dev)) { |
9197c88b | 1748 | intel_encoder->pre_pll_enable = chv_hdmi_pre_pll_enable; |
e4a1d846 CML |
1749 | intel_encoder->pre_enable = chv_hdmi_pre_enable; |
1750 | intel_encoder->enable = vlv_enable_hdmi; | |
580d3811 | 1751 | intel_encoder->post_disable = chv_hdmi_post_disable; |
e4a1d846 | 1752 | } else if (IS_VALLEYVIEW(dev)) { |
9514ac6e CML |
1753 | intel_encoder->pre_pll_enable = vlv_hdmi_pre_pll_enable; |
1754 | intel_encoder->pre_enable = vlv_hdmi_pre_enable; | |
b76cf76b | 1755 | intel_encoder->enable = vlv_enable_hdmi; |
9514ac6e | 1756 | intel_encoder->post_disable = vlv_hdmi_post_disable; |
b76cf76b | 1757 | } else { |
13732ba7 | 1758 | intel_encoder->pre_enable = intel_hdmi_pre_enable; |
b76cf76b | 1759 | intel_encoder->enable = intel_enable_hdmi; |
89b667f8 | 1760 | } |
5ab432ef | 1761 | |
b9cb234c | 1762 | intel_encoder->type = INTEL_OUTPUT_HDMI; |
882ec384 VS |
1763 | if (IS_CHERRYVIEW(dev)) { |
1764 | if (port == PORT_D) | |
1765 | intel_encoder->crtc_mask = 1 << 2; | |
1766 | else | |
1767 | intel_encoder->crtc_mask = (1 << 0) | (1 << 1); | |
1768 | } else { | |
1769 | intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2); | |
1770 | } | |
301ea74a | 1771 | intel_encoder->cloneable = 1 << INTEL_OUTPUT_ANALOG; |
c6f1495d VS |
1772 | /* |
1773 | * BSpec is unclear about HDMI+HDMI cloning on g4x, but it seems | |
1774 | * to work on real hardware. And since g4x can send infoframes to | |
1775 | * only one port anyway, nothing is lost by allowing it. | |
1776 | */ | |
1777 | if (IS_G4X(dev)) | |
1778 | intel_encoder->cloneable |= 1 << INTEL_OUTPUT_HDMI; | |
7d57382e | 1779 | |
174edf1f | 1780 | intel_dig_port->port = port; |
b242b7f7 | 1781 | intel_dig_port->hdmi.hdmi_reg = hdmi_reg; |
b9cb234c | 1782 | intel_dig_port->dp.output_reg = 0; |
55b7d6e8 | 1783 | |
b9cb234c | 1784 | intel_hdmi_init_connector(intel_dig_port, intel_connector); |
7d57382e | 1785 | } |