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7d57382e EA |
1 | /* |
2 | * Copyright 2006 Dave Airlie <airlied@linux.ie> | |
3 | * Copyright © 2006-2009 Intel Corporation | |
4 | * | |
5 | * Permission is hereby granted, free of charge, to any person obtaining a | |
6 | * copy of this software and associated documentation files (the "Software"), | |
7 | * to deal in the Software without restriction, including without limitation | |
8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
9 | * and/or sell copies of the Software, and to permit persons to whom the | |
10 | * Software is furnished to do so, subject to the following conditions: | |
11 | * | |
12 | * The above copyright notice and this permission notice (including the next | |
13 | * paragraph) shall be included in all copies or substantial portions of the | |
14 | * Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
21 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
22 | * DEALINGS IN THE SOFTWARE. | |
23 | * | |
24 | * Authors: | |
25 | * Eric Anholt <eric@anholt.net> | |
26 | * Jesse Barnes <jesse.barnes@intel.com> | |
27 | */ | |
28 | ||
29 | #include <linux/i2c.h> | |
5a0e3ad6 | 30 | #include <linux/slab.h> |
7d57382e | 31 | #include <linux/delay.h> |
178f736a | 32 | #include <linux/hdmi.h> |
760285e7 | 33 | #include <drm/drmP.h> |
c6f95f27 | 34 | #include <drm/drm_atomic_helper.h> |
760285e7 DH |
35 | #include <drm/drm_crtc.h> |
36 | #include <drm/drm_edid.h> | |
7d57382e | 37 | #include "intel_drv.h" |
760285e7 | 38 | #include <drm/i915_drm.h> |
46d196ec | 39 | #include <drm/intel_lpe_audio.h> |
7d57382e EA |
40 | #include "i915_drv.h" |
41 | ||
30add22d PZ |
42 | static struct drm_device *intel_hdmi_to_dev(struct intel_hdmi *intel_hdmi) |
43 | { | |
da63a9f2 | 44 | return hdmi_to_dig_port(intel_hdmi)->base.base.dev; |
30add22d PZ |
45 | } |
46 | ||
afba0188 DV |
47 | static void |
48 | assert_hdmi_port_disabled(struct intel_hdmi *intel_hdmi) | |
49 | { | |
30add22d | 50 | struct drm_device *dev = intel_hdmi_to_dev(intel_hdmi); |
fac5e23e | 51 | struct drm_i915_private *dev_priv = to_i915(dev); |
afba0188 DV |
52 | uint32_t enabled_bits; |
53 | ||
4f8036a2 | 54 | enabled_bits = HAS_DDI(dev_priv) ? DDI_BUF_CTL_ENABLE : SDVO_ENABLE; |
afba0188 | 55 | |
b242b7f7 | 56 | WARN(I915_READ(intel_hdmi->hdmi_reg) & enabled_bits, |
afba0188 DV |
57 | "HDMI port enabled, expecting disabled\n"); |
58 | } | |
59 | ||
f5bbfca3 | 60 | struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder) |
ea5b213a | 61 | { |
da63a9f2 PZ |
62 | struct intel_digital_port *intel_dig_port = |
63 | container_of(encoder, struct intel_digital_port, base.base); | |
64 | return &intel_dig_port->hdmi; | |
ea5b213a CW |
65 | } |
66 | ||
df0e9248 CW |
67 | static struct intel_hdmi *intel_attached_hdmi(struct drm_connector *connector) |
68 | { | |
da63a9f2 | 69 | return enc_to_intel_hdmi(&intel_attached_encoder(connector)->base); |
df0e9248 CW |
70 | } |
71 | ||
178f736a | 72 | static u32 g4x_infoframe_index(enum hdmi_infoframe_type type) |
3c17fe4b | 73 | { |
178f736a DL |
74 | switch (type) { |
75 | case HDMI_INFOFRAME_TYPE_AVI: | |
ed517fbb | 76 | return VIDEO_DIP_SELECT_AVI; |
178f736a | 77 | case HDMI_INFOFRAME_TYPE_SPD: |
ed517fbb | 78 | return VIDEO_DIP_SELECT_SPD; |
c8bb75af LD |
79 | case HDMI_INFOFRAME_TYPE_VENDOR: |
80 | return VIDEO_DIP_SELECT_VENDOR; | |
45187ace | 81 | default: |
ffc85dab | 82 | MISSING_CASE(type); |
ed517fbb | 83 | return 0; |
45187ace | 84 | } |
45187ace JB |
85 | } |
86 | ||
178f736a | 87 | static u32 g4x_infoframe_enable(enum hdmi_infoframe_type type) |
45187ace | 88 | { |
178f736a DL |
89 | switch (type) { |
90 | case HDMI_INFOFRAME_TYPE_AVI: | |
ed517fbb | 91 | return VIDEO_DIP_ENABLE_AVI; |
178f736a | 92 | case HDMI_INFOFRAME_TYPE_SPD: |
ed517fbb | 93 | return VIDEO_DIP_ENABLE_SPD; |
c8bb75af LD |
94 | case HDMI_INFOFRAME_TYPE_VENDOR: |
95 | return VIDEO_DIP_ENABLE_VENDOR; | |
fa193ff7 | 96 | default: |
ffc85dab | 97 | MISSING_CASE(type); |
ed517fbb | 98 | return 0; |
fa193ff7 | 99 | } |
fa193ff7 PZ |
100 | } |
101 | ||
178f736a | 102 | static u32 hsw_infoframe_enable(enum hdmi_infoframe_type type) |
2da8af54 | 103 | { |
178f736a DL |
104 | switch (type) { |
105 | case HDMI_INFOFRAME_TYPE_AVI: | |
2da8af54 | 106 | return VIDEO_DIP_ENABLE_AVI_HSW; |
178f736a | 107 | case HDMI_INFOFRAME_TYPE_SPD: |
2da8af54 | 108 | return VIDEO_DIP_ENABLE_SPD_HSW; |
c8bb75af LD |
109 | case HDMI_INFOFRAME_TYPE_VENDOR: |
110 | return VIDEO_DIP_ENABLE_VS_HSW; | |
2da8af54 | 111 | default: |
ffc85dab | 112 | MISSING_CASE(type); |
2da8af54 PZ |
113 | return 0; |
114 | } | |
115 | } | |
116 | ||
f0f59a00 VS |
117 | static i915_reg_t |
118 | hsw_dip_data_reg(struct drm_i915_private *dev_priv, | |
119 | enum transcoder cpu_transcoder, | |
120 | enum hdmi_infoframe_type type, | |
121 | int i) | |
2da8af54 | 122 | { |
178f736a DL |
123 | switch (type) { |
124 | case HDMI_INFOFRAME_TYPE_AVI: | |
436c6d4a | 125 | return HSW_TVIDEO_DIP_AVI_DATA(cpu_transcoder, i); |
178f736a | 126 | case HDMI_INFOFRAME_TYPE_SPD: |
436c6d4a | 127 | return HSW_TVIDEO_DIP_SPD_DATA(cpu_transcoder, i); |
c8bb75af | 128 | case HDMI_INFOFRAME_TYPE_VENDOR: |
436c6d4a | 129 | return HSW_TVIDEO_DIP_VS_DATA(cpu_transcoder, i); |
2da8af54 | 130 | default: |
ffc85dab | 131 | MISSING_CASE(type); |
f0f59a00 | 132 | return INVALID_MMIO_REG; |
2da8af54 PZ |
133 | } |
134 | } | |
135 | ||
a3da1df7 | 136 | static void g4x_write_infoframe(struct drm_encoder *encoder, |
ac240288 | 137 | const struct intel_crtc_state *crtc_state, |
178f736a | 138 | enum hdmi_infoframe_type type, |
fff63867 | 139 | const void *frame, ssize_t len) |
45187ace | 140 | { |
fff63867 | 141 | const uint32_t *data = frame; |
3c17fe4b | 142 | struct drm_device *dev = encoder->dev; |
fac5e23e | 143 | struct drm_i915_private *dev_priv = to_i915(dev); |
22509ec8 | 144 | u32 val = I915_READ(VIDEO_DIP_CTL); |
178f736a | 145 | int i; |
3c17fe4b | 146 | |
822974ae PZ |
147 | WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n"); |
148 | ||
1d4f85ac | 149 | val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ |
178f736a | 150 | val |= g4x_infoframe_index(type); |
22509ec8 | 151 | |
178f736a | 152 | val &= ~g4x_infoframe_enable(type); |
45187ace | 153 | |
22509ec8 | 154 | I915_WRITE(VIDEO_DIP_CTL, val); |
3c17fe4b | 155 | |
9d9740f0 | 156 | mmiowb(); |
45187ace | 157 | for (i = 0; i < len; i += 4) { |
3c17fe4b DH |
158 | I915_WRITE(VIDEO_DIP_DATA, *data); |
159 | data++; | |
160 | } | |
adf00b26 PZ |
161 | /* Write every possible data byte to force correct ECC calculation. */ |
162 | for (; i < VIDEO_DIP_DATA_SIZE; i += 4) | |
163 | I915_WRITE(VIDEO_DIP_DATA, 0); | |
9d9740f0 | 164 | mmiowb(); |
3c17fe4b | 165 | |
178f736a | 166 | val |= g4x_infoframe_enable(type); |
60c5ea2d | 167 | val &= ~VIDEO_DIP_FREQ_MASK; |
4b24c933 | 168 | val |= VIDEO_DIP_FREQ_VSYNC; |
45187ace | 169 | |
22509ec8 | 170 | I915_WRITE(VIDEO_DIP_CTL, val); |
9d9740f0 | 171 | POSTING_READ(VIDEO_DIP_CTL); |
3c17fe4b DH |
172 | } |
173 | ||
cda0aaaf VS |
174 | static bool g4x_infoframe_enabled(struct drm_encoder *encoder, |
175 | const struct intel_crtc_state *pipe_config) | |
e43823ec | 176 | { |
cda0aaaf | 177 | struct drm_i915_private *dev_priv = to_i915(encoder->dev); |
89a35ecd | 178 | struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); |
e43823ec JB |
179 | u32 val = I915_READ(VIDEO_DIP_CTL); |
180 | ||
ec1dc603 VS |
181 | if ((val & VIDEO_DIP_ENABLE) == 0) |
182 | return false; | |
89a35ecd | 183 | |
ec1dc603 VS |
184 | if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(intel_dig_port->port)) |
185 | return false; | |
186 | ||
187 | return val & (VIDEO_DIP_ENABLE_AVI | | |
188 | VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD); | |
e43823ec JB |
189 | } |
190 | ||
fdf1250a | 191 | static void ibx_write_infoframe(struct drm_encoder *encoder, |
ac240288 | 192 | const struct intel_crtc_state *crtc_state, |
178f736a | 193 | enum hdmi_infoframe_type type, |
fff63867 | 194 | const void *frame, ssize_t len) |
fdf1250a | 195 | { |
fff63867 | 196 | const uint32_t *data = frame; |
fdf1250a | 197 | struct drm_device *dev = encoder->dev; |
fac5e23e | 198 | struct drm_i915_private *dev_priv = to_i915(dev); |
ac240288 | 199 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc); |
f0f59a00 | 200 | i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe); |
fdf1250a | 201 | u32 val = I915_READ(reg); |
f0f59a00 | 202 | int i; |
fdf1250a | 203 | |
822974ae PZ |
204 | WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n"); |
205 | ||
fdf1250a | 206 | val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ |
178f736a | 207 | val |= g4x_infoframe_index(type); |
fdf1250a | 208 | |
178f736a | 209 | val &= ~g4x_infoframe_enable(type); |
fdf1250a PZ |
210 | |
211 | I915_WRITE(reg, val); | |
212 | ||
9d9740f0 | 213 | mmiowb(); |
fdf1250a PZ |
214 | for (i = 0; i < len; i += 4) { |
215 | I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data); | |
216 | data++; | |
217 | } | |
adf00b26 PZ |
218 | /* Write every possible data byte to force correct ECC calculation. */ |
219 | for (; i < VIDEO_DIP_DATA_SIZE; i += 4) | |
220 | I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0); | |
9d9740f0 | 221 | mmiowb(); |
fdf1250a | 222 | |
178f736a | 223 | val |= g4x_infoframe_enable(type); |
fdf1250a | 224 | val &= ~VIDEO_DIP_FREQ_MASK; |
4b24c933 | 225 | val |= VIDEO_DIP_FREQ_VSYNC; |
fdf1250a PZ |
226 | |
227 | I915_WRITE(reg, val); | |
9d9740f0 | 228 | POSTING_READ(reg); |
fdf1250a PZ |
229 | } |
230 | ||
cda0aaaf VS |
231 | static bool ibx_infoframe_enabled(struct drm_encoder *encoder, |
232 | const struct intel_crtc_state *pipe_config) | |
e43823ec | 233 | { |
cda0aaaf | 234 | struct drm_i915_private *dev_priv = to_i915(encoder->dev); |
052f62f7 | 235 | struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); |
cda0aaaf VS |
236 | enum pipe pipe = to_intel_crtc(pipe_config->base.crtc)->pipe; |
237 | i915_reg_t reg = TVIDEO_DIP_CTL(pipe); | |
e43823ec JB |
238 | u32 val = I915_READ(reg); |
239 | ||
ec1dc603 VS |
240 | if ((val & VIDEO_DIP_ENABLE) == 0) |
241 | return false; | |
242 | ||
243 | if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(intel_dig_port->port)) | |
244 | return false; | |
052f62f7 | 245 | |
ec1dc603 VS |
246 | return val & (VIDEO_DIP_ENABLE_AVI | |
247 | VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | | |
248 | VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); | |
e43823ec JB |
249 | } |
250 | ||
fdf1250a | 251 | static void cpt_write_infoframe(struct drm_encoder *encoder, |
ac240288 | 252 | const struct intel_crtc_state *crtc_state, |
178f736a | 253 | enum hdmi_infoframe_type type, |
fff63867 | 254 | const void *frame, ssize_t len) |
b055c8f3 | 255 | { |
fff63867 | 256 | const uint32_t *data = frame; |
b055c8f3 | 257 | struct drm_device *dev = encoder->dev; |
fac5e23e | 258 | struct drm_i915_private *dev_priv = to_i915(dev); |
ac240288 | 259 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc); |
f0f59a00 | 260 | i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe); |
22509ec8 | 261 | u32 val = I915_READ(reg); |
f0f59a00 | 262 | int i; |
b055c8f3 | 263 | |
822974ae PZ |
264 | WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n"); |
265 | ||
64a8fc01 | 266 | val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ |
178f736a | 267 | val |= g4x_infoframe_index(type); |
45187ace | 268 | |
ecb97851 PZ |
269 | /* The DIP control register spec says that we need to update the AVI |
270 | * infoframe without clearing its enable bit */ | |
178f736a DL |
271 | if (type != HDMI_INFOFRAME_TYPE_AVI) |
272 | val &= ~g4x_infoframe_enable(type); | |
ecb97851 | 273 | |
22509ec8 | 274 | I915_WRITE(reg, val); |
45187ace | 275 | |
9d9740f0 | 276 | mmiowb(); |
45187ace | 277 | for (i = 0; i < len; i += 4) { |
b055c8f3 JB |
278 | I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data); |
279 | data++; | |
280 | } | |
adf00b26 PZ |
281 | /* Write every possible data byte to force correct ECC calculation. */ |
282 | for (; i < VIDEO_DIP_DATA_SIZE; i += 4) | |
283 | I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0); | |
9d9740f0 | 284 | mmiowb(); |
b055c8f3 | 285 | |
178f736a | 286 | val |= g4x_infoframe_enable(type); |
60c5ea2d | 287 | val &= ~VIDEO_DIP_FREQ_MASK; |
4b24c933 | 288 | val |= VIDEO_DIP_FREQ_VSYNC; |
45187ace | 289 | |
22509ec8 | 290 | I915_WRITE(reg, val); |
9d9740f0 | 291 | POSTING_READ(reg); |
45187ace | 292 | } |
90b107c8 | 293 | |
cda0aaaf VS |
294 | static bool cpt_infoframe_enabled(struct drm_encoder *encoder, |
295 | const struct intel_crtc_state *pipe_config) | |
e43823ec | 296 | { |
cda0aaaf VS |
297 | struct drm_i915_private *dev_priv = to_i915(encoder->dev); |
298 | enum pipe pipe = to_intel_crtc(pipe_config->base.crtc)->pipe; | |
299 | u32 val = I915_READ(TVIDEO_DIP_CTL(pipe)); | |
e43823ec | 300 | |
ec1dc603 VS |
301 | if ((val & VIDEO_DIP_ENABLE) == 0) |
302 | return false; | |
303 | ||
304 | return val & (VIDEO_DIP_ENABLE_AVI | | |
305 | VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | | |
306 | VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); | |
e43823ec JB |
307 | } |
308 | ||
90b107c8 | 309 | static void vlv_write_infoframe(struct drm_encoder *encoder, |
ac240288 | 310 | const struct intel_crtc_state *crtc_state, |
178f736a | 311 | enum hdmi_infoframe_type type, |
fff63867 | 312 | const void *frame, ssize_t len) |
90b107c8 | 313 | { |
fff63867 | 314 | const uint32_t *data = frame; |
90b107c8 | 315 | struct drm_device *dev = encoder->dev; |
fac5e23e | 316 | struct drm_i915_private *dev_priv = to_i915(dev); |
ac240288 | 317 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc); |
f0f59a00 | 318 | i915_reg_t reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe); |
22509ec8 | 319 | u32 val = I915_READ(reg); |
f0f59a00 | 320 | int i; |
90b107c8 | 321 | |
822974ae PZ |
322 | WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n"); |
323 | ||
90b107c8 | 324 | val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ |
178f736a | 325 | val |= g4x_infoframe_index(type); |
22509ec8 | 326 | |
178f736a | 327 | val &= ~g4x_infoframe_enable(type); |
90b107c8 | 328 | |
22509ec8 | 329 | I915_WRITE(reg, val); |
90b107c8 | 330 | |
9d9740f0 | 331 | mmiowb(); |
90b107c8 SK |
332 | for (i = 0; i < len; i += 4) { |
333 | I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), *data); | |
334 | data++; | |
335 | } | |
adf00b26 PZ |
336 | /* Write every possible data byte to force correct ECC calculation. */ |
337 | for (; i < VIDEO_DIP_DATA_SIZE; i += 4) | |
338 | I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), 0); | |
9d9740f0 | 339 | mmiowb(); |
90b107c8 | 340 | |
178f736a | 341 | val |= g4x_infoframe_enable(type); |
60c5ea2d | 342 | val &= ~VIDEO_DIP_FREQ_MASK; |
4b24c933 | 343 | val |= VIDEO_DIP_FREQ_VSYNC; |
90b107c8 | 344 | |
22509ec8 | 345 | I915_WRITE(reg, val); |
9d9740f0 | 346 | POSTING_READ(reg); |
90b107c8 SK |
347 | } |
348 | ||
cda0aaaf VS |
349 | static bool vlv_infoframe_enabled(struct drm_encoder *encoder, |
350 | const struct intel_crtc_state *pipe_config) | |
e43823ec | 351 | { |
cda0aaaf | 352 | struct drm_i915_private *dev_priv = to_i915(encoder->dev); |
535afa2e | 353 | struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); |
cda0aaaf VS |
354 | enum pipe pipe = to_intel_crtc(pipe_config->base.crtc)->pipe; |
355 | u32 val = I915_READ(VLV_TVIDEO_DIP_CTL(pipe)); | |
e43823ec | 356 | |
ec1dc603 VS |
357 | if ((val & VIDEO_DIP_ENABLE) == 0) |
358 | return false; | |
359 | ||
360 | if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(intel_dig_port->port)) | |
361 | return false; | |
535afa2e | 362 | |
ec1dc603 VS |
363 | return val & (VIDEO_DIP_ENABLE_AVI | |
364 | VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | | |
365 | VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); | |
e43823ec JB |
366 | } |
367 | ||
8c5f5f7c | 368 | static void hsw_write_infoframe(struct drm_encoder *encoder, |
ac240288 | 369 | const struct intel_crtc_state *crtc_state, |
178f736a | 370 | enum hdmi_infoframe_type type, |
fff63867 | 371 | const void *frame, ssize_t len) |
8c5f5f7c | 372 | { |
fff63867 | 373 | const uint32_t *data = frame; |
2da8af54 | 374 | struct drm_device *dev = encoder->dev; |
fac5e23e | 375 | struct drm_i915_private *dev_priv = to_i915(dev); |
ac240288 | 376 | enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; |
f0f59a00 VS |
377 | i915_reg_t ctl_reg = HSW_TVIDEO_DIP_CTL(cpu_transcoder); |
378 | i915_reg_t data_reg; | |
178f736a | 379 | int i; |
2da8af54 | 380 | u32 val = I915_READ(ctl_reg); |
8c5f5f7c | 381 | |
436c6d4a | 382 | data_reg = hsw_dip_data_reg(dev_priv, cpu_transcoder, type, 0); |
2da8af54 | 383 | |
178f736a | 384 | val &= ~hsw_infoframe_enable(type); |
2da8af54 PZ |
385 | I915_WRITE(ctl_reg, val); |
386 | ||
9d9740f0 | 387 | mmiowb(); |
2da8af54 | 388 | for (i = 0; i < len; i += 4) { |
436c6d4a VS |
389 | I915_WRITE(hsw_dip_data_reg(dev_priv, cpu_transcoder, |
390 | type, i >> 2), *data); | |
2da8af54 PZ |
391 | data++; |
392 | } | |
adf00b26 PZ |
393 | /* Write every possible data byte to force correct ECC calculation. */ |
394 | for (; i < VIDEO_DIP_DATA_SIZE; i += 4) | |
436c6d4a VS |
395 | I915_WRITE(hsw_dip_data_reg(dev_priv, cpu_transcoder, |
396 | type, i >> 2), 0); | |
9d9740f0 | 397 | mmiowb(); |
8c5f5f7c | 398 | |
178f736a | 399 | val |= hsw_infoframe_enable(type); |
2da8af54 | 400 | I915_WRITE(ctl_reg, val); |
9d9740f0 | 401 | POSTING_READ(ctl_reg); |
8c5f5f7c ED |
402 | } |
403 | ||
cda0aaaf VS |
404 | static bool hsw_infoframe_enabled(struct drm_encoder *encoder, |
405 | const struct intel_crtc_state *pipe_config) | |
e43823ec | 406 | { |
cda0aaaf VS |
407 | struct drm_i915_private *dev_priv = to_i915(encoder->dev); |
408 | u32 val = I915_READ(HSW_TVIDEO_DIP_CTL(pipe_config->cpu_transcoder)); | |
e43823ec | 409 | |
ec1dc603 VS |
410 | return val & (VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_AVI_HSW | |
411 | VIDEO_DIP_ENABLE_GCP_HSW | VIDEO_DIP_ENABLE_VS_HSW | | |
412 | VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW); | |
e43823ec JB |
413 | } |
414 | ||
5adaea79 DL |
415 | /* |
416 | * The data we write to the DIP data buffer registers is 1 byte bigger than the | |
417 | * HDMI infoframe size because of an ECC/reserved byte at position 3 (starting | |
418 | * at 0). It's also a byte used by DisplayPort so the same DIP registers can be | |
419 | * used for both technologies. | |
420 | * | |
421 | * DW0: Reserved/ECC/DP | HB2 | HB1 | HB0 | |
422 | * DW1: DB3 | DB2 | DB1 | DB0 | |
423 | * DW2: DB7 | DB6 | DB5 | DB4 | |
424 | * DW3: ... | |
425 | * | |
426 | * (HB is Header Byte, DB is Data Byte) | |
427 | * | |
428 | * The hdmi pack() functions don't know about that hardware specific hole so we | |
429 | * trick them by giving an offset into the buffer and moving back the header | |
430 | * bytes by one. | |
431 | */ | |
9198ee5b | 432 | static void intel_write_infoframe(struct drm_encoder *encoder, |
ac240288 | 433 | const struct intel_crtc_state *crtc_state, |
9198ee5b | 434 | union hdmi_infoframe *frame) |
45187ace JB |
435 | { |
436 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); | |
5adaea79 DL |
437 | uint8_t buffer[VIDEO_DIP_DATA_SIZE]; |
438 | ssize_t len; | |
45187ace | 439 | |
5adaea79 DL |
440 | /* see comment above for the reason for this offset */ |
441 | len = hdmi_infoframe_pack(frame, buffer + 1, sizeof(buffer) - 1); | |
442 | if (len < 0) | |
443 | return; | |
444 | ||
445 | /* Insert the 'hole' (see big comment above) at position 3 */ | |
446 | buffer[0] = buffer[1]; | |
447 | buffer[1] = buffer[2]; | |
448 | buffer[2] = buffer[3]; | |
449 | buffer[3] = 0; | |
450 | len++; | |
45187ace | 451 | |
ac240288 | 452 | intel_hdmi->write_infoframe(encoder, crtc_state, frame->any.type, buffer, len); |
45187ace JB |
453 | } |
454 | ||
687f4d06 | 455 | static void intel_hdmi_set_avi_infoframe(struct drm_encoder *encoder, |
ac240288 | 456 | const struct intel_crtc_state *crtc_state) |
45187ace | 457 | { |
abedc077 | 458 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); |
779c4c28 VS |
459 | const struct drm_display_mode *adjusted_mode = |
460 | &crtc_state->base.adjusted_mode; | |
5adaea79 DL |
461 | union hdmi_infoframe frame; |
462 | int ret; | |
45187ace | 463 | |
5adaea79 DL |
464 | ret = drm_hdmi_avi_infoframe_from_display_mode(&frame.avi, |
465 | adjusted_mode); | |
466 | if (ret < 0) { | |
467 | DRM_ERROR("couldn't fill AVI infoframe\n"); | |
468 | return; | |
469 | } | |
c846b619 | 470 | |
779c4c28 | 471 | drm_hdmi_avi_infoframe_quant_range(&frame.avi, adjusted_mode, |
a2ce26f8 VS |
472 | crtc_state->limited_color_range ? |
473 | HDMI_QUANTIZATION_RANGE_LIMITED : | |
474 | HDMI_QUANTIZATION_RANGE_FULL, | |
475 | intel_hdmi->rgb_quant_range_selectable); | |
abedc077 | 476 | |
ac240288 | 477 | intel_write_infoframe(encoder, crtc_state, &frame); |
b055c8f3 JB |
478 | } |
479 | ||
ac240288 ML |
480 | static void intel_hdmi_set_spd_infoframe(struct drm_encoder *encoder, |
481 | const struct intel_crtc_state *crtc_state) | |
c0864cb3 | 482 | { |
5adaea79 DL |
483 | union hdmi_infoframe frame; |
484 | int ret; | |
485 | ||
486 | ret = hdmi_spd_infoframe_init(&frame.spd, "Intel", "Integrated gfx"); | |
487 | if (ret < 0) { | |
488 | DRM_ERROR("couldn't fill SPD infoframe\n"); | |
489 | return; | |
490 | } | |
c0864cb3 | 491 | |
5adaea79 | 492 | frame.spd.sdi = HDMI_SPD_SDI_PC; |
c0864cb3 | 493 | |
ac240288 | 494 | intel_write_infoframe(encoder, crtc_state, &frame); |
c0864cb3 JB |
495 | } |
496 | ||
c8bb75af LD |
497 | static void |
498 | intel_hdmi_set_hdmi_infoframe(struct drm_encoder *encoder, | |
ac240288 | 499 | const struct intel_crtc_state *crtc_state) |
c8bb75af LD |
500 | { |
501 | union hdmi_infoframe frame; | |
502 | int ret; | |
503 | ||
504 | ret = drm_hdmi_vendor_infoframe_from_display_mode(&frame.vendor.hdmi, | |
ac240288 | 505 | &crtc_state->base.adjusted_mode); |
c8bb75af LD |
506 | if (ret < 0) |
507 | return; | |
508 | ||
ac240288 | 509 | intel_write_infoframe(encoder, crtc_state, &frame); |
c8bb75af LD |
510 | } |
511 | ||
687f4d06 | 512 | static void g4x_set_infoframes(struct drm_encoder *encoder, |
6897b4b5 | 513 | bool enable, |
ac240288 ML |
514 | const struct intel_crtc_state *crtc_state, |
515 | const struct drm_connector_state *conn_state) | |
687f4d06 | 516 | { |
fac5e23e | 517 | struct drm_i915_private *dev_priv = to_i915(encoder->dev); |
69fde0a6 VS |
518 | struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); |
519 | struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi; | |
f0f59a00 | 520 | i915_reg_t reg = VIDEO_DIP_CTL; |
0c14c7f9 | 521 | u32 val = I915_READ(reg); |
822cdc52 | 522 | u32 port = VIDEO_DIP_PORT(intel_dig_port->port); |
0c14c7f9 | 523 | |
afba0188 DV |
524 | assert_hdmi_port_disabled(intel_hdmi); |
525 | ||
0c14c7f9 PZ |
526 | /* If the registers were not initialized yet, they might be zeroes, |
527 | * which means we're selecting the AVI DIP and we're setting its | |
528 | * frequency to once. This seems to really confuse the HW and make | |
529 | * things stop working (the register spec says the AVI always needs to | |
530 | * be sent every VSync). So here we avoid writing to the register more | |
531 | * than we need and also explicitly select the AVI DIP and explicitly | |
532 | * set its frequency to every VSync. Avoiding to write it twice seems to | |
533 | * be enough to solve the problem, but being defensive shouldn't hurt us | |
534 | * either. */ | |
535 | val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; | |
536 | ||
6897b4b5 | 537 | if (!enable) { |
0c14c7f9 PZ |
538 | if (!(val & VIDEO_DIP_ENABLE)) |
539 | return; | |
0be6f0c8 VS |
540 | if (port != (val & VIDEO_DIP_PORT_MASK)) { |
541 | DRM_DEBUG_KMS("video DIP still enabled on port %c\n", | |
542 | (val & VIDEO_DIP_PORT_MASK) >> 29); | |
543 | return; | |
544 | } | |
545 | val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI | | |
546 | VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD); | |
0c14c7f9 | 547 | I915_WRITE(reg, val); |
9d9740f0 | 548 | POSTING_READ(reg); |
0c14c7f9 PZ |
549 | return; |
550 | } | |
551 | ||
72b78c9d PZ |
552 | if (port != (val & VIDEO_DIP_PORT_MASK)) { |
553 | if (val & VIDEO_DIP_ENABLE) { | |
0be6f0c8 VS |
554 | DRM_DEBUG_KMS("video DIP already enabled on port %c\n", |
555 | (val & VIDEO_DIP_PORT_MASK) >> 29); | |
556 | return; | |
72b78c9d PZ |
557 | } |
558 | val &= ~VIDEO_DIP_PORT_MASK; | |
559 | val |= port; | |
560 | } | |
561 | ||
822974ae | 562 | val |= VIDEO_DIP_ENABLE; |
0be6f0c8 VS |
563 | val &= ~(VIDEO_DIP_ENABLE_AVI | |
564 | VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD); | |
822974ae | 565 | |
f278d972 | 566 | I915_WRITE(reg, val); |
9d9740f0 | 567 | POSTING_READ(reg); |
f278d972 | 568 | |
ac240288 ML |
569 | intel_hdmi_set_avi_infoframe(encoder, crtc_state); |
570 | intel_hdmi_set_spd_infoframe(encoder, crtc_state); | |
571 | intel_hdmi_set_hdmi_infoframe(encoder, crtc_state); | |
687f4d06 PZ |
572 | } |
573 | ||
ac240288 | 574 | static bool hdmi_sink_is_deep_color(const struct drm_connector_state *conn_state) |
6d67415f | 575 | { |
ac240288 | 576 | struct drm_connector *connector = conn_state->connector; |
6d67415f VS |
577 | |
578 | /* | |
579 | * HDMI cloning is only supported on g4x which doesn't | |
580 | * support deep color or GCP infoframes anyway so no | |
581 | * need to worry about multiple HDMI sinks here. | |
582 | */ | |
6d67415f | 583 | |
ac240288 | 584 | return connector->display_info.bpc > 8; |
6d67415f VS |
585 | } |
586 | ||
12aa3290 VS |
587 | /* |
588 | * Determine if default_phase=1 can be indicated in the GCP infoframe. | |
589 | * | |
590 | * From HDMI specification 1.4a: | |
591 | * - The first pixel of each Video Data Period shall always have a pixel packing phase of 0 | |
592 | * - The first pixel following each Video Data Period shall have a pixel packing phase of 0 | |
593 | * - The PP bits shall be constant for all GCPs and will be equal to the last packing phase | |
594 | * - The first pixel following every transition of HSYNC or VSYNC shall have a pixel packing | |
595 | * phase of 0 | |
596 | */ | |
597 | static bool gcp_default_phase_possible(int pipe_bpp, | |
598 | const struct drm_display_mode *mode) | |
599 | { | |
600 | unsigned int pixels_per_group; | |
601 | ||
602 | switch (pipe_bpp) { | |
603 | case 30: | |
604 | /* 4 pixels in 5 clocks */ | |
605 | pixels_per_group = 4; | |
606 | break; | |
607 | case 36: | |
608 | /* 2 pixels in 3 clocks */ | |
609 | pixels_per_group = 2; | |
610 | break; | |
611 | case 48: | |
612 | /* 1 pixel in 2 clocks */ | |
613 | pixels_per_group = 1; | |
614 | break; | |
615 | default: | |
616 | /* phase information not relevant for 8bpc */ | |
617 | return false; | |
618 | } | |
619 | ||
620 | return mode->crtc_hdisplay % pixels_per_group == 0 && | |
621 | mode->crtc_htotal % pixels_per_group == 0 && | |
622 | mode->crtc_hblank_start % pixels_per_group == 0 && | |
623 | mode->crtc_hblank_end % pixels_per_group == 0 && | |
624 | mode->crtc_hsync_start % pixels_per_group == 0 && | |
625 | mode->crtc_hsync_end % pixels_per_group == 0 && | |
626 | ((mode->flags & DRM_MODE_FLAG_INTERLACE) == 0 || | |
627 | mode->crtc_htotal/2 % pixels_per_group == 0); | |
628 | } | |
629 | ||
ac240288 ML |
630 | static bool intel_hdmi_set_gcp_infoframe(struct drm_encoder *encoder, |
631 | const struct intel_crtc_state *crtc_state, | |
632 | const struct drm_connector_state *conn_state) | |
6d67415f | 633 | { |
fac5e23e | 634 | struct drm_i915_private *dev_priv = to_i915(encoder->dev); |
ac240288 | 635 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); |
f0f59a00 VS |
636 | i915_reg_t reg; |
637 | u32 val = 0; | |
6d67415f VS |
638 | |
639 | if (HAS_DDI(dev_priv)) | |
ac240288 | 640 | reg = HSW_TVIDEO_DIP_GCP(crtc_state->cpu_transcoder); |
666a4537 | 641 | else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) |
6d67415f | 642 | reg = VLV_TVIDEO_DIP_GCP(crtc->pipe); |
2d1fe073 | 643 | else if (HAS_PCH_SPLIT(dev_priv)) |
6d67415f VS |
644 | reg = TVIDEO_DIP_GCP(crtc->pipe); |
645 | else | |
646 | return false; | |
647 | ||
648 | /* Indicate color depth whenever the sink supports deep color */ | |
ac240288 | 649 | if (hdmi_sink_is_deep_color(conn_state)) |
6d67415f VS |
650 | val |= GCP_COLOR_INDICATION; |
651 | ||
12aa3290 | 652 | /* Enable default_phase whenever the display mode is suitably aligned */ |
ac240288 ML |
653 | if (gcp_default_phase_possible(crtc_state->pipe_bpp, |
654 | &crtc_state->base.adjusted_mode)) | |
12aa3290 VS |
655 | val |= GCP_DEFAULT_PHASE_ENABLE; |
656 | ||
6d67415f VS |
657 | I915_WRITE(reg, val); |
658 | ||
659 | return val != 0; | |
660 | } | |
661 | ||
687f4d06 | 662 | static void ibx_set_infoframes(struct drm_encoder *encoder, |
6897b4b5 | 663 | bool enable, |
ac240288 ML |
664 | const struct intel_crtc_state *crtc_state, |
665 | const struct drm_connector_state *conn_state) | |
687f4d06 | 666 | { |
fac5e23e | 667 | struct drm_i915_private *dev_priv = to_i915(encoder->dev); |
ac240288 | 668 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc); |
69fde0a6 VS |
669 | struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); |
670 | struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi; | |
f0f59a00 | 671 | i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe); |
0c14c7f9 | 672 | u32 val = I915_READ(reg); |
822cdc52 | 673 | u32 port = VIDEO_DIP_PORT(intel_dig_port->port); |
0c14c7f9 | 674 | |
afba0188 DV |
675 | assert_hdmi_port_disabled(intel_hdmi); |
676 | ||
0c14c7f9 PZ |
677 | /* See the big comment in g4x_set_infoframes() */ |
678 | val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; | |
679 | ||
6897b4b5 | 680 | if (!enable) { |
0c14c7f9 PZ |
681 | if (!(val & VIDEO_DIP_ENABLE)) |
682 | return; | |
0be6f0c8 VS |
683 | val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI | |
684 | VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | | |
685 | VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); | |
0c14c7f9 | 686 | I915_WRITE(reg, val); |
9d9740f0 | 687 | POSTING_READ(reg); |
0c14c7f9 PZ |
688 | return; |
689 | } | |
690 | ||
72b78c9d | 691 | if (port != (val & VIDEO_DIP_PORT_MASK)) { |
0be6f0c8 VS |
692 | WARN(val & VIDEO_DIP_ENABLE, |
693 | "DIP already enabled on port %c\n", | |
694 | (val & VIDEO_DIP_PORT_MASK) >> 29); | |
72b78c9d PZ |
695 | val &= ~VIDEO_DIP_PORT_MASK; |
696 | val |= port; | |
697 | } | |
698 | ||
822974ae | 699 | val |= VIDEO_DIP_ENABLE; |
0be6f0c8 VS |
700 | val &= ~(VIDEO_DIP_ENABLE_AVI | |
701 | VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | | |
702 | VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); | |
822974ae | 703 | |
ac240288 | 704 | if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state)) |
6d67415f VS |
705 | val |= VIDEO_DIP_ENABLE_GCP; |
706 | ||
f278d972 | 707 | I915_WRITE(reg, val); |
9d9740f0 | 708 | POSTING_READ(reg); |
f278d972 | 709 | |
ac240288 ML |
710 | intel_hdmi_set_avi_infoframe(encoder, crtc_state); |
711 | intel_hdmi_set_spd_infoframe(encoder, crtc_state); | |
712 | intel_hdmi_set_hdmi_infoframe(encoder, crtc_state); | |
687f4d06 PZ |
713 | } |
714 | ||
715 | static void cpt_set_infoframes(struct drm_encoder *encoder, | |
6897b4b5 | 716 | bool enable, |
ac240288 ML |
717 | const struct intel_crtc_state *crtc_state, |
718 | const struct drm_connector_state *conn_state) | |
687f4d06 | 719 | { |
fac5e23e | 720 | struct drm_i915_private *dev_priv = to_i915(encoder->dev); |
ac240288 | 721 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc); |
0c14c7f9 | 722 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); |
f0f59a00 | 723 | i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe); |
0c14c7f9 PZ |
724 | u32 val = I915_READ(reg); |
725 | ||
afba0188 DV |
726 | assert_hdmi_port_disabled(intel_hdmi); |
727 | ||
0c14c7f9 PZ |
728 | /* See the big comment in g4x_set_infoframes() */ |
729 | val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; | |
730 | ||
6897b4b5 | 731 | if (!enable) { |
0c14c7f9 PZ |
732 | if (!(val & VIDEO_DIP_ENABLE)) |
733 | return; | |
0be6f0c8 VS |
734 | val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI | |
735 | VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | | |
736 | VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); | |
0c14c7f9 | 737 | I915_WRITE(reg, val); |
9d9740f0 | 738 | POSTING_READ(reg); |
0c14c7f9 PZ |
739 | return; |
740 | } | |
741 | ||
822974ae PZ |
742 | /* Set both together, unset both together: see the spec. */ |
743 | val |= VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI; | |
0dd87d20 | 744 | val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | |
0be6f0c8 | 745 | VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); |
822974ae | 746 | |
ac240288 | 747 | if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state)) |
6d67415f VS |
748 | val |= VIDEO_DIP_ENABLE_GCP; |
749 | ||
822974ae | 750 | I915_WRITE(reg, val); |
9d9740f0 | 751 | POSTING_READ(reg); |
822974ae | 752 | |
ac240288 ML |
753 | intel_hdmi_set_avi_infoframe(encoder, crtc_state); |
754 | intel_hdmi_set_spd_infoframe(encoder, crtc_state); | |
755 | intel_hdmi_set_hdmi_infoframe(encoder, crtc_state); | |
687f4d06 PZ |
756 | } |
757 | ||
758 | static void vlv_set_infoframes(struct drm_encoder *encoder, | |
6897b4b5 | 759 | bool enable, |
ac240288 ML |
760 | const struct intel_crtc_state *crtc_state, |
761 | const struct drm_connector_state *conn_state) | |
687f4d06 | 762 | { |
fac5e23e | 763 | struct drm_i915_private *dev_priv = to_i915(encoder->dev); |
6a2b8021 | 764 | struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); |
ac240288 | 765 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc); |
0c14c7f9 | 766 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); |
f0f59a00 | 767 | i915_reg_t reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe); |
0c14c7f9 | 768 | u32 val = I915_READ(reg); |
6a2b8021 | 769 | u32 port = VIDEO_DIP_PORT(intel_dig_port->port); |
0c14c7f9 | 770 | |
afba0188 DV |
771 | assert_hdmi_port_disabled(intel_hdmi); |
772 | ||
0c14c7f9 PZ |
773 | /* See the big comment in g4x_set_infoframes() */ |
774 | val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; | |
775 | ||
6897b4b5 | 776 | if (!enable) { |
0c14c7f9 PZ |
777 | if (!(val & VIDEO_DIP_ENABLE)) |
778 | return; | |
0be6f0c8 VS |
779 | val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI | |
780 | VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | | |
781 | VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); | |
0c14c7f9 | 782 | I915_WRITE(reg, val); |
9d9740f0 | 783 | POSTING_READ(reg); |
0c14c7f9 PZ |
784 | return; |
785 | } | |
786 | ||
6a2b8021 | 787 | if (port != (val & VIDEO_DIP_PORT_MASK)) { |
0be6f0c8 VS |
788 | WARN(val & VIDEO_DIP_ENABLE, |
789 | "DIP already enabled on port %c\n", | |
790 | (val & VIDEO_DIP_PORT_MASK) >> 29); | |
6a2b8021 JB |
791 | val &= ~VIDEO_DIP_PORT_MASK; |
792 | val |= port; | |
793 | } | |
794 | ||
822974ae | 795 | val |= VIDEO_DIP_ENABLE; |
0be6f0c8 VS |
796 | val &= ~(VIDEO_DIP_ENABLE_AVI | |
797 | VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | | |
798 | VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); | |
822974ae | 799 | |
ac240288 | 800 | if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state)) |
6d67415f VS |
801 | val |= VIDEO_DIP_ENABLE_GCP; |
802 | ||
822974ae | 803 | I915_WRITE(reg, val); |
9d9740f0 | 804 | POSTING_READ(reg); |
822974ae | 805 | |
ac240288 ML |
806 | intel_hdmi_set_avi_infoframe(encoder, crtc_state); |
807 | intel_hdmi_set_spd_infoframe(encoder, crtc_state); | |
808 | intel_hdmi_set_hdmi_infoframe(encoder, crtc_state); | |
687f4d06 PZ |
809 | } |
810 | ||
811 | static void hsw_set_infoframes(struct drm_encoder *encoder, | |
6897b4b5 | 812 | bool enable, |
ac240288 ML |
813 | const struct intel_crtc_state *crtc_state, |
814 | const struct drm_connector_state *conn_state) | |
687f4d06 | 815 | { |
fac5e23e | 816 | struct drm_i915_private *dev_priv = to_i915(encoder->dev); |
0c14c7f9 | 817 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); |
ac240288 | 818 | i915_reg_t reg = HSW_TVIDEO_DIP_CTL(crtc_state->cpu_transcoder); |
0dd87d20 | 819 | u32 val = I915_READ(reg); |
0c14c7f9 | 820 | |
afba0188 DV |
821 | assert_hdmi_port_disabled(intel_hdmi); |
822 | ||
0be6f0c8 VS |
823 | val &= ~(VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_AVI_HSW | |
824 | VIDEO_DIP_ENABLE_GCP_HSW | VIDEO_DIP_ENABLE_VS_HSW | | |
825 | VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW); | |
826 | ||
6897b4b5 | 827 | if (!enable) { |
0be6f0c8 | 828 | I915_WRITE(reg, val); |
9d9740f0 | 829 | POSTING_READ(reg); |
0c14c7f9 PZ |
830 | return; |
831 | } | |
832 | ||
ac240288 | 833 | if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state)) |
6d67415f VS |
834 | val |= VIDEO_DIP_ENABLE_GCP_HSW; |
835 | ||
0dd87d20 | 836 | I915_WRITE(reg, val); |
9d9740f0 | 837 | POSTING_READ(reg); |
0dd87d20 | 838 | |
ac240288 ML |
839 | intel_hdmi_set_avi_infoframe(encoder, crtc_state); |
840 | intel_hdmi_set_spd_infoframe(encoder, crtc_state); | |
841 | intel_hdmi_set_hdmi_infoframe(encoder, crtc_state); | |
687f4d06 PZ |
842 | } |
843 | ||
b2ccb822 VS |
844 | void intel_dp_dual_mode_set_tmds_output(struct intel_hdmi *hdmi, bool enable) |
845 | { | |
846 | struct drm_i915_private *dev_priv = to_i915(intel_hdmi_to_dev(hdmi)); | |
847 | struct i2c_adapter *adapter = | |
848 | intel_gmbus_get_adapter(dev_priv, hdmi->ddc_bus); | |
849 | ||
850 | if (hdmi->dp_dual_mode.type < DRM_DP_DUAL_MODE_TYPE2_DVI) | |
851 | return; | |
852 | ||
853 | DRM_DEBUG_KMS("%s DP dual mode adaptor TMDS output\n", | |
854 | enable ? "Enabling" : "Disabling"); | |
855 | ||
856 | drm_dp_dual_mode_set_tmds_output(hdmi->dp_dual_mode.type, | |
857 | adapter, enable); | |
858 | } | |
859 | ||
ac240288 ML |
860 | static void intel_hdmi_prepare(struct intel_encoder *encoder, |
861 | const struct intel_crtc_state *crtc_state) | |
7d57382e | 862 | { |
c59423a3 | 863 | struct drm_device *dev = encoder->base.dev; |
fac5e23e | 864 | struct drm_i915_private *dev_priv = to_i915(dev); |
ac240288 | 865 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); |
c59423a3 | 866 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); |
ac240288 | 867 | const struct drm_display_mode *adjusted_mode = &crtc_state->base.adjusted_mode; |
b242b7f7 | 868 | u32 hdmi_val; |
7d57382e | 869 | |
b2ccb822 VS |
870 | intel_dp_dual_mode_set_tmds_output(intel_hdmi, true); |
871 | ||
b242b7f7 | 872 | hdmi_val = SDVO_ENCODING_HDMI; |
ac240288 | 873 | if (!HAS_PCH_SPLIT(dev_priv) && crtc_state->limited_color_range) |
0f2a2a75 | 874 | hdmi_val |= HDMI_COLOR_RANGE_16_235; |
b599c0bc | 875 | if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) |
b242b7f7 | 876 | hdmi_val |= SDVO_VSYNC_ACTIVE_HIGH; |
b599c0bc | 877 | if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) |
b242b7f7 | 878 | hdmi_val |= SDVO_HSYNC_ACTIVE_HIGH; |
7d57382e | 879 | |
ac240288 | 880 | if (crtc_state->pipe_bpp > 24) |
4f3a8bc7 | 881 | hdmi_val |= HDMI_COLOR_FORMAT_12bpc; |
020f6704 | 882 | else |
4f3a8bc7 | 883 | hdmi_val |= SDVO_COLOR_FORMAT_8bpc; |
020f6704 | 884 | |
ac240288 | 885 | if (crtc_state->has_hdmi_sink) |
dc0fa718 | 886 | hdmi_val |= HDMI_MODE_SELECT_HDMI; |
2e3d6006 | 887 | |
6e266956 | 888 | if (HAS_PCH_CPT(dev_priv)) |
c59423a3 | 889 | hdmi_val |= SDVO_PIPE_SEL_CPT(crtc->pipe); |
920a14b2 | 890 | else if (IS_CHERRYVIEW(dev_priv)) |
44f37d1f | 891 | hdmi_val |= SDVO_PIPE_SEL_CHV(crtc->pipe); |
dc0fa718 | 892 | else |
c59423a3 | 893 | hdmi_val |= SDVO_PIPE_SEL(crtc->pipe); |
7d57382e | 894 | |
b242b7f7 PZ |
895 | I915_WRITE(intel_hdmi->hdmi_reg, hdmi_val); |
896 | POSTING_READ(intel_hdmi->hdmi_reg); | |
7d57382e EA |
897 | } |
898 | ||
85234cdc DV |
899 | static bool intel_hdmi_get_hw_state(struct intel_encoder *encoder, |
900 | enum pipe *pipe) | |
7d57382e | 901 | { |
85234cdc | 902 | struct drm_device *dev = encoder->base.dev; |
fac5e23e | 903 | struct drm_i915_private *dev_priv = to_i915(dev); |
85234cdc | 904 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); |
6d129bea | 905 | enum intel_display_power_domain power_domain; |
85234cdc | 906 | u32 tmp; |
5b092174 | 907 | bool ret; |
85234cdc | 908 | |
6d129bea | 909 | power_domain = intel_display_port_power_domain(encoder); |
5b092174 | 910 | if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) |
6d129bea ID |
911 | return false; |
912 | ||
5b092174 ID |
913 | ret = false; |
914 | ||
b242b7f7 | 915 | tmp = I915_READ(intel_hdmi->hdmi_reg); |
85234cdc DV |
916 | |
917 | if (!(tmp & SDVO_ENABLE)) | |
5b092174 | 918 | goto out; |
85234cdc | 919 | |
6e266956 | 920 | if (HAS_PCH_CPT(dev_priv)) |
85234cdc | 921 | *pipe = PORT_TO_PIPE_CPT(tmp); |
920a14b2 | 922 | else if (IS_CHERRYVIEW(dev_priv)) |
71485e0a | 923 | *pipe = SDVO_PORT_TO_PIPE_CHV(tmp); |
85234cdc DV |
924 | else |
925 | *pipe = PORT_TO_PIPE(tmp); | |
926 | ||
5b092174 ID |
927 | ret = true; |
928 | ||
929 | out: | |
930 | intel_display_power_put(dev_priv, power_domain); | |
931 | ||
932 | return ret; | |
85234cdc DV |
933 | } |
934 | ||
045ac3b5 | 935 | static void intel_hdmi_get_config(struct intel_encoder *encoder, |
5cec258b | 936 | struct intel_crtc_state *pipe_config) |
045ac3b5 JB |
937 | { |
938 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); | |
8c875fca | 939 | struct drm_device *dev = encoder->base.dev; |
fac5e23e | 940 | struct drm_i915_private *dev_priv = to_i915(dev); |
045ac3b5 | 941 | u32 tmp, flags = 0; |
18442d08 | 942 | int dotclock; |
045ac3b5 JB |
943 | |
944 | tmp = I915_READ(intel_hdmi->hdmi_reg); | |
945 | ||
946 | if (tmp & SDVO_HSYNC_ACTIVE_HIGH) | |
947 | flags |= DRM_MODE_FLAG_PHSYNC; | |
948 | else | |
949 | flags |= DRM_MODE_FLAG_NHSYNC; | |
950 | ||
951 | if (tmp & SDVO_VSYNC_ACTIVE_HIGH) | |
952 | flags |= DRM_MODE_FLAG_PVSYNC; | |
953 | else | |
954 | flags |= DRM_MODE_FLAG_NVSYNC; | |
955 | ||
6897b4b5 DV |
956 | if (tmp & HDMI_MODE_SELECT_HDMI) |
957 | pipe_config->has_hdmi_sink = true; | |
958 | ||
cda0aaaf | 959 | if (intel_hdmi->infoframe_enabled(&encoder->base, pipe_config)) |
e43823ec JB |
960 | pipe_config->has_infoframe = true; |
961 | ||
c84db770 | 962 | if (tmp & SDVO_AUDIO_ENABLE) |
9ed109a7 DV |
963 | pipe_config->has_audio = true; |
964 | ||
6e266956 | 965 | if (!HAS_PCH_SPLIT(dev_priv) && |
8c875fca VS |
966 | tmp & HDMI_COLOR_RANGE_16_235) |
967 | pipe_config->limited_color_range = true; | |
968 | ||
2d112de7 | 969 | pipe_config->base.adjusted_mode.flags |= flags; |
18442d08 VS |
970 | |
971 | if ((tmp & SDVO_COLOR_FORMAT_MASK) == HDMI_COLOR_FORMAT_12bpc) | |
972 | dotclock = pipe_config->port_clock * 2 / 3; | |
973 | else | |
974 | dotclock = pipe_config->port_clock; | |
975 | ||
be69a133 VS |
976 | if (pipe_config->pixel_multiplier) |
977 | dotclock /= pipe_config->pixel_multiplier; | |
978 | ||
2d112de7 | 979 | pipe_config->base.adjusted_mode.crtc_clock = dotclock; |
d4d6279a ACO |
980 | |
981 | pipe_config->lane_count = 4; | |
045ac3b5 JB |
982 | } |
983 | ||
df18e721 ML |
984 | static void intel_enable_hdmi_audio(struct intel_encoder *encoder, |
985 | struct intel_crtc_state *pipe_config, | |
986 | struct drm_connector_state *conn_state) | |
d1b1589c | 987 | { |
ac240288 | 988 | struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc); |
d1b1589c | 989 | |
ac240288 | 990 | WARN_ON(!pipe_config->has_hdmi_sink); |
d1b1589c VS |
991 | DRM_DEBUG_DRIVER("Enabling HDMI audio on pipe %c\n", |
992 | pipe_name(crtc->pipe)); | |
bbf35e9d | 993 | intel_audio_codec_enable(encoder, pipe_config, conn_state); |
d1b1589c VS |
994 | } |
995 | ||
fd6bbda9 ML |
996 | static void g4x_enable_hdmi(struct intel_encoder *encoder, |
997 | struct intel_crtc_state *pipe_config, | |
998 | struct drm_connector_state *conn_state) | |
7d57382e | 999 | { |
5ab432ef | 1000 | struct drm_device *dev = encoder->base.dev; |
fac5e23e | 1001 | struct drm_i915_private *dev_priv = to_i915(dev); |
5ab432ef | 1002 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); |
7d57382e EA |
1003 | u32 temp; |
1004 | ||
b242b7f7 | 1005 | temp = I915_READ(intel_hdmi->hdmi_reg); |
d8a2d0e0 | 1006 | |
bf868c7d | 1007 | temp |= SDVO_ENABLE; |
df18e721 | 1008 | if (pipe_config->has_audio) |
bf868c7d | 1009 | temp |= SDVO_AUDIO_ENABLE; |
7a87c289 | 1010 | |
bf868c7d VS |
1011 | I915_WRITE(intel_hdmi->hdmi_reg, temp); |
1012 | POSTING_READ(intel_hdmi->hdmi_reg); | |
1013 | ||
df18e721 ML |
1014 | if (pipe_config->has_audio) |
1015 | intel_enable_hdmi_audio(encoder, pipe_config, conn_state); | |
bf868c7d VS |
1016 | } |
1017 | ||
fd6bbda9 ML |
1018 | static void ibx_enable_hdmi(struct intel_encoder *encoder, |
1019 | struct intel_crtc_state *pipe_config, | |
1020 | struct drm_connector_state *conn_state) | |
bf868c7d VS |
1021 | { |
1022 | struct drm_device *dev = encoder->base.dev; | |
fac5e23e | 1023 | struct drm_i915_private *dev_priv = to_i915(dev); |
bf868c7d VS |
1024 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); |
1025 | u32 temp; | |
1026 | ||
1027 | temp = I915_READ(intel_hdmi->hdmi_reg); | |
d8a2d0e0 | 1028 | |
bf868c7d | 1029 | temp |= SDVO_ENABLE; |
ac240288 | 1030 | if (pipe_config->has_audio) |
bf868c7d | 1031 | temp |= SDVO_AUDIO_ENABLE; |
5ab432ef | 1032 | |
bf868c7d VS |
1033 | /* |
1034 | * HW workaround, need to write this twice for issue | |
1035 | * that may result in first write getting masked. | |
1036 | */ | |
1037 | I915_WRITE(intel_hdmi->hdmi_reg, temp); | |
1038 | POSTING_READ(intel_hdmi->hdmi_reg); | |
b242b7f7 PZ |
1039 | I915_WRITE(intel_hdmi->hdmi_reg, temp); |
1040 | POSTING_READ(intel_hdmi->hdmi_reg); | |
5ab432ef | 1041 | |
bf868c7d VS |
1042 | /* |
1043 | * HW workaround, need to toggle enable bit off and on | |
1044 | * for 12bpc with pixel repeat. | |
1045 | * | |
1046 | * FIXME: BSpec says this should be done at the end of | |
1047 | * of the modeset sequence, so not sure if this isn't too soon. | |
5ab432ef | 1048 | */ |
df18e721 ML |
1049 | if (pipe_config->pipe_bpp > 24 && |
1050 | pipe_config->pixel_multiplier > 1) { | |
bf868c7d VS |
1051 | I915_WRITE(intel_hdmi->hdmi_reg, temp & ~SDVO_ENABLE); |
1052 | POSTING_READ(intel_hdmi->hdmi_reg); | |
1053 | ||
1054 | /* | |
1055 | * HW workaround, need to write this twice for issue | |
1056 | * that may result in first write getting masked. | |
1057 | */ | |
1058 | I915_WRITE(intel_hdmi->hdmi_reg, temp); | |
1059 | POSTING_READ(intel_hdmi->hdmi_reg); | |
b242b7f7 PZ |
1060 | I915_WRITE(intel_hdmi->hdmi_reg, temp); |
1061 | POSTING_READ(intel_hdmi->hdmi_reg); | |
7d57382e | 1062 | } |
c1dec79a | 1063 | |
df18e721 ML |
1064 | if (pipe_config->has_audio) |
1065 | intel_enable_hdmi_audio(encoder, pipe_config, conn_state); | |
d1b1589c VS |
1066 | } |
1067 | ||
fd6bbda9 ML |
1068 | static void cpt_enable_hdmi(struct intel_encoder *encoder, |
1069 | struct intel_crtc_state *pipe_config, | |
1070 | struct drm_connector_state *conn_state) | |
d1b1589c VS |
1071 | { |
1072 | struct drm_device *dev = encoder->base.dev; | |
fac5e23e | 1073 | struct drm_i915_private *dev_priv = to_i915(dev); |
ac240288 | 1074 | struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc); |
d1b1589c VS |
1075 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); |
1076 | enum pipe pipe = crtc->pipe; | |
1077 | u32 temp; | |
1078 | ||
1079 | temp = I915_READ(intel_hdmi->hdmi_reg); | |
1080 | ||
1081 | temp |= SDVO_ENABLE; | |
df18e721 | 1082 | if (pipe_config->has_audio) |
d1b1589c VS |
1083 | temp |= SDVO_AUDIO_ENABLE; |
1084 | ||
1085 | /* | |
1086 | * WaEnableHDMI8bpcBefore12bpc:snb,ivb | |
1087 | * | |
1088 | * The procedure for 12bpc is as follows: | |
1089 | * 1. disable HDMI clock gating | |
1090 | * 2. enable HDMI with 8bpc | |
1091 | * 3. enable HDMI with 12bpc | |
1092 | * 4. enable HDMI clock gating | |
1093 | */ | |
1094 | ||
df18e721 | 1095 | if (pipe_config->pipe_bpp > 24) { |
d1b1589c VS |
1096 | I915_WRITE(TRANS_CHICKEN1(pipe), |
1097 | I915_READ(TRANS_CHICKEN1(pipe)) | | |
1098 | TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE); | |
1099 | ||
1100 | temp &= ~SDVO_COLOR_FORMAT_MASK; | |
1101 | temp |= SDVO_COLOR_FORMAT_8bpc; | |
c1dec79a | 1102 | } |
d1b1589c VS |
1103 | |
1104 | I915_WRITE(intel_hdmi->hdmi_reg, temp); | |
1105 | POSTING_READ(intel_hdmi->hdmi_reg); | |
1106 | ||
df18e721 | 1107 | if (pipe_config->pipe_bpp > 24) { |
d1b1589c VS |
1108 | temp &= ~SDVO_COLOR_FORMAT_MASK; |
1109 | temp |= HDMI_COLOR_FORMAT_12bpc; | |
1110 | ||
1111 | I915_WRITE(intel_hdmi->hdmi_reg, temp); | |
1112 | POSTING_READ(intel_hdmi->hdmi_reg); | |
1113 | ||
1114 | I915_WRITE(TRANS_CHICKEN1(pipe), | |
1115 | I915_READ(TRANS_CHICKEN1(pipe)) & | |
1116 | ~TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE); | |
1117 | } | |
1118 | ||
df18e721 ML |
1119 | if (pipe_config->has_audio) |
1120 | intel_enable_hdmi_audio(encoder, pipe_config, conn_state); | |
b76cf76b | 1121 | } |
89b667f8 | 1122 | |
fd6bbda9 ML |
1123 | static void vlv_enable_hdmi(struct intel_encoder *encoder, |
1124 | struct intel_crtc_state *pipe_config, | |
1125 | struct drm_connector_state *conn_state) | |
b76cf76b | 1126 | { |
5ab432ef DV |
1127 | } |
1128 | ||
fd6bbda9 ML |
1129 | static void intel_disable_hdmi(struct intel_encoder *encoder, |
1130 | struct intel_crtc_state *old_crtc_state, | |
1131 | struct drm_connector_state *old_conn_state) | |
5ab432ef DV |
1132 | { |
1133 | struct drm_device *dev = encoder->base.dev; | |
fac5e23e | 1134 | struct drm_i915_private *dev_priv = to_i915(dev); |
5ab432ef | 1135 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); |
ac240288 | 1136 | struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc); |
5ab432ef | 1137 | u32 temp; |
5ab432ef | 1138 | |
b242b7f7 | 1139 | temp = I915_READ(intel_hdmi->hdmi_reg); |
5ab432ef | 1140 | |
1612c8bd | 1141 | temp &= ~(SDVO_ENABLE | SDVO_AUDIO_ENABLE); |
b242b7f7 PZ |
1142 | I915_WRITE(intel_hdmi->hdmi_reg, temp); |
1143 | POSTING_READ(intel_hdmi->hdmi_reg); | |
1612c8bd VS |
1144 | |
1145 | /* | |
1146 | * HW workaround for IBX, we need to move the port | |
1147 | * to transcoder A after disabling it to allow the | |
1148 | * matching DP port to be enabled on transcoder A. | |
1149 | */ | |
6e266956 | 1150 | if (HAS_PCH_IBX(dev_priv) && crtc->pipe == PIPE_B) { |
0c241d5b VS |
1151 | /* |
1152 | * We get CPU/PCH FIFO underruns on the other pipe when | |
1153 | * doing the workaround. Sweep them under the rug. | |
1154 | */ | |
1155 | intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, false); | |
1156 | intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false); | |
1157 | ||
1612c8bd VS |
1158 | temp &= ~SDVO_PIPE_B_SELECT; |
1159 | temp |= SDVO_ENABLE; | |
1160 | /* | |
1161 | * HW workaround, need to write this twice for issue | |
1162 | * that may result in first write getting masked. | |
1163 | */ | |
1164 | I915_WRITE(intel_hdmi->hdmi_reg, temp); | |
1165 | POSTING_READ(intel_hdmi->hdmi_reg); | |
1166 | I915_WRITE(intel_hdmi->hdmi_reg, temp); | |
1167 | POSTING_READ(intel_hdmi->hdmi_reg); | |
1168 | ||
1169 | temp &= ~SDVO_ENABLE; | |
1170 | I915_WRITE(intel_hdmi->hdmi_reg, temp); | |
1171 | POSTING_READ(intel_hdmi->hdmi_reg); | |
0c241d5b | 1172 | |
0f0f74bc | 1173 | intel_wait_for_vblank_if_active(dev_priv, PIPE_A); |
0c241d5b VS |
1174 | intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true); |
1175 | intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true); | |
1612c8bd | 1176 | } |
6d67415f | 1177 | |
ac240288 | 1178 | intel_hdmi->set_infoframes(&encoder->base, false, old_crtc_state, old_conn_state); |
b2ccb822 VS |
1179 | |
1180 | intel_dp_dual_mode_set_tmds_output(intel_hdmi, false); | |
7d57382e EA |
1181 | } |
1182 | ||
fd6bbda9 ML |
1183 | static void g4x_disable_hdmi(struct intel_encoder *encoder, |
1184 | struct intel_crtc_state *old_crtc_state, | |
1185 | struct drm_connector_state *old_conn_state) | |
a4790cec | 1186 | { |
df18e721 | 1187 | if (old_crtc_state->has_audio) |
a4790cec VS |
1188 | intel_audio_codec_disable(encoder); |
1189 | ||
fd6bbda9 | 1190 | intel_disable_hdmi(encoder, old_crtc_state, old_conn_state); |
a4790cec VS |
1191 | } |
1192 | ||
fd6bbda9 ML |
1193 | static void pch_disable_hdmi(struct intel_encoder *encoder, |
1194 | struct intel_crtc_state *old_crtc_state, | |
1195 | struct drm_connector_state *old_conn_state) | |
a4790cec | 1196 | { |
df18e721 | 1197 | if (old_crtc_state->has_audio) |
a4790cec VS |
1198 | intel_audio_codec_disable(encoder); |
1199 | } | |
1200 | ||
fd6bbda9 ML |
1201 | static void pch_post_disable_hdmi(struct intel_encoder *encoder, |
1202 | struct intel_crtc_state *old_crtc_state, | |
1203 | struct drm_connector_state *old_conn_state) | |
a4790cec | 1204 | { |
fd6bbda9 | 1205 | intel_disable_hdmi(encoder, old_crtc_state, old_conn_state); |
a4790cec VS |
1206 | } |
1207 | ||
b1ba124d | 1208 | static int intel_hdmi_source_max_tmds_clock(struct drm_i915_private *dev_priv) |
7d148ef5 | 1209 | { |
b1ba124d | 1210 | if (IS_G4X(dev_priv)) |
7d148ef5 | 1211 | return 165000; |
b1ba124d | 1212 | else if (IS_HASWELL(dev_priv) || INTEL_INFO(dev_priv)->gen >= 8) |
7d148ef5 DV |
1213 | return 300000; |
1214 | else | |
1215 | return 225000; | |
1216 | } | |
1217 | ||
b1ba124d VS |
1218 | static int hdmi_port_clock_limit(struct intel_hdmi *hdmi, |
1219 | bool respect_downstream_limits) | |
1220 | { | |
1221 | struct drm_device *dev = intel_hdmi_to_dev(hdmi); | |
1222 | int max_tmds_clock = intel_hdmi_source_max_tmds_clock(to_i915(dev)); | |
1223 | ||
1224 | if (respect_downstream_limits) { | |
8cadab0a VS |
1225 | struct intel_connector *connector = hdmi->attached_connector; |
1226 | const struct drm_display_info *info = &connector->base.display_info; | |
1227 | ||
b1ba124d VS |
1228 | if (hdmi->dp_dual_mode.max_tmds_clock) |
1229 | max_tmds_clock = min(max_tmds_clock, | |
1230 | hdmi->dp_dual_mode.max_tmds_clock); | |
8cadab0a VS |
1231 | |
1232 | if (info->max_tmds_clock) | |
1233 | max_tmds_clock = min(max_tmds_clock, | |
1234 | info->max_tmds_clock); | |
1235 | else if (!hdmi->has_hdmi_sink) | |
b1ba124d VS |
1236 | max_tmds_clock = min(max_tmds_clock, 165000); |
1237 | } | |
1238 | ||
1239 | return max_tmds_clock; | |
1240 | } | |
1241 | ||
e64e739e VS |
1242 | static enum drm_mode_status |
1243 | hdmi_port_clock_valid(struct intel_hdmi *hdmi, | |
b1ba124d | 1244 | int clock, bool respect_downstream_limits) |
e64e739e | 1245 | { |
e2d214ae | 1246 | struct drm_i915_private *dev_priv = to_i915(intel_hdmi_to_dev(hdmi)); |
e64e739e VS |
1247 | |
1248 | if (clock < 25000) | |
1249 | return MODE_CLOCK_LOW; | |
b1ba124d | 1250 | if (clock > hdmi_port_clock_limit(hdmi, respect_downstream_limits)) |
e64e739e VS |
1251 | return MODE_CLOCK_HIGH; |
1252 | ||
5e6ccc0b | 1253 | /* BXT DPLL can't generate 223-240 MHz */ |
cc3f90f0 | 1254 | if (IS_GEN9_LP(dev_priv) && clock > 223333 && clock < 240000) |
5e6ccc0b VS |
1255 | return MODE_CLOCK_RANGE; |
1256 | ||
1257 | /* CHV DPLL can't generate 216-240 MHz */ | |
e2d214ae | 1258 | if (IS_CHERRYVIEW(dev_priv) && clock > 216000 && clock < 240000) |
e64e739e VS |
1259 | return MODE_CLOCK_RANGE; |
1260 | ||
1261 | return MODE_OK; | |
1262 | } | |
1263 | ||
c19de8eb DL |
1264 | static enum drm_mode_status |
1265 | intel_hdmi_mode_valid(struct drm_connector *connector, | |
1266 | struct drm_display_mode *mode) | |
7d57382e | 1267 | { |
e64e739e VS |
1268 | struct intel_hdmi *hdmi = intel_attached_hdmi(connector); |
1269 | struct drm_device *dev = intel_hdmi_to_dev(hdmi); | |
49cff963 | 1270 | struct drm_i915_private *dev_priv = to_i915(dev); |
e64e739e VS |
1271 | enum drm_mode_status status; |
1272 | int clock; | |
587bf496 | 1273 | int max_dotclk = to_i915(connector->dev)->max_dotclk_freq; |
e64e739e VS |
1274 | |
1275 | if (mode->flags & DRM_MODE_FLAG_DBLSCAN) | |
1276 | return MODE_NO_DBLESCAN; | |
697c4078 | 1277 | |
e64e739e | 1278 | clock = mode->clock; |
587bf496 MK |
1279 | |
1280 | if ((mode->flags & DRM_MODE_FLAG_3D_MASK) == DRM_MODE_FLAG_3D_FRAME_PACKING) | |
1281 | clock *= 2; | |
1282 | ||
1283 | if (clock > max_dotclk) | |
1284 | return MODE_CLOCK_HIGH; | |
1285 | ||
697c4078 CT |
1286 | if (mode->flags & DRM_MODE_FLAG_DBLCLK) |
1287 | clock *= 2; | |
1288 | ||
e64e739e VS |
1289 | /* check if we can do 8bpc */ |
1290 | status = hdmi_port_clock_valid(hdmi, clock, true); | |
7d57382e | 1291 | |
e64e739e | 1292 | /* if we can't do 8bpc we may still be able to do 12bpc */ |
49cff963 | 1293 | if (!HAS_GMCH_DISPLAY(dev_priv) && status != MODE_OK) |
e64e739e | 1294 | status = hdmi_port_clock_valid(hdmi, clock * 3 / 2, true); |
7d57382e | 1295 | |
e64e739e | 1296 | return status; |
7d57382e EA |
1297 | } |
1298 | ||
77f06c86 | 1299 | static bool hdmi_12bpc_possible(struct intel_crtc_state *crtc_state) |
71800632 | 1300 | { |
9c31b087 VS |
1301 | struct drm_i915_private *dev_priv = |
1302 | to_i915(crtc_state->base.crtc->dev); | |
1303 | struct drm_atomic_state *state = crtc_state->base.state; | |
1304 | struct drm_connector_state *connector_state; | |
1305 | struct drm_connector *connector; | |
1306 | int i; | |
71800632 | 1307 | |
9c31b087 | 1308 | if (HAS_GMCH_DISPLAY(dev_priv)) |
71800632 VS |
1309 | return false; |
1310 | ||
71800632 VS |
1311 | /* |
1312 | * HDMI 12bpc affects the clocks, so it's only possible | |
1313 | * when not cloning with other encoder types. | |
1314 | */ | |
9c31b087 VS |
1315 | if (crtc_state->output_types != 1 << INTEL_OUTPUT_HDMI) |
1316 | return false; | |
1317 | ||
1318 | for_each_connector_in_state(state, connector, connector_state, i) { | |
1319 | const struct drm_display_info *info = &connector->display_info; | |
1320 | ||
1321 | if (connector_state->crtc != crtc_state->base.crtc) | |
1322 | continue; | |
1323 | ||
1324 | if ((info->edid_hdmi_dc_modes & DRM_EDID_HDMI_DC_36) == 0) | |
1325 | return false; | |
1326 | } | |
1327 | ||
1328 | return true; | |
71800632 VS |
1329 | } |
1330 | ||
5bfe2ac0 | 1331 | bool intel_hdmi_compute_config(struct intel_encoder *encoder, |
0a478c27 ML |
1332 | struct intel_crtc_state *pipe_config, |
1333 | struct drm_connector_state *conn_state) | |
7d57382e | 1334 | { |
5bfe2ac0 | 1335 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); |
4f8036a2 | 1336 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
2d112de7 | 1337 | struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; |
e64e739e VS |
1338 | int clock_8bpc = pipe_config->base.adjusted_mode.crtc_clock; |
1339 | int clock_12bpc = clock_8bpc * 3 / 2; | |
e29c22c0 | 1340 | int desired_bpp; |
3685a8f3 | 1341 | |
6897b4b5 DV |
1342 | pipe_config->has_hdmi_sink = intel_hdmi->has_hdmi_sink; |
1343 | ||
e43823ec JB |
1344 | if (pipe_config->has_hdmi_sink) |
1345 | pipe_config->has_infoframe = true; | |
1346 | ||
55bc60db VS |
1347 | if (intel_hdmi->color_range_auto) { |
1348 | /* See CEA-861-E - 5.1 Default Encoding Parameters */ | |
0f2a2a75 VS |
1349 | pipe_config->limited_color_range = |
1350 | pipe_config->has_hdmi_sink && | |
c8127cf0 VS |
1351 | drm_default_rgb_quant_range(adjusted_mode) == |
1352 | HDMI_QUANTIZATION_RANGE_LIMITED; | |
0f2a2a75 VS |
1353 | } else { |
1354 | pipe_config->limited_color_range = | |
1355 | intel_hdmi->limited_color_range; | |
55bc60db VS |
1356 | } |
1357 | ||
697c4078 CT |
1358 | if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK) { |
1359 | pipe_config->pixel_multiplier = 2; | |
e64e739e | 1360 | clock_8bpc *= 2; |
3320e37f | 1361 | clock_12bpc *= 2; |
697c4078 CT |
1362 | } |
1363 | ||
4f8036a2 | 1364 | if (HAS_PCH_SPLIT(dev_priv) && !HAS_DDI(dev_priv)) |
5bfe2ac0 DV |
1365 | pipe_config->has_pch_encoder = true; |
1366 | ||
9ed109a7 DV |
1367 | if (pipe_config->has_hdmi_sink && intel_hdmi->has_audio) |
1368 | pipe_config->has_audio = true; | |
1369 | ||
4e53c2e0 DV |
1370 | /* |
1371 | * HDMI is either 12 or 8, so if the display lets 10bpc sneak | |
1372 | * through, clamp it down. Note that g4x/vlv don't support 12bpc hdmi | |
325b9d04 DV |
1373 | * outputs. We also need to check that the higher clock still fits |
1374 | * within limits. | |
4e53c2e0 | 1375 | */ |
6897b4b5 | 1376 | if (pipe_config->pipe_bpp > 8*3 && pipe_config->has_hdmi_sink && |
b1ba124d | 1377 | hdmi_port_clock_valid(intel_hdmi, clock_12bpc, true) == MODE_OK && |
7a0baa62 | 1378 | hdmi_12bpc_possible(pipe_config)) { |
e29c22c0 DV |
1379 | DRM_DEBUG_KMS("picking bpc to 12 for HDMI output\n"); |
1380 | desired_bpp = 12*3; | |
325b9d04 DV |
1381 | |
1382 | /* Need to adjust the port link by 1.5x for 12bpc. */ | |
ff9a6750 | 1383 | pipe_config->port_clock = clock_12bpc; |
4e53c2e0 | 1384 | } else { |
e29c22c0 DV |
1385 | DRM_DEBUG_KMS("picking bpc to 8 for HDMI output\n"); |
1386 | desired_bpp = 8*3; | |
e64e739e VS |
1387 | |
1388 | pipe_config->port_clock = clock_8bpc; | |
e29c22c0 DV |
1389 | } |
1390 | ||
1391 | if (!pipe_config->bw_constrained) { | |
1392 | DRM_DEBUG_KMS("forcing pipe bpc to %i for HDMI\n", desired_bpp); | |
1393 | pipe_config->pipe_bpp = desired_bpp; | |
4e53c2e0 DV |
1394 | } |
1395 | ||
e64e739e VS |
1396 | if (hdmi_port_clock_valid(intel_hdmi, pipe_config->port_clock, |
1397 | false) != MODE_OK) { | |
1398 | DRM_DEBUG_KMS("unsupported HDMI clock, rejecting mode\n"); | |
325b9d04 DV |
1399 | return false; |
1400 | } | |
1401 | ||
28b468a0 VS |
1402 | /* Set user selected PAR to incoming mode's member */ |
1403 | adjusted_mode->picture_aspect_ratio = intel_hdmi->aspect_ratio; | |
1404 | ||
d4d6279a ACO |
1405 | pipe_config->lane_count = 4; |
1406 | ||
7d57382e EA |
1407 | return true; |
1408 | } | |
1409 | ||
953ece69 CW |
1410 | static void |
1411 | intel_hdmi_unset_edid(struct drm_connector *connector) | |
9dff6af8 | 1412 | { |
df0e9248 | 1413 | struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); |
9dff6af8 | 1414 | |
953ece69 CW |
1415 | intel_hdmi->has_hdmi_sink = false; |
1416 | intel_hdmi->has_audio = false; | |
1417 | intel_hdmi->rgb_quant_range_selectable = false; | |
1418 | ||
b1ba124d VS |
1419 | intel_hdmi->dp_dual_mode.type = DRM_DP_DUAL_MODE_NONE; |
1420 | intel_hdmi->dp_dual_mode.max_tmds_clock = 0; | |
1421 | ||
953ece69 CW |
1422 | kfree(to_intel_connector(connector)->detect_edid); |
1423 | to_intel_connector(connector)->detect_edid = NULL; | |
1424 | } | |
1425 | ||
b1ba124d | 1426 | static void |
d6199256 | 1427 | intel_hdmi_dp_dual_mode_detect(struct drm_connector *connector, bool has_edid) |
b1ba124d VS |
1428 | { |
1429 | struct drm_i915_private *dev_priv = to_i915(connector->dev); | |
1430 | struct intel_hdmi *hdmi = intel_attached_hdmi(connector); | |
d6199256 | 1431 | enum port port = hdmi_to_dig_port(hdmi)->port; |
b1ba124d VS |
1432 | struct i2c_adapter *adapter = |
1433 | intel_gmbus_get_adapter(dev_priv, hdmi->ddc_bus); | |
1434 | enum drm_dp_dual_mode_type type = drm_dp_dual_mode_detect(adapter); | |
1435 | ||
d6199256 VS |
1436 | /* |
1437 | * Type 1 DVI adaptors are not required to implement any | |
1438 | * registers, so we can't always detect their presence. | |
1439 | * Ideally we should be able to check the state of the | |
1440 | * CONFIG1 pin, but no such luck on our hardware. | |
1441 | * | |
1442 | * The only method left to us is to check the VBT to see | |
1443 | * if the port is a dual mode capable DP port. But let's | |
1444 | * only do that when we sucesfully read the EDID, to avoid | |
1445 | * confusing log messages about DP dual mode adaptors when | |
1446 | * there's nothing connected to the port. | |
1447 | */ | |
1448 | if (type == DRM_DP_DUAL_MODE_UNKNOWN) { | |
1449 | if (has_edid && | |
1450 | intel_bios_is_port_dp_dual_mode(dev_priv, port)) { | |
1451 | DRM_DEBUG_KMS("Assuming DP dual mode adaptor presence based on VBT\n"); | |
1452 | type = DRM_DP_DUAL_MODE_TYPE1_DVI; | |
1453 | } else { | |
1454 | type = DRM_DP_DUAL_MODE_NONE; | |
1455 | } | |
1456 | } | |
1457 | ||
1458 | if (type == DRM_DP_DUAL_MODE_NONE) | |
b1ba124d VS |
1459 | return; |
1460 | ||
1461 | hdmi->dp_dual_mode.type = type; | |
1462 | hdmi->dp_dual_mode.max_tmds_clock = | |
1463 | drm_dp_dual_mode_max_tmds_clock(type, adapter); | |
1464 | ||
1465 | DRM_DEBUG_KMS("DP dual mode adaptor (%s) detected (max TMDS clock: %d kHz)\n", | |
1466 | drm_dp_get_dual_mode_type_name(type), | |
1467 | hdmi->dp_dual_mode.max_tmds_clock); | |
1468 | } | |
1469 | ||
953ece69 | 1470 | static bool |
23f889bd | 1471 | intel_hdmi_set_edid(struct drm_connector *connector) |
953ece69 CW |
1472 | { |
1473 | struct drm_i915_private *dev_priv = to_i915(connector->dev); | |
1474 | struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); | |
23f889bd | 1475 | struct edid *edid; |
953ece69 | 1476 | bool connected = false; |
164c8598 | 1477 | |
23f889bd | 1478 | intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS); |
671dedd2 | 1479 | |
23f889bd DW |
1480 | edid = drm_get_edid(connector, |
1481 | intel_gmbus_get_adapter(dev_priv, | |
1482 | intel_hdmi->ddc_bus)); | |
2ded9e27 | 1483 | |
23f889bd | 1484 | intel_hdmi_dp_dual_mode_detect(connector, edid != NULL); |
b1ba124d | 1485 | |
23f889bd | 1486 | intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS); |
30ad48b7 | 1487 | |
953ece69 CW |
1488 | to_intel_connector(connector)->detect_edid = edid; |
1489 | if (edid && edid->input & DRM_EDID_INPUT_DIGITAL) { | |
1490 | intel_hdmi->rgb_quant_range_selectable = | |
1491 | drm_rgb_quant_range_selectable(edid); | |
1492 | ||
1493 | intel_hdmi->has_audio = drm_detect_monitor_audio(edid); | |
b1d7e4b4 WF |
1494 | if (intel_hdmi->force_audio != HDMI_AUDIO_AUTO) |
1495 | intel_hdmi->has_audio = | |
953ece69 CW |
1496 | intel_hdmi->force_audio == HDMI_AUDIO_ON; |
1497 | ||
1498 | if (intel_hdmi->force_audio != HDMI_AUDIO_OFF_DVI) | |
1499 | intel_hdmi->has_hdmi_sink = | |
1500 | drm_detect_hdmi_monitor(edid); | |
1501 | ||
1502 | connected = true; | |
55b7d6e8 CW |
1503 | } |
1504 | ||
953ece69 CW |
1505 | return connected; |
1506 | } | |
1507 | ||
8166fcea DV |
1508 | static enum drm_connector_status |
1509 | intel_hdmi_detect(struct drm_connector *connector, bool force) | |
953ece69 | 1510 | { |
8166fcea | 1511 | enum drm_connector_status status; |
8166fcea | 1512 | struct drm_i915_private *dev_priv = to_i915(connector->dev); |
953ece69 | 1513 | |
8166fcea DV |
1514 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", |
1515 | connector->base.id, connector->name); | |
1516 | ||
29bb94bb ID |
1517 | intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS); |
1518 | ||
8166fcea | 1519 | intel_hdmi_unset_edid(connector); |
0b5e88dc | 1520 | |
23f889bd | 1521 | if (intel_hdmi_set_edid(connector)) { |
953ece69 CW |
1522 | struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); |
1523 | ||
1524 | hdmi_to_dig_port(intel_hdmi)->base.type = INTEL_OUTPUT_HDMI; | |
1525 | status = connector_status_connected; | |
8166fcea | 1526 | } else |
953ece69 | 1527 | status = connector_status_disconnected; |
671dedd2 | 1528 | |
29bb94bb ID |
1529 | intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS); |
1530 | ||
2ded9e27 | 1531 | return status; |
7d57382e EA |
1532 | } |
1533 | ||
953ece69 CW |
1534 | static void |
1535 | intel_hdmi_force(struct drm_connector *connector) | |
7d57382e | 1536 | { |
953ece69 | 1537 | struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); |
7d57382e | 1538 | |
953ece69 CW |
1539 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", |
1540 | connector->base.id, connector->name); | |
7d57382e | 1541 | |
953ece69 | 1542 | intel_hdmi_unset_edid(connector); |
671dedd2 | 1543 | |
953ece69 CW |
1544 | if (connector->status != connector_status_connected) |
1545 | return; | |
671dedd2 | 1546 | |
23f889bd | 1547 | intel_hdmi_set_edid(connector); |
953ece69 CW |
1548 | hdmi_to_dig_port(intel_hdmi)->base.type = INTEL_OUTPUT_HDMI; |
1549 | } | |
671dedd2 | 1550 | |
953ece69 CW |
1551 | static int intel_hdmi_get_modes(struct drm_connector *connector) |
1552 | { | |
1553 | struct edid *edid; | |
1554 | ||
1555 | edid = to_intel_connector(connector)->detect_edid; | |
1556 | if (edid == NULL) | |
1557 | return 0; | |
671dedd2 | 1558 | |
953ece69 | 1559 | return intel_connector_update_modes(connector, edid); |
7d57382e EA |
1560 | } |
1561 | ||
1aad7ac0 CW |
1562 | static bool |
1563 | intel_hdmi_detect_audio(struct drm_connector *connector) | |
1564 | { | |
1aad7ac0 | 1565 | bool has_audio = false; |
953ece69 | 1566 | struct edid *edid; |
1aad7ac0 | 1567 | |
953ece69 CW |
1568 | edid = to_intel_connector(connector)->detect_edid; |
1569 | if (edid && edid->input & DRM_EDID_INPUT_DIGITAL) | |
1570 | has_audio = drm_detect_monitor_audio(edid); | |
671dedd2 | 1571 | |
1aad7ac0 CW |
1572 | return has_audio; |
1573 | } | |
1574 | ||
55b7d6e8 CW |
1575 | static int |
1576 | intel_hdmi_set_property(struct drm_connector *connector, | |
ed517fbb PZ |
1577 | struct drm_property *property, |
1578 | uint64_t val) | |
55b7d6e8 CW |
1579 | { |
1580 | struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); | |
da63a9f2 PZ |
1581 | struct intel_digital_port *intel_dig_port = |
1582 | hdmi_to_dig_port(intel_hdmi); | |
fac5e23e | 1583 | struct drm_i915_private *dev_priv = to_i915(connector->dev); |
55b7d6e8 CW |
1584 | int ret; |
1585 | ||
662595df | 1586 | ret = drm_object_property_set_value(&connector->base, property, val); |
55b7d6e8 CW |
1587 | if (ret) |
1588 | return ret; | |
1589 | ||
3f43c48d | 1590 | if (property == dev_priv->force_audio_property) { |
b1d7e4b4 | 1591 | enum hdmi_force_audio i = val; |
1aad7ac0 CW |
1592 | bool has_audio; |
1593 | ||
1594 | if (i == intel_hdmi->force_audio) | |
55b7d6e8 CW |
1595 | return 0; |
1596 | ||
1aad7ac0 | 1597 | intel_hdmi->force_audio = i; |
55b7d6e8 | 1598 | |
b1d7e4b4 | 1599 | if (i == HDMI_AUDIO_AUTO) |
1aad7ac0 CW |
1600 | has_audio = intel_hdmi_detect_audio(connector); |
1601 | else | |
b1d7e4b4 | 1602 | has_audio = (i == HDMI_AUDIO_ON); |
1aad7ac0 | 1603 | |
b1d7e4b4 WF |
1604 | if (i == HDMI_AUDIO_OFF_DVI) |
1605 | intel_hdmi->has_hdmi_sink = 0; | |
55b7d6e8 | 1606 | |
1aad7ac0 | 1607 | intel_hdmi->has_audio = has_audio; |
55b7d6e8 CW |
1608 | goto done; |
1609 | } | |
1610 | ||
e953fd7b | 1611 | if (property == dev_priv->broadcast_rgb_property) { |
ae4edb80 | 1612 | bool old_auto = intel_hdmi->color_range_auto; |
0f2a2a75 | 1613 | bool old_range = intel_hdmi->limited_color_range; |
ae4edb80 | 1614 | |
55bc60db VS |
1615 | switch (val) { |
1616 | case INTEL_BROADCAST_RGB_AUTO: | |
1617 | intel_hdmi->color_range_auto = true; | |
1618 | break; | |
1619 | case INTEL_BROADCAST_RGB_FULL: | |
1620 | intel_hdmi->color_range_auto = false; | |
0f2a2a75 | 1621 | intel_hdmi->limited_color_range = false; |
55bc60db VS |
1622 | break; |
1623 | case INTEL_BROADCAST_RGB_LIMITED: | |
1624 | intel_hdmi->color_range_auto = false; | |
0f2a2a75 | 1625 | intel_hdmi->limited_color_range = true; |
55bc60db VS |
1626 | break; |
1627 | default: | |
1628 | return -EINVAL; | |
1629 | } | |
ae4edb80 DV |
1630 | |
1631 | if (old_auto == intel_hdmi->color_range_auto && | |
0f2a2a75 | 1632 | old_range == intel_hdmi->limited_color_range) |
ae4edb80 DV |
1633 | return 0; |
1634 | ||
e953fd7b CW |
1635 | goto done; |
1636 | } | |
1637 | ||
94a11ddc VK |
1638 | if (property == connector->dev->mode_config.aspect_ratio_property) { |
1639 | switch (val) { | |
1640 | case DRM_MODE_PICTURE_ASPECT_NONE: | |
1641 | intel_hdmi->aspect_ratio = HDMI_PICTURE_ASPECT_NONE; | |
1642 | break; | |
1643 | case DRM_MODE_PICTURE_ASPECT_4_3: | |
1644 | intel_hdmi->aspect_ratio = HDMI_PICTURE_ASPECT_4_3; | |
1645 | break; | |
1646 | case DRM_MODE_PICTURE_ASPECT_16_9: | |
1647 | intel_hdmi->aspect_ratio = HDMI_PICTURE_ASPECT_16_9; | |
1648 | break; | |
1649 | default: | |
1650 | return -EINVAL; | |
1651 | } | |
1652 | goto done; | |
1653 | } | |
1654 | ||
55b7d6e8 CW |
1655 | return -EINVAL; |
1656 | ||
1657 | done: | |
c0c36b94 CW |
1658 | if (intel_dig_port->base.base.crtc) |
1659 | intel_crtc_restore_mode(intel_dig_port->base.base.crtc); | |
55b7d6e8 CW |
1660 | |
1661 | return 0; | |
1662 | } | |
1663 | ||
fd6bbda9 ML |
1664 | static void intel_hdmi_pre_enable(struct intel_encoder *encoder, |
1665 | struct intel_crtc_state *pipe_config, | |
1666 | struct drm_connector_state *conn_state) | |
13732ba7 JB |
1667 | { |
1668 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); | |
13732ba7 | 1669 | |
ac240288 | 1670 | intel_hdmi_prepare(encoder, pipe_config); |
4cde8a21 | 1671 | |
6897b4b5 | 1672 | intel_hdmi->set_infoframes(&encoder->base, |
df18e721 | 1673 | pipe_config->has_hdmi_sink, |
ac240288 | 1674 | pipe_config, conn_state); |
13732ba7 JB |
1675 | } |
1676 | ||
fd6bbda9 ML |
1677 | static void vlv_hdmi_pre_enable(struct intel_encoder *encoder, |
1678 | struct intel_crtc_state *pipe_config, | |
1679 | struct drm_connector_state *conn_state) | |
89b667f8 JB |
1680 | { |
1681 | struct intel_digital_port *dport = enc_to_dig_port(&encoder->base); | |
13732ba7 | 1682 | struct intel_hdmi *intel_hdmi = &dport->hdmi; |
89b667f8 | 1683 | struct drm_device *dev = encoder->base.dev; |
fac5e23e | 1684 | struct drm_i915_private *dev_priv = to_i915(dev); |
5f68c275 ACO |
1685 | |
1686 | vlv_phy_pre_encoder_enable(encoder); | |
b76cf76b | 1687 | |
53d98725 ACO |
1688 | /* HDMI 1.0V-2dB */ |
1689 | vlv_set_phy_signal_level(encoder, 0x2b245f5f, 0x00002000, 0x5578b83a, | |
1690 | 0x2b247878); | |
1691 | ||
6897b4b5 | 1692 | intel_hdmi->set_infoframes(&encoder->base, |
df18e721 | 1693 | pipe_config->has_hdmi_sink, |
ac240288 | 1694 | pipe_config, conn_state); |
13732ba7 | 1695 | |
fd6bbda9 | 1696 | g4x_enable_hdmi(encoder, pipe_config, conn_state); |
b76cf76b | 1697 | |
9b6de0a1 | 1698 | vlv_wait_port_ready(dev_priv, dport, 0x0); |
89b667f8 JB |
1699 | } |
1700 | ||
fd6bbda9 ML |
1701 | static void vlv_hdmi_pre_pll_enable(struct intel_encoder *encoder, |
1702 | struct intel_crtc_state *pipe_config, | |
1703 | struct drm_connector_state *conn_state) | |
89b667f8 | 1704 | { |
ac240288 | 1705 | intel_hdmi_prepare(encoder, pipe_config); |
4cde8a21 | 1706 | |
6da2e616 | 1707 | vlv_phy_pre_pll_enable(encoder); |
89b667f8 JB |
1708 | } |
1709 | ||
fd6bbda9 ML |
1710 | static void chv_hdmi_pre_pll_enable(struct intel_encoder *encoder, |
1711 | struct intel_crtc_state *pipe_config, | |
1712 | struct drm_connector_state *conn_state) | |
9197c88b | 1713 | { |
ac240288 | 1714 | intel_hdmi_prepare(encoder, pipe_config); |
625695f8 | 1715 | |
419b1b7a | 1716 | chv_phy_pre_pll_enable(encoder); |
9197c88b VS |
1717 | } |
1718 | ||
fd6bbda9 ML |
1719 | static void chv_hdmi_post_pll_disable(struct intel_encoder *encoder, |
1720 | struct intel_crtc_state *old_crtc_state, | |
1721 | struct drm_connector_state *old_conn_state) | |
d6db995f | 1722 | { |
204970b5 | 1723 | chv_phy_post_pll_disable(encoder); |
d6db995f VS |
1724 | } |
1725 | ||
fd6bbda9 ML |
1726 | static void vlv_hdmi_post_disable(struct intel_encoder *encoder, |
1727 | struct intel_crtc_state *old_crtc_state, | |
1728 | struct drm_connector_state *old_conn_state) | |
89b667f8 | 1729 | { |
89b667f8 | 1730 | /* Reset lanes to avoid HDMI flicker (VLV w/a) */ |
0f572ebe | 1731 | vlv_phy_reset_lanes(encoder); |
89b667f8 JB |
1732 | } |
1733 | ||
fd6bbda9 ML |
1734 | static void chv_hdmi_post_disable(struct intel_encoder *encoder, |
1735 | struct intel_crtc_state *old_crtc_state, | |
1736 | struct drm_connector_state *old_conn_state) | |
580d3811 | 1737 | { |
580d3811 | 1738 | struct drm_device *dev = encoder->base.dev; |
fac5e23e | 1739 | struct drm_i915_private *dev_priv = to_i915(dev); |
580d3811 | 1740 | |
a580516d | 1741 | mutex_lock(&dev_priv->sb_lock); |
580d3811 | 1742 | |
a8f327fb VS |
1743 | /* Assert data lane reset */ |
1744 | chv_data_lane_soft_reset(encoder, true); | |
580d3811 | 1745 | |
a580516d | 1746 | mutex_unlock(&dev_priv->sb_lock); |
580d3811 VS |
1747 | } |
1748 | ||
fd6bbda9 ML |
1749 | static void chv_hdmi_pre_enable(struct intel_encoder *encoder, |
1750 | struct intel_crtc_state *pipe_config, | |
1751 | struct drm_connector_state *conn_state) | |
e4a1d846 CML |
1752 | { |
1753 | struct intel_digital_port *dport = enc_to_dig_port(&encoder->base); | |
b4eb1564 | 1754 | struct intel_hdmi *intel_hdmi = &dport->hdmi; |
e4a1d846 | 1755 | struct drm_device *dev = encoder->base.dev; |
fac5e23e | 1756 | struct drm_i915_private *dev_priv = to_i915(dev); |
2e523e98 | 1757 | |
e7d2a717 | 1758 | chv_phy_pre_encoder_enable(encoder); |
a02ef3c7 | 1759 | |
e4a1d846 CML |
1760 | /* FIXME: Program the support xxx V-dB */ |
1761 | /* Use 800mV-0dB */ | |
b7fa22d8 | 1762 | chv_set_phy_signal_level(encoder, 128, 102, false); |
e4a1d846 | 1763 | |
b4eb1564 | 1764 | intel_hdmi->set_infoframes(&encoder->base, |
ac240288 ML |
1765 | pipe_config->has_hdmi_sink, |
1766 | pipe_config, conn_state); | |
b4eb1564 | 1767 | |
fd6bbda9 | 1768 | g4x_enable_hdmi(encoder, pipe_config, conn_state); |
e4a1d846 | 1769 | |
9b6de0a1 | 1770 | vlv_wait_port_ready(dev_priv, dport, 0x0); |
b0b33846 VS |
1771 | |
1772 | /* Second common lane will stay alive on its own now */ | |
e7d2a717 | 1773 | chv_phy_release_cl2_override(encoder); |
e4a1d846 CML |
1774 | } |
1775 | ||
7d57382e EA |
1776 | static void intel_hdmi_destroy(struct drm_connector *connector) |
1777 | { | |
10e972d3 | 1778 | kfree(to_intel_connector(connector)->detect_edid); |
7d57382e | 1779 | drm_connector_cleanup(connector); |
674e2d08 | 1780 | kfree(connector); |
7d57382e EA |
1781 | } |
1782 | ||
7d57382e | 1783 | static const struct drm_connector_funcs intel_hdmi_connector_funcs = { |
4d688a2a | 1784 | .dpms = drm_atomic_helper_connector_dpms, |
7d57382e | 1785 | .detect = intel_hdmi_detect, |
953ece69 | 1786 | .force = intel_hdmi_force, |
7d57382e | 1787 | .fill_modes = drm_helper_probe_single_connector_modes, |
55b7d6e8 | 1788 | .set_property = intel_hdmi_set_property, |
2545e4a6 | 1789 | .atomic_get_property = intel_connector_atomic_get_property, |
1ebaa0b9 | 1790 | .late_register = intel_connector_register, |
c191eca1 | 1791 | .early_unregister = intel_connector_unregister, |
7d57382e | 1792 | .destroy = intel_hdmi_destroy, |
c6f95f27 | 1793 | .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, |
98969725 | 1794 | .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, |
7d57382e EA |
1795 | }; |
1796 | ||
1797 | static const struct drm_connector_helper_funcs intel_hdmi_connector_helper_funcs = { | |
1798 | .get_modes = intel_hdmi_get_modes, | |
1799 | .mode_valid = intel_hdmi_mode_valid, | |
7d57382e EA |
1800 | }; |
1801 | ||
7d57382e | 1802 | static const struct drm_encoder_funcs intel_hdmi_enc_funcs = { |
ea5b213a | 1803 | .destroy = intel_encoder_destroy, |
7d57382e EA |
1804 | }; |
1805 | ||
55b7d6e8 CW |
1806 | static void |
1807 | intel_hdmi_add_properties(struct intel_hdmi *intel_hdmi, struct drm_connector *connector) | |
1808 | { | |
3f43c48d | 1809 | intel_attach_force_audio_property(connector); |
e953fd7b | 1810 | intel_attach_broadcast_rgb_property(connector); |
55bc60db | 1811 | intel_hdmi->color_range_auto = true; |
94a11ddc VK |
1812 | intel_attach_aspect_ratio_property(connector); |
1813 | intel_hdmi->aspect_ratio = HDMI_PICTURE_ASPECT_NONE; | |
55b7d6e8 CW |
1814 | } |
1815 | ||
e4ab73a1 VS |
1816 | static u8 intel_hdmi_ddc_pin(struct drm_i915_private *dev_priv, |
1817 | enum port port) | |
1818 | { | |
1819 | const struct ddi_vbt_port_info *info = | |
1820 | &dev_priv->vbt.ddi_port_info[port]; | |
1821 | u8 ddc_pin; | |
1822 | ||
1823 | if (info->alternate_ddc_pin) { | |
1824 | DRM_DEBUG_KMS("Using DDC pin 0x%x for port %c (VBT)\n", | |
1825 | info->alternate_ddc_pin, port_name(port)); | |
1826 | return info->alternate_ddc_pin; | |
1827 | } | |
1828 | ||
1829 | switch (port) { | |
1830 | case PORT_B: | |
cc3f90f0 | 1831 | if (IS_GEN9_LP(dev_priv)) |
e4ab73a1 VS |
1832 | ddc_pin = GMBUS_PIN_1_BXT; |
1833 | else | |
1834 | ddc_pin = GMBUS_PIN_DPB; | |
1835 | break; | |
1836 | case PORT_C: | |
cc3f90f0 | 1837 | if (IS_GEN9_LP(dev_priv)) |
e4ab73a1 VS |
1838 | ddc_pin = GMBUS_PIN_2_BXT; |
1839 | else | |
1840 | ddc_pin = GMBUS_PIN_DPC; | |
1841 | break; | |
1842 | case PORT_D: | |
1843 | if (IS_CHERRYVIEW(dev_priv)) | |
1844 | ddc_pin = GMBUS_PIN_DPD_CHV; | |
1845 | else | |
1846 | ddc_pin = GMBUS_PIN_DPD; | |
1847 | break; | |
1848 | default: | |
1849 | MISSING_CASE(port); | |
1850 | ddc_pin = GMBUS_PIN_DPB; | |
1851 | break; | |
1852 | } | |
1853 | ||
1854 | DRM_DEBUG_KMS("Using DDC pin 0x%x for port %c (platform default)\n", | |
1855 | ddc_pin, port_name(port)); | |
1856 | ||
1857 | return ddc_pin; | |
1858 | } | |
1859 | ||
00c09d70 PZ |
1860 | void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port, |
1861 | struct intel_connector *intel_connector) | |
7d57382e | 1862 | { |
b9cb234c PZ |
1863 | struct drm_connector *connector = &intel_connector->base; |
1864 | struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi; | |
1865 | struct intel_encoder *intel_encoder = &intel_dig_port->base; | |
1866 | struct drm_device *dev = intel_encoder->base.dev; | |
fac5e23e | 1867 | struct drm_i915_private *dev_priv = to_i915(dev); |
174edf1f | 1868 | enum port port = intel_dig_port->port; |
373a3cf7 | 1869 | |
22f35042 VS |
1870 | DRM_DEBUG_KMS("Adding HDMI connector on port %c\n", |
1871 | port_name(port)); | |
1872 | ||
ccb1a831 VS |
1873 | if (WARN(intel_dig_port->max_lanes < 4, |
1874 | "Not enough lanes (%d) for HDMI on port %c\n", | |
1875 | intel_dig_port->max_lanes, port_name(port))) | |
1876 | return; | |
1877 | ||
7d57382e | 1878 | drm_connector_init(dev, connector, &intel_hdmi_connector_funcs, |
8d91104a | 1879 | DRM_MODE_CONNECTOR_HDMIA); |
7d57382e EA |
1880 | drm_connector_helper_add(connector, &intel_hdmi_connector_helper_funcs); |
1881 | ||
c3febcc4 | 1882 | connector->interlace_allowed = 1; |
7d57382e | 1883 | connector->doublescan_allowed = 0; |
573e74ad | 1884 | connector->stereo_allowed = 1; |
66a9278e | 1885 | |
e4ab73a1 VS |
1886 | intel_hdmi->ddc_bus = intel_hdmi_ddc_pin(dev_priv, port); |
1887 | ||
08d644ad DV |
1888 | switch (port) { |
1889 | case PORT_B: | |
cf1d5883 SJ |
1890 | /* |
1891 | * On BXT A0/A1, sw needs to activate DDIA HPD logic and | |
1892 | * interrupts to check the external panel connection. | |
1893 | */ | |
e87a005d | 1894 | if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) |
cf1d5883 SJ |
1895 | intel_encoder->hpd_pin = HPD_PORT_A; |
1896 | else | |
1897 | intel_encoder->hpd_pin = HPD_PORT_B; | |
08d644ad DV |
1898 | break; |
1899 | case PORT_C: | |
1d843f9d | 1900 | intel_encoder->hpd_pin = HPD_PORT_C; |
08d644ad DV |
1901 | break; |
1902 | case PORT_D: | |
1d843f9d | 1903 | intel_encoder->hpd_pin = HPD_PORT_D; |
08d644ad | 1904 | break; |
11c1b657 | 1905 | case PORT_E: |
11c1b657 XZ |
1906 | intel_encoder->hpd_pin = HPD_PORT_E; |
1907 | break; | |
08d644ad | 1908 | default: |
e4ab73a1 VS |
1909 | MISSING_CASE(port); |
1910 | return; | |
f8aed700 | 1911 | } |
7d57382e | 1912 | |
920a14b2 | 1913 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { |
90b107c8 | 1914 | intel_hdmi->write_infoframe = vlv_write_infoframe; |
687f4d06 | 1915 | intel_hdmi->set_infoframes = vlv_set_infoframes; |
e43823ec | 1916 | intel_hdmi->infoframe_enabled = vlv_infoframe_enabled; |
9beb5fea | 1917 | } else if (IS_G4X(dev_priv)) { |
7637bfdb JB |
1918 | intel_hdmi->write_infoframe = g4x_write_infoframe; |
1919 | intel_hdmi->set_infoframes = g4x_set_infoframes; | |
e43823ec | 1920 | intel_hdmi->infoframe_enabled = g4x_infoframe_enabled; |
4f8036a2 | 1921 | } else if (HAS_DDI(dev_priv)) { |
8c5f5f7c | 1922 | intel_hdmi->write_infoframe = hsw_write_infoframe; |
687f4d06 | 1923 | intel_hdmi->set_infoframes = hsw_set_infoframes; |
e43823ec | 1924 | intel_hdmi->infoframe_enabled = hsw_infoframe_enabled; |
6e266956 | 1925 | } else if (HAS_PCH_IBX(dev_priv)) { |
fdf1250a | 1926 | intel_hdmi->write_infoframe = ibx_write_infoframe; |
687f4d06 | 1927 | intel_hdmi->set_infoframes = ibx_set_infoframes; |
e43823ec | 1928 | intel_hdmi->infoframe_enabled = ibx_infoframe_enabled; |
fdf1250a PZ |
1929 | } else { |
1930 | intel_hdmi->write_infoframe = cpt_write_infoframe; | |
687f4d06 | 1931 | intel_hdmi->set_infoframes = cpt_set_infoframes; |
e43823ec | 1932 | intel_hdmi->infoframe_enabled = cpt_infoframe_enabled; |
64a8fc01 | 1933 | } |
45187ace | 1934 | |
4f8036a2 | 1935 | if (HAS_DDI(dev_priv)) |
bcbc889b PZ |
1936 | intel_connector->get_hw_state = intel_ddi_connector_get_hw_state; |
1937 | else | |
1938 | intel_connector->get_hw_state = intel_connector_get_hw_state; | |
b9cb234c PZ |
1939 | |
1940 | intel_hdmi_add_properties(intel_hdmi, connector); | |
1941 | ||
1942 | intel_connector_attach_encoder(intel_connector, intel_encoder); | |
d8b4c43a | 1943 | intel_hdmi->attached_connector = intel_connector; |
b9cb234c PZ |
1944 | |
1945 | /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written | |
1946 | * 0xd. Failure to do so will result in spurious interrupts being | |
1947 | * generated on the port when a cable is not attached. | |
1948 | */ | |
50a0bc90 | 1949 | if (IS_G4X(dev_priv) && !IS_GM45(dev_priv)) { |
b9cb234c PZ |
1950 | u32 temp = I915_READ(PEG_BAND_GAP_DATA); |
1951 | I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd); | |
1952 | } | |
1953 | } | |
1954 | ||
c39055b0 | 1955 | void intel_hdmi_init(struct drm_i915_private *dev_priv, |
f0f59a00 | 1956 | i915_reg_t hdmi_reg, enum port port) |
b9cb234c PZ |
1957 | { |
1958 | struct intel_digital_port *intel_dig_port; | |
1959 | struct intel_encoder *intel_encoder; | |
b9cb234c PZ |
1960 | struct intel_connector *intel_connector; |
1961 | ||
b14c5679 | 1962 | intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL); |
b9cb234c PZ |
1963 | if (!intel_dig_port) |
1964 | return; | |
1965 | ||
08d9bc92 | 1966 | intel_connector = intel_connector_alloc(); |
b9cb234c PZ |
1967 | if (!intel_connector) { |
1968 | kfree(intel_dig_port); | |
1969 | return; | |
1970 | } | |
1971 | ||
1972 | intel_encoder = &intel_dig_port->base; | |
b9cb234c | 1973 | |
c39055b0 ACO |
1974 | drm_encoder_init(&dev_priv->drm, &intel_encoder->base, |
1975 | &intel_hdmi_enc_funcs, DRM_MODE_ENCODER_TMDS, | |
1976 | "HDMI %c", port_name(port)); | |
00c09d70 | 1977 | |
5bfe2ac0 | 1978 | intel_encoder->compute_config = intel_hdmi_compute_config; |
6e266956 | 1979 | if (HAS_PCH_SPLIT(dev_priv)) { |
a4790cec VS |
1980 | intel_encoder->disable = pch_disable_hdmi; |
1981 | intel_encoder->post_disable = pch_post_disable_hdmi; | |
1982 | } else { | |
1983 | intel_encoder->disable = g4x_disable_hdmi; | |
1984 | } | |
00c09d70 | 1985 | intel_encoder->get_hw_state = intel_hdmi_get_hw_state; |
045ac3b5 | 1986 | intel_encoder->get_config = intel_hdmi_get_config; |
920a14b2 | 1987 | if (IS_CHERRYVIEW(dev_priv)) { |
9197c88b | 1988 | intel_encoder->pre_pll_enable = chv_hdmi_pre_pll_enable; |
e4a1d846 CML |
1989 | intel_encoder->pre_enable = chv_hdmi_pre_enable; |
1990 | intel_encoder->enable = vlv_enable_hdmi; | |
580d3811 | 1991 | intel_encoder->post_disable = chv_hdmi_post_disable; |
d6db995f | 1992 | intel_encoder->post_pll_disable = chv_hdmi_post_pll_disable; |
11a914c2 | 1993 | } else if (IS_VALLEYVIEW(dev_priv)) { |
9514ac6e CML |
1994 | intel_encoder->pre_pll_enable = vlv_hdmi_pre_pll_enable; |
1995 | intel_encoder->pre_enable = vlv_hdmi_pre_enable; | |
b76cf76b | 1996 | intel_encoder->enable = vlv_enable_hdmi; |
9514ac6e | 1997 | intel_encoder->post_disable = vlv_hdmi_post_disable; |
b76cf76b | 1998 | } else { |
13732ba7 | 1999 | intel_encoder->pre_enable = intel_hdmi_pre_enable; |
6e266956 | 2000 | if (HAS_PCH_CPT(dev_priv)) |
d1b1589c | 2001 | intel_encoder->enable = cpt_enable_hdmi; |
6e266956 | 2002 | else if (HAS_PCH_IBX(dev_priv)) |
bf868c7d | 2003 | intel_encoder->enable = ibx_enable_hdmi; |
d1b1589c | 2004 | else |
bf868c7d | 2005 | intel_encoder->enable = g4x_enable_hdmi; |
89b667f8 | 2006 | } |
5ab432ef | 2007 | |
b9cb234c | 2008 | intel_encoder->type = INTEL_OUTPUT_HDMI; |
03cdc1d4 | 2009 | intel_encoder->port = port; |
920a14b2 | 2010 | if (IS_CHERRYVIEW(dev_priv)) { |
882ec384 VS |
2011 | if (port == PORT_D) |
2012 | intel_encoder->crtc_mask = 1 << 2; | |
2013 | else | |
2014 | intel_encoder->crtc_mask = (1 << 0) | (1 << 1); | |
2015 | } else { | |
2016 | intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2); | |
2017 | } | |
301ea74a | 2018 | intel_encoder->cloneable = 1 << INTEL_OUTPUT_ANALOG; |
c6f1495d VS |
2019 | /* |
2020 | * BSpec is unclear about HDMI+HDMI cloning on g4x, but it seems | |
2021 | * to work on real hardware. And since g4x can send infoframes to | |
2022 | * only one port anyway, nothing is lost by allowing it. | |
2023 | */ | |
9beb5fea | 2024 | if (IS_G4X(dev_priv)) |
c6f1495d | 2025 | intel_encoder->cloneable |= 1 << INTEL_OUTPUT_HDMI; |
7d57382e | 2026 | |
174edf1f | 2027 | intel_dig_port->port = port; |
b242b7f7 | 2028 | intel_dig_port->hdmi.hdmi_reg = hdmi_reg; |
f0f59a00 | 2029 | intel_dig_port->dp.output_reg = INVALID_MMIO_REG; |
ccb1a831 | 2030 | intel_dig_port->max_lanes = 4; |
55b7d6e8 | 2031 | |
b9cb234c | 2032 | intel_hdmi_init_connector(intel_dig_port, intel_connector); |
7d57382e | 2033 | } |