]>
Commit | Line | Data |
---|---|---|
7d57382e EA |
1 | /* |
2 | * Copyright 2006 Dave Airlie <airlied@linux.ie> | |
3 | * Copyright © 2006-2009 Intel Corporation | |
4 | * | |
5 | * Permission is hereby granted, free of charge, to any person obtaining a | |
6 | * copy of this software and associated documentation files (the "Software"), | |
7 | * to deal in the Software without restriction, including without limitation | |
8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
9 | * and/or sell copies of the Software, and to permit persons to whom the | |
10 | * Software is furnished to do so, subject to the following conditions: | |
11 | * | |
12 | * The above copyright notice and this permission notice (including the next | |
13 | * paragraph) shall be included in all copies or substantial portions of the | |
14 | * Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
21 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
22 | * DEALINGS IN THE SOFTWARE. | |
23 | * | |
24 | * Authors: | |
25 | * Eric Anholt <eric@anholt.net> | |
26 | * Jesse Barnes <jesse.barnes@intel.com> | |
27 | */ | |
28 | ||
29 | #include <linux/i2c.h> | |
5a0e3ad6 | 30 | #include <linux/slab.h> |
7d57382e EA |
31 | #include <linux/delay.h> |
32 | #include "drmP.h" | |
33 | #include "drm.h" | |
34 | #include "drm_crtc.h" | |
aa93d632 | 35 | #include "drm_edid.h" |
7d57382e EA |
36 | #include "intel_drv.h" |
37 | #include "i915_drm.h" | |
38 | #include "i915_drv.h" | |
39 | ||
ea5b213a CW |
40 | struct intel_hdmi { |
41 | struct intel_encoder base; | |
7d57382e | 42 | u32 sdvox_reg; |
f899fc64 | 43 | int ddc_bus; |
e953fd7b | 44 | uint32_t color_range; |
9dff6af8 | 45 | bool has_hdmi_sink; |
2e3d6006 | 46 | bool has_audio; |
55b7d6e8 | 47 | int force_audio; |
7d57382e EA |
48 | }; |
49 | ||
ea5b213a CW |
50 | static struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder) |
51 | { | |
4ef69c7a | 52 | return container_of(encoder, struct intel_hdmi, base.base); |
ea5b213a CW |
53 | } |
54 | ||
df0e9248 CW |
55 | static struct intel_hdmi *intel_attached_hdmi(struct drm_connector *connector) |
56 | { | |
57 | return container_of(intel_attached_encoder(connector), | |
58 | struct intel_hdmi, base); | |
59 | } | |
60 | ||
3c17fe4b DH |
61 | void intel_dip_infoframe_csum(struct dip_infoframe *avi_if) |
62 | { | |
63 | uint8_t *data = (uint8_t *)avi_if; | |
64 | uint8_t sum = 0; | |
65 | unsigned i; | |
66 | ||
67 | avi_if->checksum = 0; | |
68 | avi_if->ecc = 0; | |
69 | ||
70 | for (i = 0; i < sizeof(*avi_if); i++) | |
71 | sum += data[i]; | |
72 | ||
73 | avi_if->checksum = 0x100 - sum; | |
74 | } | |
75 | ||
76 | static void intel_hdmi_set_avi_infoframe(struct drm_encoder *encoder) | |
77 | { | |
78 | struct dip_infoframe avi_if = { | |
79 | .type = DIP_TYPE_AVI, | |
80 | .ver = DIP_VERSION_AVI, | |
81 | .len = DIP_LEN_AVI, | |
82 | }; | |
83 | uint32_t *data = (uint32_t *)&avi_if; | |
84 | struct drm_device *dev = encoder->dev; | |
85 | struct drm_i915_private *dev_priv = dev->dev_private; | |
86 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); | |
87 | u32 port; | |
88 | unsigned i; | |
89 | ||
90 | if (!intel_hdmi->has_hdmi_sink) | |
91 | return; | |
92 | ||
93 | /* XXX first guess at handling video port, is this corrent? */ | |
94 | if (intel_hdmi->sdvox_reg == SDVOB) | |
95 | port = VIDEO_DIP_PORT_B; | |
96 | else if (intel_hdmi->sdvox_reg == SDVOC) | |
97 | port = VIDEO_DIP_PORT_C; | |
98 | else | |
99 | return; | |
100 | ||
101 | I915_WRITE(VIDEO_DIP_CTL, VIDEO_DIP_ENABLE | port | | |
102 | VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC); | |
103 | ||
104 | intel_dip_infoframe_csum(&avi_if); | |
105 | for (i = 0; i < sizeof(avi_if); i += 4) { | |
106 | I915_WRITE(VIDEO_DIP_DATA, *data); | |
107 | data++; | |
108 | } | |
109 | ||
110 | I915_WRITE(VIDEO_DIP_CTL, VIDEO_DIP_ENABLE | port | | |
111 | VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC | | |
112 | VIDEO_DIP_ENABLE_AVI); | |
113 | } | |
114 | ||
b055c8f3 JB |
115 | static void intel_ironlake_hdmi_set_avi_infoframe(struct drm_encoder *encoder) |
116 | { | |
117 | struct dip_infoframe avi_if = { | |
118 | .type = DIP_TYPE_AVI, | |
119 | .ver = DIP_VERSION_AVI, | |
120 | .len = DIP_LEN_AVI, | |
121 | }; | |
122 | uint32_t *data = (uint32_t *)&avi_if; | |
123 | struct drm_device *dev = encoder->dev; | |
124 | struct drm_i915_private *dev_priv = dev->dev_private; | |
125 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); | |
126 | struct drm_crtc *crtc = encoder->crtc; | |
127 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
128 | int reg = TVIDEO_DIP_CTL(intel_crtc->pipe); | |
129 | unsigned i; | |
130 | ||
131 | if (!intel_hdmi->has_hdmi_sink) | |
132 | return; | |
133 | ||
134 | intel_wait_for_vblank(dev, intel_crtc->pipe); | |
135 | ||
136 | I915_WRITE(reg, VIDEO_DIP_SELECT_AVI); | |
137 | ||
138 | intel_dip_infoframe_csum(&avi_if); | |
139 | for (i = 0; i < sizeof(avi_if); i += 4) { | |
140 | I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data); | |
141 | data++; | |
142 | } | |
143 | ||
144 | I915_WRITE(reg, VIDEO_DIP_ENABLE | VIDEO_DIP_SELECT_AVI | | |
145 | VIDEO_DIP_FREQ_VSYNC | (DIP_LEN_AVI << 8) | | |
146 | VIDEO_DIP_ENABLE_AVI); | |
147 | } | |
148 | ||
7d57382e EA |
149 | static void intel_hdmi_mode_set(struct drm_encoder *encoder, |
150 | struct drm_display_mode *mode, | |
151 | struct drm_display_mode *adjusted_mode) | |
152 | { | |
153 | struct drm_device *dev = encoder->dev; | |
154 | struct drm_i915_private *dev_priv = dev->dev_private; | |
155 | struct drm_crtc *crtc = encoder->crtc; | |
156 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
ea5b213a | 157 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); |
7d57382e EA |
158 | u32 sdvox; |
159 | ||
b599c0bc | 160 | sdvox = SDVO_ENCODING_HDMI | SDVO_BORDER_ENABLE; |
5d4fac97 JB |
161 | if (!HAS_PCH_SPLIT(dev)) |
162 | sdvox |= intel_hdmi->color_range; | |
b599c0bc AJ |
163 | if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) |
164 | sdvox |= SDVO_VSYNC_ACTIVE_HIGH; | |
165 | if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) | |
166 | sdvox |= SDVO_HSYNC_ACTIVE_HIGH; | |
7d57382e | 167 | |
020f6704 JB |
168 | if (intel_crtc->bpp > 24) |
169 | sdvox |= COLOR_FORMAT_12bpc; | |
170 | else | |
171 | sdvox |= COLOR_FORMAT_8bpc; | |
172 | ||
2e3d6006 ZW |
173 | /* Required on CPT */ |
174 | if (intel_hdmi->has_hdmi_sink && HAS_PCH_CPT(dev)) | |
175 | sdvox |= HDMI_MODE_SELECT; | |
176 | ||
3c17fe4b | 177 | if (intel_hdmi->has_audio) { |
7d57382e | 178 | sdvox |= SDVO_AUDIO_ENABLE; |
3c17fe4b DH |
179 | sdvox |= SDVO_NULL_PACKETS_DURING_VSYNC; |
180 | } | |
7d57382e | 181 | |
0f229062 ZW |
182 | if (intel_crtc->pipe == 1) { |
183 | if (HAS_PCH_CPT(dev)) | |
184 | sdvox |= PORT_TRANS_B_SEL_CPT; | |
185 | else | |
186 | sdvox |= SDVO_PIPE_B_SELECT; | |
187 | } | |
7d57382e | 188 | |
ea5b213a CW |
189 | I915_WRITE(intel_hdmi->sdvox_reg, sdvox); |
190 | POSTING_READ(intel_hdmi->sdvox_reg); | |
3c17fe4b | 191 | |
b055c8f3 JB |
192 | if (HAS_PCH_SPLIT(dev)) |
193 | intel_ironlake_hdmi_set_avi_infoframe(encoder); | |
194 | else | |
195 | intel_hdmi_set_avi_infoframe(encoder); | |
7d57382e EA |
196 | } |
197 | ||
198 | static void intel_hdmi_dpms(struct drm_encoder *encoder, int mode) | |
199 | { | |
200 | struct drm_device *dev = encoder->dev; | |
201 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ea5b213a | 202 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); |
7d57382e EA |
203 | u32 temp; |
204 | ||
ea5b213a | 205 | temp = I915_READ(intel_hdmi->sdvox_reg); |
d8a2d0e0 ZW |
206 | |
207 | /* HW workaround, need to toggle enable bit off and on for 12bpc, but | |
208 | * we do this anyway which shows more stable in testing. | |
209 | */ | |
c619eed4 | 210 | if (HAS_PCH_SPLIT(dev)) { |
ea5b213a CW |
211 | I915_WRITE(intel_hdmi->sdvox_reg, temp & ~SDVO_ENABLE); |
212 | POSTING_READ(intel_hdmi->sdvox_reg); | |
d8a2d0e0 ZW |
213 | } |
214 | ||
215 | if (mode != DRM_MODE_DPMS_ON) { | |
216 | temp &= ~SDVO_ENABLE; | |
7d57382e | 217 | } else { |
d8a2d0e0 | 218 | temp |= SDVO_ENABLE; |
7d57382e | 219 | } |
d8a2d0e0 | 220 | |
ea5b213a CW |
221 | I915_WRITE(intel_hdmi->sdvox_reg, temp); |
222 | POSTING_READ(intel_hdmi->sdvox_reg); | |
d8a2d0e0 ZW |
223 | |
224 | /* HW workaround, need to write this twice for issue that may result | |
225 | * in first write getting masked. | |
226 | */ | |
c619eed4 | 227 | if (HAS_PCH_SPLIT(dev)) { |
ea5b213a CW |
228 | I915_WRITE(intel_hdmi->sdvox_reg, temp); |
229 | POSTING_READ(intel_hdmi->sdvox_reg); | |
d8a2d0e0 | 230 | } |
7d57382e EA |
231 | } |
232 | ||
7d57382e EA |
233 | static int intel_hdmi_mode_valid(struct drm_connector *connector, |
234 | struct drm_display_mode *mode) | |
235 | { | |
236 | if (mode->clock > 165000) | |
237 | return MODE_CLOCK_HIGH; | |
238 | if (mode->clock < 20000) | |
5cbba41d | 239 | return MODE_CLOCK_LOW; |
7d57382e EA |
240 | |
241 | if (mode->flags & DRM_MODE_FLAG_DBLSCAN) | |
242 | return MODE_NO_DBLESCAN; | |
243 | ||
244 | return MODE_OK; | |
245 | } | |
246 | ||
247 | static bool intel_hdmi_mode_fixup(struct drm_encoder *encoder, | |
248 | struct drm_display_mode *mode, | |
249 | struct drm_display_mode *adjusted_mode) | |
250 | { | |
251 | return true; | |
252 | } | |
253 | ||
aa93d632 | 254 | static enum drm_connector_status |
930a9e28 | 255 | intel_hdmi_detect(struct drm_connector *connector, bool force) |
9dff6af8 | 256 | { |
df0e9248 | 257 | struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); |
f899fc64 CW |
258 | struct drm_i915_private *dev_priv = connector->dev->dev_private; |
259 | struct edid *edid; | |
aa93d632 | 260 | enum drm_connector_status status = connector_status_disconnected; |
9dff6af8 | 261 | |
ea5b213a | 262 | intel_hdmi->has_hdmi_sink = false; |
2e3d6006 | 263 | intel_hdmi->has_audio = false; |
f899fc64 CW |
264 | edid = drm_get_edid(connector, |
265 | &dev_priv->gmbus[intel_hdmi->ddc_bus].adapter); | |
2ded9e27 | 266 | |
aa93d632 | 267 | if (edid) { |
be9f1c4f | 268 | if (edid->input & DRM_EDID_INPUT_DIGITAL) { |
aa93d632 | 269 | status = connector_status_connected; |
ea5b213a | 270 | intel_hdmi->has_hdmi_sink = drm_detect_hdmi_monitor(edid); |
2e3d6006 | 271 | intel_hdmi->has_audio = drm_detect_monitor_audio(edid); |
aa93d632 | 272 | } |
674e2d08 | 273 | connector->display_info.raw_edid = NULL; |
aa93d632 | 274 | kfree(edid); |
9dff6af8 | 275 | } |
30ad48b7 | 276 | |
55b7d6e8 CW |
277 | if (status == connector_status_connected) { |
278 | if (intel_hdmi->force_audio) | |
279 | intel_hdmi->has_audio = intel_hdmi->force_audio > 0; | |
280 | } | |
281 | ||
2ded9e27 | 282 | return status; |
7d57382e EA |
283 | } |
284 | ||
285 | static int intel_hdmi_get_modes(struct drm_connector *connector) | |
286 | { | |
df0e9248 | 287 | struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); |
f899fc64 | 288 | struct drm_i915_private *dev_priv = connector->dev->dev_private; |
7d57382e EA |
289 | |
290 | /* We should parse the EDID data and find out if it's an HDMI sink so | |
291 | * we can send audio to it. | |
292 | */ | |
293 | ||
f899fc64 CW |
294 | return intel_ddc_get_modes(connector, |
295 | &dev_priv->gmbus[intel_hdmi->ddc_bus].adapter); | |
7d57382e EA |
296 | } |
297 | ||
1aad7ac0 CW |
298 | static bool |
299 | intel_hdmi_detect_audio(struct drm_connector *connector) | |
300 | { | |
301 | struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); | |
302 | struct drm_i915_private *dev_priv = connector->dev->dev_private; | |
303 | struct edid *edid; | |
304 | bool has_audio = false; | |
305 | ||
306 | edid = drm_get_edid(connector, | |
307 | &dev_priv->gmbus[intel_hdmi->ddc_bus].adapter); | |
308 | if (edid) { | |
309 | if (edid->input & DRM_EDID_INPUT_DIGITAL) | |
310 | has_audio = drm_detect_monitor_audio(edid); | |
311 | ||
312 | connector->display_info.raw_edid = NULL; | |
313 | kfree(edid); | |
314 | } | |
315 | ||
316 | return has_audio; | |
317 | } | |
318 | ||
55b7d6e8 CW |
319 | static int |
320 | intel_hdmi_set_property(struct drm_connector *connector, | |
321 | struct drm_property *property, | |
322 | uint64_t val) | |
323 | { | |
324 | struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); | |
e953fd7b | 325 | struct drm_i915_private *dev_priv = connector->dev->dev_private; |
55b7d6e8 CW |
326 | int ret; |
327 | ||
328 | ret = drm_connector_property_set_value(connector, property, val); | |
329 | if (ret) | |
330 | return ret; | |
331 | ||
3f43c48d | 332 | if (property == dev_priv->force_audio_property) { |
1aad7ac0 CW |
333 | int i = val; |
334 | bool has_audio; | |
335 | ||
336 | if (i == intel_hdmi->force_audio) | |
55b7d6e8 CW |
337 | return 0; |
338 | ||
1aad7ac0 | 339 | intel_hdmi->force_audio = i; |
55b7d6e8 | 340 | |
1aad7ac0 CW |
341 | if (i == 0) |
342 | has_audio = intel_hdmi_detect_audio(connector); | |
343 | else | |
344 | has_audio = i > 0; | |
345 | ||
346 | if (has_audio == intel_hdmi->has_audio) | |
55b7d6e8 CW |
347 | return 0; |
348 | ||
1aad7ac0 | 349 | intel_hdmi->has_audio = has_audio; |
55b7d6e8 CW |
350 | goto done; |
351 | } | |
352 | ||
e953fd7b CW |
353 | if (property == dev_priv->broadcast_rgb_property) { |
354 | if (val == !!intel_hdmi->color_range) | |
355 | return 0; | |
356 | ||
357 | intel_hdmi->color_range = val ? SDVO_COLOR_RANGE_16_235 : 0; | |
358 | goto done; | |
359 | } | |
360 | ||
55b7d6e8 CW |
361 | return -EINVAL; |
362 | ||
363 | done: | |
364 | if (intel_hdmi->base.base.crtc) { | |
365 | struct drm_crtc *crtc = intel_hdmi->base.base.crtc; | |
366 | drm_crtc_helper_set_mode(crtc, &crtc->mode, | |
367 | crtc->x, crtc->y, | |
368 | crtc->fb); | |
369 | } | |
370 | ||
371 | return 0; | |
372 | } | |
373 | ||
7d57382e EA |
374 | static void intel_hdmi_destroy(struct drm_connector *connector) |
375 | { | |
7d57382e EA |
376 | drm_sysfs_connector_remove(connector); |
377 | drm_connector_cleanup(connector); | |
674e2d08 | 378 | kfree(connector); |
7d57382e EA |
379 | } |
380 | ||
381 | static const struct drm_encoder_helper_funcs intel_hdmi_helper_funcs = { | |
382 | .dpms = intel_hdmi_dpms, | |
383 | .mode_fixup = intel_hdmi_mode_fixup, | |
384 | .prepare = intel_encoder_prepare, | |
385 | .mode_set = intel_hdmi_mode_set, | |
386 | .commit = intel_encoder_commit, | |
387 | }; | |
388 | ||
389 | static const struct drm_connector_funcs intel_hdmi_connector_funcs = { | |
c9fb15f6 | 390 | .dpms = drm_helper_connector_dpms, |
7d57382e EA |
391 | .detect = intel_hdmi_detect, |
392 | .fill_modes = drm_helper_probe_single_connector_modes, | |
55b7d6e8 | 393 | .set_property = intel_hdmi_set_property, |
7d57382e EA |
394 | .destroy = intel_hdmi_destroy, |
395 | }; | |
396 | ||
397 | static const struct drm_connector_helper_funcs intel_hdmi_connector_helper_funcs = { | |
398 | .get_modes = intel_hdmi_get_modes, | |
399 | .mode_valid = intel_hdmi_mode_valid, | |
df0e9248 | 400 | .best_encoder = intel_best_encoder, |
7d57382e EA |
401 | }; |
402 | ||
7d57382e | 403 | static const struct drm_encoder_funcs intel_hdmi_enc_funcs = { |
ea5b213a | 404 | .destroy = intel_encoder_destroy, |
7d57382e EA |
405 | }; |
406 | ||
55b7d6e8 CW |
407 | static void |
408 | intel_hdmi_add_properties(struct intel_hdmi *intel_hdmi, struct drm_connector *connector) | |
409 | { | |
3f43c48d | 410 | intel_attach_force_audio_property(connector); |
e953fd7b | 411 | intel_attach_broadcast_rgb_property(connector); |
55b7d6e8 CW |
412 | } |
413 | ||
7d57382e EA |
414 | void intel_hdmi_init(struct drm_device *dev, int sdvox_reg) |
415 | { | |
416 | struct drm_i915_private *dev_priv = dev->dev_private; | |
417 | struct drm_connector *connector; | |
21d40d37 | 418 | struct intel_encoder *intel_encoder; |
674e2d08 | 419 | struct intel_connector *intel_connector; |
ea5b213a | 420 | struct intel_hdmi *intel_hdmi; |
7d57382e | 421 | |
ea5b213a CW |
422 | intel_hdmi = kzalloc(sizeof(struct intel_hdmi), GFP_KERNEL); |
423 | if (!intel_hdmi) | |
7d57382e | 424 | return; |
674e2d08 ZW |
425 | |
426 | intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL); | |
427 | if (!intel_connector) { | |
ea5b213a | 428 | kfree(intel_hdmi); |
674e2d08 ZW |
429 | return; |
430 | } | |
431 | ||
ea5b213a | 432 | intel_encoder = &intel_hdmi->base; |
373a3cf7 CW |
433 | drm_encoder_init(dev, &intel_encoder->base, &intel_hdmi_enc_funcs, |
434 | DRM_MODE_ENCODER_TMDS); | |
435 | ||
674e2d08 | 436 | connector = &intel_connector->base; |
7d57382e | 437 | drm_connector_init(dev, connector, &intel_hdmi_connector_funcs, |
8d91104a | 438 | DRM_MODE_CONNECTOR_HDMIA); |
7d57382e EA |
439 | drm_connector_helper_add(connector, &intel_hdmi_connector_helper_funcs); |
440 | ||
21d40d37 | 441 | intel_encoder->type = INTEL_OUTPUT_HDMI; |
7d57382e | 442 | |
eb1f8e4f | 443 | connector->polled = DRM_CONNECTOR_POLL_HPD; |
7d57382e EA |
444 | connector->interlace_allowed = 0; |
445 | connector->doublescan_allowed = 0; | |
21d40d37 | 446 | intel_encoder->crtc_mask = (1 << 0) | (1 << 1); |
7d57382e EA |
447 | |
448 | /* Set up the DDC bus. */ | |
f8aed700 | 449 | if (sdvox_reg == SDVOB) { |
21d40d37 | 450 | intel_encoder->clone_mask = (1 << INTEL_HDMIB_CLONE_BIT); |
f899fc64 | 451 | intel_hdmi->ddc_bus = GMBUS_PORT_DPB; |
b01f2c3a | 452 | dev_priv->hotplug_supported_mask |= HDMIB_HOTPLUG_INT_STATUS; |
f8aed700 | 453 | } else if (sdvox_reg == SDVOC) { |
21d40d37 | 454 | intel_encoder->clone_mask = (1 << INTEL_HDMIC_CLONE_BIT); |
f899fc64 | 455 | intel_hdmi->ddc_bus = GMBUS_PORT_DPC; |
b01f2c3a | 456 | dev_priv->hotplug_supported_mask |= HDMIC_HOTPLUG_INT_STATUS; |
f8aed700 | 457 | } else if (sdvox_reg == HDMIB) { |
21d40d37 | 458 | intel_encoder->clone_mask = (1 << INTEL_HDMID_CLONE_BIT); |
f899fc64 | 459 | intel_hdmi->ddc_bus = GMBUS_PORT_DPB; |
b01f2c3a | 460 | dev_priv->hotplug_supported_mask |= HDMIB_HOTPLUG_INT_STATUS; |
f8aed700 | 461 | } else if (sdvox_reg == HDMIC) { |
21d40d37 | 462 | intel_encoder->clone_mask = (1 << INTEL_HDMIE_CLONE_BIT); |
f899fc64 | 463 | intel_hdmi->ddc_bus = GMBUS_PORT_DPC; |
b01f2c3a | 464 | dev_priv->hotplug_supported_mask |= HDMIC_HOTPLUG_INT_STATUS; |
f8aed700 | 465 | } else if (sdvox_reg == HDMID) { |
21d40d37 | 466 | intel_encoder->clone_mask = (1 << INTEL_HDMIF_CLONE_BIT); |
f899fc64 | 467 | intel_hdmi->ddc_bus = GMBUS_PORT_DPD; |
b01f2c3a | 468 | dev_priv->hotplug_supported_mask |= HDMID_HOTPLUG_INT_STATUS; |
f8aed700 | 469 | } |
7d57382e | 470 | |
ea5b213a | 471 | intel_hdmi->sdvox_reg = sdvox_reg; |
7d57382e | 472 | |
4ef69c7a | 473 | drm_encoder_helper_add(&intel_encoder->base, &intel_hdmi_helper_funcs); |
7d57382e | 474 | |
55b7d6e8 CW |
475 | intel_hdmi_add_properties(intel_hdmi, connector); |
476 | ||
df0e9248 | 477 | intel_connector_attach_encoder(intel_connector, intel_encoder); |
7d57382e EA |
478 | drm_sysfs_connector_add(connector); |
479 | ||
480 | /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written | |
481 | * 0xd. Failure to do so will result in spurious interrupts being | |
482 | * generated on the port when a cable is not attached. | |
483 | */ | |
484 | if (IS_G4X(dev) && !IS_GM45(dev)) { | |
485 | u32 temp = I915_READ(PEG_BAND_GAP_DATA); | |
486 | I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd); | |
487 | } | |
7d57382e | 488 | } |