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7d57382e EA |
1 | /* |
2 | * Copyright 2006 Dave Airlie <airlied@linux.ie> | |
3 | * Copyright © 2006-2009 Intel Corporation | |
4 | * | |
5 | * Permission is hereby granted, free of charge, to any person obtaining a | |
6 | * copy of this software and associated documentation files (the "Software"), | |
7 | * to deal in the Software without restriction, including without limitation | |
8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
9 | * and/or sell copies of the Software, and to permit persons to whom the | |
10 | * Software is furnished to do so, subject to the following conditions: | |
11 | * | |
12 | * The above copyright notice and this permission notice (including the next | |
13 | * paragraph) shall be included in all copies or substantial portions of the | |
14 | * Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
21 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
22 | * DEALINGS IN THE SOFTWARE. | |
23 | * | |
24 | * Authors: | |
25 | * Eric Anholt <eric@anholt.net> | |
26 | * Jesse Barnes <jesse.barnes@intel.com> | |
27 | */ | |
28 | ||
29 | #include <linux/i2c.h> | |
5a0e3ad6 | 30 | #include <linux/slab.h> |
7d57382e | 31 | #include <linux/delay.h> |
178f736a | 32 | #include <linux/hdmi.h> |
760285e7 | 33 | #include <drm/drmP.h> |
c6f95f27 | 34 | #include <drm/drm_atomic_helper.h> |
760285e7 DH |
35 | #include <drm/drm_crtc.h> |
36 | #include <drm/drm_edid.h> | |
15953637 | 37 | #include <drm/drm_scdc_helper.h> |
7d57382e | 38 | #include "intel_drv.h" |
760285e7 | 39 | #include <drm/i915_drm.h> |
46d196ec | 40 | #include <drm/intel_lpe_audio.h> |
7d57382e EA |
41 | #include "i915_drv.h" |
42 | ||
30add22d PZ |
43 | static struct drm_device *intel_hdmi_to_dev(struct intel_hdmi *intel_hdmi) |
44 | { | |
da63a9f2 | 45 | return hdmi_to_dig_port(intel_hdmi)->base.base.dev; |
30add22d PZ |
46 | } |
47 | ||
afba0188 DV |
48 | static void |
49 | assert_hdmi_port_disabled(struct intel_hdmi *intel_hdmi) | |
50 | { | |
30add22d | 51 | struct drm_device *dev = intel_hdmi_to_dev(intel_hdmi); |
fac5e23e | 52 | struct drm_i915_private *dev_priv = to_i915(dev); |
afba0188 DV |
53 | uint32_t enabled_bits; |
54 | ||
4f8036a2 | 55 | enabled_bits = HAS_DDI(dev_priv) ? DDI_BUF_CTL_ENABLE : SDVO_ENABLE; |
afba0188 | 56 | |
b242b7f7 | 57 | WARN(I915_READ(intel_hdmi->hdmi_reg) & enabled_bits, |
afba0188 DV |
58 | "HDMI port enabled, expecting disabled\n"); |
59 | } | |
60 | ||
f5bbfca3 | 61 | struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder) |
ea5b213a | 62 | { |
da63a9f2 PZ |
63 | struct intel_digital_port *intel_dig_port = |
64 | container_of(encoder, struct intel_digital_port, base.base); | |
65 | return &intel_dig_port->hdmi; | |
ea5b213a CW |
66 | } |
67 | ||
df0e9248 CW |
68 | static struct intel_hdmi *intel_attached_hdmi(struct drm_connector *connector) |
69 | { | |
da63a9f2 | 70 | return enc_to_intel_hdmi(&intel_attached_encoder(connector)->base); |
df0e9248 CW |
71 | } |
72 | ||
178f736a | 73 | static u32 g4x_infoframe_index(enum hdmi_infoframe_type type) |
3c17fe4b | 74 | { |
178f736a DL |
75 | switch (type) { |
76 | case HDMI_INFOFRAME_TYPE_AVI: | |
ed517fbb | 77 | return VIDEO_DIP_SELECT_AVI; |
178f736a | 78 | case HDMI_INFOFRAME_TYPE_SPD: |
ed517fbb | 79 | return VIDEO_DIP_SELECT_SPD; |
c8bb75af LD |
80 | case HDMI_INFOFRAME_TYPE_VENDOR: |
81 | return VIDEO_DIP_SELECT_VENDOR; | |
45187ace | 82 | default: |
ffc85dab | 83 | MISSING_CASE(type); |
ed517fbb | 84 | return 0; |
45187ace | 85 | } |
45187ace JB |
86 | } |
87 | ||
178f736a | 88 | static u32 g4x_infoframe_enable(enum hdmi_infoframe_type type) |
45187ace | 89 | { |
178f736a DL |
90 | switch (type) { |
91 | case HDMI_INFOFRAME_TYPE_AVI: | |
ed517fbb | 92 | return VIDEO_DIP_ENABLE_AVI; |
178f736a | 93 | case HDMI_INFOFRAME_TYPE_SPD: |
ed517fbb | 94 | return VIDEO_DIP_ENABLE_SPD; |
c8bb75af LD |
95 | case HDMI_INFOFRAME_TYPE_VENDOR: |
96 | return VIDEO_DIP_ENABLE_VENDOR; | |
fa193ff7 | 97 | default: |
ffc85dab | 98 | MISSING_CASE(type); |
ed517fbb | 99 | return 0; |
fa193ff7 | 100 | } |
fa193ff7 PZ |
101 | } |
102 | ||
178f736a | 103 | static u32 hsw_infoframe_enable(enum hdmi_infoframe_type type) |
2da8af54 | 104 | { |
178f736a DL |
105 | switch (type) { |
106 | case HDMI_INFOFRAME_TYPE_AVI: | |
2da8af54 | 107 | return VIDEO_DIP_ENABLE_AVI_HSW; |
178f736a | 108 | case HDMI_INFOFRAME_TYPE_SPD: |
2da8af54 | 109 | return VIDEO_DIP_ENABLE_SPD_HSW; |
c8bb75af LD |
110 | case HDMI_INFOFRAME_TYPE_VENDOR: |
111 | return VIDEO_DIP_ENABLE_VS_HSW; | |
2da8af54 | 112 | default: |
ffc85dab | 113 | MISSING_CASE(type); |
2da8af54 PZ |
114 | return 0; |
115 | } | |
116 | } | |
117 | ||
f0f59a00 VS |
118 | static i915_reg_t |
119 | hsw_dip_data_reg(struct drm_i915_private *dev_priv, | |
120 | enum transcoder cpu_transcoder, | |
121 | enum hdmi_infoframe_type type, | |
122 | int i) | |
2da8af54 | 123 | { |
178f736a DL |
124 | switch (type) { |
125 | case HDMI_INFOFRAME_TYPE_AVI: | |
436c6d4a | 126 | return HSW_TVIDEO_DIP_AVI_DATA(cpu_transcoder, i); |
178f736a | 127 | case HDMI_INFOFRAME_TYPE_SPD: |
436c6d4a | 128 | return HSW_TVIDEO_DIP_SPD_DATA(cpu_transcoder, i); |
c8bb75af | 129 | case HDMI_INFOFRAME_TYPE_VENDOR: |
436c6d4a | 130 | return HSW_TVIDEO_DIP_VS_DATA(cpu_transcoder, i); |
2da8af54 | 131 | default: |
ffc85dab | 132 | MISSING_CASE(type); |
f0f59a00 | 133 | return INVALID_MMIO_REG; |
2da8af54 PZ |
134 | } |
135 | } | |
136 | ||
a3da1df7 | 137 | static void g4x_write_infoframe(struct drm_encoder *encoder, |
ac240288 | 138 | const struct intel_crtc_state *crtc_state, |
178f736a | 139 | enum hdmi_infoframe_type type, |
fff63867 | 140 | const void *frame, ssize_t len) |
45187ace | 141 | { |
fff63867 | 142 | const uint32_t *data = frame; |
3c17fe4b | 143 | struct drm_device *dev = encoder->dev; |
fac5e23e | 144 | struct drm_i915_private *dev_priv = to_i915(dev); |
22509ec8 | 145 | u32 val = I915_READ(VIDEO_DIP_CTL); |
178f736a | 146 | int i; |
3c17fe4b | 147 | |
822974ae PZ |
148 | WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n"); |
149 | ||
1d4f85ac | 150 | val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ |
178f736a | 151 | val |= g4x_infoframe_index(type); |
22509ec8 | 152 | |
178f736a | 153 | val &= ~g4x_infoframe_enable(type); |
45187ace | 154 | |
22509ec8 | 155 | I915_WRITE(VIDEO_DIP_CTL, val); |
3c17fe4b | 156 | |
9d9740f0 | 157 | mmiowb(); |
45187ace | 158 | for (i = 0; i < len; i += 4) { |
3c17fe4b DH |
159 | I915_WRITE(VIDEO_DIP_DATA, *data); |
160 | data++; | |
161 | } | |
adf00b26 PZ |
162 | /* Write every possible data byte to force correct ECC calculation. */ |
163 | for (; i < VIDEO_DIP_DATA_SIZE; i += 4) | |
164 | I915_WRITE(VIDEO_DIP_DATA, 0); | |
9d9740f0 | 165 | mmiowb(); |
3c17fe4b | 166 | |
178f736a | 167 | val |= g4x_infoframe_enable(type); |
60c5ea2d | 168 | val &= ~VIDEO_DIP_FREQ_MASK; |
4b24c933 | 169 | val |= VIDEO_DIP_FREQ_VSYNC; |
45187ace | 170 | |
22509ec8 | 171 | I915_WRITE(VIDEO_DIP_CTL, val); |
9d9740f0 | 172 | POSTING_READ(VIDEO_DIP_CTL); |
3c17fe4b DH |
173 | } |
174 | ||
cda0aaaf VS |
175 | static bool g4x_infoframe_enabled(struct drm_encoder *encoder, |
176 | const struct intel_crtc_state *pipe_config) | |
e43823ec | 177 | { |
cda0aaaf | 178 | struct drm_i915_private *dev_priv = to_i915(encoder->dev); |
89a35ecd | 179 | struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); |
e43823ec JB |
180 | u32 val = I915_READ(VIDEO_DIP_CTL); |
181 | ||
ec1dc603 VS |
182 | if ((val & VIDEO_DIP_ENABLE) == 0) |
183 | return false; | |
89a35ecd | 184 | |
ec1dc603 VS |
185 | if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(intel_dig_port->port)) |
186 | return false; | |
187 | ||
188 | return val & (VIDEO_DIP_ENABLE_AVI | | |
189 | VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD); | |
e43823ec JB |
190 | } |
191 | ||
fdf1250a | 192 | static void ibx_write_infoframe(struct drm_encoder *encoder, |
ac240288 | 193 | const struct intel_crtc_state *crtc_state, |
178f736a | 194 | enum hdmi_infoframe_type type, |
fff63867 | 195 | const void *frame, ssize_t len) |
fdf1250a | 196 | { |
fff63867 | 197 | const uint32_t *data = frame; |
fdf1250a | 198 | struct drm_device *dev = encoder->dev; |
fac5e23e | 199 | struct drm_i915_private *dev_priv = to_i915(dev); |
ac240288 | 200 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc); |
f0f59a00 | 201 | i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe); |
fdf1250a | 202 | u32 val = I915_READ(reg); |
f0f59a00 | 203 | int i; |
fdf1250a | 204 | |
822974ae PZ |
205 | WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n"); |
206 | ||
fdf1250a | 207 | val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ |
178f736a | 208 | val |= g4x_infoframe_index(type); |
fdf1250a | 209 | |
178f736a | 210 | val &= ~g4x_infoframe_enable(type); |
fdf1250a PZ |
211 | |
212 | I915_WRITE(reg, val); | |
213 | ||
9d9740f0 | 214 | mmiowb(); |
fdf1250a PZ |
215 | for (i = 0; i < len; i += 4) { |
216 | I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data); | |
217 | data++; | |
218 | } | |
adf00b26 PZ |
219 | /* Write every possible data byte to force correct ECC calculation. */ |
220 | for (; i < VIDEO_DIP_DATA_SIZE; i += 4) | |
221 | I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0); | |
9d9740f0 | 222 | mmiowb(); |
fdf1250a | 223 | |
178f736a | 224 | val |= g4x_infoframe_enable(type); |
fdf1250a | 225 | val &= ~VIDEO_DIP_FREQ_MASK; |
4b24c933 | 226 | val |= VIDEO_DIP_FREQ_VSYNC; |
fdf1250a PZ |
227 | |
228 | I915_WRITE(reg, val); | |
9d9740f0 | 229 | POSTING_READ(reg); |
fdf1250a PZ |
230 | } |
231 | ||
cda0aaaf VS |
232 | static bool ibx_infoframe_enabled(struct drm_encoder *encoder, |
233 | const struct intel_crtc_state *pipe_config) | |
e43823ec | 234 | { |
cda0aaaf | 235 | struct drm_i915_private *dev_priv = to_i915(encoder->dev); |
052f62f7 | 236 | struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); |
cda0aaaf VS |
237 | enum pipe pipe = to_intel_crtc(pipe_config->base.crtc)->pipe; |
238 | i915_reg_t reg = TVIDEO_DIP_CTL(pipe); | |
e43823ec JB |
239 | u32 val = I915_READ(reg); |
240 | ||
ec1dc603 VS |
241 | if ((val & VIDEO_DIP_ENABLE) == 0) |
242 | return false; | |
243 | ||
244 | if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(intel_dig_port->port)) | |
245 | return false; | |
052f62f7 | 246 | |
ec1dc603 VS |
247 | return val & (VIDEO_DIP_ENABLE_AVI | |
248 | VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | | |
249 | VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); | |
e43823ec JB |
250 | } |
251 | ||
fdf1250a | 252 | static void cpt_write_infoframe(struct drm_encoder *encoder, |
ac240288 | 253 | const struct intel_crtc_state *crtc_state, |
178f736a | 254 | enum hdmi_infoframe_type type, |
fff63867 | 255 | const void *frame, ssize_t len) |
b055c8f3 | 256 | { |
fff63867 | 257 | const uint32_t *data = frame; |
b055c8f3 | 258 | struct drm_device *dev = encoder->dev; |
fac5e23e | 259 | struct drm_i915_private *dev_priv = to_i915(dev); |
ac240288 | 260 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc); |
f0f59a00 | 261 | i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe); |
22509ec8 | 262 | u32 val = I915_READ(reg); |
f0f59a00 | 263 | int i; |
b055c8f3 | 264 | |
822974ae PZ |
265 | WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n"); |
266 | ||
64a8fc01 | 267 | val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ |
178f736a | 268 | val |= g4x_infoframe_index(type); |
45187ace | 269 | |
ecb97851 PZ |
270 | /* The DIP control register spec says that we need to update the AVI |
271 | * infoframe without clearing its enable bit */ | |
178f736a DL |
272 | if (type != HDMI_INFOFRAME_TYPE_AVI) |
273 | val &= ~g4x_infoframe_enable(type); | |
ecb97851 | 274 | |
22509ec8 | 275 | I915_WRITE(reg, val); |
45187ace | 276 | |
9d9740f0 | 277 | mmiowb(); |
45187ace | 278 | for (i = 0; i < len; i += 4) { |
b055c8f3 JB |
279 | I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data); |
280 | data++; | |
281 | } | |
adf00b26 PZ |
282 | /* Write every possible data byte to force correct ECC calculation. */ |
283 | for (; i < VIDEO_DIP_DATA_SIZE; i += 4) | |
284 | I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0); | |
9d9740f0 | 285 | mmiowb(); |
b055c8f3 | 286 | |
178f736a | 287 | val |= g4x_infoframe_enable(type); |
60c5ea2d | 288 | val &= ~VIDEO_DIP_FREQ_MASK; |
4b24c933 | 289 | val |= VIDEO_DIP_FREQ_VSYNC; |
45187ace | 290 | |
22509ec8 | 291 | I915_WRITE(reg, val); |
9d9740f0 | 292 | POSTING_READ(reg); |
45187ace | 293 | } |
90b107c8 | 294 | |
cda0aaaf VS |
295 | static bool cpt_infoframe_enabled(struct drm_encoder *encoder, |
296 | const struct intel_crtc_state *pipe_config) | |
e43823ec | 297 | { |
cda0aaaf VS |
298 | struct drm_i915_private *dev_priv = to_i915(encoder->dev); |
299 | enum pipe pipe = to_intel_crtc(pipe_config->base.crtc)->pipe; | |
300 | u32 val = I915_READ(TVIDEO_DIP_CTL(pipe)); | |
e43823ec | 301 | |
ec1dc603 VS |
302 | if ((val & VIDEO_DIP_ENABLE) == 0) |
303 | return false; | |
304 | ||
305 | return val & (VIDEO_DIP_ENABLE_AVI | | |
306 | VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | | |
307 | VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); | |
e43823ec JB |
308 | } |
309 | ||
90b107c8 | 310 | static void vlv_write_infoframe(struct drm_encoder *encoder, |
ac240288 | 311 | const struct intel_crtc_state *crtc_state, |
178f736a | 312 | enum hdmi_infoframe_type type, |
fff63867 | 313 | const void *frame, ssize_t len) |
90b107c8 | 314 | { |
fff63867 | 315 | const uint32_t *data = frame; |
90b107c8 | 316 | struct drm_device *dev = encoder->dev; |
fac5e23e | 317 | struct drm_i915_private *dev_priv = to_i915(dev); |
ac240288 | 318 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc); |
f0f59a00 | 319 | i915_reg_t reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe); |
22509ec8 | 320 | u32 val = I915_READ(reg); |
f0f59a00 | 321 | int i; |
90b107c8 | 322 | |
822974ae PZ |
323 | WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n"); |
324 | ||
90b107c8 | 325 | val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ |
178f736a | 326 | val |= g4x_infoframe_index(type); |
22509ec8 | 327 | |
178f736a | 328 | val &= ~g4x_infoframe_enable(type); |
90b107c8 | 329 | |
22509ec8 | 330 | I915_WRITE(reg, val); |
90b107c8 | 331 | |
9d9740f0 | 332 | mmiowb(); |
90b107c8 SK |
333 | for (i = 0; i < len; i += 4) { |
334 | I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), *data); | |
335 | data++; | |
336 | } | |
adf00b26 PZ |
337 | /* Write every possible data byte to force correct ECC calculation. */ |
338 | for (; i < VIDEO_DIP_DATA_SIZE; i += 4) | |
339 | I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), 0); | |
9d9740f0 | 340 | mmiowb(); |
90b107c8 | 341 | |
178f736a | 342 | val |= g4x_infoframe_enable(type); |
60c5ea2d | 343 | val &= ~VIDEO_DIP_FREQ_MASK; |
4b24c933 | 344 | val |= VIDEO_DIP_FREQ_VSYNC; |
90b107c8 | 345 | |
22509ec8 | 346 | I915_WRITE(reg, val); |
9d9740f0 | 347 | POSTING_READ(reg); |
90b107c8 SK |
348 | } |
349 | ||
cda0aaaf VS |
350 | static bool vlv_infoframe_enabled(struct drm_encoder *encoder, |
351 | const struct intel_crtc_state *pipe_config) | |
e43823ec | 352 | { |
cda0aaaf | 353 | struct drm_i915_private *dev_priv = to_i915(encoder->dev); |
535afa2e | 354 | struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); |
cda0aaaf VS |
355 | enum pipe pipe = to_intel_crtc(pipe_config->base.crtc)->pipe; |
356 | u32 val = I915_READ(VLV_TVIDEO_DIP_CTL(pipe)); | |
e43823ec | 357 | |
ec1dc603 VS |
358 | if ((val & VIDEO_DIP_ENABLE) == 0) |
359 | return false; | |
360 | ||
361 | if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(intel_dig_port->port)) | |
362 | return false; | |
535afa2e | 363 | |
ec1dc603 VS |
364 | return val & (VIDEO_DIP_ENABLE_AVI | |
365 | VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | | |
366 | VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); | |
e43823ec JB |
367 | } |
368 | ||
8c5f5f7c | 369 | static void hsw_write_infoframe(struct drm_encoder *encoder, |
ac240288 | 370 | const struct intel_crtc_state *crtc_state, |
178f736a | 371 | enum hdmi_infoframe_type type, |
fff63867 | 372 | const void *frame, ssize_t len) |
8c5f5f7c | 373 | { |
fff63867 | 374 | const uint32_t *data = frame; |
2da8af54 | 375 | struct drm_device *dev = encoder->dev; |
fac5e23e | 376 | struct drm_i915_private *dev_priv = to_i915(dev); |
ac240288 | 377 | enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; |
f0f59a00 VS |
378 | i915_reg_t ctl_reg = HSW_TVIDEO_DIP_CTL(cpu_transcoder); |
379 | i915_reg_t data_reg; | |
178f736a | 380 | int i; |
2da8af54 | 381 | u32 val = I915_READ(ctl_reg); |
8c5f5f7c | 382 | |
436c6d4a | 383 | data_reg = hsw_dip_data_reg(dev_priv, cpu_transcoder, type, 0); |
2da8af54 | 384 | |
178f736a | 385 | val &= ~hsw_infoframe_enable(type); |
2da8af54 PZ |
386 | I915_WRITE(ctl_reg, val); |
387 | ||
9d9740f0 | 388 | mmiowb(); |
2da8af54 | 389 | for (i = 0; i < len; i += 4) { |
436c6d4a VS |
390 | I915_WRITE(hsw_dip_data_reg(dev_priv, cpu_transcoder, |
391 | type, i >> 2), *data); | |
2da8af54 PZ |
392 | data++; |
393 | } | |
adf00b26 PZ |
394 | /* Write every possible data byte to force correct ECC calculation. */ |
395 | for (; i < VIDEO_DIP_DATA_SIZE; i += 4) | |
436c6d4a VS |
396 | I915_WRITE(hsw_dip_data_reg(dev_priv, cpu_transcoder, |
397 | type, i >> 2), 0); | |
9d9740f0 | 398 | mmiowb(); |
8c5f5f7c | 399 | |
178f736a | 400 | val |= hsw_infoframe_enable(type); |
2da8af54 | 401 | I915_WRITE(ctl_reg, val); |
9d9740f0 | 402 | POSTING_READ(ctl_reg); |
8c5f5f7c ED |
403 | } |
404 | ||
cda0aaaf VS |
405 | static bool hsw_infoframe_enabled(struct drm_encoder *encoder, |
406 | const struct intel_crtc_state *pipe_config) | |
e43823ec | 407 | { |
cda0aaaf VS |
408 | struct drm_i915_private *dev_priv = to_i915(encoder->dev); |
409 | u32 val = I915_READ(HSW_TVIDEO_DIP_CTL(pipe_config->cpu_transcoder)); | |
e43823ec | 410 | |
ec1dc603 VS |
411 | return val & (VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_AVI_HSW | |
412 | VIDEO_DIP_ENABLE_GCP_HSW | VIDEO_DIP_ENABLE_VS_HSW | | |
413 | VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW); | |
e43823ec JB |
414 | } |
415 | ||
5adaea79 DL |
416 | /* |
417 | * The data we write to the DIP data buffer registers is 1 byte bigger than the | |
418 | * HDMI infoframe size because of an ECC/reserved byte at position 3 (starting | |
419 | * at 0). It's also a byte used by DisplayPort so the same DIP registers can be | |
420 | * used for both technologies. | |
421 | * | |
422 | * DW0: Reserved/ECC/DP | HB2 | HB1 | HB0 | |
423 | * DW1: DB3 | DB2 | DB1 | DB0 | |
424 | * DW2: DB7 | DB6 | DB5 | DB4 | |
425 | * DW3: ... | |
426 | * | |
427 | * (HB is Header Byte, DB is Data Byte) | |
428 | * | |
429 | * The hdmi pack() functions don't know about that hardware specific hole so we | |
430 | * trick them by giving an offset into the buffer and moving back the header | |
431 | * bytes by one. | |
432 | */ | |
9198ee5b | 433 | static void intel_write_infoframe(struct drm_encoder *encoder, |
ac240288 | 434 | const struct intel_crtc_state *crtc_state, |
9198ee5b | 435 | union hdmi_infoframe *frame) |
45187ace JB |
436 | { |
437 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); | |
5adaea79 DL |
438 | uint8_t buffer[VIDEO_DIP_DATA_SIZE]; |
439 | ssize_t len; | |
45187ace | 440 | |
5adaea79 DL |
441 | /* see comment above for the reason for this offset */ |
442 | len = hdmi_infoframe_pack(frame, buffer + 1, sizeof(buffer) - 1); | |
443 | if (len < 0) | |
444 | return; | |
445 | ||
446 | /* Insert the 'hole' (see big comment above) at position 3 */ | |
447 | buffer[0] = buffer[1]; | |
448 | buffer[1] = buffer[2]; | |
449 | buffer[2] = buffer[3]; | |
450 | buffer[3] = 0; | |
451 | len++; | |
45187ace | 452 | |
ac240288 | 453 | intel_hdmi->write_infoframe(encoder, crtc_state, frame->any.type, buffer, len); |
45187ace JB |
454 | } |
455 | ||
687f4d06 | 456 | static void intel_hdmi_set_avi_infoframe(struct drm_encoder *encoder, |
ac240288 | 457 | const struct intel_crtc_state *crtc_state) |
45187ace | 458 | { |
abedc077 | 459 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); |
779c4c28 VS |
460 | const struct drm_display_mode *adjusted_mode = |
461 | &crtc_state->base.adjusted_mode; | |
5adaea79 DL |
462 | union hdmi_infoframe frame; |
463 | int ret; | |
45187ace | 464 | |
5adaea79 DL |
465 | ret = drm_hdmi_avi_infoframe_from_display_mode(&frame.avi, |
466 | adjusted_mode); | |
467 | if (ret < 0) { | |
468 | DRM_ERROR("couldn't fill AVI infoframe\n"); | |
469 | return; | |
470 | } | |
c846b619 | 471 | |
779c4c28 | 472 | drm_hdmi_avi_infoframe_quant_range(&frame.avi, adjusted_mode, |
a2ce26f8 VS |
473 | crtc_state->limited_color_range ? |
474 | HDMI_QUANTIZATION_RANGE_LIMITED : | |
475 | HDMI_QUANTIZATION_RANGE_FULL, | |
476 | intel_hdmi->rgb_quant_range_selectable); | |
abedc077 | 477 | |
ac240288 | 478 | intel_write_infoframe(encoder, crtc_state, &frame); |
b055c8f3 JB |
479 | } |
480 | ||
ac240288 ML |
481 | static void intel_hdmi_set_spd_infoframe(struct drm_encoder *encoder, |
482 | const struct intel_crtc_state *crtc_state) | |
c0864cb3 | 483 | { |
5adaea79 DL |
484 | union hdmi_infoframe frame; |
485 | int ret; | |
486 | ||
487 | ret = hdmi_spd_infoframe_init(&frame.spd, "Intel", "Integrated gfx"); | |
488 | if (ret < 0) { | |
489 | DRM_ERROR("couldn't fill SPD infoframe\n"); | |
490 | return; | |
491 | } | |
c0864cb3 | 492 | |
5adaea79 | 493 | frame.spd.sdi = HDMI_SPD_SDI_PC; |
c0864cb3 | 494 | |
ac240288 | 495 | intel_write_infoframe(encoder, crtc_state, &frame); |
c0864cb3 JB |
496 | } |
497 | ||
c8bb75af LD |
498 | static void |
499 | intel_hdmi_set_hdmi_infoframe(struct drm_encoder *encoder, | |
ac240288 | 500 | const struct intel_crtc_state *crtc_state) |
c8bb75af LD |
501 | { |
502 | union hdmi_infoframe frame; | |
503 | int ret; | |
504 | ||
505 | ret = drm_hdmi_vendor_infoframe_from_display_mode(&frame.vendor.hdmi, | |
ac240288 | 506 | &crtc_state->base.adjusted_mode); |
c8bb75af LD |
507 | if (ret < 0) |
508 | return; | |
509 | ||
ac240288 | 510 | intel_write_infoframe(encoder, crtc_state, &frame); |
c8bb75af LD |
511 | } |
512 | ||
687f4d06 | 513 | static void g4x_set_infoframes(struct drm_encoder *encoder, |
6897b4b5 | 514 | bool enable, |
ac240288 ML |
515 | const struct intel_crtc_state *crtc_state, |
516 | const struct drm_connector_state *conn_state) | |
687f4d06 | 517 | { |
fac5e23e | 518 | struct drm_i915_private *dev_priv = to_i915(encoder->dev); |
69fde0a6 VS |
519 | struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); |
520 | struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi; | |
f0f59a00 | 521 | i915_reg_t reg = VIDEO_DIP_CTL; |
0c14c7f9 | 522 | u32 val = I915_READ(reg); |
822cdc52 | 523 | u32 port = VIDEO_DIP_PORT(intel_dig_port->port); |
0c14c7f9 | 524 | |
afba0188 DV |
525 | assert_hdmi_port_disabled(intel_hdmi); |
526 | ||
0c14c7f9 PZ |
527 | /* If the registers were not initialized yet, they might be zeroes, |
528 | * which means we're selecting the AVI DIP and we're setting its | |
529 | * frequency to once. This seems to really confuse the HW and make | |
530 | * things stop working (the register spec says the AVI always needs to | |
531 | * be sent every VSync). So here we avoid writing to the register more | |
532 | * than we need and also explicitly select the AVI DIP and explicitly | |
533 | * set its frequency to every VSync. Avoiding to write it twice seems to | |
534 | * be enough to solve the problem, but being defensive shouldn't hurt us | |
535 | * either. */ | |
536 | val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; | |
537 | ||
6897b4b5 | 538 | if (!enable) { |
0c14c7f9 PZ |
539 | if (!(val & VIDEO_DIP_ENABLE)) |
540 | return; | |
0be6f0c8 VS |
541 | if (port != (val & VIDEO_DIP_PORT_MASK)) { |
542 | DRM_DEBUG_KMS("video DIP still enabled on port %c\n", | |
543 | (val & VIDEO_DIP_PORT_MASK) >> 29); | |
544 | return; | |
545 | } | |
546 | val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI | | |
547 | VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD); | |
0c14c7f9 | 548 | I915_WRITE(reg, val); |
9d9740f0 | 549 | POSTING_READ(reg); |
0c14c7f9 PZ |
550 | return; |
551 | } | |
552 | ||
72b78c9d PZ |
553 | if (port != (val & VIDEO_DIP_PORT_MASK)) { |
554 | if (val & VIDEO_DIP_ENABLE) { | |
0be6f0c8 VS |
555 | DRM_DEBUG_KMS("video DIP already enabled on port %c\n", |
556 | (val & VIDEO_DIP_PORT_MASK) >> 29); | |
557 | return; | |
72b78c9d PZ |
558 | } |
559 | val &= ~VIDEO_DIP_PORT_MASK; | |
560 | val |= port; | |
561 | } | |
562 | ||
822974ae | 563 | val |= VIDEO_DIP_ENABLE; |
0be6f0c8 VS |
564 | val &= ~(VIDEO_DIP_ENABLE_AVI | |
565 | VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD); | |
822974ae | 566 | |
f278d972 | 567 | I915_WRITE(reg, val); |
9d9740f0 | 568 | POSTING_READ(reg); |
f278d972 | 569 | |
ac240288 ML |
570 | intel_hdmi_set_avi_infoframe(encoder, crtc_state); |
571 | intel_hdmi_set_spd_infoframe(encoder, crtc_state); | |
572 | intel_hdmi_set_hdmi_infoframe(encoder, crtc_state); | |
687f4d06 PZ |
573 | } |
574 | ||
ac240288 | 575 | static bool hdmi_sink_is_deep_color(const struct drm_connector_state *conn_state) |
6d67415f | 576 | { |
ac240288 | 577 | struct drm_connector *connector = conn_state->connector; |
6d67415f VS |
578 | |
579 | /* | |
580 | * HDMI cloning is only supported on g4x which doesn't | |
581 | * support deep color or GCP infoframes anyway so no | |
582 | * need to worry about multiple HDMI sinks here. | |
583 | */ | |
6d67415f | 584 | |
ac240288 | 585 | return connector->display_info.bpc > 8; |
6d67415f VS |
586 | } |
587 | ||
12aa3290 VS |
588 | /* |
589 | * Determine if default_phase=1 can be indicated in the GCP infoframe. | |
590 | * | |
591 | * From HDMI specification 1.4a: | |
592 | * - The first pixel of each Video Data Period shall always have a pixel packing phase of 0 | |
593 | * - The first pixel following each Video Data Period shall have a pixel packing phase of 0 | |
594 | * - The PP bits shall be constant for all GCPs and will be equal to the last packing phase | |
595 | * - The first pixel following every transition of HSYNC or VSYNC shall have a pixel packing | |
596 | * phase of 0 | |
597 | */ | |
598 | static bool gcp_default_phase_possible(int pipe_bpp, | |
599 | const struct drm_display_mode *mode) | |
600 | { | |
601 | unsigned int pixels_per_group; | |
602 | ||
603 | switch (pipe_bpp) { | |
604 | case 30: | |
605 | /* 4 pixels in 5 clocks */ | |
606 | pixels_per_group = 4; | |
607 | break; | |
608 | case 36: | |
609 | /* 2 pixels in 3 clocks */ | |
610 | pixels_per_group = 2; | |
611 | break; | |
612 | case 48: | |
613 | /* 1 pixel in 2 clocks */ | |
614 | pixels_per_group = 1; | |
615 | break; | |
616 | default: | |
617 | /* phase information not relevant for 8bpc */ | |
618 | return false; | |
619 | } | |
620 | ||
621 | return mode->crtc_hdisplay % pixels_per_group == 0 && | |
622 | mode->crtc_htotal % pixels_per_group == 0 && | |
623 | mode->crtc_hblank_start % pixels_per_group == 0 && | |
624 | mode->crtc_hblank_end % pixels_per_group == 0 && | |
625 | mode->crtc_hsync_start % pixels_per_group == 0 && | |
626 | mode->crtc_hsync_end % pixels_per_group == 0 && | |
627 | ((mode->flags & DRM_MODE_FLAG_INTERLACE) == 0 || | |
628 | mode->crtc_htotal/2 % pixels_per_group == 0); | |
629 | } | |
630 | ||
ac240288 ML |
631 | static bool intel_hdmi_set_gcp_infoframe(struct drm_encoder *encoder, |
632 | const struct intel_crtc_state *crtc_state, | |
633 | const struct drm_connector_state *conn_state) | |
6d67415f | 634 | { |
fac5e23e | 635 | struct drm_i915_private *dev_priv = to_i915(encoder->dev); |
ac240288 | 636 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); |
f0f59a00 VS |
637 | i915_reg_t reg; |
638 | u32 val = 0; | |
6d67415f VS |
639 | |
640 | if (HAS_DDI(dev_priv)) | |
ac240288 | 641 | reg = HSW_TVIDEO_DIP_GCP(crtc_state->cpu_transcoder); |
666a4537 | 642 | else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) |
6d67415f | 643 | reg = VLV_TVIDEO_DIP_GCP(crtc->pipe); |
2d1fe073 | 644 | else if (HAS_PCH_SPLIT(dev_priv)) |
6d67415f VS |
645 | reg = TVIDEO_DIP_GCP(crtc->pipe); |
646 | else | |
647 | return false; | |
648 | ||
649 | /* Indicate color depth whenever the sink supports deep color */ | |
ac240288 | 650 | if (hdmi_sink_is_deep_color(conn_state)) |
6d67415f VS |
651 | val |= GCP_COLOR_INDICATION; |
652 | ||
12aa3290 | 653 | /* Enable default_phase whenever the display mode is suitably aligned */ |
ac240288 ML |
654 | if (gcp_default_phase_possible(crtc_state->pipe_bpp, |
655 | &crtc_state->base.adjusted_mode)) | |
12aa3290 VS |
656 | val |= GCP_DEFAULT_PHASE_ENABLE; |
657 | ||
6d67415f VS |
658 | I915_WRITE(reg, val); |
659 | ||
660 | return val != 0; | |
661 | } | |
662 | ||
687f4d06 | 663 | static void ibx_set_infoframes(struct drm_encoder *encoder, |
6897b4b5 | 664 | bool enable, |
ac240288 ML |
665 | const struct intel_crtc_state *crtc_state, |
666 | const struct drm_connector_state *conn_state) | |
687f4d06 | 667 | { |
fac5e23e | 668 | struct drm_i915_private *dev_priv = to_i915(encoder->dev); |
ac240288 | 669 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc); |
69fde0a6 VS |
670 | struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); |
671 | struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi; | |
f0f59a00 | 672 | i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe); |
0c14c7f9 | 673 | u32 val = I915_READ(reg); |
822cdc52 | 674 | u32 port = VIDEO_DIP_PORT(intel_dig_port->port); |
0c14c7f9 | 675 | |
afba0188 DV |
676 | assert_hdmi_port_disabled(intel_hdmi); |
677 | ||
0c14c7f9 PZ |
678 | /* See the big comment in g4x_set_infoframes() */ |
679 | val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; | |
680 | ||
6897b4b5 | 681 | if (!enable) { |
0c14c7f9 PZ |
682 | if (!(val & VIDEO_DIP_ENABLE)) |
683 | return; | |
0be6f0c8 VS |
684 | val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI | |
685 | VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | | |
686 | VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); | |
0c14c7f9 | 687 | I915_WRITE(reg, val); |
9d9740f0 | 688 | POSTING_READ(reg); |
0c14c7f9 PZ |
689 | return; |
690 | } | |
691 | ||
72b78c9d | 692 | if (port != (val & VIDEO_DIP_PORT_MASK)) { |
0be6f0c8 VS |
693 | WARN(val & VIDEO_DIP_ENABLE, |
694 | "DIP already enabled on port %c\n", | |
695 | (val & VIDEO_DIP_PORT_MASK) >> 29); | |
72b78c9d PZ |
696 | val &= ~VIDEO_DIP_PORT_MASK; |
697 | val |= port; | |
698 | } | |
699 | ||
822974ae | 700 | val |= VIDEO_DIP_ENABLE; |
0be6f0c8 VS |
701 | val &= ~(VIDEO_DIP_ENABLE_AVI | |
702 | VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | | |
703 | VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); | |
822974ae | 704 | |
ac240288 | 705 | if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state)) |
6d67415f VS |
706 | val |= VIDEO_DIP_ENABLE_GCP; |
707 | ||
f278d972 | 708 | I915_WRITE(reg, val); |
9d9740f0 | 709 | POSTING_READ(reg); |
f278d972 | 710 | |
ac240288 ML |
711 | intel_hdmi_set_avi_infoframe(encoder, crtc_state); |
712 | intel_hdmi_set_spd_infoframe(encoder, crtc_state); | |
713 | intel_hdmi_set_hdmi_infoframe(encoder, crtc_state); | |
687f4d06 PZ |
714 | } |
715 | ||
716 | static void cpt_set_infoframes(struct drm_encoder *encoder, | |
6897b4b5 | 717 | bool enable, |
ac240288 ML |
718 | const struct intel_crtc_state *crtc_state, |
719 | const struct drm_connector_state *conn_state) | |
687f4d06 | 720 | { |
fac5e23e | 721 | struct drm_i915_private *dev_priv = to_i915(encoder->dev); |
ac240288 | 722 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc); |
0c14c7f9 | 723 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); |
f0f59a00 | 724 | i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe); |
0c14c7f9 PZ |
725 | u32 val = I915_READ(reg); |
726 | ||
afba0188 DV |
727 | assert_hdmi_port_disabled(intel_hdmi); |
728 | ||
0c14c7f9 PZ |
729 | /* See the big comment in g4x_set_infoframes() */ |
730 | val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; | |
731 | ||
6897b4b5 | 732 | if (!enable) { |
0c14c7f9 PZ |
733 | if (!(val & VIDEO_DIP_ENABLE)) |
734 | return; | |
0be6f0c8 VS |
735 | val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI | |
736 | VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | | |
737 | VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); | |
0c14c7f9 | 738 | I915_WRITE(reg, val); |
9d9740f0 | 739 | POSTING_READ(reg); |
0c14c7f9 PZ |
740 | return; |
741 | } | |
742 | ||
822974ae PZ |
743 | /* Set both together, unset both together: see the spec. */ |
744 | val |= VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI; | |
0dd87d20 | 745 | val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | |
0be6f0c8 | 746 | VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); |
822974ae | 747 | |
ac240288 | 748 | if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state)) |
6d67415f VS |
749 | val |= VIDEO_DIP_ENABLE_GCP; |
750 | ||
822974ae | 751 | I915_WRITE(reg, val); |
9d9740f0 | 752 | POSTING_READ(reg); |
822974ae | 753 | |
ac240288 ML |
754 | intel_hdmi_set_avi_infoframe(encoder, crtc_state); |
755 | intel_hdmi_set_spd_infoframe(encoder, crtc_state); | |
756 | intel_hdmi_set_hdmi_infoframe(encoder, crtc_state); | |
687f4d06 PZ |
757 | } |
758 | ||
759 | static void vlv_set_infoframes(struct drm_encoder *encoder, | |
6897b4b5 | 760 | bool enable, |
ac240288 ML |
761 | const struct intel_crtc_state *crtc_state, |
762 | const struct drm_connector_state *conn_state) | |
687f4d06 | 763 | { |
fac5e23e | 764 | struct drm_i915_private *dev_priv = to_i915(encoder->dev); |
6a2b8021 | 765 | struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); |
ac240288 | 766 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc); |
0c14c7f9 | 767 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); |
f0f59a00 | 768 | i915_reg_t reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe); |
0c14c7f9 | 769 | u32 val = I915_READ(reg); |
6a2b8021 | 770 | u32 port = VIDEO_DIP_PORT(intel_dig_port->port); |
0c14c7f9 | 771 | |
afba0188 DV |
772 | assert_hdmi_port_disabled(intel_hdmi); |
773 | ||
0c14c7f9 PZ |
774 | /* See the big comment in g4x_set_infoframes() */ |
775 | val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; | |
776 | ||
6897b4b5 | 777 | if (!enable) { |
0c14c7f9 PZ |
778 | if (!(val & VIDEO_DIP_ENABLE)) |
779 | return; | |
0be6f0c8 VS |
780 | val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI | |
781 | VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | | |
782 | VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); | |
0c14c7f9 | 783 | I915_WRITE(reg, val); |
9d9740f0 | 784 | POSTING_READ(reg); |
0c14c7f9 PZ |
785 | return; |
786 | } | |
787 | ||
6a2b8021 | 788 | if (port != (val & VIDEO_DIP_PORT_MASK)) { |
0be6f0c8 VS |
789 | WARN(val & VIDEO_DIP_ENABLE, |
790 | "DIP already enabled on port %c\n", | |
791 | (val & VIDEO_DIP_PORT_MASK) >> 29); | |
6a2b8021 JB |
792 | val &= ~VIDEO_DIP_PORT_MASK; |
793 | val |= port; | |
794 | } | |
795 | ||
822974ae | 796 | val |= VIDEO_DIP_ENABLE; |
0be6f0c8 VS |
797 | val &= ~(VIDEO_DIP_ENABLE_AVI | |
798 | VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | | |
799 | VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); | |
822974ae | 800 | |
ac240288 | 801 | if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state)) |
6d67415f VS |
802 | val |= VIDEO_DIP_ENABLE_GCP; |
803 | ||
822974ae | 804 | I915_WRITE(reg, val); |
9d9740f0 | 805 | POSTING_READ(reg); |
822974ae | 806 | |
ac240288 ML |
807 | intel_hdmi_set_avi_infoframe(encoder, crtc_state); |
808 | intel_hdmi_set_spd_infoframe(encoder, crtc_state); | |
809 | intel_hdmi_set_hdmi_infoframe(encoder, crtc_state); | |
687f4d06 PZ |
810 | } |
811 | ||
812 | static void hsw_set_infoframes(struct drm_encoder *encoder, | |
6897b4b5 | 813 | bool enable, |
ac240288 ML |
814 | const struct intel_crtc_state *crtc_state, |
815 | const struct drm_connector_state *conn_state) | |
687f4d06 | 816 | { |
fac5e23e | 817 | struct drm_i915_private *dev_priv = to_i915(encoder->dev); |
0c14c7f9 | 818 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); |
ac240288 | 819 | i915_reg_t reg = HSW_TVIDEO_DIP_CTL(crtc_state->cpu_transcoder); |
0dd87d20 | 820 | u32 val = I915_READ(reg); |
0c14c7f9 | 821 | |
afba0188 DV |
822 | assert_hdmi_port_disabled(intel_hdmi); |
823 | ||
0be6f0c8 VS |
824 | val &= ~(VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_AVI_HSW | |
825 | VIDEO_DIP_ENABLE_GCP_HSW | VIDEO_DIP_ENABLE_VS_HSW | | |
826 | VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW); | |
827 | ||
6897b4b5 | 828 | if (!enable) { |
0be6f0c8 | 829 | I915_WRITE(reg, val); |
9d9740f0 | 830 | POSTING_READ(reg); |
0c14c7f9 PZ |
831 | return; |
832 | } | |
833 | ||
ac240288 | 834 | if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state)) |
6d67415f VS |
835 | val |= VIDEO_DIP_ENABLE_GCP_HSW; |
836 | ||
0dd87d20 | 837 | I915_WRITE(reg, val); |
9d9740f0 | 838 | POSTING_READ(reg); |
0dd87d20 | 839 | |
ac240288 ML |
840 | intel_hdmi_set_avi_infoframe(encoder, crtc_state); |
841 | intel_hdmi_set_spd_infoframe(encoder, crtc_state); | |
842 | intel_hdmi_set_hdmi_infoframe(encoder, crtc_state); | |
687f4d06 PZ |
843 | } |
844 | ||
b2ccb822 VS |
845 | void intel_dp_dual_mode_set_tmds_output(struct intel_hdmi *hdmi, bool enable) |
846 | { | |
847 | struct drm_i915_private *dev_priv = to_i915(intel_hdmi_to_dev(hdmi)); | |
848 | struct i2c_adapter *adapter = | |
849 | intel_gmbus_get_adapter(dev_priv, hdmi->ddc_bus); | |
850 | ||
851 | if (hdmi->dp_dual_mode.type < DRM_DP_DUAL_MODE_TYPE2_DVI) | |
852 | return; | |
853 | ||
f0a95b85 AM |
854 | if (dev_priv->bypass_tmds_oe) { |
855 | DRM_DEBUG_KMS("Bypassing TMDS_OE setting\n"); | |
856 | return; | |
857 | } | |
858 | ||
b2ccb822 VS |
859 | DRM_DEBUG_KMS("%s DP dual mode adaptor TMDS output\n", |
860 | enable ? "Enabling" : "Disabling"); | |
861 | ||
862 | drm_dp_dual_mode_set_tmds_output(hdmi->dp_dual_mode.type, | |
863 | adapter, enable); | |
864 | } | |
865 | ||
ac240288 ML |
866 | static void intel_hdmi_prepare(struct intel_encoder *encoder, |
867 | const struct intel_crtc_state *crtc_state) | |
7d57382e | 868 | { |
c59423a3 | 869 | struct drm_device *dev = encoder->base.dev; |
fac5e23e | 870 | struct drm_i915_private *dev_priv = to_i915(dev); |
ac240288 | 871 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); |
c59423a3 | 872 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); |
ac240288 | 873 | const struct drm_display_mode *adjusted_mode = &crtc_state->base.adjusted_mode; |
b242b7f7 | 874 | u32 hdmi_val; |
7d57382e | 875 | |
b2ccb822 VS |
876 | intel_dp_dual_mode_set_tmds_output(intel_hdmi, true); |
877 | ||
b242b7f7 | 878 | hdmi_val = SDVO_ENCODING_HDMI; |
ac240288 | 879 | if (!HAS_PCH_SPLIT(dev_priv) && crtc_state->limited_color_range) |
0f2a2a75 | 880 | hdmi_val |= HDMI_COLOR_RANGE_16_235; |
b599c0bc | 881 | if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) |
b242b7f7 | 882 | hdmi_val |= SDVO_VSYNC_ACTIVE_HIGH; |
b599c0bc | 883 | if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) |
b242b7f7 | 884 | hdmi_val |= SDVO_HSYNC_ACTIVE_HIGH; |
7d57382e | 885 | |
ac240288 | 886 | if (crtc_state->pipe_bpp > 24) |
4f3a8bc7 | 887 | hdmi_val |= HDMI_COLOR_FORMAT_12bpc; |
020f6704 | 888 | else |
4f3a8bc7 | 889 | hdmi_val |= SDVO_COLOR_FORMAT_8bpc; |
020f6704 | 890 | |
ac240288 | 891 | if (crtc_state->has_hdmi_sink) |
dc0fa718 | 892 | hdmi_val |= HDMI_MODE_SELECT_HDMI; |
2e3d6006 | 893 | |
6e266956 | 894 | if (HAS_PCH_CPT(dev_priv)) |
c59423a3 | 895 | hdmi_val |= SDVO_PIPE_SEL_CPT(crtc->pipe); |
920a14b2 | 896 | else if (IS_CHERRYVIEW(dev_priv)) |
44f37d1f | 897 | hdmi_val |= SDVO_PIPE_SEL_CHV(crtc->pipe); |
dc0fa718 | 898 | else |
c59423a3 | 899 | hdmi_val |= SDVO_PIPE_SEL(crtc->pipe); |
7d57382e | 900 | |
b242b7f7 PZ |
901 | I915_WRITE(intel_hdmi->hdmi_reg, hdmi_val); |
902 | POSTING_READ(intel_hdmi->hdmi_reg); | |
7d57382e EA |
903 | } |
904 | ||
85234cdc DV |
905 | static bool intel_hdmi_get_hw_state(struct intel_encoder *encoder, |
906 | enum pipe *pipe) | |
7d57382e | 907 | { |
85234cdc | 908 | struct drm_device *dev = encoder->base.dev; |
fac5e23e | 909 | struct drm_i915_private *dev_priv = to_i915(dev); |
85234cdc DV |
910 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); |
911 | u32 tmp; | |
5b092174 | 912 | bool ret; |
85234cdc | 913 | |
79f255a0 ACO |
914 | if (!intel_display_power_get_if_enabled(dev_priv, |
915 | encoder->power_domain)) | |
6d129bea ID |
916 | return false; |
917 | ||
5b092174 ID |
918 | ret = false; |
919 | ||
b242b7f7 | 920 | tmp = I915_READ(intel_hdmi->hdmi_reg); |
85234cdc DV |
921 | |
922 | if (!(tmp & SDVO_ENABLE)) | |
5b092174 | 923 | goto out; |
85234cdc | 924 | |
6e266956 | 925 | if (HAS_PCH_CPT(dev_priv)) |
85234cdc | 926 | *pipe = PORT_TO_PIPE_CPT(tmp); |
920a14b2 | 927 | else if (IS_CHERRYVIEW(dev_priv)) |
71485e0a | 928 | *pipe = SDVO_PORT_TO_PIPE_CHV(tmp); |
85234cdc DV |
929 | else |
930 | *pipe = PORT_TO_PIPE(tmp); | |
931 | ||
5b092174 ID |
932 | ret = true; |
933 | ||
934 | out: | |
79f255a0 | 935 | intel_display_power_put(dev_priv, encoder->power_domain); |
5b092174 ID |
936 | |
937 | return ret; | |
85234cdc DV |
938 | } |
939 | ||
045ac3b5 | 940 | static void intel_hdmi_get_config(struct intel_encoder *encoder, |
5cec258b | 941 | struct intel_crtc_state *pipe_config) |
045ac3b5 JB |
942 | { |
943 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); | |
8c875fca | 944 | struct drm_device *dev = encoder->base.dev; |
fac5e23e | 945 | struct drm_i915_private *dev_priv = to_i915(dev); |
045ac3b5 | 946 | u32 tmp, flags = 0; |
18442d08 | 947 | int dotclock; |
045ac3b5 JB |
948 | |
949 | tmp = I915_READ(intel_hdmi->hdmi_reg); | |
950 | ||
951 | if (tmp & SDVO_HSYNC_ACTIVE_HIGH) | |
952 | flags |= DRM_MODE_FLAG_PHSYNC; | |
953 | else | |
954 | flags |= DRM_MODE_FLAG_NHSYNC; | |
955 | ||
956 | if (tmp & SDVO_VSYNC_ACTIVE_HIGH) | |
957 | flags |= DRM_MODE_FLAG_PVSYNC; | |
958 | else | |
959 | flags |= DRM_MODE_FLAG_NVSYNC; | |
960 | ||
6897b4b5 DV |
961 | if (tmp & HDMI_MODE_SELECT_HDMI) |
962 | pipe_config->has_hdmi_sink = true; | |
963 | ||
cda0aaaf | 964 | if (intel_hdmi->infoframe_enabled(&encoder->base, pipe_config)) |
e43823ec JB |
965 | pipe_config->has_infoframe = true; |
966 | ||
c84db770 | 967 | if (tmp & SDVO_AUDIO_ENABLE) |
9ed109a7 DV |
968 | pipe_config->has_audio = true; |
969 | ||
6e266956 | 970 | if (!HAS_PCH_SPLIT(dev_priv) && |
8c875fca VS |
971 | tmp & HDMI_COLOR_RANGE_16_235) |
972 | pipe_config->limited_color_range = true; | |
973 | ||
2d112de7 | 974 | pipe_config->base.adjusted_mode.flags |= flags; |
18442d08 VS |
975 | |
976 | if ((tmp & SDVO_COLOR_FORMAT_MASK) == HDMI_COLOR_FORMAT_12bpc) | |
977 | dotclock = pipe_config->port_clock * 2 / 3; | |
978 | else | |
979 | dotclock = pipe_config->port_clock; | |
980 | ||
be69a133 VS |
981 | if (pipe_config->pixel_multiplier) |
982 | dotclock /= pipe_config->pixel_multiplier; | |
983 | ||
2d112de7 | 984 | pipe_config->base.adjusted_mode.crtc_clock = dotclock; |
d4d6279a ACO |
985 | |
986 | pipe_config->lane_count = 4; | |
045ac3b5 JB |
987 | } |
988 | ||
df18e721 ML |
989 | static void intel_enable_hdmi_audio(struct intel_encoder *encoder, |
990 | struct intel_crtc_state *pipe_config, | |
991 | struct drm_connector_state *conn_state) | |
d1b1589c | 992 | { |
ac240288 | 993 | struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc); |
d1b1589c | 994 | |
ac240288 | 995 | WARN_ON(!pipe_config->has_hdmi_sink); |
d1b1589c VS |
996 | DRM_DEBUG_DRIVER("Enabling HDMI audio on pipe %c\n", |
997 | pipe_name(crtc->pipe)); | |
bbf35e9d | 998 | intel_audio_codec_enable(encoder, pipe_config, conn_state); |
d1b1589c VS |
999 | } |
1000 | ||
fd6bbda9 ML |
1001 | static void g4x_enable_hdmi(struct intel_encoder *encoder, |
1002 | struct intel_crtc_state *pipe_config, | |
1003 | struct drm_connector_state *conn_state) | |
7d57382e | 1004 | { |
5ab432ef | 1005 | struct drm_device *dev = encoder->base.dev; |
fac5e23e | 1006 | struct drm_i915_private *dev_priv = to_i915(dev); |
5ab432ef | 1007 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); |
7d57382e EA |
1008 | u32 temp; |
1009 | ||
b242b7f7 | 1010 | temp = I915_READ(intel_hdmi->hdmi_reg); |
d8a2d0e0 | 1011 | |
bf868c7d | 1012 | temp |= SDVO_ENABLE; |
df18e721 | 1013 | if (pipe_config->has_audio) |
bf868c7d | 1014 | temp |= SDVO_AUDIO_ENABLE; |
7a87c289 | 1015 | |
bf868c7d VS |
1016 | I915_WRITE(intel_hdmi->hdmi_reg, temp); |
1017 | POSTING_READ(intel_hdmi->hdmi_reg); | |
1018 | ||
df18e721 ML |
1019 | if (pipe_config->has_audio) |
1020 | intel_enable_hdmi_audio(encoder, pipe_config, conn_state); | |
bf868c7d VS |
1021 | } |
1022 | ||
fd6bbda9 ML |
1023 | static void ibx_enable_hdmi(struct intel_encoder *encoder, |
1024 | struct intel_crtc_state *pipe_config, | |
1025 | struct drm_connector_state *conn_state) | |
bf868c7d VS |
1026 | { |
1027 | struct drm_device *dev = encoder->base.dev; | |
fac5e23e | 1028 | struct drm_i915_private *dev_priv = to_i915(dev); |
bf868c7d VS |
1029 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); |
1030 | u32 temp; | |
1031 | ||
1032 | temp = I915_READ(intel_hdmi->hdmi_reg); | |
d8a2d0e0 | 1033 | |
bf868c7d | 1034 | temp |= SDVO_ENABLE; |
ac240288 | 1035 | if (pipe_config->has_audio) |
bf868c7d | 1036 | temp |= SDVO_AUDIO_ENABLE; |
5ab432ef | 1037 | |
bf868c7d VS |
1038 | /* |
1039 | * HW workaround, need to write this twice for issue | |
1040 | * that may result in first write getting masked. | |
1041 | */ | |
1042 | I915_WRITE(intel_hdmi->hdmi_reg, temp); | |
1043 | POSTING_READ(intel_hdmi->hdmi_reg); | |
b242b7f7 PZ |
1044 | I915_WRITE(intel_hdmi->hdmi_reg, temp); |
1045 | POSTING_READ(intel_hdmi->hdmi_reg); | |
5ab432ef | 1046 | |
bf868c7d VS |
1047 | /* |
1048 | * HW workaround, need to toggle enable bit off and on | |
1049 | * for 12bpc with pixel repeat. | |
1050 | * | |
1051 | * FIXME: BSpec says this should be done at the end of | |
1052 | * of the modeset sequence, so not sure if this isn't too soon. | |
5ab432ef | 1053 | */ |
df18e721 ML |
1054 | if (pipe_config->pipe_bpp > 24 && |
1055 | pipe_config->pixel_multiplier > 1) { | |
bf868c7d VS |
1056 | I915_WRITE(intel_hdmi->hdmi_reg, temp & ~SDVO_ENABLE); |
1057 | POSTING_READ(intel_hdmi->hdmi_reg); | |
1058 | ||
1059 | /* | |
1060 | * HW workaround, need to write this twice for issue | |
1061 | * that may result in first write getting masked. | |
1062 | */ | |
1063 | I915_WRITE(intel_hdmi->hdmi_reg, temp); | |
1064 | POSTING_READ(intel_hdmi->hdmi_reg); | |
b242b7f7 PZ |
1065 | I915_WRITE(intel_hdmi->hdmi_reg, temp); |
1066 | POSTING_READ(intel_hdmi->hdmi_reg); | |
7d57382e | 1067 | } |
c1dec79a | 1068 | |
df18e721 ML |
1069 | if (pipe_config->has_audio) |
1070 | intel_enable_hdmi_audio(encoder, pipe_config, conn_state); | |
d1b1589c VS |
1071 | } |
1072 | ||
fd6bbda9 ML |
1073 | static void cpt_enable_hdmi(struct intel_encoder *encoder, |
1074 | struct intel_crtc_state *pipe_config, | |
1075 | struct drm_connector_state *conn_state) | |
d1b1589c VS |
1076 | { |
1077 | struct drm_device *dev = encoder->base.dev; | |
fac5e23e | 1078 | struct drm_i915_private *dev_priv = to_i915(dev); |
ac240288 | 1079 | struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc); |
d1b1589c VS |
1080 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); |
1081 | enum pipe pipe = crtc->pipe; | |
1082 | u32 temp; | |
1083 | ||
1084 | temp = I915_READ(intel_hdmi->hdmi_reg); | |
1085 | ||
1086 | temp |= SDVO_ENABLE; | |
df18e721 | 1087 | if (pipe_config->has_audio) |
d1b1589c VS |
1088 | temp |= SDVO_AUDIO_ENABLE; |
1089 | ||
1090 | /* | |
1091 | * WaEnableHDMI8bpcBefore12bpc:snb,ivb | |
1092 | * | |
1093 | * The procedure for 12bpc is as follows: | |
1094 | * 1. disable HDMI clock gating | |
1095 | * 2. enable HDMI with 8bpc | |
1096 | * 3. enable HDMI with 12bpc | |
1097 | * 4. enable HDMI clock gating | |
1098 | */ | |
1099 | ||
df18e721 | 1100 | if (pipe_config->pipe_bpp > 24) { |
d1b1589c VS |
1101 | I915_WRITE(TRANS_CHICKEN1(pipe), |
1102 | I915_READ(TRANS_CHICKEN1(pipe)) | | |
1103 | TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE); | |
1104 | ||
1105 | temp &= ~SDVO_COLOR_FORMAT_MASK; | |
1106 | temp |= SDVO_COLOR_FORMAT_8bpc; | |
c1dec79a | 1107 | } |
d1b1589c VS |
1108 | |
1109 | I915_WRITE(intel_hdmi->hdmi_reg, temp); | |
1110 | POSTING_READ(intel_hdmi->hdmi_reg); | |
1111 | ||
df18e721 | 1112 | if (pipe_config->pipe_bpp > 24) { |
d1b1589c VS |
1113 | temp &= ~SDVO_COLOR_FORMAT_MASK; |
1114 | temp |= HDMI_COLOR_FORMAT_12bpc; | |
1115 | ||
1116 | I915_WRITE(intel_hdmi->hdmi_reg, temp); | |
1117 | POSTING_READ(intel_hdmi->hdmi_reg); | |
1118 | ||
1119 | I915_WRITE(TRANS_CHICKEN1(pipe), | |
1120 | I915_READ(TRANS_CHICKEN1(pipe)) & | |
1121 | ~TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE); | |
1122 | } | |
1123 | ||
df18e721 ML |
1124 | if (pipe_config->has_audio) |
1125 | intel_enable_hdmi_audio(encoder, pipe_config, conn_state); | |
b76cf76b | 1126 | } |
89b667f8 | 1127 | |
fd6bbda9 ML |
1128 | static void vlv_enable_hdmi(struct intel_encoder *encoder, |
1129 | struct intel_crtc_state *pipe_config, | |
1130 | struct drm_connector_state *conn_state) | |
b76cf76b | 1131 | { |
5ab432ef DV |
1132 | } |
1133 | ||
fd6bbda9 ML |
1134 | static void intel_disable_hdmi(struct intel_encoder *encoder, |
1135 | struct intel_crtc_state *old_crtc_state, | |
1136 | struct drm_connector_state *old_conn_state) | |
5ab432ef DV |
1137 | { |
1138 | struct drm_device *dev = encoder->base.dev; | |
fac5e23e | 1139 | struct drm_i915_private *dev_priv = to_i915(dev); |
5ab432ef | 1140 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); |
ac240288 | 1141 | struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc); |
5ab432ef | 1142 | u32 temp; |
5ab432ef | 1143 | |
b242b7f7 | 1144 | temp = I915_READ(intel_hdmi->hdmi_reg); |
5ab432ef | 1145 | |
1612c8bd | 1146 | temp &= ~(SDVO_ENABLE | SDVO_AUDIO_ENABLE); |
b242b7f7 PZ |
1147 | I915_WRITE(intel_hdmi->hdmi_reg, temp); |
1148 | POSTING_READ(intel_hdmi->hdmi_reg); | |
1612c8bd VS |
1149 | |
1150 | /* | |
1151 | * HW workaround for IBX, we need to move the port | |
1152 | * to transcoder A after disabling it to allow the | |
1153 | * matching DP port to be enabled on transcoder A. | |
1154 | */ | |
6e266956 | 1155 | if (HAS_PCH_IBX(dev_priv) && crtc->pipe == PIPE_B) { |
0c241d5b VS |
1156 | /* |
1157 | * We get CPU/PCH FIFO underruns on the other pipe when | |
1158 | * doing the workaround. Sweep them under the rug. | |
1159 | */ | |
1160 | intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, false); | |
1161 | intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false); | |
1162 | ||
1612c8bd VS |
1163 | temp &= ~SDVO_PIPE_B_SELECT; |
1164 | temp |= SDVO_ENABLE; | |
1165 | /* | |
1166 | * HW workaround, need to write this twice for issue | |
1167 | * that may result in first write getting masked. | |
1168 | */ | |
1169 | I915_WRITE(intel_hdmi->hdmi_reg, temp); | |
1170 | POSTING_READ(intel_hdmi->hdmi_reg); | |
1171 | I915_WRITE(intel_hdmi->hdmi_reg, temp); | |
1172 | POSTING_READ(intel_hdmi->hdmi_reg); | |
1173 | ||
1174 | temp &= ~SDVO_ENABLE; | |
1175 | I915_WRITE(intel_hdmi->hdmi_reg, temp); | |
1176 | POSTING_READ(intel_hdmi->hdmi_reg); | |
0c241d5b | 1177 | |
0f0f74bc | 1178 | intel_wait_for_vblank_if_active(dev_priv, PIPE_A); |
0c241d5b VS |
1179 | intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true); |
1180 | intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true); | |
1612c8bd | 1181 | } |
6d67415f | 1182 | |
ac240288 | 1183 | intel_hdmi->set_infoframes(&encoder->base, false, old_crtc_state, old_conn_state); |
b2ccb822 VS |
1184 | |
1185 | intel_dp_dual_mode_set_tmds_output(intel_hdmi, false); | |
7d57382e EA |
1186 | } |
1187 | ||
fd6bbda9 ML |
1188 | static void g4x_disable_hdmi(struct intel_encoder *encoder, |
1189 | struct intel_crtc_state *old_crtc_state, | |
1190 | struct drm_connector_state *old_conn_state) | |
a4790cec | 1191 | { |
df18e721 | 1192 | if (old_crtc_state->has_audio) |
a4790cec VS |
1193 | intel_audio_codec_disable(encoder); |
1194 | ||
fd6bbda9 | 1195 | intel_disable_hdmi(encoder, old_crtc_state, old_conn_state); |
a4790cec VS |
1196 | } |
1197 | ||
fd6bbda9 ML |
1198 | static void pch_disable_hdmi(struct intel_encoder *encoder, |
1199 | struct intel_crtc_state *old_crtc_state, | |
1200 | struct drm_connector_state *old_conn_state) | |
a4790cec | 1201 | { |
df18e721 | 1202 | if (old_crtc_state->has_audio) |
a4790cec VS |
1203 | intel_audio_codec_disable(encoder); |
1204 | } | |
1205 | ||
fd6bbda9 ML |
1206 | static void pch_post_disable_hdmi(struct intel_encoder *encoder, |
1207 | struct intel_crtc_state *old_crtc_state, | |
1208 | struct drm_connector_state *old_conn_state) | |
a4790cec | 1209 | { |
fd6bbda9 | 1210 | intel_disable_hdmi(encoder, old_crtc_state, old_conn_state); |
a4790cec VS |
1211 | } |
1212 | ||
b1ba124d | 1213 | static int intel_hdmi_source_max_tmds_clock(struct drm_i915_private *dev_priv) |
7d148ef5 | 1214 | { |
b1ba124d | 1215 | if (IS_G4X(dev_priv)) |
7d148ef5 | 1216 | return 165000; |
14292b7f SS |
1217 | else if (IS_GEMINILAKE(dev_priv)) |
1218 | return 594000; | |
b1ba124d | 1219 | else if (IS_HASWELL(dev_priv) || INTEL_INFO(dev_priv)->gen >= 8) |
7d148ef5 DV |
1220 | return 300000; |
1221 | else | |
1222 | return 225000; | |
1223 | } | |
1224 | ||
b1ba124d | 1225 | static int hdmi_port_clock_limit(struct intel_hdmi *hdmi, |
7a5ca19f ML |
1226 | bool respect_downstream_limits, |
1227 | bool force_dvi) | |
b1ba124d VS |
1228 | { |
1229 | struct drm_device *dev = intel_hdmi_to_dev(hdmi); | |
1230 | int max_tmds_clock = intel_hdmi_source_max_tmds_clock(to_i915(dev)); | |
1231 | ||
1232 | if (respect_downstream_limits) { | |
8cadab0a VS |
1233 | struct intel_connector *connector = hdmi->attached_connector; |
1234 | const struct drm_display_info *info = &connector->base.display_info; | |
1235 | ||
b1ba124d VS |
1236 | if (hdmi->dp_dual_mode.max_tmds_clock) |
1237 | max_tmds_clock = min(max_tmds_clock, | |
1238 | hdmi->dp_dual_mode.max_tmds_clock); | |
8cadab0a VS |
1239 | |
1240 | if (info->max_tmds_clock) | |
1241 | max_tmds_clock = min(max_tmds_clock, | |
1242 | info->max_tmds_clock); | |
7a5ca19f | 1243 | else if (!hdmi->has_hdmi_sink || force_dvi) |
b1ba124d VS |
1244 | max_tmds_clock = min(max_tmds_clock, 165000); |
1245 | } | |
1246 | ||
1247 | return max_tmds_clock; | |
1248 | } | |
1249 | ||
e64e739e VS |
1250 | static enum drm_mode_status |
1251 | hdmi_port_clock_valid(struct intel_hdmi *hdmi, | |
7a5ca19f ML |
1252 | int clock, bool respect_downstream_limits, |
1253 | bool force_dvi) | |
e64e739e | 1254 | { |
e2d214ae | 1255 | struct drm_i915_private *dev_priv = to_i915(intel_hdmi_to_dev(hdmi)); |
e64e739e VS |
1256 | |
1257 | if (clock < 25000) | |
1258 | return MODE_CLOCK_LOW; | |
7a5ca19f | 1259 | if (clock > hdmi_port_clock_limit(hdmi, respect_downstream_limits, force_dvi)) |
e64e739e VS |
1260 | return MODE_CLOCK_HIGH; |
1261 | ||
5e6ccc0b | 1262 | /* BXT DPLL can't generate 223-240 MHz */ |
cc3f90f0 | 1263 | if (IS_GEN9_LP(dev_priv) && clock > 223333 && clock < 240000) |
5e6ccc0b VS |
1264 | return MODE_CLOCK_RANGE; |
1265 | ||
1266 | /* CHV DPLL can't generate 216-240 MHz */ | |
e2d214ae | 1267 | if (IS_CHERRYVIEW(dev_priv) && clock > 216000 && clock < 240000) |
e64e739e VS |
1268 | return MODE_CLOCK_RANGE; |
1269 | ||
1270 | return MODE_OK; | |
1271 | } | |
1272 | ||
c19de8eb DL |
1273 | static enum drm_mode_status |
1274 | intel_hdmi_mode_valid(struct drm_connector *connector, | |
1275 | struct drm_display_mode *mode) | |
7d57382e | 1276 | { |
e64e739e VS |
1277 | struct intel_hdmi *hdmi = intel_attached_hdmi(connector); |
1278 | struct drm_device *dev = intel_hdmi_to_dev(hdmi); | |
49cff963 | 1279 | struct drm_i915_private *dev_priv = to_i915(dev); |
e64e739e VS |
1280 | enum drm_mode_status status; |
1281 | int clock; | |
587bf496 | 1282 | int max_dotclk = to_i915(connector->dev)->max_dotclk_freq; |
7a5ca19f ML |
1283 | bool force_dvi = |
1284 | READ_ONCE(to_intel_digital_connector_state(connector->state)->force_audio) == HDMI_AUDIO_OFF_DVI; | |
e64e739e VS |
1285 | |
1286 | if (mode->flags & DRM_MODE_FLAG_DBLSCAN) | |
1287 | return MODE_NO_DBLESCAN; | |
697c4078 | 1288 | |
e64e739e | 1289 | clock = mode->clock; |
587bf496 MK |
1290 | |
1291 | if ((mode->flags & DRM_MODE_FLAG_3D_MASK) == DRM_MODE_FLAG_3D_FRAME_PACKING) | |
1292 | clock *= 2; | |
1293 | ||
1294 | if (clock > max_dotclk) | |
1295 | return MODE_CLOCK_HIGH; | |
1296 | ||
697c4078 CT |
1297 | if (mode->flags & DRM_MODE_FLAG_DBLCLK) |
1298 | clock *= 2; | |
1299 | ||
e64e739e | 1300 | /* check if we can do 8bpc */ |
7a5ca19f | 1301 | status = hdmi_port_clock_valid(hdmi, clock, true, force_dvi); |
7d57382e | 1302 | |
e64e739e | 1303 | /* if we can't do 8bpc we may still be able to do 12bpc */ |
7a5ca19f ML |
1304 | if (!HAS_GMCH_DISPLAY(dev_priv) && status != MODE_OK && hdmi->has_hdmi_sink && !force_dvi) |
1305 | status = hdmi_port_clock_valid(hdmi, clock * 3 / 2, true, force_dvi); | |
7d57382e | 1306 | |
e64e739e | 1307 | return status; |
7d57382e EA |
1308 | } |
1309 | ||
77f06c86 | 1310 | static bool hdmi_12bpc_possible(struct intel_crtc_state *crtc_state) |
71800632 | 1311 | { |
c750bdd3 VS |
1312 | struct drm_i915_private *dev_priv = |
1313 | to_i915(crtc_state->base.crtc->dev); | |
1314 | struct drm_atomic_state *state = crtc_state->base.state; | |
1315 | struct drm_connector_state *connector_state; | |
1316 | struct drm_connector *connector; | |
1317 | int i; | |
71800632 | 1318 | |
c750bdd3 | 1319 | if (HAS_GMCH_DISPLAY(dev_priv)) |
71800632 VS |
1320 | return false; |
1321 | ||
71800632 VS |
1322 | /* |
1323 | * HDMI 12bpc affects the clocks, so it's only possible | |
1324 | * when not cloning with other encoder types. | |
1325 | */ | |
c750bdd3 VS |
1326 | if (crtc_state->output_types != 1 << INTEL_OUTPUT_HDMI) |
1327 | return false; | |
1328 | ||
1329 | for_each_connector_in_state(state, connector, connector_state, i) { | |
1330 | const struct drm_display_info *info = &connector->display_info; | |
1331 | ||
1332 | if (connector_state->crtc != crtc_state->base.crtc) | |
1333 | continue; | |
1334 | ||
1335 | if ((info->edid_hdmi_dc_modes & DRM_EDID_HDMI_DC_36) == 0) | |
1336 | return false; | |
1337 | } | |
1338 | ||
46649d8b ACO |
1339 | /* Display Wa #1139 */ |
1340 | if (IS_GLK_REVID(dev_priv, 0, GLK_REVID_A1) && | |
1341 | crtc_state->base.adjusted_mode.htotal > 5460) | |
1342 | return false; | |
1343 | ||
c750bdd3 | 1344 | return true; |
71800632 VS |
1345 | } |
1346 | ||
5bfe2ac0 | 1347 | bool intel_hdmi_compute_config(struct intel_encoder *encoder, |
0a478c27 ML |
1348 | struct intel_crtc_state *pipe_config, |
1349 | struct drm_connector_state *conn_state) | |
7d57382e | 1350 | { |
5bfe2ac0 | 1351 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); |
4f8036a2 | 1352 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
2d112de7 | 1353 | struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; |
15953637 | 1354 | struct drm_scdc *scdc = &conn_state->connector->display_info.hdmi.scdc; |
7a5ca19f ML |
1355 | struct intel_digital_connector_state *intel_conn_state = |
1356 | to_intel_digital_connector_state(conn_state); | |
e64e739e VS |
1357 | int clock_8bpc = pipe_config->base.adjusted_mode.crtc_clock; |
1358 | int clock_12bpc = clock_8bpc * 3 / 2; | |
e29c22c0 | 1359 | int desired_bpp; |
7a5ca19f | 1360 | bool force_dvi = intel_conn_state->force_audio == HDMI_AUDIO_OFF_DVI; |
3685a8f3 | 1361 | |
7a5ca19f | 1362 | pipe_config->has_hdmi_sink = !force_dvi && intel_hdmi->has_hdmi_sink; |
6897b4b5 | 1363 | |
e43823ec JB |
1364 | if (pipe_config->has_hdmi_sink) |
1365 | pipe_config->has_infoframe = true; | |
1366 | ||
7a5ca19f | 1367 | if (intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_AUTO) { |
55bc60db | 1368 | /* See CEA-861-E - 5.1 Default Encoding Parameters */ |
0f2a2a75 VS |
1369 | pipe_config->limited_color_range = |
1370 | pipe_config->has_hdmi_sink && | |
c8127cf0 VS |
1371 | drm_default_rgb_quant_range(adjusted_mode) == |
1372 | HDMI_QUANTIZATION_RANGE_LIMITED; | |
0f2a2a75 VS |
1373 | } else { |
1374 | pipe_config->limited_color_range = | |
7a5ca19f | 1375 | intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_LIMITED; |
55bc60db VS |
1376 | } |
1377 | ||
697c4078 CT |
1378 | if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK) { |
1379 | pipe_config->pixel_multiplier = 2; | |
e64e739e | 1380 | clock_8bpc *= 2; |
3320e37f | 1381 | clock_12bpc *= 2; |
697c4078 CT |
1382 | } |
1383 | ||
4f8036a2 | 1384 | if (HAS_PCH_SPLIT(dev_priv) && !HAS_DDI(dev_priv)) |
5bfe2ac0 DV |
1385 | pipe_config->has_pch_encoder = true; |
1386 | ||
7a5ca19f ML |
1387 | if (pipe_config->has_hdmi_sink) { |
1388 | if (intel_conn_state->force_audio == HDMI_AUDIO_AUTO) | |
1389 | pipe_config->has_audio = intel_hdmi->has_audio; | |
1390 | else | |
1391 | pipe_config->has_audio = | |
1392 | intel_conn_state->force_audio == HDMI_AUDIO_ON; | |
1393 | } | |
9ed109a7 | 1394 | |
4e53c2e0 DV |
1395 | /* |
1396 | * HDMI is either 12 or 8, so if the display lets 10bpc sneak | |
1397 | * through, clamp it down. Note that g4x/vlv don't support 12bpc hdmi | |
325b9d04 DV |
1398 | * outputs. We also need to check that the higher clock still fits |
1399 | * within limits. | |
4e53c2e0 | 1400 | */ |
7a5ca19f ML |
1401 | if (pipe_config->pipe_bpp > 8*3 && pipe_config->has_hdmi_sink && !force_dvi && |
1402 | hdmi_port_clock_valid(intel_hdmi, clock_12bpc, true, force_dvi) == MODE_OK && | |
7a0baa62 | 1403 | hdmi_12bpc_possible(pipe_config)) { |
e29c22c0 DV |
1404 | DRM_DEBUG_KMS("picking bpc to 12 for HDMI output\n"); |
1405 | desired_bpp = 12*3; | |
325b9d04 DV |
1406 | |
1407 | /* Need to adjust the port link by 1.5x for 12bpc. */ | |
ff9a6750 | 1408 | pipe_config->port_clock = clock_12bpc; |
4e53c2e0 | 1409 | } else { |
e29c22c0 DV |
1410 | DRM_DEBUG_KMS("picking bpc to 8 for HDMI output\n"); |
1411 | desired_bpp = 8*3; | |
e64e739e VS |
1412 | |
1413 | pipe_config->port_clock = clock_8bpc; | |
e29c22c0 DV |
1414 | } |
1415 | ||
1416 | if (!pipe_config->bw_constrained) { | |
b64b7a60 | 1417 | DRM_DEBUG_KMS("forcing pipe bpp to %i for HDMI\n", desired_bpp); |
e29c22c0 | 1418 | pipe_config->pipe_bpp = desired_bpp; |
4e53c2e0 DV |
1419 | } |
1420 | ||
e64e739e | 1421 | if (hdmi_port_clock_valid(intel_hdmi, pipe_config->port_clock, |
7a5ca19f | 1422 | false, force_dvi) != MODE_OK) { |
e64e739e | 1423 | DRM_DEBUG_KMS("unsupported HDMI clock, rejecting mode\n"); |
325b9d04 DV |
1424 | return false; |
1425 | } | |
1426 | ||
28b468a0 | 1427 | /* Set user selected PAR to incoming mode's member */ |
0e9f25d0 | 1428 | adjusted_mode->picture_aspect_ratio = conn_state->picture_aspect_ratio; |
28b468a0 | 1429 | |
d4d6279a ACO |
1430 | pipe_config->lane_count = 4; |
1431 | ||
15953637 SS |
1432 | if (scdc->scrambling.supported && IS_GEMINILAKE(dev_priv)) { |
1433 | if (scdc->scrambling.low_rates) | |
1434 | pipe_config->hdmi_scrambling = true; | |
1435 | ||
1436 | if (pipe_config->port_clock > 340000) { | |
1437 | pipe_config->hdmi_scrambling = true; | |
1438 | pipe_config->hdmi_high_tmds_clock_ratio = true; | |
1439 | } | |
1440 | } | |
1441 | ||
7d57382e EA |
1442 | return true; |
1443 | } | |
1444 | ||
953ece69 CW |
1445 | static void |
1446 | intel_hdmi_unset_edid(struct drm_connector *connector) | |
9dff6af8 | 1447 | { |
df0e9248 | 1448 | struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); |
9dff6af8 | 1449 | |
953ece69 CW |
1450 | intel_hdmi->has_hdmi_sink = false; |
1451 | intel_hdmi->has_audio = false; | |
1452 | intel_hdmi->rgb_quant_range_selectable = false; | |
1453 | ||
b1ba124d VS |
1454 | intel_hdmi->dp_dual_mode.type = DRM_DP_DUAL_MODE_NONE; |
1455 | intel_hdmi->dp_dual_mode.max_tmds_clock = 0; | |
1456 | ||
953ece69 CW |
1457 | kfree(to_intel_connector(connector)->detect_edid); |
1458 | to_intel_connector(connector)->detect_edid = NULL; | |
1459 | } | |
1460 | ||
b1ba124d | 1461 | static void |
d6199256 | 1462 | intel_hdmi_dp_dual_mode_detect(struct drm_connector *connector, bool has_edid) |
b1ba124d VS |
1463 | { |
1464 | struct drm_i915_private *dev_priv = to_i915(connector->dev); | |
1465 | struct intel_hdmi *hdmi = intel_attached_hdmi(connector); | |
d6199256 | 1466 | enum port port = hdmi_to_dig_port(hdmi)->port; |
b1ba124d VS |
1467 | struct i2c_adapter *adapter = |
1468 | intel_gmbus_get_adapter(dev_priv, hdmi->ddc_bus); | |
1469 | enum drm_dp_dual_mode_type type = drm_dp_dual_mode_detect(adapter); | |
1470 | ||
d6199256 VS |
1471 | /* |
1472 | * Type 1 DVI adaptors are not required to implement any | |
1473 | * registers, so we can't always detect their presence. | |
1474 | * Ideally we should be able to check the state of the | |
1475 | * CONFIG1 pin, but no such luck on our hardware. | |
1476 | * | |
1477 | * The only method left to us is to check the VBT to see | |
1478 | * if the port is a dual mode capable DP port. But let's | |
1479 | * only do that when we sucesfully read the EDID, to avoid | |
1480 | * confusing log messages about DP dual mode adaptors when | |
1481 | * there's nothing connected to the port. | |
1482 | */ | |
1483 | if (type == DRM_DP_DUAL_MODE_UNKNOWN) { | |
1484 | if (has_edid && | |
1485 | intel_bios_is_port_dp_dual_mode(dev_priv, port)) { | |
1486 | DRM_DEBUG_KMS("Assuming DP dual mode adaptor presence based on VBT\n"); | |
1487 | type = DRM_DP_DUAL_MODE_TYPE1_DVI; | |
1488 | } else { | |
1489 | type = DRM_DP_DUAL_MODE_NONE; | |
1490 | } | |
1491 | } | |
1492 | ||
1493 | if (type == DRM_DP_DUAL_MODE_NONE) | |
b1ba124d VS |
1494 | return; |
1495 | ||
1496 | hdmi->dp_dual_mode.type = type; | |
1497 | hdmi->dp_dual_mode.max_tmds_clock = | |
1498 | drm_dp_dual_mode_max_tmds_clock(type, adapter); | |
1499 | ||
1500 | DRM_DEBUG_KMS("DP dual mode adaptor (%s) detected (max TMDS clock: %d kHz)\n", | |
1501 | drm_dp_get_dual_mode_type_name(type), | |
1502 | hdmi->dp_dual_mode.max_tmds_clock); | |
1503 | } | |
1504 | ||
953ece69 | 1505 | static bool |
23f889bd | 1506 | intel_hdmi_set_edid(struct drm_connector *connector) |
953ece69 CW |
1507 | { |
1508 | struct drm_i915_private *dev_priv = to_i915(connector->dev); | |
1509 | struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); | |
23f889bd | 1510 | struct edid *edid; |
953ece69 | 1511 | bool connected = false; |
164c8598 | 1512 | |
23f889bd | 1513 | intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS); |
671dedd2 | 1514 | |
23f889bd DW |
1515 | edid = drm_get_edid(connector, |
1516 | intel_gmbus_get_adapter(dev_priv, | |
1517 | intel_hdmi->ddc_bus)); | |
2ded9e27 | 1518 | |
23f889bd | 1519 | intel_hdmi_dp_dual_mode_detect(connector, edid != NULL); |
b1ba124d | 1520 | |
23f889bd | 1521 | intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS); |
30ad48b7 | 1522 | |
953ece69 CW |
1523 | to_intel_connector(connector)->detect_edid = edid; |
1524 | if (edid && edid->input & DRM_EDID_INPUT_DIGITAL) { | |
1525 | intel_hdmi->rgb_quant_range_selectable = | |
1526 | drm_rgb_quant_range_selectable(edid); | |
1527 | ||
1528 | intel_hdmi->has_audio = drm_detect_monitor_audio(edid); | |
7a5ca19f | 1529 | intel_hdmi->has_hdmi_sink = drm_detect_hdmi_monitor(edid); |
953ece69 CW |
1530 | |
1531 | connected = true; | |
55b7d6e8 CW |
1532 | } |
1533 | ||
953ece69 CW |
1534 | return connected; |
1535 | } | |
1536 | ||
8166fcea DV |
1537 | static enum drm_connector_status |
1538 | intel_hdmi_detect(struct drm_connector *connector, bool force) | |
953ece69 | 1539 | { |
8166fcea | 1540 | enum drm_connector_status status; |
8166fcea | 1541 | struct drm_i915_private *dev_priv = to_i915(connector->dev); |
953ece69 | 1542 | |
8166fcea DV |
1543 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", |
1544 | connector->base.id, connector->name); | |
1545 | ||
29bb94bb ID |
1546 | intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS); |
1547 | ||
8166fcea | 1548 | intel_hdmi_unset_edid(connector); |
0b5e88dc | 1549 | |
23f889bd | 1550 | if (intel_hdmi_set_edid(connector)) { |
953ece69 CW |
1551 | struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); |
1552 | ||
1553 | hdmi_to_dig_port(intel_hdmi)->base.type = INTEL_OUTPUT_HDMI; | |
1554 | status = connector_status_connected; | |
8166fcea | 1555 | } else |
953ece69 | 1556 | status = connector_status_disconnected; |
671dedd2 | 1557 | |
29bb94bb ID |
1558 | intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS); |
1559 | ||
2ded9e27 | 1560 | return status; |
7d57382e EA |
1561 | } |
1562 | ||
953ece69 CW |
1563 | static void |
1564 | intel_hdmi_force(struct drm_connector *connector) | |
7d57382e | 1565 | { |
953ece69 | 1566 | struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); |
7d57382e | 1567 | |
953ece69 CW |
1568 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", |
1569 | connector->base.id, connector->name); | |
7d57382e | 1570 | |
953ece69 | 1571 | intel_hdmi_unset_edid(connector); |
671dedd2 | 1572 | |
953ece69 CW |
1573 | if (connector->status != connector_status_connected) |
1574 | return; | |
671dedd2 | 1575 | |
23f889bd | 1576 | intel_hdmi_set_edid(connector); |
953ece69 CW |
1577 | hdmi_to_dig_port(intel_hdmi)->base.type = INTEL_OUTPUT_HDMI; |
1578 | } | |
671dedd2 | 1579 | |
953ece69 CW |
1580 | static int intel_hdmi_get_modes(struct drm_connector *connector) |
1581 | { | |
1582 | struct edid *edid; | |
1583 | ||
1584 | edid = to_intel_connector(connector)->detect_edid; | |
1585 | if (edid == NULL) | |
1586 | return 0; | |
671dedd2 | 1587 | |
953ece69 | 1588 | return intel_connector_update_modes(connector, edid); |
7d57382e EA |
1589 | } |
1590 | ||
fd6bbda9 ML |
1591 | static void intel_hdmi_pre_enable(struct intel_encoder *encoder, |
1592 | struct intel_crtc_state *pipe_config, | |
1593 | struct drm_connector_state *conn_state) | |
13732ba7 JB |
1594 | { |
1595 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); | |
13732ba7 | 1596 | |
ac240288 | 1597 | intel_hdmi_prepare(encoder, pipe_config); |
4cde8a21 | 1598 | |
6897b4b5 | 1599 | intel_hdmi->set_infoframes(&encoder->base, |
df18e721 | 1600 | pipe_config->has_hdmi_sink, |
ac240288 | 1601 | pipe_config, conn_state); |
13732ba7 JB |
1602 | } |
1603 | ||
fd6bbda9 ML |
1604 | static void vlv_hdmi_pre_enable(struct intel_encoder *encoder, |
1605 | struct intel_crtc_state *pipe_config, | |
1606 | struct drm_connector_state *conn_state) | |
89b667f8 JB |
1607 | { |
1608 | struct intel_digital_port *dport = enc_to_dig_port(&encoder->base); | |
13732ba7 | 1609 | struct intel_hdmi *intel_hdmi = &dport->hdmi; |
89b667f8 | 1610 | struct drm_device *dev = encoder->base.dev; |
fac5e23e | 1611 | struct drm_i915_private *dev_priv = to_i915(dev); |
5f68c275 ACO |
1612 | |
1613 | vlv_phy_pre_encoder_enable(encoder); | |
b76cf76b | 1614 | |
53d98725 ACO |
1615 | /* HDMI 1.0V-2dB */ |
1616 | vlv_set_phy_signal_level(encoder, 0x2b245f5f, 0x00002000, 0x5578b83a, | |
1617 | 0x2b247878); | |
1618 | ||
6897b4b5 | 1619 | intel_hdmi->set_infoframes(&encoder->base, |
df18e721 | 1620 | pipe_config->has_hdmi_sink, |
ac240288 | 1621 | pipe_config, conn_state); |
13732ba7 | 1622 | |
fd6bbda9 | 1623 | g4x_enable_hdmi(encoder, pipe_config, conn_state); |
b76cf76b | 1624 | |
9b6de0a1 | 1625 | vlv_wait_port_ready(dev_priv, dport, 0x0); |
89b667f8 JB |
1626 | } |
1627 | ||
fd6bbda9 ML |
1628 | static void vlv_hdmi_pre_pll_enable(struct intel_encoder *encoder, |
1629 | struct intel_crtc_state *pipe_config, | |
1630 | struct drm_connector_state *conn_state) | |
89b667f8 | 1631 | { |
ac240288 | 1632 | intel_hdmi_prepare(encoder, pipe_config); |
4cde8a21 | 1633 | |
6da2e616 | 1634 | vlv_phy_pre_pll_enable(encoder); |
89b667f8 JB |
1635 | } |
1636 | ||
fd6bbda9 ML |
1637 | static void chv_hdmi_pre_pll_enable(struct intel_encoder *encoder, |
1638 | struct intel_crtc_state *pipe_config, | |
1639 | struct drm_connector_state *conn_state) | |
9197c88b | 1640 | { |
ac240288 | 1641 | intel_hdmi_prepare(encoder, pipe_config); |
625695f8 | 1642 | |
419b1b7a | 1643 | chv_phy_pre_pll_enable(encoder); |
9197c88b VS |
1644 | } |
1645 | ||
fd6bbda9 ML |
1646 | static void chv_hdmi_post_pll_disable(struct intel_encoder *encoder, |
1647 | struct intel_crtc_state *old_crtc_state, | |
1648 | struct drm_connector_state *old_conn_state) | |
d6db995f | 1649 | { |
204970b5 | 1650 | chv_phy_post_pll_disable(encoder); |
d6db995f VS |
1651 | } |
1652 | ||
fd6bbda9 ML |
1653 | static void vlv_hdmi_post_disable(struct intel_encoder *encoder, |
1654 | struct intel_crtc_state *old_crtc_state, | |
1655 | struct drm_connector_state *old_conn_state) | |
89b667f8 | 1656 | { |
89b667f8 | 1657 | /* Reset lanes to avoid HDMI flicker (VLV w/a) */ |
0f572ebe | 1658 | vlv_phy_reset_lanes(encoder); |
89b667f8 JB |
1659 | } |
1660 | ||
fd6bbda9 ML |
1661 | static void chv_hdmi_post_disable(struct intel_encoder *encoder, |
1662 | struct intel_crtc_state *old_crtc_state, | |
1663 | struct drm_connector_state *old_conn_state) | |
580d3811 | 1664 | { |
580d3811 | 1665 | struct drm_device *dev = encoder->base.dev; |
fac5e23e | 1666 | struct drm_i915_private *dev_priv = to_i915(dev); |
580d3811 | 1667 | |
a580516d | 1668 | mutex_lock(&dev_priv->sb_lock); |
580d3811 | 1669 | |
a8f327fb VS |
1670 | /* Assert data lane reset */ |
1671 | chv_data_lane_soft_reset(encoder, true); | |
580d3811 | 1672 | |
a580516d | 1673 | mutex_unlock(&dev_priv->sb_lock); |
580d3811 VS |
1674 | } |
1675 | ||
fd6bbda9 ML |
1676 | static void chv_hdmi_pre_enable(struct intel_encoder *encoder, |
1677 | struct intel_crtc_state *pipe_config, | |
1678 | struct drm_connector_state *conn_state) | |
e4a1d846 CML |
1679 | { |
1680 | struct intel_digital_port *dport = enc_to_dig_port(&encoder->base); | |
b4eb1564 | 1681 | struct intel_hdmi *intel_hdmi = &dport->hdmi; |
e4a1d846 | 1682 | struct drm_device *dev = encoder->base.dev; |
fac5e23e | 1683 | struct drm_i915_private *dev_priv = to_i915(dev); |
2e523e98 | 1684 | |
e7d2a717 | 1685 | chv_phy_pre_encoder_enable(encoder); |
a02ef3c7 | 1686 | |
e4a1d846 CML |
1687 | /* FIXME: Program the support xxx V-dB */ |
1688 | /* Use 800mV-0dB */ | |
b7fa22d8 | 1689 | chv_set_phy_signal_level(encoder, 128, 102, false); |
e4a1d846 | 1690 | |
b4eb1564 | 1691 | intel_hdmi->set_infoframes(&encoder->base, |
ac240288 ML |
1692 | pipe_config->has_hdmi_sink, |
1693 | pipe_config, conn_state); | |
b4eb1564 | 1694 | |
fd6bbda9 | 1695 | g4x_enable_hdmi(encoder, pipe_config, conn_state); |
e4a1d846 | 1696 | |
9b6de0a1 | 1697 | vlv_wait_port_ready(dev_priv, dport, 0x0); |
b0b33846 VS |
1698 | |
1699 | /* Second common lane will stay alive on its own now */ | |
e7d2a717 | 1700 | chv_phy_release_cl2_override(encoder); |
e4a1d846 CML |
1701 | } |
1702 | ||
7d57382e EA |
1703 | static void intel_hdmi_destroy(struct drm_connector *connector) |
1704 | { | |
10e972d3 | 1705 | kfree(to_intel_connector(connector)->detect_edid); |
7d57382e | 1706 | drm_connector_cleanup(connector); |
674e2d08 | 1707 | kfree(connector); |
7d57382e EA |
1708 | } |
1709 | ||
7d57382e | 1710 | static const struct drm_connector_funcs intel_hdmi_connector_funcs = { |
4d688a2a | 1711 | .dpms = drm_atomic_helper_connector_dpms, |
7d57382e | 1712 | .detect = intel_hdmi_detect, |
953ece69 | 1713 | .force = intel_hdmi_force, |
7d57382e | 1714 | .fill_modes = drm_helper_probe_single_connector_modes, |
7a5ca19f ML |
1715 | .set_property = drm_atomic_helper_connector_set_property, |
1716 | .atomic_get_property = intel_digital_connector_atomic_get_property, | |
1717 | .atomic_set_property = intel_digital_connector_atomic_set_property, | |
1ebaa0b9 | 1718 | .late_register = intel_connector_register, |
c191eca1 | 1719 | .early_unregister = intel_connector_unregister, |
7d57382e | 1720 | .destroy = intel_hdmi_destroy, |
c6f95f27 | 1721 | .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, |
7a5ca19f | 1722 | .atomic_duplicate_state = intel_digital_connector_duplicate_state, |
7d57382e EA |
1723 | }; |
1724 | ||
1725 | static const struct drm_connector_helper_funcs intel_hdmi_connector_helper_funcs = { | |
1726 | .get_modes = intel_hdmi_get_modes, | |
1727 | .mode_valid = intel_hdmi_mode_valid, | |
7a5ca19f | 1728 | .atomic_check = intel_digital_connector_atomic_check, |
7d57382e EA |
1729 | }; |
1730 | ||
7d57382e | 1731 | static const struct drm_encoder_funcs intel_hdmi_enc_funcs = { |
ea5b213a | 1732 | .destroy = intel_encoder_destroy, |
7d57382e EA |
1733 | }; |
1734 | ||
55b7d6e8 CW |
1735 | static void |
1736 | intel_hdmi_add_properties(struct intel_hdmi *intel_hdmi, struct drm_connector *connector) | |
1737 | { | |
3f43c48d | 1738 | intel_attach_force_audio_property(connector); |
e953fd7b | 1739 | intel_attach_broadcast_rgb_property(connector); |
94a11ddc | 1740 | intel_attach_aspect_ratio_property(connector); |
0e9f25d0 | 1741 | connector->state->picture_aspect_ratio = HDMI_PICTURE_ASPECT_NONE; |
55b7d6e8 CW |
1742 | } |
1743 | ||
15953637 SS |
1744 | /* |
1745 | * intel_hdmi_handle_sink_scrambling: handle sink scrambling/clock ratio setup | |
1746 | * @encoder: intel_encoder | |
1747 | * @connector: drm_connector | |
1748 | * @high_tmds_clock_ratio = bool to indicate if the function needs to set | |
1749 | * or reset the high tmds clock ratio for scrambling | |
1750 | * @scrambling: bool to Indicate if the function needs to set or reset | |
1751 | * sink scrambling | |
1752 | * | |
1753 | * This function handles scrambling on HDMI 2.0 capable sinks. | |
1754 | * If required clock rate is > 340 Mhz && scrambling is supported by sink | |
1755 | * it enables scrambling. This should be called before enabling the HDMI | |
1756 | * 2.0 port, as the sink can choose to disable the scrambling if it doesn't | |
1757 | * detect a scrambled clock within 100 ms. | |
1758 | */ | |
1759 | void intel_hdmi_handle_sink_scrambling(struct intel_encoder *encoder, | |
1760 | struct drm_connector *connector, | |
1761 | bool high_tmds_clock_ratio, | |
1762 | bool scrambling) | |
1763 | { | |
1764 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); | |
1765 | struct drm_i915_private *dev_priv = connector->dev->dev_private; | |
1766 | struct drm_scrambling *sink_scrambling = | |
1767 | &connector->display_info.hdmi.scdc.scrambling; | |
1768 | struct i2c_adapter *adptr = intel_gmbus_get_adapter(dev_priv, | |
1769 | intel_hdmi->ddc_bus); | |
1770 | bool ret; | |
1771 | ||
1772 | if (!sink_scrambling->supported) | |
1773 | return; | |
1774 | ||
1775 | DRM_DEBUG_KMS("Setting sink scrambling for enc:%s connector:%s\n", | |
1776 | encoder->base.name, connector->name); | |
1777 | ||
1778 | /* Set TMDS bit clock ratio to 1/40 or 1/10 */ | |
1779 | ret = drm_scdc_set_high_tmds_clock_ratio(adptr, high_tmds_clock_ratio); | |
1780 | if (!ret) { | |
1781 | DRM_ERROR("Set TMDS ratio failed\n"); | |
1782 | return; | |
1783 | } | |
1784 | ||
1785 | /* Enable/disable sink scrambling */ | |
1786 | ret = drm_scdc_set_scrambling(adptr, scrambling); | |
1787 | if (!ret) { | |
1788 | DRM_ERROR("Set sink scrambling failed\n"); | |
1789 | return; | |
1790 | } | |
1791 | ||
1792 | DRM_DEBUG_KMS("sink scrambling handled\n"); | |
1793 | } | |
1794 | ||
e4ab73a1 VS |
1795 | static u8 intel_hdmi_ddc_pin(struct drm_i915_private *dev_priv, |
1796 | enum port port) | |
1797 | { | |
1798 | const struct ddi_vbt_port_info *info = | |
1799 | &dev_priv->vbt.ddi_port_info[port]; | |
1800 | u8 ddc_pin; | |
1801 | ||
1802 | if (info->alternate_ddc_pin) { | |
1803 | DRM_DEBUG_KMS("Using DDC pin 0x%x for port %c (VBT)\n", | |
1804 | info->alternate_ddc_pin, port_name(port)); | |
1805 | return info->alternate_ddc_pin; | |
1806 | } | |
1807 | ||
1808 | switch (port) { | |
1809 | case PORT_B: | |
3d02352c | 1810 | if (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv)) |
e4ab73a1 VS |
1811 | ddc_pin = GMBUS_PIN_1_BXT; |
1812 | else | |
1813 | ddc_pin = GMBUS_PIN_DPB; | |
1814 | break; | |
1815 | case PORT_C: | |
3d02352c | 1816 | if (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv)) |
e4ab73a1 VS |
1817 | ddc_pin = GMBUS_PIN_2_BXT; |
1818 | else | |
1819 | ddc_pin = GMBUS_PIN_DPC; | |
1820 | break; | |
1821 | case PORT_D: | |
3d02352c RV |
1822 | if (HAS_PCH_CNP(dev_priv)) |
1823 | ddc_pin = GMBUS_PIN_4_CNP; | |
1824 | else if (IS_CHERRYVIEW(dev_priv)) | |
e4ab73a1 VS |
1825 | ddc_pin = GMBUS_PIN_DPD_CHV; |
1826 | else | |
1827 | ddc_pin = GMBUS_PIN_DPD; | |
1828 | break; | |
1829 | default: | |
1830 | MISSING_CASE(port); | |
1831 | ddc_pin = GMBUS_PIN_DPB; | |
1832 | break; | |
1833 | } | |
1834 | ||
1835 | DRM_DEBUG_KMS("Using DDC pin 0x%x for port %c (platform default)\n", | |
1836 | ddc_pin, port_name(port)); | |
1837 | ||
1838 | return ddc_pin; | |
1839 | } | |
1840 | ||
00c09d70 PZ |
1841 | void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port, |
1842 | struct intel_connector *intel_connector) | |
7d57382e | 1843 | { |
b9cb234c PZ |
1844 | struct drm_connector *connector = &intel_connector->base; |
1845 | struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi; | |
1846 | struct intel_encoder *intel_encoder = &intel_dig_port->base; | |
1847 | struct drm_device *dev = intel_encoder->base.dev; | |
fac5e23e | 1848 | struct drm_i915_private *dev_priv = to_i915(dev); |
174edf1f | 1849 | enum port port = intel_dig_port->port; |
373a3cf7 | 1850 | |
22f35042 VS |
1851 | DRM_DEBUG_KMS("Adding HDMI connector on port %c\n", |
1852 | port_name(port)); | |
1853 | ||
ccb1a831 VS |
1854 | if (WARN(intel_dig_port->max_lanes < 4, |
1855 | "Not enough lanes (%d) for HDMI on port %c\n", | |
1856 | intel_dig_port->max_lanes, port_name(port))) | |
1857 | return; | |
1858 | ||
7d57382e | 1859 | drm_connector_init(dev, connector, &intel_hdmi_connector_funcs, |
8d91104a | 1860 | DRM_MODE_CONNECTOR_HDMIA); |
7d57382e EA |
1861 | drm_connector_helper_add(connector, &intel_hdmi_connector_helper_funcs); |
1862 | ||
c3febcc4 | 1863 | connector->interlace_allowed = 1; |
7d57382e | 1864 | connector->doublescan_allowed = 0; |
573e74ad | 1865 | connector->stereo_allowed = 1; |
66a9278e | 1866 | |
e4ab73a1 VS |
1867 | intel_hdmi->ddc_bus = intel_hdmi_ddc_pin(dev_priv, port); |
1868 | ||
08d644ad DV |
1869 | switch (port) { |
1870 | case PORT_B: | |
ca4c3890 | 1871 | intel_encoder->hpd_pin = HPD_PORT_B; |
08d644ad DV |
1872 | break; |
1873 | case PORT_C: | |
1d843f9d | 1874 | intel_encoder->hpd_pin = HPD_PORT_C; |
08d644ad DV |
1875 | break; |
1876 | case PORT_D: | |
1d843f9d | 1877 | intel_encoder->hpd_pin = HPD_PORT_D; |
08d644ad | 1878 | break; |
11c1b657 | 1879 | case PORT_E: |
11c1b657 XZ |
1880 | intel_encoder->hpd_pin = HPD_PORT_E; |
1881 | break; | |
08d644ad | 1882 | default: |
e4ab73a1 VS |
1883 | MISSING_CASE(port); |
1884 | return; | |
f8aed700 | 1885 | } |
7d57382e | 1886 | |
920a14b2 | 1887 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { |
90b107c8 | 1888 | intel_hdmi->write_infoframe = vlv_write_infoframe; |
687f4d06 | 1889 | intel_hdmi->set_infoframes = vlv_set_infoframes; |
e43823ec | 1890 | intel_hdmi->infoframe_enabled = vlv_infoframe_enabled; |
9beb5fea | 1891 | } else if (IS_G4X(dev_priv)) { |
7637bfdb JB |
1892 | intel_hdmi->write_infoframe = g4x_write_infoframe; |
1893 | intel_hdmi->set_infoframes = g4x_set_infoframes; | |
e43823ec | 1894 | intel_hdmi->infoframe_enabled = g4x_infoframe_enabled; |
4f8036a2 | 1895 | } else if (HAS_DDI(dev_priv)) { |
8c5f5f7c | 1896 | intel_hdmi->write_infoframe = hsw_write_infoframe; |
687f4d06 | 1897 | intel_hdmi->set_infoframes = hsw_set_infoframes; |
e43823ec | 1898 | intel_hdmi->infoframe_enabled = hsw_infoframe_enabled; |
6e266956 | 1899 | } else if (HAS_PCH_IBX(dev_priv)) { |
fdf1250a | 1900 | intel_hdmi->write_infoframe = ibx_write_infoframe; |
687f4d06 | 1901 | intel_hdmi->set_infoframes = ibx_set_infoframes; |
e43823ec | 1902 | intel_hdmi->infoframe_enabled = ibx_infoframe_enabled; |
fdf1250a PZ |
1903 | } else { |
1904 | intel_hdmi->write_infoframe = cpt_write_infoframe; | |
687f4d06 | 1905 | intel_hdmi->set_infoframes = cpt_set_infoframes; |
e43823ec | 1906 | intel_hdmi->infoframe_enabled = cpt_infoframe_enabled; |
64a8fc01 | 1907 | } |
45187ace | 1908 | |
4f8036a2 | 1909 | if (HAS_DDI(dev_priv)) |
bcbc889b PZ |
1910 | intel_connector->get_hw_state = intel_ddi_connector_get_hw_state; |
1911 | else | |
1912 | intel_connector->get_hw_state = intel_connector_get_hw_state; | |
b9cb234c PZ |
1913 | |
1914 | intel_hdmi_add_properties(intel_hdmi, connector); | |
1915 | ||
1916 | intel_connector_attach_encoder(intel_connector, intel_encoder); | |
d8b4c43a | 1917 | intel_hdmi->attached_connector = intel_connector; |
b9cb234c PZ |
1918 | |
1919 | /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written | |
1920 | * 0xd. Failure to do so will result in spurious interrupts being | |
1921 | * generated on the port when a cable is not attached. | |
1922 | */ | |
50a0bc90 | 1923 | if (IS_G4X(dev_priv) && !IS_GM45(dev_priv)) { |
b9cb234c PZ |
1924 | u32 temp = I915_READ(PEG_BAND_GAP_DATA); |
1925 | I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd); | |
1926 | } | |
1927 | } | |
1928 | ||
c39055b0 | 1929 | void intel_hdmi_init(struct drm_i915_private *dev_priv, |
f0f59a00 | 1930 | i915_reg_t hdmi_reg, enum port port) |
b9cb234c PZ |
1931 | { |
1932 | struct intel_digital_port *intel_dig_port; | |
1933 | struct intel_encoder *intel_encoder; | |
b9cb234c PZ |
1934 | struct intel_connector *intel_connector; |
1935 | ||
b14c5679 | 1936 | intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL); |
b9cb234c PZ |
1937 | if (!intel_dig_port) |
1938 | return; | |
1939 | ||
08d9bc92 | 1940 | intel_connector = intel_connector_alloc(); |
b9cb234c PZ |
1941 | if (!intel_connector) { |
1942 | kfree(intel_dig_port); | |
1943 | return; | |
1944 | } | |
1945 | ||
1946 | intel_encoder = &intel_dig_port->base; | |
b9cb234c | 1947 | |
c39055b0 ACO |
1948 | drm_encoder_init(&dev_priv->drm, &intel_encoder->base, |
1949 | &intel_hdmi_enc_funcs, DRM_MODE_ENCODER_TMDS, | |
1950 | "HDMI %c", port_name(port)); | |
00c09d70 | 1951 | |
5bfe2ac0 | 1952 | intel_encoder->compute_config = intel_hdmi_compute_config; |
6e266956 | 1953 | if (HAS_PCH_SPLIT(dev_priv)) { |
a4790cec VS |
1954 | intel_encoder->disable = pch_disable_hdmi; |
1955 | intel_encoder->post_disable = pch_post_disable_hdmi; | |
1956 | } else { | |
1957 | intel_encoder->disable = g4x_disable_hdmi; | |
1958 | } | |
00c09d70 | 1959 | intel_encoder->get_hw_state = intel_hdmi_get_hw_state; |
045ac3b5 | 1960 | intel_encoder->get_config = intel_hdmi_get_config; |
920a14b2 | 1961 | if (IS_CHERRYVIEW(dev_priv)) { |
9197c88b | 1962 | intel_encoder->pre_pll_enable = chv_hdmi_pre_pll_enable; |
e4a1d846 CML |
1963 | intel_encoder->pre_enable = chv_hdmi_pre_enable; |
1964 | intel_encoder->enable = vlv_enable_hdmi; | |
580d3811 | 1965 | intel_encoder->post_disable = chv_hdmi_post_disable; |
d6db995f | 1966 | intel_encoder->post_pll_disable = chv_hdmi_post_pll_disable; |
11a914c2 | 1967 | } else if (IS_VALLEYVIEW(dev_priv)) { |
9514ac6e CML |
1968 | intel_encoder->pre_pll_enable = vlv_hdmi_pre_pll_enable; |
1969 | intel_encoder->pre_enable = vlv_hdmi_pre_enable; | |
b76cf76b | 1970 | intel_encoder->enable = vlv_enable_hdmi; |
9514ac6e | 1971 | intel_encoder->post_disable = vlv_hdmi_post_disable; |
b76cf76b | 1972 | } else { |
13732ba7 | 1973 | intel_encoder->pre_enable = intel_hdmi_pre_enable; |
6e266956 | 1974 | if (HAS_PCH_CPT(dev_priv)) |
d1b1589c | 1975 | intel_encoder->enable = cpt_enable_hdmi; |
6e266956 | 1976 | else if (HAS_PCH_IBX(dev_priv)) |
bf868c7d | 1977 | intel_encoder->enable = ibx_enable_hdmi; |
d1b1589c | 1978 | else |
bf868c7d | 1979 | intel_encoder->enable = g4x_enable_hdmi; |
89b667f8 | 1980 | } |
5ab432ef | 1981 | |
b9cb234c | 1982 | intel_encoder->type = INTEL_OUTPUT_HDMI; |
79f255a0 | 1983 | intel_encoder->power_domain = intel_port_to_power_domain(port); |
03cdc1d4 | 1984 | intel_encoder->port = port; |
920a14b2 | 1985 | if (IS_CHERRYVIEW(dev_priv)) { |
882ec384 VS |
1986 | if (port == PORT_D) |
1987 | intel_encoder->crtc_mask = 1 << 2; | |
1988 | else | |
1989 | intel_encoder->crtc_mask = (1 << 0) | (1 << 1); | |
1990 | } else { | |
1991 | intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2); | |
1992 | } | |
301ea74a | 1993 | intel_encoder->cloneable = 1 << INTEL_OUTPUT_ANALOG; |
c6f1495d VS |
1994 | /* |
1995 | * BSpec is unclear about HDMI+HDMI cloning on g4x, but it seems | |
1996 | * to work on real hardware. And since g4x can send infoframes to | |
1997 | * only one port anyway, nothing is lost by allowing it. | |
1998 | */ | |
9beb5fea | 1999 | if (IS_G4X(dev_priv)) |
c6f1495d | 2000 | intel_encoder->cloneable |= 1 << INTEL_OUTPUT_HDMI; |
7d57382e | 2001 | |
174edf1f | 2002 | intel_dig_port->port = port; |
b242b7f7 | 2003 | intel_dig_port->hdmi.hdmi_reg = hdmi_reg; |
f0f59a00 | 2004 | intel_dig_port->dp.output_reg = INVALID_MMIO_REG; |
ccb1a831 | 2005 | intel_dig_port->max_lanes = 4; |
55b7d6e8 | 2006 | |
b9cb234c | 2007 | intel_hdmi_init_connector(intel_dig_port, intel_connector); |
7d57382e | 2008 | } |