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7d57382e EA |
1 | /* |
2 | * Copyright 2006 Dave Airlie <airlied@linux.ie> | |
3 | * Copyright © 2006-2009 Intel Corporation | |
4 | * | |
5 | * Permission is hereby granted, free of charge, to any person obtaining a | |
6 | * copy of this software and associated documentation files (the "Software"), | |
7 | * to deal in the Software without restriction, including without limitation | |
8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
9 | * and/or sell copies of the Software, and to permit persons to whom the | |
10 | * Software is furnished to do so, subject to the following conditions: | |
11 | * | |
12 | * The above copyright notice and this permission notice (including the next | |
13 | * paragraph) shall be included in all copies or substantial portions of the | |
14 | * Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
21 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
22 | * DEALINGS IN THE SOFTWARE. | |
23 | * | |
24 | * Authors: | |
25 | * Eric Anholt <eric@anholt.net> | |
26 | * Jesse Barnes <jesse.barnes@intel.com> | |
27 | */ | |
28 | ||
29 | #include <linux/i2c.h> | |
5a0e3ad6 | 30 | #include <linux/slab.h> |
7d57382e | 31 | #include <linux/delay.h> |
760285e7 DH |
32 | #include <drm/drmP.h> |
33 | #include <drm/drm_crtc.h> | |
34 | #include <drm/drm_edid.h> | |
7d57382e | 35 | #include "intel_drv.h" |
760285e7 | 36 | #include <drm/i915_drm.h> |
7d57382e EA |
37 | #include "i915_drv.h" |
38 | ||
afba0188 DV |
39 | static void |
40 | assert_hdmi_port_disabled(struct intel_hdmi *intel_hdmi) | |
41 | { | |
42 | struct drm_device *dev = intel_hdmi->base.base.dev; | |
43 | struct drm_i915_private *dev_priv = dev->dev_private; | |
44 | uint32_t enabled_bits; | |
45 | ||
46 | enabled_bits = IS_HASWELL(dev) ? DDI_BUF_CTL_ENABLE : SDVO_ENABLE; | |
47 | ||
48 | WARN(I915_READ(intel_hdmi->sdvox_reg) & enabled_bits, | |
49 | "HDMI port enabled, expecting disabled\n"); | |
50 | } | |
51 | ||
f5bbfca3 | 52 | struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder) |
ea5b213a | 53 | { |
4ef69c7a | 54 | return container_of(encoder, struct intel_hdmi, base.base); |
ea5b213a CW |
55 | } |
56 | ||
df0e9248 CW |
57 | static struct intel_hdmi *intel_attached_hdmi(struct drm_connector *connector) |
58 | { | |
59 | return container_of(intel_attached_encoder(connector), | |
60 | struct intel_hdmi, base); | |
61 | } | |
62 | ||
45187ace | 63 | void intel_dip_infoframe_csum(struct dip_infoframe *frame) |
3c17fe4b | 64 | { |
45187ace | 65 | uint8_t *data = (uint8_t *)frame; |
3c17fe4b DH |
66 | uint8_t sum = 0; |
67 | unsigned i; | |
68 | ||
45187ace JB |
69 | frame->checksum = 0; |
70 | frame->ecc = 0; | |
3c17fe4b | 71 | |
64a8fc01 | 72 | for (i = 0; i < frame->len + DIP_HEADER_SIZE; i++) |
3c17fe4b DH |
73 | sum += data[i]; |
74 | ||
45187ace | 75 | frame->checksum = 0x100 - sum; |
3c17fe4b DH |
76 | } |
77 | ||
bc2481f3 | 78 | static u32 g4x_infoframe_index(struct dip_infoframe *frame) |
3c17fe4b | 79 | { |
45187ace JB |
80 | switch (frame->type) { |
81 | case DIP_TYPE_AVI: | |
ed517fbb | 82 | return VIDEO_DIP_SELECT_AVI; |
45187ace | 83 | case DIP_TYPE_SPD: |
ed517fbb | 84 | return VIDEO_DIP_SELECT_SPD; |
45187ace JB |
85 | default: |
86 | DRM_DEBUG_DRIVER("unknown info frame type %d\n", frame->type); | |
ed517fbb | 87 | return 0; |
45187ace | 88 | } |
45187ace JB |
89 | } |
90 | ||
bc2481f3 | 91 | static u32 g4x_infoframe_enable(struct dip_infoframe *frame) |
45187ace | 92 | { |
45187ace JB |
93 | switch (frame->type) { |
94 | case DIP_TYPE_AVI: | |
ed517fbb | 95 | return VIDEO_DIP_ENABLE_AVI; |
45187ace | 96 | case DIP_TYPE_SPD: |
ed517fbb | 97 | return VIDEO_DIP_ENABLE_SPD; |
fa193ff7 PZ |
98 | default: |
99 | DRM_DEBUG_DRIVER("unknown info frame type %d\n", frame->type); | |
ed517fbb | 100 | return 0; |
fa193ff7 | 101 | } |
fa193ff7 PZ |
102 | } |
103 | ||
2da8af54 PZ |
104 | static u32 hsw_infoframe_enable(struct dip_infoframe *frame) |
105 | { | |
106 | switch (frame->type) { | |
107 | case DIP_TYPE_AVI: | |
108 | return VIDEO_DIP_ENABLE_AVI_HSW; | |
109 | case DIP_TYPE_SPD: | |
110 | return VIDEO_DIP_ENABLE_SPD_HSW; | |
111 | default: | |
112 | DRM_DEBUG_DRIVER("unknown info frame type %d\n", frame->type); | |
113 | return 0; | |
114 | } | |
115 | } | |
116 | ||
117 | static u32 hsw_infoframe_data_reg(struct dip_infoframe *frame, enum pipe pipe) | |
118 | { | |
119 | switch (frame->type) { | |
120 | case DIP_TYPE_AVI: | |
121 | return HSW_TVIDEO_DIP_AVI_DATA(pipe); | |
122 | case DIP_TYPE_SPD: | |
123 | return HSW_TVIDEO_DIP_SPD_DATA(pipe); | |
124 | default: | |
125 | DRM_DEBUG_DRIVER("unknown info frame type %d\n", frame->type); | |
126 | return 0; | |
127 | } | |
128 | } | |
129 | ||
a3da1df7 DV |
130 | static void g4x_write_infoframe(struct drm_encoder *encoder, |
131 | struct dip_infoframe *frame) | |
45187ace JB |
132 | { |
133 | uint32_t *data = (uint32_t *)frame; | |
3c17fe4b DH |
134 | struct drm_device *dev = encoder->dev; |
135 | struct drm_i915_private *dev_priv = dev->dev_private; | |
22509ec8 | 136 | u32 val = I915_READ(VIDEO_DIP_CTL); |
45187ace | 137 | unsigned i, len = DIP_HEADER_SIZE + frame->len; |
3c17fe4b | 138 | |
822974ae PZ |
139 | WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n"); |
140 | ||
1d4f85ac | 141 | val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ |
bc2481f3 | 142 | val |= g4x_infoframe_index(frame); |
22509ec8 | 143 | |
bc2481f3 | 144 | val &= ~g4x_infoframe_enable(frame); |
45187ace | 145 | |
22509ec8 | 146 | I915_WRITE(VIDEO_DIP_CTL, val); |
3c17fe4b | 147 | |
9d9740f0 | 148 | mmiowb(); |
45187ace | 149 | for (i = 0; i < len; i += 4) { |
3c17fe4b DH |
150 | I915_WRITE(VIDEO_DIP_DATA, *data); |
151 | data++; | |
152 | } | |
adf00b26 PZ |
153 | /* Write every possible data byte to force correct ECC calculation. */ |
154 | for (; i < VIDEO_DIP_DATA_SIZE; i += 4) | |
155 | I915_WRITE(VIDEO_DIP_DATA, 0); | |
9d9740f0 | 156 | mmiowb(); |
3c17fe4b | 157 | |
bc2481f3 | 158 | val |= g4x_infoframe_enable(frame); |
60c5ea2d | 159 | val &= ~VIDEO_DIP_FREQ_MASK; |
4b24c933 | 160 | val |= VIDEO_DIP_FREQ_VSYNC; |
45187ace | 161 | |
22509ec8 | 162 | I915_WRITE(VIDEO_DIP_CTL, val); |
9d9740f0 | 163 | POSTING_READ(VIDEO_DIP_CTL); |
3c17fe4b DH |
164 | } |
165 | ||
fdf1250a PZ |
166 | static void ibx_write_infoframe(struct drm_encoder *encoder, |
167 | struct dip_infoframe *frame) | |
168 | { | |
169 | uint32_t *data = (uint32_t *)frame; | |
170 | struct drm_device *dev = encoder->dev; | |
171 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ed517fbb | 172 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); |
fdf1250a PZ |
173 | int reg = TVIDEO_DIP_CTL(intel_crtc->pipe); |
174 | unsigned i, len = DIP_HEADER_SIZE + frame->len; | |
175 | u32 val = I915_READ(reg); | |
176 | ||
822974ae PZ |
177 | WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n"); |
178 | ||
fdf1250a | 179 | val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ |
bc2481f3 | 180 | val |= g4x_infoframe_index(frame); |
fdf1250a | 181 | |
bc2481f3 | 182 | val &= ~g4x_infoframe_enable(frame); |
fdf1250a PZ |
183 | |
184 | I915_WRITE(reg, val); | |
185 | ||
9d9740f0 | 186 | mmiowb(); |
fdf1250a PZ |
187 | for (i = 0; i < len; i += 4) { |
188 | I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data); | |
189 | data++; | |
190 | } | |
adf00b26 PZ |
191 | /* Write every possible data byte to force correct ECC calculation. */ |
192 | for (; i < VIDEO_DIP_DATA_SIZE; i += 4) | |
193 | I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0); | |
9d9740f0 | 194 | mmiowb(); |
fdf1250a | 195 | |
bc2481f3 | 196 | val |= g4x_infoframe_enable(frame); |
fdf1250a | 197 | val &= ~VIDEO_DIP_FREQ_MASK; |
4b24c933 | 198 | val |= VIDEO_DIP_FREQ_VSYNC; |
fdf1250a PZ |
199 | |
200 | I915_WRITE(reg, val); | |
9d9740f0 | 201 | POSTING_READ(reg); |
fdf1250a PZ |
202 | } |
203 | ||
204 | static void cpt_write_infoframe(struct drm_encoder *encoder, | |
205 | struct dip_infoframe *frame) | |
b055c8f3 | 206 | { |
45187ace | 207 | uint32_t *data = (uint32_t *)frame; |
b055c8f3 JB |
208 | struct drm_device *dev = encoder->dev; |
209 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ed517fbb | 210 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); |
b055c8f3 | 211 | int reg = TVIDEO_DIP_CTL(intel_crtc->pipe); |
45187ace | 212 | unsigned i, len = DIP_HEADER_SIZE + frame->len; |
22509ec8 | 213 | u32 val = I915_READ(reg); |
b055c8f3 | 214 | |
822974ae PZ |
215 | WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n"); |
216 | ||
64a8fc01 | 217 | val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ |
bc2481f3 | 218 | val |= g4x_infoframe_index(frame); |
45187ace | 219 | |
ecb97851 PZ |
220 | /* The DIP control register spec says that we need to update the AVI |
221 | * infoframe without clearing its enable bit */ | |
822974ae | 222 | if (frame->type != DIP_TYPE_AVI) |
bc2481f3 | 223 | val &= ~g4x_infoframe_enable(frame); |
ecb97851 | 224 | |
22509ec8 | 225 | I915_WRITE(reg, val); |
45187ace | 226 | |
9d9740f0 | 227 | mmiowb(); |
45187ace | 228 | for (i = 0; i < len; i += 4) { |
b055c8f3 JB |
229 | I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data); |
230 | data++; | |
231 | } | |
adf00b26 PZ |
232 | /* Write every possible data byte to force correct ECC calculation. */ |
233 | for (; i < VIDEO_DIP_DATA_SIZE; i += 4) | |
234 | I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0); | |
9d9740f0 | 235 | mmiowb(); |
b055c8f3 | 236 | |
bc2481f3 | 237 | val |= g4x_infoframe_enable(frame); |
60c5ea2d | 238 | val &= ~VIDEO_DIP_FREQ_MASK; |
4b24c933 | 239 | val |= VIDEO_DIP_FREQ_VSYNC; |
45187ace | 240 | |
22509ec8 | 241 | I915_WRITE(reg, val); |
9d9740f0 | 242 | POSTING_READ(reg); |
45187ace | 243 | } |
90b107c8 SK |
244 | |
245 | static void vlv_write_infoframe(struct drm_encoder *encoder, | |
246 | struct dip_infoframe *frame) | |
247 | { | |
248 | uint32_t *data = (uint32_t *)frame; | |
249 | struct drm_device *dev = encoder->dev; | |
250 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ed517fbb | 251 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); |
90b107c8 SK |
252 | int reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe); |
253 | unsigned i, len = DIP_HEADER_SIZE + frame->len; | |
22509ec8 | 254 | u32 val = I915_READ(reg); |
90b107c8 | 255 | |
822974ae PZ |
256 | WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n"); |
257 | ||
90b107c8 | 258 | val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ |
bc2481f3 | 259 | val |= g4x_infoframe_index(frame); |
22509ec8 | 260 | |
bc2481f3 | 261 | val &= ~g4x_infoframe_enable(frame); |
90b107c8 | 262 | |
22509ec8 | 263 | I915_WRITE(reg, val); |
90b107c8 | 264 | |
9d9740f0 | 265 | mmiowb(); |
90b107c8 SK |
266 | for (i = 0; i < len; i += 4) { |
267 | I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), *data); | |
268 | data++; | |
269 | } | |
adf00b26 PZ |
270 | /* Write every possible data byte to force correct ECC calculation. */ |
271 | for (; i < VIDEO_DIP_DATA_SIZE; i += 4) | |
272 | I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), 0); | |
9d9740f0 | 273 | mmiowb(); |
90b107c8 | 274 | |
bc2481f3 | 275 | val |= g4x_infoframe_enable(frame); |
60c5ea2d | 276 | val &= ~VIDEO_DIP_FREQ_MASK; |
4b24c933 | 277 | val |= VIDEO_DIP_FREQ_VSYNC; |
90b107c8 | 278 | |
22509ec8 | 279 | I915_WRITE(reg, val); |
9d9740f0 | 280 | POSTING_READ(reg); |
90b107c8 SK |
281 | } |
282 | ||
8c5f5f7c | 283 | static void hsw_write_infoframe(struct drm_encoder *encoder, |
ed517fbb | 284 | struct dip_infoframe *frame) |
8c5f5f7c | 285 | { |
2da8af54 PZ |
286 | uint32_t *data = (uint32_t *)frame; |
287 | struct drm_device *dev = encoder->dev; | |
288 | struct drm_i915_private *dev_priv = dev->dev_private; | |
289 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); | |
290 | u32 ctl_reg = HSW_TVIDEO_DIP_CTL(intel_crtc->pipe); | |
291 | u32 data_reg = hsw_infoframe_data_reg(frame, intel_crtc->pipe); | |
292 | unsigned int i, len = DIP_HEADER_SIZE + frame->len; | |
293 | u32 val = I915_READ(ctl_reg); | |
8c5f5f7c | 294 | |
2da8af54 PZ |
295 | if (data_reg == 0) |
296 | return; | |
297 | ||
2da8af54 PZ |
298 | val &= ~hsw_infoframe_enable(frame); |
299 | I915_WRITE(ctl_reg, val); | |
300 | ||
9d9740f0 | 301 | mmiowb(); |
2da8af54 PZ |
302 | for (i = 0; i < len; i += 4) { |
303 | I915_WRITE(data_reg + i, *data); | |
304 | data++; | |
305 | } | |
adf00b26 PZ |
306 | /* Write every possible data byte to force correct ECC calculation. */ |
307 | for (; i < VIDEO_DIP_DATA_SIZE; i += 4) | |
308 | I915_WRITE(data_reg + i, 0); | |
9d9740f0 | 309 | mmiowb(); |
8c5f5f7c | 310 | |
2da8af54 PZ |
311 | val |= hsw_infoframe_enable(frame); |
312 | I915_WRITE(ctl_reg, val); | |
9d9740f0 | 313 | POSTING_READ(ctl_reg); |
8c5f5f7c ED |
314 | } |
315 | ||
45187ace JB |
316 | static void intel_set_infoframe(struct drm_encoder *encoder, |
317 | struct dip_infoframe *frame) | |
318 | { | |
319 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); | |
320 | ||
45187ace JB |
321 | intel_dip_infoframe_csum(frame); |
322 | intel_hdmi->write_infoframe(encoder, frame); | |
323 | } | |
324 | ||
687f4d06 | 325 | static void intel_hdmi_set_avi_infoframe(struct drm_encoder *encoder, |
c846b619 | 326 | struct drm_display_mode *adjusted_mode) |
45187ace JB |
327 | { |
328 | struct dip_infoframe avi_if = { | |
329 | .type = DIP_TYPE_AVI, | |
330 | .ver = DIP_VERSION_AVI, | |
331 | .len = DIP_LEN_AVI, | |
332 | }; | |
333 | ||
c846b619 PZ |
334 | if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK) |
335 | avi_if.body.avi.YQ_CN_PR |= DIP_AVI_PR_2; | |
336 | ||
45187ace | 337 | intel_set_infoframe(encoder, &avi_if); |
b055c8f3 JB |
338 | } |
339 | ||
687f4d06 | 340 | static void intel_hdmi_set_spd_infoframe(struct drm_encoder *encoder) |
c0864cb3 JB |
341 | { |
342 | struct dip_infoframe spd_if; | |
343 | ||
344 | memset(&spd_if, 0, sizeof(spd_if)); | |
345 | spd_if.type = DIP_TYPE_SPD; | |
346 | spd_if.ver = DIP_VERSION_SPD; | |
347 | spd_if.len = DIP_LEN_SPD; | |
348 | strcpy(spd_if.body.spd.vn, "Intel"); | |
349 | strcpy(spd_if.body.spd.pd, "Integrated gfx"); | |
350 | spd_if.body.spd.sdi = DIP_SPD_PC; | |
351 | ||
352 | intel_set_infoframe(encoder, &spd_if); | |
353 | } | |
354 | ||
687f4d06 PZ |
355 | static void g4x_set_infoframes(struct drm_encoder *encoder, |
356 | struct drm_display_mode *adjusted_mode) | |
357 | { | |
0c14c7f9 PZ |
358 | struct drm_i915_private *dev_priv = encoder->dev->dev_private; |
359 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); | |
360 | u32 reg = VIDEO_DIP_CTL; | |
361 | u32 val = I915_READ(reg); | |
72b78c9d | 362 | u32 port; |
0c14c7f9 | 363 | |
afba0188 DV |
364 | assert_hdmi_port_disabled(intel_hdmi); |
365 | ||
0c14c7f9 PZ |
366 | /* If the registers were not initialized yet, they might be zeroes, |
367 | * which means we're selecting the AVI DIP and we're setting its | |
368 | * frequency to once. This seems to really confuse the HW and make | |
369 | * things stop working (the register spec says the AVI always needs to | |
370 | * be sent every VSync). So here we avoid writing to the register more | |
371 | * than we need and also explicitly select the AVI DIP and explicitly | |
372 | * set its frequency to every VSync. Avoiding to write it twice seems to | |
373 | * be enough to solve the problem, but being defensive shouldn't hurt us | |
374 | * either. */ | |
375 | val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; | |
376 | ||
377 | if (!intel_hdmi->has_hdmi_sink) { | |
378 | if (!(val & VIDEO_DIP_ENABLE)) | |
379 | return; | |
380 | val &= ~VIDEO_DIP_ENABLE; | |
381 | I915_WRITE(reg, val); | |
9d9740f0 | 382 | POSTING_READ(reg); |
0c14c7f9 PZ |
383 | return; |
384 | } | |
385 | ||
f278d972 PZ |
386 | switch (intel_hdmi->sdvox_reg) { |
387 | case SDVOB: | |
72b78c9d | 388 | port = VIDEO_DIP_PORT_B; |
f278d972 PZ |
389 | break; |
390 | case SDVOC: | |
72b78c9d | 391 | port = VIDEO_DIP_PORT_C; |
f278d972 PZ |
392 | break; |
393 | default: | |
57df2ae9 | 394 | BUG(); |
f278d972 PZ |
395 | return; |
396 | } | |
397 | ||
72b78c9d PZ |
398 | if (port != (val & VIDEO_DIP_PORT_MASK)) { |
399 | if (val & VIDEO_DIP_ENABLE) { | |
400 | val &= ~VIDEO_DIP_ENABLE; | |
401 | I915_WRITE(reg, val); | |
9d9740f0 | 402 | POSTING_READ(reg); |
72b78c9d PZ |
403 | } |
404 | val &= ~VIDEO_DIP_PORT_MASK; | |
405 | val |= port; | |
406 | } | |
407 | ||
822974ae | 408 | val |= VIDEO_DIP_ENABLE; |
0dd87d20 | 409 | val &= ~VIDEO_DIP_ENABLE_VENDOR; |
822974ae | 410 | |
f278d972 | 411 | I915_WRITE(reg, val); |
9d9740f0 | 412 | POSTING_READ(reg); |
f278d972 | 413 | |
687f4d06 PZ |
414 | intel_hdmi_set_avi_infoframe(encoder, adjusted_mode); |
415 | intel_hdmi_set_spd_infoframe(encoder); | |
416 | } | |
417 | ||
418 | static void ibx_set_infoframes(struct drm_encoder *encoder, | |
419 | struct drm_display_mode *adjusted_mode) | |
420 | { | |
0c14c7f9 PZ |
421 | struct drm_i915_private *dev_priv = encoder->dev->dev_private; |
422 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); | |
423 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); | |
424 | u32 reg = TVIDEO_DIP_CTL(intel_crtc->pipe); | |
425 | u32 val = I915_READ(reg); | |
72b78c9d | 426 | u32 port; |
0c14c7f9 | 427 | |
afba0188 DV |
428 | assert_hdmi_port_disabled(intel_hdmi); |
429 | ||
0c14c7f9 PZ |
430 | /* See the big comment in g4x_set_infoframes() */ |
431 | val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; | |
432 | ||
433 | if (!intel_hdmi->has_hdmi_sink) { | |
434 | if (!(val & VIDEO_DIP_ENABLE)) | |
435 | return; | |
436 | val &= ~VIDEO_DIP_ENABLE; | |
437 | I915_WRITE(reg, val); | |
9d9740f0 | 438 | POSTING_READ(reg); |
0c14c7f9 PZ |
439 | return; |
440 | } | |
441 | ||
f278d972 PZ |
442 | switch (intel_hdmi->sdvox_reg) { |
443 | case HDMIB: | |
72b78c9d | 444 | port = VIDEO_DIP_PORT_B; |
f278d972 PZ |
445 | break; |
446 | case HDMIC: | |
72b78c9d | 447 | port = VIDEO_DIP_PORT_C; |
f278d972 PZ |
448 | break; |
449 | case HDMID: | |
72b78c9d | 450 | port = VIDEO_DIP_PORT_D; |
f278d972 PZ |
451 | break; |
452 | default: | |
57df2ae9 | 453 | BUG(); |
f278d972 PZ |
454 | return; |
455 | } | |
456 | ||
72b78c9d PZ |
457 | if (port != (val & VIDEO_DIP_PORT_MASK)) { |
458 | if (val & VIDEO_DIP_ENABLE) { | |
459 | val &= ~VIDEO_DIP_ENABLE; | |
460 | I915_WRITE(reg, val); | |
9d9740f0 | 461 | POSTING_READ(reg); |
72b78c9d PZ |
462 | } |
463 | val &= ~VIDEO_DIP_PORT_MASK; | |
464 | val |= port; | |
465 | } | |
466 | ||
822974ae | 467 | val |= VIDEO_DIP_ENABLE; |
0dd87d20 PZ |
468 | val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | |
469 | VIDEO_DIP_ENABLE_GCP); | |
822974ae | 470 | |
f278d972 | 471 | I915_WRITE(reg, val); |
9d9740f0 | 472 | POSTING_READ(reg); |
f278d972 | 473 | |
687f4d06 PZ |
474 | intel_hdmi_set_avi_infoframe(encoder, adjusted_mode); |
475 | intel_hdmi_set_spd_infoframe(encoder); | |
476 | } | |
477 | ||
478 | static void cpt_set_infoframes(struct drm_encoder *encoder, | |
479 | struct drm_display_mode *adjusted_mode) | |
480 | { | |
0c14c7f9 PZ |
481 | struct drm_i915_private *dev_priv = encoder->dev->dev_private; |
482 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); | |
483 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); | |
484 | u32 reg = TVIDEO_DIP_CTL(intel_crtc->pipe); | |
485 | u32 val = I915_READ(reg); | |
486 | ||
afba0188 DV |
487 | assert_hdmi_port_disabled(intel_hdmi); |
488 | ||
0c14c7f9 PZ |
489 | /* See the big comment in g4x_set_infoframes() */ |
490 | val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; | |
491 | ||
492 | if (!intel_hdmi->has_hdmi_sink) { | |
493 | if (!(val & VIDEO_DIP_ENABLE)) | |
494 | return; | |
495 | val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI); | |
496 | I915_WRITE(reg, val); | |
9d9740f0 | 497 | POSTING_READ(reg); |
0c14c7f9 PZ |
498 | return; |
499 | } | |
500 | ||
822974ae PZ |
501 | /* Set both together, unset both together: see the spec. */ |
502 | val |= VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI; | |
0dd87d20 PZ |
503 | val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | |
504 | VIDEO_DIP_ENABLE_GCP); | |
822974ae PZ |
505 | |
506 | I915_WRITE(reg, val); | |
9d9740f0 | 507 | POSTING_READ(reg); |
822974ae | 508 | |
687f4d06 PZ |
509 | intel_hdmi_set_avi_infoframe(encoder, adjusted_mode); |
510 | intel_hdmi_set_spd_infoframe(encoder); | |
511 | } | |
512 | ||
513 | static void vlv_set_infoframes(struct drm_encoder *encoder, | |
514 | struct drm_display_mode *adjusted_mode) | |
515 | { | |
0c14c7f9 PZ |
516 | struct drm_i915_private *dev_priv = encoder->dev->dev_private; |
517 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); | |
518 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); | |
519 | u32 reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe); | |
520 | u32 val = I915_READ(reg); | |
521 | ||
afba0188 DV |
522 | assert_hdmi_port_disabled(intel_hdmi); |
523 | ||
0c14c7f9 PZ |
524 | /* See the big comment in g4x_set_infoframes() */ |
525 | val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; | |
526 | ||
527 | if (!intel_hdmi->has_hdmi_sink) { | |
528 | if (!(val & VIDEO_DIP_ENABLE)) | |
529 | return; | |
530 | val &= ~VIDEO_DIP_ENABLE; | |
531 | I915_WRITE(reg, val); | |
9d9740f0 | 532 | POSTING_READ(reg); |
0c14c7f9 PZ |
533 | return; |
534 | } | |
535 | ||
822974ae | 536 | val |= VIDEO_DIP_ENABLE; |
0dd87d20 PZ |
537 | val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | |
538 | VIDEO_DIP_ENABLE_GCP); | |
822974ae PZ |
539 | |
540 | I915_WRITE(reg, val); | |
9d9740f0 | 541 | POSTING_READ(reg); |
822974ae | 542 | |
687f4d06 PZ |
543 | intel_hdmi_set_avi_infoframe(encoder, adjusted_mode); |
544 | intel_hdmi_set_spd_infoframe(encoder); | |
545 | } | |
546 | ||
547 | static void hsw_set_infoframes(struct drm_encoder *encoder, | |
548 | struct drm_display_mode *adjusted_mode) | |
549 | { | |
0c14c7f9 PZ |
550 | struct drm_i915_private *dev_priv = encoder->dev->dev_private; |
551 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); | |
552 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); | |
553 | u32 reg = HSW_TVIDEO_DIP_CTL(intel_crtc->pipe); | |
0dd87d20 | 554 | u32 val = I915_READ(reg); |
0c14c7f9 | 555 | |
afba0188 DV |
556 | assert_hdmi_port_disabled(intel_hdmi); |
557 | ||
0c14c7f9 PZ |
558 | if (!intel_hdmi->has_hdmi_sink) { |
559 | I915_WRITE(reg, 0); | |
9d9740f0 | 560 | POSTING_READ(reg); |
0c14c7f9 PZ |
561 | return; |
562 | } | |
563 | ||
0dd87d20 PZ |
564 | val &= ~(VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_GCP_HSW | |
565 | VIDEO_DIP_ENABLE_VS_HSW | VIDEO_DIP_ENABLE_GMP_HSW); | |
566 | ||
567 | I915_WRITE(reg, val); | |
9d9740f0 | 568 | POSTING_READ(reg); |
0dd87d20 | 569 | |
687f4d06 PZ |
570 | intel_hdmi_set_avi_infoframe(encoder, adjusted_mode); |
571 | intel_hdmi_set_spd_infoframe(encoder); | |
572 | } | |
573 | ||
7d57382e EA |
574 | static void intel_hdmi_mode_set(struct drm_encoder *encoder, |
575 | struct drm_display_mode *mode, | |
576 | struct drm_display_mode *adjusted_mode) | |
577 | { | |
578 | struct drm_device *dev = encoder->dev; | |
579 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ed517fbb | 580 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); |
ea5b213a | 581 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); |
7d57382e EA |
582 | u32 sdvox; |
583 | ||
b659c3db | 584 | sdvox = SDVO_ENCODING_HDMI; |
5d4fac97 JB |
585 | if (!HAS_PCH_SPLIT(dev)) |
586 | sdvox |= intel_hdmi->color_range; | |
b599c0bc AJ |
587 | if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) |
588 | sdvox |= SDVO_VSYNC_ACTIVE_HIGH; | |
589 | if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) | |
590 | sdvox |= SDVO_HSYNC_ACTIVE_HIGH; | |
7d57382e | 591 | |
020f6704 JB |
592 | if (intel_crtc->bpp > 24) |
593 | sdvox |= COLOR_FORMAT_12bpc; | |
594 | else | |
595 | sdvox |= COLOR_FORMAT_8bpc; | |
596 | ||
2e3d6006 ZW |
597 | /* Required on CPT */ |
598 | if (intel_hdmi->has_hdmi_sink && HAS_PCH_CPT(dev)) | |
599 | sdvox |= HDMI_MODE_SELECT; | |
600 | ||
3c17fe4b | 601 | if (intel_hdmi->has_audio) { |
e0dac65e WF |
602 | DRM_DEBUG_DRIVER("Enabling HDMI audio on pipe %c\n", |
603 | pipe_name(intel_crtc->pipe)); | |
7d57382e | 604 | sdvox |= SDVO_AUDIO_ENABLE; |
3c17fe4b | 605 | sdvox |= SDVO_NULL_PACKETS_DURING_VSYNC; |
e0dac65e | 606 | intel_write_eld(encoder, adjusted_mode); |
3c17fe4b | 607 | } |
7d57382e | 608 | |
75770564 JB |
609 | if (HAS_PCH_CPT(dev)) |
610 | sdvox |= PORT_TRANS_SEL_CPT(intel_crtc->pipe); | |
7a87c289 | 611 | else if (intel_crtc->pipe == PIPE_B) |
75770564 | 612 | sdvox |= SDVO_PIPE_B_SELECT; |
7d57382e | 613 | |
ea5b213a CW |
614 | I915_WRITE(intel_hdmi->sdvox_reg, sdvox); |
615 | POSTING_READ(intel_hdmi->sdvox_reg); | |
3c17fe4b | 616 | |
687f4d06 | 617 | intel_hdmi->set_infoframes(encoder, adjusted_mode); |
7d57382e EA |
618 | } |
619 | ||
85234cdc DV |
620 | static bool intel_hdmi_get_hw_state(struct intel_encoder *encoder, |
621 | enum pipe *pipe) | |
7d57382e | 622 | { |
85234cdc | 623 | struct drm_device *dev = encoder->base.dev; |
7d57382e | 624 | struct drm_i915_private *dev_priv = dev->dev_private; |
85234cdc DV |
625 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); |
626 | u32 tmp; | |
627 | ||
628 | tmp = I915_READ(intel_hdmi->sdvox_reg); | |
629 | ||
630 | if (!(tmp & SDVO_ENABLE)) | |
631 | return false; | |
632 | ||
633 | if (HAS_PCH_CPT(dev)) | |
634 | *pipe = PORT_TO_PIPE_CPT(tmp); | |
635 | else | |
636 | *pipe = PORT_TO_PIPE(tmp); | |
637 | ||
638 | return true; | |
639 | } | |
640 | ||
5ab432ef | 641 | static void intel_enable_hdmi(struct intel_encoder *encoder) |
7d57382e | 642 | { |
5ab432ef | 643 | struct drm_device *dev = encoder->base.dev; |
7d57382e | 644 | struct drm_i915_private *dev_priv = dev->dev_private; |
5ab432ef | 645 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); |
7d57382e | 646 | u32 temp; |
2deed761 WF |
647 | u32 enable_bits = SDVO_ENABLE; |
648 | ||
649 | if (intel_hdmi->has_audio) | |
650 | enable_bits |= SDVO_AUDIO_ENABLE; | |
7d57382e | 651 | |
ea5b213a | 652 | temp = I915_READ(intel_hdmi->sdvox_reg); |
d8a2d0e0 | 653 | |
7a87c289 DV |
654 | /* HW workaround for IBX, we need to move the port to transcoder A |
655 | * before disabling it. */ | |
656 | if (HAS_PCH_IBX(dev)) { | |
5ab432ef | 657 | struct drm_crtc *crtc = encoder->base.crtc; |
7a87c289 DV |
658 | int pipe = crtc ? to_intel_crtc(crtc)->pipe : -1; |
659 | ||
5ab432ef DV |
660 | /* Restore the transcoder select bit. */ |
661 | if (pipe == PIPE_B) | |
662 | enable_bits |= SDVO_PIPE_B_SELECT; | |
7a87c289 DV |
663 | } |
664 | ||
d8a2d0e0 ZW |
665 | /* HW workaround, need to toggle enable bit off and on for 12bpc, but |
666 | * we do this anyway which shows more stable in testing. | |
667 | */ | |
c619eed4 | 668 | if (HAS_PCH_SPLIT(dev)) { |
ea5b213a CW |
669 | I915_WRITE(intel_hdmi->sdvox_reg, temp & ~SDVO_ENABLE); |
670 | POSTING_READ(intel_hdmi->sdvox_reg); | |
d8a2d0e0 ZW |
671 | } |
672 | ||
5ab432ef DV |
673 | temp |= enable_bits; |
674 | ||
675 | I915_WRITE(intel_hdmi->sdvox_reg, temp); | |
676 | POSTING_READ(intel_hdmi->sdvox_reg); | |
677 | ||
678 | /* HW workaround, need to write this twice for issue that may result | |
679 | * in first write getting masked. | |
680 | */ | |
681 | if (HAS_PCH_SPLIT(dev)) { | |
682 | I915_WRITE(intel_hdmi->sdvox_reg, temp); | |
683 | POSTING_READ(intel_hdmi->sdvox_reg); | |
7d57382e | 684 | } |
5ab432ef DV |
685 | } |
686 | ||
687 | static void intel_disable_hdmi(struct intel_encoder *encoder) | |
688 | { | |
689 | struct drm_device *dev = encoder->base.dev; | |
690 | struct drm_i915_private *dev_priv = dev->dev_private; | |
691 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); | |
692 | u32 temp; | |
3cce574f | 693 | u32 enable_bits = SDVO_ENABLE | SDVO_AUDIO_ENABLE; |
5ab432ef DV |
694 | |
695 | temp = I915_READ(intel_hdmi->sdvox_reg); | |
696 | ||
697 | /* HW workaround for IBX, we need to move the port to transcoder A | |
698 | * before disabling it. */ | |
699 | if (HAS_PCH_IBX(dev)) { | |
700 | struct drm_crtc *crtc = encoder->base.crtc; | |
701 | int pipe = crtc ? to_intel_crtc(crtc)->pipe : -1; | |
702 | ||
703 | if (temp & SDVO_PIPE_B_SELECT) { | |
704 | temp &= ~SDVO_PIPE_B_SELECT; | |
705 | I915_WRITE(intel_hdmi->sdvox_reg, temp); | |
706 | POSTING_READ(intel_hdmi->sdvox_reg); | |
707 | ||
708 | /* Again we need to write this twice. */ | |
709 | I915_WRITE(intel_hdmi->sdvox_reg, temp); | |
710 | POSTING_READ(intel_hdmi->sdvox_reg); | |
711 | ||
712 | /* Transcoder selection bits only update | |
713 | * effectively on vblank. */ | |
714 | if (crtc) | |
715 | intel_wait_for_vblank(dev, pipe); | |
716 | else | |
717 | msleep(50); | |
718 | } | |
7d57382e | 719 | } |
d8a2d0e0 | 720 | |
5ab432ef DV |
721 | /* HW workaround, need to toggle enable bit off and on for 12bpc, but |
722 | * we do this anyway which shows more stable in testing. | |
723 | */ | |
724 | if (HAS_PCH_SPLIT(dev)) { | |
725 | I915_WRITE(intel_hdmi->sdvox_reg, temp & ~SDVO_ENABLE); | |
726 | POSTING_READ(intel_hdmi->sdvox_reg); | |
727 | } | |
728 | ||
729 | temp &= ~enable_bits; | |
d8a2d0e0 | 730 | |
ea5b213a CW |
731 | I915_WRITE(intel_hdmi->sdvox_reg, temp); |
732 | POSTING_READ(intel_hdmi->sdvox_reg); | |
d8a2d0e0 ZW |
733 | |
734 | /* HW workaround, need to write this twice for issue that may result | |
735 | * in first write getting masked. | |
736 | */ | |
c619eed4 | 737 | if (HAS_PCH_SPLIT(dev)) { |
ea5b213a CW |
738 | I915_WRITE(intel_hdmi->sdvox_reg, temp); |
739 | POSTING_READ(intel_hdmi->sdvox_reg); | |
d8a2d0e0 | 740 | } |
7d57382e EA |
741 | } |
742 | ||
7d57382e EA |
743 | static int intel_hdmi_mode_valid(struct drm_connector *connector, |
744 | struct drm_display_mode *mode) | |
745 | { | |
746 | if (mode->clock > 165000) | |
747 | return MODE_CLOCK_HIGH; | |
748 | if (mode->clock < 20000) | |
5cbba41d | 749 | return MODE_CLOCK_LOW; |
7d57382e EA |
750 | |
751 | if (mode->flags & DRM_MODE_FLAG_DBLSCAN) | |
752 | return MODE_NO_DBLESCAN; | |
753 | ||
754 | return MODE_OK; | |
755 | } | |
756 | ||
757 | static bool intel_hdmi_mode_fixup(struct drm_encoder *encoder, | |
e811f5ae | 758 | const struct drm_display_mode *mode, |
7d57382e EA |
759 | struct drm_display_mode *adjusted_mode) |
760 | { | |
761 | return true; | |
762 | } | |
763 | ||
8ec22b21 CW |
764 | static bool g4x_hdmi_connected(struct intel_hdmi *intel_hdmi) |
765 | { | |
766 | struct drm_device *dev = intel_hdmi->base.base.dev; | |
767 | struct drm_i915_private *dev_priv = dev->dev_private; | |
768 | uint32_t bit; | |
769 | ||
770 | switch (intel_hdmi->sdvox_reg) { | |
eeafaaca | 771 | case SDVOB: |
8ec22b21 CW |
772 | bit = HDMIB_HOTPLUG_LIVE_STATUS; |
773 | break; | |
eeafaaca | 774 | case SDVOC: |
8ec22b21 CW |
775 | bit = HDMIC_HOTPLUG_LIVE_STATUS; |
776 | break; | |
8ec22b21 CW |
777 | default: |
778 | bit = 0; | |
779 | break; | |
780 | } | |
781 | ||
782 | return I915_READ(PORT_HOTPLUG_STAT) & bit; | |
783 | } | |
784 | ||
aa93d632 | 785 | static enum drm_connector_status |
930a9e28 | 786 | intel_hdmi_detect(struct drm_connector *connector, bool force) |
9dff6af8 | 787 | { |
df0e9248 | 788 | struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); |
f899fc64 CW |
789 | struct drm_i915_private *dev_priv = connector->dev->dev_private; |
790 | struct edid *edid; | |
aa93d632 | 791 | enum drm_connector_status status = connector_status_disconnected; |
9dff6af8 | 792 | |
8ec22b21 CW |
793 | if (IS_G4X(connector->dev) && !g4x_hdmi_connected(intel_hdmi)) |
794 | return status; | |
795 | ||
ea5b213a | 796 | intel_hdmi->has_hdmi_sink = false; |
2e3d6006 | 797 | intel_hdmi->has_audio = false; |
f899fc64 | 798 | edid = drm_get_edid(connector, |
3bd7d909 DK |
799 | intel_gmbus_get_adapter(dev_priv, |
800 | intel_hdmi->ddc_bus)); | |
2ded9e27 | 801 | |
aa93d632 | 802 | if (edid) { |
be9f1c4f | 803 | if (edid->input & DRM_EDID_INPUT_DIGITAL) { |
aa93d632 | 804 | status = connector_status_connected; |
b1d7e4b4 WF |
805 | if (intel_hdmi->force_audio != HDMI_AUDIO_OFF_DVI) |
806 | intel_hdmi->has_hdmi_sink = | |
807 | drm_detect_hdmi_monitor(edid); | |
2e3d6006 | 808 | intel_hdmi->has_audio = drm_detect_monitor_audio(edid); |
aa93d632 | 809 | } |
aa93d632 | 810 | kfree(edid); |
9dff6af8 | 811 | } |
30ad48b7 | 812 | |
55b7d6e8 | 813 | if (status == connector_status_connected) { |
b1d7e4b4 WF |
814 | if (intel_hdmi->force_audio != HDMI_AUDIO_AUTO) |
815 | intel_hdmi->has_audio = | |
816 | (intel_hdmi->force_audio == HDMI_AUDIO_ON); | |
55b7d6e8 CW |
817 | } |
818 | ||
2ded9e27 | 819 | return status; |
7d57382e EA |
820 | } |
821 | ||
822 | static int intel_hdmi_get_modes(struct drm_connector *connector) | |
823 | { | |
df0e9248 | 824 | struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); |
f899fc64 | 825 | struct drm_i915_private *dev_priv = connector->dev->dev_private; |
7d57382e EA |
826 | |
827 | /* We should parse the EDID data and find out if it's an HDMI sink so | |
828 | * we can send audio to it. | |
829 | */ | |
830 | ||
f899fc64 | 831 | return intel_ddc_get_modes(connector, |
3bd7d909 DK |
832 | intel_gmbus_get_adapter(dev_priv, |
833 | intel_hdmi->ddc_bus)); | |
7d57382e EA |
834 | } |
835 | ||
1aad7ac0 CW |
836 | static bool |
837 | intel_hdmi_detect_audio(struct drm_connector *connector) | |
838 | { | |
839 | struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); | |
840 | struct drm_i915_private *dev_priv = connector->dev->dev_private; | |
841 | struct edid *edid; | |
842 | bool has_audio = false; | |
843 | ||
844 | edid = drm_get_edid(connector, | |
3bd7d909 DK |
845 | intel_gmbus_get_adapter(dev_priv, |
846 | intel_hdmi->ddc_bus)); | |
1aad7ac0 CW |
847 | if (edid) { |
848 | if (edid->input & DRM_EDID_INPUT_DIGITAL) | |
849 | has_audio = drm_detect_monitor_audio(edid); | |
1aad7ac0 CW |
850 | kfree(edid); |
851 | } | |
852 | ||
853 | return has_audio; | |
854 | } | |
855 | ||
55b7d6e8 CW |
856 | static int |
857 | intel_hdmi_set_property(struct drm_connector *connector, | |
ed517fbb PZ |
858 | struct drm_property *property, |
859 | uint64_t val) | |
55b7d6e8 CW |
860 | { |
861 | struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); | |
e953fd7b | 862 | struct drm_i915_private *dev_priv = connector->dev->dev_private; |
55b7d6e8 CW |
863 | int ret; |
864 | ||
865 | ret = drm_connector_property_set_value(connector, property, val); | |
866 | if (ret) | |
867 | return ret; | |
868 | ||
3f43c48d | 869 | if (property == dev_priv->force_audio_property) { |
b1d7e4b4 | 870 | enum hdmi_force_audio i = val; |
1aad7ac0 CW |
871 | bool has_audio; |
872 | ||
873 | if (i == intel_hdmi->force_audio) | |
55b7d6e8 CW |
874 | return 0; |
875 | ||
1aad7ac0 | 876 | intel_hdmi->force_audio = i; |
55b7d6e8 | 877 | |
b1d7e4b4 | 878 | if (i == HDMI_AUDIO_AUTO) |
1aad7ac0 CW |
879 | has_audio = intel_hdmi_detect_audio(connector); |
880 | else | |
b1d7e4b4 | 881 | has_audio = (i == HDMI_AUDIO_ON); |
1aad7ac0 | 882 | |
b1d7e4b4 WF |
883 | if (i == HDMI_AUDIO_OFF_DVI) |
884 | intel_hdmi->has_hdmi_sink = 0; | |
55b7d6e8 | 885 | |
1aad7ac0 | 886 | intel_hdmi->has_audio = has_audio; |
55b7d6e8 CW |
887 | goto done; |
888 | } | |
889 | ||
e953fd7b CW |
890 | if (property == dev_priv->broadcast_rgb_property) { |
891 | if (val == !!intel_hdmi->color_range) | |
892 | return 0; | |
893 | ||
894 | intel_hdmi->color_range = val ? SDVO_COLOR_RANGE_16_235 : 0; | |
895 | goto done; | |
896 | } | |
897 | ||
55b7d6e8 CW |
898 | return -EINVAL; |
899 | ||
900 | done: | |
901 | if (intel_hdmi->base.base.crtc) { | |
902 | struct drm_crtc *crtc = intel_hdmi->base.base.crtc; | |
a6778b3c DV |
903 | intel_set_mode(crtc, &crtc->mode, |
904 | crtc->x, crtc->y, crtc->fb); | |
55b7d6e8 CW |
905 | } |
906 | ||
907 | return 0; | |
908 | } | |
909 | ||
7d57382e EA |
910 | static void intel_hdmi_destroy(struct drm_connector *connector) |
911 | { | |
7d57382e EA |
912 | drm_sysfs_connector_remove(connector); |
913 | drm_connector_cleanup(connector); | |
674e2d08 | 914 | kfree(connector); |
7d57382e EA |
915 | } |
916 | ||
72662e10 | 917 | static const struct drm_encoder_helper_funcs intel_hdmi_helper_funcs_hsw = { |
72662e10 | 918 | .mode_fixup = intel_hdmi_mode_fixup, |
72662e10 | 919 | .mode_set = intel_ddi_mode_set, |
1f703855 | 920 | .disable = intel_encoder_noop, |
72662e10 ED |
921 | }; |
922 | ||
7d57382e | 923 | static const struct drm_encoder_helper_funcs intel_hdmi_helper_funcs = { |
7d57382e | 924 | .mode_fixup = intel_hdmi_mode_fixup, |
7d57382e | 925 | .mode_set = intel_hdmi_mode_set, |
1f703855 | 926 | .disable = intel_encoder_noop, |
7d57382e EA |
927 | }; |
928 | ||
929 | static const struct drm_connector_funcs intel_hdmi_connector_funcs = { | |
5ab432ef | 930 | .dpms = intel_connector_dpms, |
7d57382e EA |
931 | .detect = intel_hdmi_detect, |
932 | .fill_modes = drm_helper_probe_single_connector_modes, | |
55b7d6e8 | 933 | .set_property = intel_hdmi_set_property, |
7d57382e EA |
934 | .destroy = intel_hdmi_destroy, |
935 | }; | |
936 | ||
937 | static const struct drm_connector_helper_funcs intel_hdmi_connector_helper_funcs = { | |
938 | .get_modes = intel_hdmi_get_modes, | |
939 | .mode_valid = intel_hdmi_mode_valid, | |
df0e9248 | 940 | .best_encoder = intel_best_encoder, |
7d57382e EA |
941 | }; |
942 | ||
7d57382e | 943 | static const struct drm_encoder_funcs intel_hdmi_enc_funcs = { |
ea5b213a | 944 | .destroy = intel_encoder_destroy, |
7d57382e EA |
945 | }; |
946 | ||
55b7d6e8 CW |
947 | static void |
948 | intel_hdmi_add_properties(struct intel_hdmi *intel_hdmi, struct drm_connector *connector) | |
949 | { | |
3f43c48d | 950 | intel_attach_force_audio_property(connector); |
e953fd7b | 951 | intel_attach_broadcast_rgb_property(connector); |
55b7d6e8 CW |
952 | } |
953 | ||
08d644ad | 954 | void intel_hdmi_init(struct drm_device *dev, int sdvox_reg, enum port port) |
7d57382e EA |
955 | { |
956 | struct drm_i915_private *dev_priv = dev->dev_private; | |
957 | struct drm_connector *connector; | |
21d40d37 | 958 | struct intel_encoder *intel_encoder; |
674e2d08 | 959 | struct intel_connector *intel_connector; |
ea5b213a | 960 | struct intel_hdmi *intel_hdmi; |
7d57382e | 961 | |
ea5b213a CW |
962 | intel_hdmi = kzalloc(sizeof(struct intel_hdmi), GFP_KERNEL); |
963 | if (!intel_hdmi) | |
7d57382e | 964 | return; |
674e2d08 ZW |
965 | |
966 | intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL); | |
967 | if (!intel_connector) { | |
ea5b213a | 968 | kfree(intel_hdmi); |
674e2d08 ZW |
969 | return; |
970 | } | |
971 | ||
ea5b213a | 972 | intel_encoder = &intel_hdmi->base; |
373a3cf7 CW |
973 | drm_encoder_init(dev, &intel_encoder->base, &intel_hdmi_enc_funcs, |
974 | DRM_MODE_ENCODER_TMDS); | |
975 | ||
674e2d08 | 976 | connector = &intel_connector->base; |
7d57382e | 977 | drm_connector_init(dev, connector, &intel_hdmi_connector_funcs, |
8d91104a | 978 | DRM_MODE_CONNECTOR_HDMIA); |
7d57382e EA |
979 | drm_connector_helper_add(connector, &intel_hdmi_connector_helper_funcs); |
980 | ||
21d40d37 | 981 | intel_encoder->type = INTEL_OUTPUT_HDMI; |
7d57382e | 982 | |
eb1f8e4f | 983 | connector->polled = DRM_CONNECTOR_POLL_HPD; |
c3febcc4 | 984 | connector->interlace_allowed = 1; |
7d57382e | 985 | connector->doublescan_allowed = 0; |
27f8227b | 986 | intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2); |
7d57382e | 987 | |
66a9278e DV |
988 | intel_encoder->cloneable = false; |
989 | ||
08d644ad DV |
990 | intel_hdmi->ddi_port = port; |
991 | switch (port) { | |
992 | case PORT_B: | |
f899fc64 | 993 | intel_hdmi->ddc_bus = GMBUS_PORT_DPB; |
b01f2c3a | 994 | dev_priv->hotplug_supported_mask |= HDMIB_HOTPLUG_INT_STATUS; |
08d644ad DV |
995 | break; |
996 | case PORT_C: | |
7ceae0a5 | 997 | intel_hdmi->ddc_bus = GMBUS_PORT_DPC; |
7ceae0a5 | 998 | dev_priv->hotplug_supported_mask |= HDMIC_HOTPLUG_INT_STATUS; |
08d644ad DV |
999 | break; |
1000 | case PORT_D: | |
7ceae0a5 | 1001 | intel_hdmi->ddc_bus = GMBUS_PORT_DPD; |
7ceae0a5 | 1002 | dev_priv->hotplug_supported_mask |= HDMID_HOTPLUG_INT_STATUS; |
08d644ad DV |
1003 | break; |
1004 | case PORT_A: | |
1005 | /* Internal port only for eDP. */ | |
1006 | default: | |
6e4c1677 | 1007 | BUG(); |
f8aed700 | 1008 | } |
7d57382e | 1009 | |
ea5b213a | 1010 | intel_hdmi->sdvox_reg = sdvox_reg; |
7d57382e | 1011 | |
64a8fc01 | 1012 | if (!HAS_PCH_SPLIT(dev)) { |
a3da1df7 | 1013 | intel_hdmi->write_infoframe = g4x_write_infoframe; |
687f4d06 | 1014 | intel_hdmi->set_infoframes = g4x_set_infoframes; |
90b107c8 SK |
1015 | } else if (IS_VALLEYVIEW(dev)) { |
1016 | intel_hdmi->write_infoframe = vlv_write_infoframe; | |
687f4d06 | 1017 | intel_hdmi->set_infoframes = vlv_set_infoframes; |
8c5f5f7c | 1018 | } else if (IS_HASWELL(dev)) { |
8c5f5f7c | 1019 | intel_hdmi->write_infoframe = hsw_write_infoframe; |
687f4d06 | 1020 | intel_hdmi->set_infoframes = hsw_set_infoframes; |
fdf1250a PZ |
1021 | } else if (HAS_PCH_IBX(dev)) { |
1022 | intel_hdmi->write_infoframe = ibx_write_infoframe; | |
687f4d06 | 1023 | intel_hdmi->set_infoframes = ibx_set_infoframes; |
fdf1250a PZ |
1024 | } else { |
1025 | intel_hdmi->write_infoframe = cpt_write_infoframe; | |
687f4d06 | 1026 | intel_hdmi->set_infoframes = cpt_set_infoframes; |
64a8fc01 | 1027 | } |
45187ace | 1028 | |
5ab432ef | 1029 | if (IS_HASWELL(dev)) { |
6441ab5f | 1030 | intel_encoder->pre_enable = intel_ddi_pre_enable; |
5ab432ef DV |
1031 | intel_encoder->enable = intel_enable_ddi; |
1032 | intel_encoder->disable = intel_disable_ddi; | |
6441ab5f | 1033 | intel_encoder->post_disable = intel_ddi_post_disable; |
85234cdc | 1034 | intel_encoder->get_hw_state = intel_ddi_get_hw_state; |
5ab432ef DV |
1035 | drm_encoder_helper_add(&intel_encoder->base, |
1036 | &intel_hdmi_helper_funcs_hsw); | |
1037 | } else { | |
1038 | intel_encoder->enable = intel_enable_hdmi; | |
1039 | intel_encoder->disable = intel_disable_hdmi; | |
85234cdc | 1040 | intel_encoder->get_hw_state = intel_hdmi_get_hw_state; |
5ab432ef DV |
1041 | drm_encoder_helper_add(&intel_encoder->base, |
1042 | &intel_hdmi_helper_funcs); | |
1043 | } | |
85234cdc | 1044 | intel_connector->get_hw_state = intel_connector_get_hw_state; |
5ab432ef | 1045 | |
7d57382e | 1046 | |
55b7d6e8 CW |
1047 | intel_hdmi_add_properties(intel_hdmi, connector); |
1048 | ||
df0e9248 | 1049 | intel_connector_attach_encoder(intel_connector, intel_encoder); |
7d57382e EA |
1050 | drm_sysfs_connector_add(connector); |
1051 | ||
1052 | /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written | |
1053 | * 0xd. Failure to do so will result in spurious interrupts being | |
1054 | * generated on the port when a cable is not attached. | |
1055 | */ | |
1056 | if (IS_G4X(dev) && !IS_GM45(dev)) { | |
1057 | u32 temp = I915_READ(PEG_BAND_GAP_DATA); | |
1058 | I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd); | |
1059 | } | |
7d57382e | 1060 | } |